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May 2011 www.altera.com Monthly Spotlight

Video: See Stratix V FPGA Running at 14.1 Gbps—Now Shipping Get a progress update on silicon checkout for production Stratix® V FPGAs, the industry's first 28-nm high-end FPGAs. You'll also see an eye diagram illustrating transceiver performance. Samples of Stratix V FPGAs are now shipping. Watch the video today!

FPGAs, CPLDs, ASICs

Altera Breaks Semiconductor Record for Most Transistors on an IC Stratix V FPGAs are the industry's first devices to feature 3.9 billion transistors—the most transistors ever packed onto an IC.

Software, Intellectual Property, and Development Kits

Download New Quartus® II Software v11.0 with Qsys New release includes production quality Qsys System Integration Tool offering higher performance with network-on-chip (NoC) technology, hierarchical support, and faster board bring-up. Get details on what's new.

3 Online Demos: Qsys System Integration Tool in Action Check out the 3 new online demos showing the new Qsys simulation, debug capabilities, and migration from SOPC Builder.

Video: 5 Reasons to Use MP32 in Your Custom Embedded Design You can now use the first MIPS®-compatible soft processor in your next FPGA design. The MP32 processor is also the first soft processor that runs Wind River's VxWorks operating system. Watch a video of MP32 in action!

Accelerate Development with Kontron COM Express FPGA Starterkit This kit, featuring a Cyclone® IV FPGA as an I/O companion solution to the Intel® Atom™ processor, is ideal for industrial automation and infotainment.

Read SNUG Conference Paper: Creating Reusable Design Blocks Click to enlarge This award-winning paper focuses on architecting reusable IP, coding guidelines for IP reuse, and IP packaging for ease of reuse.

Technology and End Markets

Simplify Video Surveillance Camera Design Learn about the industry's first wide dynamic range (WDR) video surveillance chipset that supports Apical's image sensor pipeline and AltaSens' 1080p60 image sensor.

Support and Literature

Download the Stratix V User Guide Lite Looking for specific information on designing with Stratix V FPGAs? Try this quick and easy manual. A must for all designers! From the Forum: Creating Multiple Frame-Buffer IP Design Read the forum and join the discussion to learn how to create multiple frame-buffer IP designs.

From the Wiki: TSE with MII/GMII Interface Hardware Test Download this reference design that performs hardware testing without using memory map drivers for Triple Speed Ethernet (TSE) configuration.

Training and Events

New Instructor-Led Course: System Integration with Qsys Learn key features of Qsys. Build hierarchical systems quickly by integrating IP with custom logic, and optimize designs for performance.

Altera in the News

Altera Honored by EE Times as the 2010 Company of the Year Altera receives prestigious ACE Award as a result of its innovation, technology leadership and revenue growth.