Bridge Rectifier with Improved Power Quality Using Capacitive Network

Sagar Gupta Nimesh V, Vinod John Cypress Technology India Pvt. Ltd. Department of Karnataka, India Indian Institute of Science Bangalore, Karnataka, India Email: [email protected] Email: [email protected], [email protected]

Abstract—Widely distributed single-phase power electronic rectifier loads are increasing source of harmonics in power distri- bution system. These harmonics have many well known adverse impacts on the power system. So it is necessary to improve the power quality of the rectifiers. This paper presents a novel single phase rectifier in which are used in parallel with in one leg of the rectifier. A general analytical model of the proposed topology is obtained. The closed form expressions (a) (b) for the rectifier waveforms helps in parameter selection that leads to optimal performance in terms of input current THD. A comparative study of different topologies of rectifiers are done in terms of input , current waveform distortion, output dc voltage , and desired target for dc output voltage. The proposed topology reduces the total harmonic distortion from 145 percent in normal rectifier to 63 percent while maintaining voltage ripple less then 0.3 percent. The proposed topology keeps dc bus ripple small while simultaneously providing better THD. (c) The passive components considered for improving harmonic Fig. 1. Rectifier topologies (a) Diode rectifier with capacitive output filter injection are 2 small capacitors. The additional cost required (b) Voltage doubler rectifier (c) Split full bridge rectifier. for the proposed rectifier is low, the proposed rectifier also has a higher efficiency than the other commonly used topologies. TABLE I IEC 61000-3-2 HARMONIC LIMITSFOR CLASS C EQUIPMENTSFOR I.INTRODUCTION INPUTPOWER < 25 W Non-linear loads such as controlled and uncontrolled, single Harmonic (n) Limit(% of the fundamental input current) phase and three phase rectifiers injects considerable amount of 3 86 lower order harmonics into the grid and distorts the voltage 5 61 at point of common coupling [1], [2]. Harmonics cause ex- cessive heating, pulsating and reduced torque in motors and generators, increased heating and voltage stresses in capacitor, voltage and input current[9]. So for lower power applications malfunction of switch gears and relays and reduces the life of PFE rectifier circuits, diode rectifier with capacitive filter, as products [3], [4]. It is therefore necessary to reduce harmonic shown in Fig. 1(a), and voltage doubler rectifier with two in electric power system. Also in case of dc loads it is split capacitances, as shown in Fig. 1(b), are preferred. It important to get low ripple in output dc voltage for its proper is well known that diode rectifier with capacitive filter, as functioning [5]. So it is necessary to provide dc output at shown in Fig. 1(a), has negligible output voltage ripple but low ripple keeping the harmonics injected in the line to a injects significant amount of lower order harmonics into the reasonable low value. grid. Voltage doubler, shown in Fig. 1(b), has low harmonic Passive Front End (PFE) rectifiers followed by injection when Cs is kept small but ripple in output voltage Correction (PFC) stage, and Active Front End (AFE) rectifiers is considerably high. maintains dc bus voltage at desired level and harmonics According to IEC 61000-3-2, equipments are classified in injected, at switching frequency, can be filtered out using 4 categories, Class A, Class B, Class C and Class D. Lighting first order filters [6], [7], [8]. Using the above mentioned equipments, whose front end is a rectifier, falls into Class C topologies, for low power applications such as LED lighting, and harmonic standards for these equipments is summarized in increases the cost as it requires active switches such as MOS- Table I. In this paper a new Split Capacitor Full Bridge (SCFB) FET or IGBT and additional sensors, for controlling dc bus rectifier is proposed. The proposed SCFB rectifier shown in Fig. 1(c) is suited for low power applications. SCFB rectifier This work was supported by CPRI, Ministry of Power, Government of India, is a combination of diode rectifier with capacitive filter and under the project Power conversion, control, and protection technologies for microgrid. voltage doubler topology. Initial simulation studies comparing the three topologies shown in Fig. 1 is summarized in section 978-1-4673-8888-7/16/$31.00 © 2016 IEEE TABLE II VALESANDPARAMETERSCONSIDEREDFORTHESTUDY (A)BASE positive half cycle of vg. Conducting elements of in each VALUES (B) PARAMETERS mode is shown as dark black shade and the non-conducting elements are in light black shades, as shown in Fig. 2. The main assumptions for this analysis are: Parameter Base Value Vb 340 V Parameter Value(per unit) 1) Diodes are assumed ideal. Pb 25 W Vg 240 V (0.71) 2) ESR of the capacitances have been ignored. fb 50 Hz Po 25 W (1) 3) Ratio ∆ Vo/Vo  1. Ib 73.53 mA RL 5 kΩ (1.08) Zb 4624 Ω L 2 mH (136 µ) A. Mode-I from t1 < t < t2 Lb 14.7 H Rg 5 Ω (1.08 m) C 688.9 nF b (b) In Mode-I, during positive half cycle of the grid supply (a) diode D1 starts conducting, at t = t1. At t = t1, vc1(t1) = V1 = Vg(t1), vc2(t1) = V2 , iL(t1) = 0 and v0(t) = vc1(t) + vc2(t). The governing equations for circuit shown in Fig. 2(a) II. The analytical closed form expressions for waveforms are can be written as, covered in section III and Appendix. The equations for wave- Z diL 1 forms of SCFB rectifier that are derived in this paper are used vg(t) = iLRg + L + i1dt + V1 (1) dt Cs for circuit optimization. This leads to circuit parameters that 1 Z meet tight dc voltage ripple requirement while simultaneously v0(t) = iRRL = icdt + V1 + V2 (2) C having minimum input voltage distortion. Section IV details L analytical, simulation and experimental results. This section During this mode, upper split capacitor (vc1(t)) charges from also covers the effects of line inductance and load capacitance grid and lower split capacitor(vc2(t)) discharges into load and in optimal values split capacitor and THD of line current grid. This mode ends when either diode D1 stops conducting, drawn, section V concludes the paper. current drawn from grid goes to zero, or vc2(t) has fallen to zero. II.SIMULATION STUDIES B. Mode-II from t < t < t Initially simulations on all three topologies, shown in Fig. 1 2 3 was carried to check the performance of the proposed model. Mode-II starts at t2 when diode D2 starts conducting that Per unit values and design specifications of the converter used is vc2(t2) = 0 and D1 is already conducting. Let vc1(t2) = for simulation are given in Table II(a) and II(b) respectively. VmII1 and iL(t2) = IL0. Fig. 2(b) shows the equivalent circuit Po,Vg, fs = 50 Hz, RL Lg,Rg are rated power, grid and the equations for this mode can be written as, voltage rms, grid frequency, line impedance and load resis- di 1 Z v (t) = i R + L L + i dt + V tance, respectively. With line impedance neglected, effects g L g 1 mII1 (3) dt Cs of variations in values of load capacitance, CL, and split 1 Z capacitance, Cs, in grid current THD and ripple in output v0(t) = iRRL = icdt + VmII1 (4) CL voltage is studied. Summary of the results in tabulated in Table. III. It can be observed that the proposed SCFB topology As diode D2 is conducting, this ensures that the lower split has the advantages of both the normal rectifier with low capacitor does not charge in opposite direction, so vC2(t) in output voltage ripple, and voltage doubler circuit with lesser this mode will remain zero. This mode ends when diode D1 distortion in line current drawn. stops conducting, that is current drawn from the grid dies down to zero. III.ANALYSIS OF SCFBRECTIFIER C. Mode-III from t < t < t Fig. 2 shows the split capacitor full bridge (SCFB) rectifier 3 4 and its operating modes. The grid is modeled as a sinusoidal Mode-III occurs when the current iL reaches zero at the end of Mode-I with vc1(t2) and vc2(t2) > 0. In this case time voltage source vg in series with line impedance consisting of t3 equals to the instant t2 which is the end of Mode-I. In this Rg and L in series. The load is modeled as a resistor(RL). For modeling of the topology different modes of operation mode, no diodes are conducting, therefore the current from are identified and the governing equations of these modes the grid is zero and load is supplied by the energy stored in capacitors, C C . At t = t , let v (t ) = V and are covered in this section. The analysis is carried out for L s 3 C1 3 mIII1

TABLE III COMPARISON OF STANDARD RECTIFIER, VOLTAGE DOUBLER AND SCFB RECTIFIER WITH VARIATION OF Cs AND CL

Topology 1(Normal Rectifier) Topology 2(Voltage Doubler) Topology 3 (SCFB Rectifier) Cs(µF)(pu) CL(µF)(pu) Vo(V)(pu) ∆V (V)(pu) THD(%) Vo(V)(pu) ∆V (V)(pu) THD(%) Vo(V)(pu) ∆V (V)(pu) THD(%) 222 (322.6) 222 (322.6) 338 (1.0) 2.9 (8.5 m) 357 72 (0.3) 104 (0.3) 4.6 339 (1.0) 3.5 (0.01) 338 470 (666.7) 470 (666.7) 339 (1.0) 1.4 (4.1 m) 386 137 (0.4) 178 (0.5) 8.1 310 (1.0) 2.0 (5.9 m) 341 1000 (1.5 k) 1000 (1428.6) 340 (1.0) 0.8 (7.5 m) 394 224 (0.7) 235 (0.7) 20 340 (1.0) 1.4 (4.1 m) 263 2000 (3.3 k) 2000 (29.1) 340 (1.0) 0.3 (0.9 m) 395 313 (1.0) 230 (0.7) 33 340 (1.0) 1.6 (4.7m) 65 2x106 (3.3 M) 222 (322.6) 338 (1.0) 2.9 (8.5 m) 357 679 (2.0) 1.4 (4.0 m) 438 679 (2.0) 1.3 (3.8 m) 458 (a) (b)

(c) (d) Fig. 2. Different modes of operation for the SCFB rectifier (a) Mode-I, (b) Mode-II, (c) Mode-III, and (d) Mode-IV.

(a) (b) (c) Fig. 3. Circuit performance as a function of load capacitance and split capacitance showing (a) Percentage total harmonic distortion (b) Output voltage ripple ∆Vo and (c) Average output voltage Vo.

vC2(t3) = VmIII2 . Equivalent circuit for this mode is shown parameters. All remaining and currents in the circuit in Fig. 2(c), governing equations for this mode is, can be obtained from these capacitor voltages. For an input voltage of Vg = 240 V and load resistance v0(t) = iRRL = vC1(t) + vC2(t) (5) of RL = 5 kΩ(load power of around 22 W), the effect of (t−t3)/τ1 v0(t) = (VmIII1 + VmIII2 )e (6) variations in CL and Cs on THD, Vo and ∆ Vo is shown in CL + Cs/2 Fig. 3. From these results it is seen that minimum THD is τ1 = (7) RL obtained when Cs = 1.647 µ F for a particular value of CL and the value of CL is chosen such that ∆ Vo is less than 1 V D. Mode-IV from t < t < T + t 4 2 1 and it is 470 µ F . It can also be observed, from Fig. 3(a) that Mode-IV occurs at the end of Mode-II when iL reaches 0 the minimum of the THD is not significantly affected by CL. with vC2(t) = 0. Hence time t4 matches with time t3 of It can also be seen from Fig.3(b) that low values of CL leads Mode-II. In this diode D2 is conducting and load is supplied to high ripple in the dc bus voltage. Also Fig. 3(c) shows that by energy stored in capacitors CL Cs. Let Mode-IV start at larger values for Cs lead to increase in the average dc bus t4 and vC1 = VmIV1 , the equivalent circuit is shown in Fig. voltage. 2(d) and the governing equations are given by, From Fig. 3(a), it can be concluded that by choosing a specific value of split capacitance(C ),minimum THD injec- v (t) = i R = v (t) (8) s 0 R L C1 tion can be obtained of a particular load. Also Fig. 3(b) t−t4 τ v0(t) = VmIV1 e (9) shows that output voltage ripple are mainly controlled by load C + C capacitance(CL), so THD and output voltage ripple can be τ = L s (10) RL controlled independently. The solutions of above mentioned differential equations for 1) For small value of split capacitor(Cs < 2 µF ), vc2(t) mode-I and mode-II is given in the Appendix. Analytical falls to zero before diode D1 stops conducting in positive expressions in (6), (9), (11), (16) and (18) provide expressions half cycle of supply then we get Mode-I followed by for the capacitor voltage waveforms in terms of the circuit Mode-II and finally Mode-IV. In this case Mode I starts at t1 = 0. For this mode, vg and iL, vc1 and vc2, and (a) (b) (c)

(d) (e) (f)

Fig. 4. Analytical Results for different modes of operation, Cs = 1 µF (a, b, c) and for Cs = 3 µF (d, e, f): (a, d) Grid voltage, vg and current drawn from grid, iL(t), in per unit. (b, e) Voltage across upper split capacitor, vc1(t) and lower split capacitors, vc2(t). (c, f) Output voltage Vo.

(a) (b) (c) Fig. 5. Comparison of input voltage and current waveforms (a) Results from analytical model (b) Results obtained from simulation (c) Experimental measurements: Grid voltage(CH2: 2 V/div, 50:1 probe) and current(CH1: 20 mA/div).

TABLE IV Vo are shown in Figs. 4(a), (b), (c), respectively. HARMONIC ANALYSIS OF LINE CURRENTOF SCFBRECTIFIER FOR 2) For large value of split capacitor(Cs > 2 µF ), diode D1 Pout = 23 W stops conducting before vc2(t) falls to zero in positive half cycle of supply. In this case Mode-I followed by Harmonic Order Analytical Experimental Fundamental(50 Hz) 100 (0.156A) 100 (0.1575A) Mode-III. Also, in this case the start of Mode-I is at 3rd 41 45.7 t1 6= 0. For this case, vg and iL, vc1 and vc2, and Vo 5th 26.9 21.4 are shown in Figs. 4(d), (e), (f), respectively. 7th 8.9 11.6 th It is observed from analysis, simulation and experiments that 9 19.4 23.5 11th 5.33 2.9 selection of capacitance parameters such that the initiation of 13th 15.3 17.4 Mode-III immediately after Mode-I leads to minimum source 15th 5.3 6.3 current THD. Fig. 5 shows the supply voltage and supply 17th 12.4 1.4 19th 5.6 6.2 current for L = 2mH Rg = 5Ω Cs = 1.65µF CL = Total THD 66.7 62.48 470µF RL = 5000Ω. For RL = 5000Ω, Cs = 1.65µ is the lowest point of THD injection.

IV. ANALYTICAL,SIMULATION AND EXPERIMENTAL results, shown in Fig. 5(b), and experimental results, shown RESULTS in Fig. 5(c), matches closely. THD of the current drawn Analysis, simulation and detailed experimental studies are from the grid for analytical, simulation and experimental are performed the proposed topology shown in Fig. 1(c). Design 66.7%, 66.7% and 62.5% respectively. Table. IV summarizes ratings of the converter are covered in section II. Effects of the harmonics, up to 950 Hz. This meets the IEC 61000-3- line inductanceL and load capacitance CL in optimal split 2 requirements specified in Table. I. The small deviation in capacitance Cs and THD in line current is also discussed in experimental measured THD is due to the non zero resistances this section. Fig. 5 shows the grid voltage and current drawn of the diodes and rectifier, which also shows in terms of from the grid. Analytical results, shown in Fig.5(a), simulation the reduced oscillations in the waveform. Efficiency of SCFB 100 100 2 100 80 80 1.5 80 60 60 60 40 40 1 40 20 20 0.5 20 0 0 2 4 6 8 10 2 4 6 8 10 0 1000 2000 3000 4000 0 1000 2000 3000 4000

(a) (b) (c) (d)

Fig. 6. (a) Variation of Cs with L, (b) Variation of THD with L, (c) Variation of Cs with CL, (d) Variation of THD with CL.

rectifier is measured to be 99.36% and that of diode rectifier A. Mode-I from t1 < t < t2 in Fig. 1(a) is 98.29% in experimental studies. The equations (1) & and (2) in Section III A form a fourth A. Effect of Line Inductance order system. The roots of the characteristic equation are solved assuming well separated circuit poles[5]. Values of line inductance(L) varies from few µH to few mH. Effect of variations in L on Cs is shown in Fig. 6(c). It 0 2 −yt0 0 C4 0 vc2(t ) = −Vmωny[A4e + B4cosωt + sinωt + can be seen that values Cs decreases with increase in L. For a ω C = 1.65µF L ! particular value of s0 , effect of on line current 0 −D E −ξωnt 4 0 4 0 e sin(ωdt + φ) + sinωdt ] THD is shown in Fig. 6(b). In the circuit shown in Fig.1(a), p2 1 − ξ2 ωd line current THD decreases with increase in L, but in SCFB ! rectifier the increase in L affects slowly and increase in THD 0 0 0 −B −yt 2 −yt −ξωnt 5 0 +V2e −yωnV1[A5e +e sin(ωdt + φ) level. p2 1 − ξ2

B. Effect of Load Capacitance C5 0 + sinωdt ] (11) The ripple in output voltage decreases as the optimal load ωd capacitance CL increases. Effect of variations in CL on Cs is where, C shown in Fig. 6(c). It can be seen that this value of s remains s a constant for CL greater than 10 µF . For a particular value of RL(Cs + CL) + 2CsRg ωn = (12) Cs0 = 1.65µF , the effect of CL in line current THD is shown RLLCs(Cs + 2CL) in Fig. 6(d). As opposed the topology shown in Fig. 1(a), in 1 SCFB rectifier the line current THD remains almost a constant y = (13) for higher values of load capacitance CL. So the value of CL RL(Cs + CL) + 2CsRg is chosen to be 470 µF to so that voltage ripple is within a desirable limit. 2LCs + RCsRg(Cs + 2CL) ξ = p V. CONCLUSION 2 LCsRL(Cs + 2CL)[RL(Cs + 2CL) + 2CsRg] (14) In this paper a SCFB rectifier is proposed to reduce the p2 2 p2 1 − ξ ω = ω 1 − ξ2, φ = tan−1 (15) harmonic injection in the line by using capacitive components. d n ξ Two capacitances(X rated) are used to affect the input line current so that input line current harmonics are reduced. The and, A   0  analytical modeling of the new topology is systematically 4 B4  0  performed. The results are verified with simulation results   −1   C4  = P  CLRLsinωt1  and experimental results. The analytical model is used to D  C R ωcosωt + sinωt  find the value of capacitances(C ) for which minimal line  4  L L 1 1 s E ωcosωt current THD can be obtained for a particular load. Also it 4 1     is shown that ripple in output voltage can be independently A5 0 −1 controlled by load capacitance(CL). The proposed rectifier B5 = N  LCs  circuit also operates with a higher efficiency compared to C5 CsRg − CLRL standard rectifiers.

APPENDIX For a rectifier most important thing to be known are its output voltage for it output characteristics, and line current to know it input performance. Equations which are obtained by analysis in Mode-I and Mode-II are solved here to get V0 and iL. where,

0 2 −yt0 0 C1 0 L + RLRg(CL + Cs) v0(t ) = RLCsVmωny[A1e + B1cosωt + sinωt + p = + ω 2LR (C + C ) ! L L s 0 −D E s −ξωnt 1 0 1 0 e sin(ωdt + φ) + sinωdt ] L + RLRg(CL + Cs) RL + Rg p2 2 ω ( )2 − 1 − ξ d 2LR (C + C ) LR (C + C ) " # L L s L L s 0 0 −B C −yt −ξωnt 2 0 2 0 +V1 A2e + e sin(ωdt + φ) + sinωdt p2 1 − ξ2 ωd L + R R (C + C ) q = L g L s − " # 2LR (C + C ) 0 0 −B C L L s −yt −ξωnt 2 0 2 0 +V2 A2e + e sin(ωdt + φ) + sinωdt s p2 1 − ξ2 ωd L + RLRg(CL + Cs) RL + Rg ( )2 − (16) 2LRL(CL + Cs) LRL(CL + Cs) where, A6  0      B6 −1  0  A1 0   = Q ×   C6  sinωt2  B1  0    −1   D6 ωcosωt2 C1  = P  sinωt1  D  ωcosωt  where,  1  1   E1 0 1 0 1 1 p + q 1 q p  where Q =  2 2   pq p + q ω ω   1 1 0 1 0  0 pq2 ω2q ω2p  2ξωn 2ξωn + y 1 y 1  00  2 2 2 2  00 di(t ) 00 00 P = ω + ωn ωn + 2ξωny 2ξωn + y ω y  iL(t )Rg + L = vg(t ) − vo(t ) (19)  2 2 2 2 2  dt00 2ξωnω ωny ωn + 2ξωny ωny ω  2 2 2 2 ωnω 0 ωny 0 ωny Knowing the grid voltage and Vo(t) in (18), the input current     iL(t) is solved in Mode-II. The expressions for source current A2 1 and output voltage are used to obtain THD and voltage design −1 2 B2 = N 2ξωn − 2LCsωny trade off relationship shown in Fig. 3. 2 C2 ωn(1 − 2yCsRg)     REFERENCES A3 1 −1 2 [1] T. M. Blooming and D. J. Carnovale, “Application of ieee std 519-1992 B3 = N 2ξωn − 2LCsωny harmonic limits,” in Pulp and Paper Industry Technical Conference, 2006. 2 C3 ωnyRLCL Conference Record of Annual. IEEE, 2006, pp. 1–9. [2] B. Singh et al., “A review of single-phase improved power quality AC- where, N is given by DC converters,” IEEE Trans. Ind. Electron., vol. 50, no. 5, pp. 962–981,   Oct. 2003. 1 1 0 [3] A. Mansoor, W. Grady, A. Chowdhury, and M. Samotyi, “An investigation N = 2ξωn y 1 of harmonics attenuation and diversity among distributed single-phase ω2 0 y power electronic loads,” in Transmission and Distribution Conference, n 1994., Proceedings of the 1994 IEEE Power Engineering Society. IEEE, 1994, pp. 110–116. 0 [4] M. Chen, Z. Qian, and X. Yuan, “Frequency-domain analysis of uncon- 0 di(t ) 0 0 0 iL(t )Rg + L 0 = vg(t ) − vo(t ) + vC2(t ) (17) trolled rectifiers,” in Applied Power Electronics Conference and Exposi- dt tion, 2004. APEC’04. Nineteenth Annual IEEE, vol. 2. IEEE, 2004, pp. The solutions for vo(t) in (11) and vc2(t) in (16) is used to 804–809. [5] R. W. Erickson and D. Maksimovic, Fundamentals of power electronics. evaluate iL(t) in (17). Springer Science & Business Media, 2007. [6] J. Rodr´ıguez et al., “PWM regenerative rectifiers: State of the art,” IEEE B. Mode-II from t2 < t < t3 Trans. Ind. Electron., vol. 52, no. 1, pp. 5–22, Feb. 2005. [7] A. Prasad et al., “An active power factor correction technique for three- phase diode rectifiers,” IEEE Trans. Power Electron., vol. 6, no. 1, pp. 83–92, Jan. 1991. 00 Vm(RL + Rg) 00 B6 00 vo(t ) = [A6cosωt + sinωt [8] B. Ooi et al., “An integrated AC drive system using a controlled-current RLL(CL + Cs) ω PWM rectifier/inverter link,” IEEE Trans. Power Electron., vol. 3, no. 1, 00 00 + C e−pt + D e−qt ]+ pp. 64–71, Jan. 1988. 6 6 [9] D. C. Lee and D. S. Lim, “AC voltage and current sensorless control of iL(t2)(RL + Rg) h −pt00 −qt00 i three-phase PWM rectifiers,” IEEE Trans. Power Electron., vol. 17, no. 6, e − e + VmII1 pp. 883–890, Oct. 2002. RL(q − p)(CL + Cs)   2Rg −pt00 −qt00 − (p + q) e + e L  −pt00 −qt00   + e − e  (18)  2 2(q − p) 