Diode Bridge Rectifier with Improved Power Quality Using Capacitive Network Sagar Gupta Nimesh V, Vinod John Cypress Semiconductor Technology India Pvt. Ltd. Department of Electrical Engineering Karnataka, India Indian Institute of Science Bangalore, Karnataka, India Email: [email protected] Email: [email protected], [email protected] Abstract—Widely distributed single-phase power electronic rectifier loads are increasing source of harmonics in power distri- bution system. These harmonics have many well known adverse impacts on the power system. So it is necessary to improve the power quality of the rectifiers. This paper presents a novel single phase rectifier in which capacitors are used in parallel with diodes in one leg of the rectifier. A general analytical model of the proposed topology is obtained. The closed form expressions (a) (b) for the rectifier waveforms helps in parameter selection that leads to optimal performance in terms of input current THD. A comparative study of different topologies of rectifiers are done in terms of input voltage, current waveform distortion, output dc voltage ripple, and desired target for dc output voltage. The proposed topology reduces the total harmonic distortion from 145 percent in normal rectifier to 63 percent while maintaining voltage ripple less then 0.3 percent. The proposed topology keeps dc bus ripple small while simultaneously providing better THD. (c) The passive components considered for improving harmonic Fig. 1. Rectifier topologies (a) Diode rectifier with capacitive output filter injection are 2 small capacitors. The additional cost required (b) Voltage doubler rectifier (c) Split capacitor full bridge rectifier. for the proposed rectifier is low, the proposed rectifier also has a higher efficiency than the other commonly used topologies. TABLE I IEC 61000-3-2 HARMONIC LIMITS FOR CLASS C EQUIPMENTS FOR I. INTRODUCTION INPUT POWER < 25 W Non-linear loads such as controlled and uncontrolled, single Harmonic (n) Limit(% of the fundamental input current) phase and three phase rectifiers injects considerable amount of 3 86 lower order harmonics into the grid and distorts the voltage 5 61 at point of common coupling [1], [2]. Harmonics cause ex- cessive heating, pulsating and reduced torque in motors and generators, increased heating and voltage stresses in capacitor, voltage and input current[9]. So for lower power applications malfunction of switch gears and relays and reduces the life of PFE rectifier circuits, diode rectifier with capacitive filter, as products [3], [4]. It is therefore necessary to reduce harmonic shown in Fig. 1(a), and voltage doubler rectifier with two in electric power system. Also in case of dc loads it is split capacitances, as shown in Fig. 1(b), are preferred. It important to get low ripple in output dc voltage for its proper is well known that diode rectifier with capacitive filter, as functioning [5]. So it is necessary to provide dc output at shown in Fig. 1(a), has negligible output voltage ripple but low ripple keeping the harmonics injected in the line to a injects significant amount of lower order harmonics into the reasonable low value. grid. Voltage doubler, shown in Fig. 1(b), has low harmonic Passive Front End (PFE) rectifiers followed by Power Factor injection when Cs is kept small but ripple in output voltage Correction (PFC) stage, and Active Front End (AFE) rectifiers is considerably high. maintains dc bus voltage at desired level and harmonics According to IEC 61000-3-2, equipments are classified in injected, at switching frequency, can be filtered out using 4 categories, Class A, Class B, Class C and Class D. Lighting first order filters [6], [7], [8]. Using the above mentioned equipments, whose front end is a rectifier, falls into Class C topologies, for low power applications such as LED lighting, and harmonic standards for these equipments is summarized in increases the cost as it requires active switches such as MOS- Table I. In this paper a new Split Capacitor Full Bridge (SCFB) FET or IGBT and additional sensors, for controlling dc bus rectifier is proposed. The proposed SCFB rectifier shown in Fig. 1(c) is suited for low power applications. SCFB rectifier This work was supported by CPRI, Ministry of Power, Government of India, is a combination of diode rectifier with capacitive filter and under the project Power conversion, control, and protection technologies for microgrid. voltage doubler topology. Initial simulation studies comparing the three topologies shown in Fig. 1 is summarized in section 978-1-4673-8888-7/16/$31.00 © 2016 IEEE TABLE II VALES AND PARAMETERS CONSIDERED FOR THE STUDY (A)BASE positive half cycle of vg. Conducting elements of in each VALUES (B)RECTIFIER PARAMETERS mode is shown as dark black shade and the non-conducting elements are in light black shades, as shown in Fig. 2. The main assumptions for this analysis are: Parameter Base Value Vb 340 V Parameter Value(per unit) 1) Diodes are assumed ideal. Pb 25 W Vg 240 V (0.71) 2) ESR of the capacitances have been ignored. fb 50 Hz Po 25 W (1) 3) Ratio ∆ Vo=Vo 1. Ib 73.53 mA RL 5 kΩ (1.08) Zb 4624 Ω L 2 mH (136 µ) A. Mode-I from t1 < t < t2 Lb 14.7 H Rg 5 Ω (1.08 m) C 688.9 nF b (b) In Mode-I, during positive half cycle of the grid supply (a) diode D1 starts conducting, at t = t1. At t = t1, vc1(t1) = V1 = Vg(t1), vc2(t1) = V2 , iL(t1) = 0 and v0(t) = vc1(t) + vc2(t). The governing equations for circuit shown in Fig. 2(a) II. The analytical closed form expressions for waveforms are can be written as, covered in section III and Appendix. The equations for wave- Z diL 1 forms of SCFB rectifier that are derived in this paper are used vg(t) = iLRg + L + i1dt + V1 (1) dt Cs for circuit optimization. This leads to circuit parameters that 1 Z meet tight dc voltage ripple requirement while simultaneously v0(t) = iRRL = icdt + V1 + V2 (2) C having minimum input voltage distortion. Section IV details L analytical, simulation and experimental results. This section During this mode, upper split capacitor (vc1(t)) charges from also covers the effects of line inductance and load capacitance grid and lower split capacitor(vc2(t)) discharges into load and in optimal values split capacitor and THD of line current grid. This mode ends when either diode D1 stops conducting, drawn, section V concludes the paper. current drawn from grid goes to zero, or vc2(t) has fallen to zero. II. SIMULATION STUDIES B. Mode-II from t < t < t Initially simulations on all three topologies, shown in Fig. 1 2 3 was carried to check the performance of the proposed model. Mode-II starts at t2 when diode D2 starts conducting that Per unit values and design specifications of the converter used is vc2(t2) = 0 and D1 is already conducting. Let vc1(t2) = for simulation are given in Table II(a) and II(b) respectively. VmII1 and iL(t2) = IL0. Fig. 2(b) shows the equivalent circuit Po;Vg; fs = 50 Hz; RL Lg;Rg are rated power, grid and the equations for this mode can be written as, voltage rms, grid frequency, line impedance and load resis- di 1 Z v (t) = i R + L L + i dt + V tance, respectively. With line impedance neglected, effects g L g 1 mII1 (3) dt Cs of variations in values of load capacitance, CL, and split 1 Z capacitance, Cs, in grid current THD and ripple in output v0(t) = iRRL = icdt + VmII1 (4) CL voltage is studied. Summary of the results in tabulated in Table. III. It can be observed that the proposed SCFB topology As diode D2 is conducting, this ensures that the lower split has the advantages of both the normal rectifier with low capacitor does not charge in opposite direction, so vC2(t) in output voltage ripple, and voltage doubler circuit with lesser this mode will remain zero. This mode ends when diode D1 distortion in line current drawn. stops conducting, that is current drawn from the grid dies down to zero. III. ANALYSIS OF SCFB RECTIFIER C. Mode-III from t < t < t Fig. 2 shows the split capacitor full bridge (SCFB) rectifier 3 4 and its operating modes. The grid is modeled as a sinusoidal Mode-III occurs when the current iL reaches zero at the end of Mode-I with vc1(t2) and vc2(t2) > 0. In this case time voltage source vg in series with line impedance consisting of t3 equals to the instant t2 which is the end of Mode-I. In this Rg and L in series. The load is modeled as a resistor(RL). For modeling of the topology different modes of operation mode, no diodes are conducting, therefore the current from are identified and the governing equations of these modes the grid is zero and load is supplied by the energy stored in capacitors, C C . At t = t , let v (t ) = V and are covered in this section. The analysis is carried out for L s 3 C1 3 mIII1 TABLE III COMPARISON OF STANDARD RECTIFIER, VOLTAGE DOUBLER AND SCFB RECTIFIER WITH VARIATION OF Cs AND CL Topology 1(Normal Rectifier) Topology 2(Voltage Doubler) Topology 3 (SCFB Rectifier) Cs(µF)(pu) CL(µF)(pu) Vo(V)(pu) ∆V (V)(pu) THD(%) Vo(V)(pu) ∆V (V)(pu) THD(%) Vo(V)(pu) ∆V (V)(pu) THD(%) 222 (322.6) 222 (322.6) 338 (1.0) 2.9 (8.5 m) 357 72 (0.3) 104 (0.3) 4.6 339 (1.0) 3.5 (0.01) 338 470 (666.7) 470 (666.7) 339 (1.0) 1.4 (4.1 m) 386 137 (0.4) 178 (0.5) 8.1 310 (1.0) 2.0 (5.9 m) 341 1000 (1.5 k) 1000 (1428.6) 340 (1.0) 0.8 (7.5 m) 394 224 (0.7) 235 (0.7) 20 340 (1.0) 1.4 (4.1 m) 263 2000 (3.3 k) 2000 (29.1) 340 (1.0) 0.3 (0.9 m) 395 313 (1.0) 230 (0.7) 33 340 (1.0) 1.6 (4.7m) 65 2x106 (3.3 M) 222 (322.6) 338 (1.0) 2.9 (8.5 m) 357 679 (2.0) 1.4 (4.0 m) 438 679 (2.0) 1.3 (3.8 m) 458 (a) (b) (c) (d) Fig.