(19) United States (12) Patent Application Publication (10) Pub

US 20080301364A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2008/0301364 A1 Lauterbach et al. (43) Pub. Date: Dec. 4, 2008

(54) CACHING OF MICROCODE EMULATION Publication Classi?cation MEMORY (51) Int. Cl. G06F 12/00 (2006.01) (76) Inventors: Gary Lauterbach’ L05 Altos’ CA (52) US. Cl...... 711/113; 711/E12.001 (US); Bruce R. Holloway, Boulder (57) ABSTRACT Creek, CA (U S); Michael Gerard _ _ _ _ Butler San Jose CA (Us). Sean A processor mcludes a cache hierarchy including a level-1 Lie Sa’ma Clara ’CA (Us) ’ cache and a higher-level cache. The processor maps a portion ’ ’ of physical memory space to a portion of the higher-level cache, executes instructions, at least some of Which comprise Correspondence Address; microcode, alloWs microcode to access the portion of the MEYERTONS, HOOD, KIVLIN, KOWERT & higher-level cache, and prevents instructions that do not com GOETZEL (AMD) prise microcode from accessing the portion of the higher P_()_ BOX 398 level cache. The ?rst portion of the physical memory space AUSTIN TX 78767_0398 (Us) can be permanently allocated for use by microcode. The ’ processor can move one or more cache lines of the ?rst portion of the higher-level cache from the higher-level cache (21) App1_ NO; 11/754,589 to a ?rst portion of the level-1 cache, alloW microcode to access the ?rst portion of the ?rst level-1 cache, and prevent instructions that do not comprise microcode from accessing (22) Filed: May 29, 2007 the ?rst portion of the ?rst level-1 cache.

100 i,

F ______I I | 167 | 161 f 163 165 l I = = I1", I L1 Data Cache 166 2 11 2 I V \ V E 7 L2 Data Cache I Memory I Execution 1? 162 Load/Store ‘P 164 I30 I E | Unit g Unit g 11 ' .— l | \V 172 Mlcrocode | | I Emulation I I 171 *6" Memory @ I | v | l 1 174 | | I | I L1 TLB @ I | ‘ ‘ | I >173 12mm | I| Core Q : | l l l | Processor m l |______Patent Application Publication Dec. 4, 2008 Sheet 1 0f 5 US 2008/0301364 A1

100 i,

FIG. 1 Patent Application Publication Dec. 4, 2008 Sheet 2 0f 5 US 2008/0301364 A1

/f Virtual Memory Address Space 210

E Physical Memory Address Space 220

[i L2 Cache Space 230 / E / / L1 Cache Space 240 a y \ m m \ 222 E 243 H 24_2 221 a w

FIG. 2 Patent Application Publication Dec. 4, 2008 Sheet 3 0f 5 US 2008/0301364 A1

Begin -- Memory Access Request 300

Microcode Access Check TLBs For 'ignal Detected? 31 Matching Entry @

Matching Matching No Allow Access To Entry Found In L1 Entry Found In L2 Translate Address m Microcode Emulation ‘ll-57w ‘ll-EVE Memory m

ddress ln Microco Emulation Memory? Move Cache Line From @ m

V V Refill- TLB & PreventM Access

" w Access Targeted Cache Line @ V

V nd -- Memory Access Request FIG. 3 Patent Application Publication Dec. 4, 2008 Sheet 4 0f 5 US 2008/0301364 A1

400 Begin -- Microcode Emulation Memory L1 Access

icrocode Emulation Memory Line Cached In

Yes Find Cache Line In L2 Cache @ v l

Fill L1 Cache Line From L2 Cache E

V Access Target Block in L1 Cache @

nd -- Microcode Emulation Memory L1 Access

FIG. 4 Patent Application Publication Dec. 4, 2008 Sheet 5 of 5 US 2008/0301364 A1

I Memory @

CACHING OF MICROCODE EMULATION processes While maintaining the advantages of caching the MEMORY microcode emulation memory.

BACKGROUND OF THE INVENTION SUMMARY OF THE INVENTION

[0001] 1. Field of the Invention [0007] Various embodiments of a processor, a computer [0002] This invention relates to microprocessors and, more system, and methods are disclosed. The processor includes a particularly, to emulation of complex instructions by micro cache hierarchy including at least a ?rst level-l cache and a higher-level cache. The processor is con?gured to map a ?rst code, and still more particularly, to caching of memory used portion of a physical memory space to a ?rst portion of the during such emulation. higher-level cache, execute instructions, at least some of [0003] 2. Description of the Related Art Which comprise microcode, alloW microcode to access the [0004] While it is desirable for microprocessors to maintain ?rst portion of the higher-level cache, and prevent instruc compatibility With a complex instruction set computer tions that do not comprise microcode from accessing the ?rst (CISC) architecture, other architectures offer improved portion of the higher-level cache. In one embodiment, the higher-level cache is a level-2 cache. In another embodiment, execution speed and performance. Microprocessor designers the ?rst portion of the physical memory space is permanently have attempted to achieve both CISC compatibility and high allocated for use by microcode. performance by emulating CISC instructions. For example, [0008] In a further embodiment, the processor is con?gured superscalar, reduced instruction set computer (RISC) archi to move one or more cache lines of the ?rst portion of the tectures may include microcode that performs CISC instruc higher-level cache from the higher-level cache to a ?rst por tion emulation. During the emulation process, microcode tion of the ?rst level-l cache. The processor is further con makes use of a scratchpad memory for saving intermediate ?gured to alloW microcode to access the ?rst portion of the values. To maintain high performance, it is desirable for a ?rst level-l cache and prevent instructions that do not com microprocessor’s microcode to be able to access the emula prise microcode from accessing the ?rst portion of the ?rst tion memory as quickly as possible. level-l cache. [0005] In addition, microprocessors commonly include [0009] In a still further embodiment, the processor is con ?gured to detect a microcode access signal. The processor is multiple memory caches, arranged hierarchically and shared further con?gured to prevent instructions from accessing the by multiple cores or execution units. A variety of caching ?rst portion of the physical memory space if the microcode architectures are used and include various combinations of access signal is not asserted and alloW instructions to access on-chip cache and off-chip cache. Memory operations that the ?rst portion of the physical memory space if the micro read data from cache or memory may be referred to more code access signal is asserted. succinctly herein as “loads”. Memory operations that Write [0010] In a still further embodiment, the processor includes data to cache or memory may be referred to more succinctly a translation lookaside buffer (TLB), Wherein to prevent herein as “stores”. A load or a store may target a particular instructions that do not comprise microcode from accessing cache line (or portion of a cache line) and include an address the ?rst portion of the physical memory space the processor is identifying the targeted line as Well as including data to be further con?gured to disalloW TLB re?lls to the ?rst portion loaded from or stored Within the cache line. Since cache of the physical memory space. accesses are faster than memory accesses, various caching techniques are used to increase the likelihood that data is BRIEF DESCRIPTION OF THE DRAWINGS located in a cache When a core or execution unit needs to access it, thereby improving execution speed. Consequently [0011] FIG. 1 is a generaliZed block diagram of one caching the microcode emulation memory offers the perfor embodiment of a computer system. mance advantage of the relatively faster access time of cache [0012] FIG. 2 illustrates one embodiment of a virtual memory compared to system memory. The shortest access memory and cache architecture. times are generally those associated With the loWest level of [0013] FIG. 3 illustrates one embodiment of a process for the cache hierarchy, commonly referred to as Ll-cache, or accessing a memory hierarchy including microcode emula simply Ll. Therefore, it is desirable to cache the microcode tion memory. emulation memory in L1 . Such performance advantages have [0014] FIG. 4 illustrates one embodiment of a process for often been reinforced by the permanent allocation of a portion accessing microcode emulation memory in a level-l cache. of L1 for microcode emulation memory. [0015] FIG. 5 is a block diagram of one embodiment ofa [0006] Of course, the performance advantages of using the computer system including a L2 data cache and microcode Ll-cache Would bene?t other processes as Well. Conse emulation memory coupled to a variety of system compo quently, it is desirable to make the Ll-cache as large as nents. possible to increase the availability of L1 -cache space for any [0016] While the invention is susceptible to various modi process. HoWever, increasing the siZe of L1 increases the cost ?cations and alternative forms, speci?c embodiments are and complexity of the microprocessor. Also, if the microcode shoWn by Way of example in the draWings and are herein emulation memory is permanently allocated in L1, this por described in detail. It should be understood, hoWever, that tion of L1 is not available to other processes. In order to draWings and detailed descriptions thereto are not intended to address the above concerns, What is needed is a Way to limit the invention to the particular form disclosed, but on the improve availability of space in a given siZe Ll-cache to all contrary, the invention is to cover all modi?cations, equiva US 2008/0301364 A1 Dec. 4, 2008

lents and alternatives falling Within the spirit and scope of the referred to as a TLB re?ll. Further details of the operation of present invention as de?ned by the appended claims. data caches 126 and 130 and TLBs 128 and 140 that account for and avoid corruption of microcode emulation memory DETAILED DESCRIPTION 135 are presented beloW. [0017] FIG. 1 is a generalized block diagram of one [0020] FIG. 2 illustrates one embodiment of a virtual embodiment of a computer system 100. In the illustrated memory and cache architecture that may be used With pro embodiment, processor 110 is shoWn coupled to a memory cessor 110. In the illustration, a virtual memory space 210 is 150. Memory 150 may include SDRAM, SRAM, ROM, shoWn, portions of Which are mapped to a physical memory DRAM and/or other conventional memory devices. Proces address space 220. Portions of physical memory address sor 110 includes a core 120, an L2 data cache 130, and an L2 space 220 are shoWn mapped to L2 cache space 230, portions translation lookaside buffer (TLB) 140. Core 120 includes an of Which are in turn mapped to L1 cache space 240. Each execution unit 122, a load/ store unit 124, an L1 data cache application that executes on processor 110 may employ a 126, and an L1 TLB 128. L2 data cache 130 includes a separate virtual memory address space. Virtual memory microcode emulation memory 135. In alternative embodi address space 210, as shoWn in FIG. 2, includes blocks 211 ments, processor 110 may include more than one core, each 215 that represent the portions of virtual memory that are core including a level-l data cache and each core sharing a mapped to physical memory address space 220 and are avail single level-2 data cache. In one alternative embodiment, Ll able to be accessed by an application at a given point in time. data cache 126 may be separate from core 120. In other Similarly, physical memory address space 220 includes alternative embodiments, additional cache levels may be blocks 221-224 that represent the portions of physical included in computer system 100, such as a level-3 cache, memory that are cached in L2 cache space 230. LikeWise, L2 either included in processor 110 or separate from processor cache space 230 includes blocks 231-233 that represent the 110. In these and other alternative embodiments, microcode portions of L2 cache that are cached in L1 cache space 240. emulation memory 135 may be included in any cache level More particularly, blocks 231, 232, and 233 of L2 cache space above level-l. A variety of other embodiments are also con 230 are mapped to blocks 242, 243, and 241 ofLl cache space templated. HoWever, for ease of understanding, the examples 240, respectively. In various embodiments, each block that folloW Will assume that space is permanently allocated in described above may represent one of a set of cache lines, a level-2 data cache for microcode emulation memory 135. blocks of a uniform siZe, a group of cache lines or blocks, or [0018] During operation, execution unit 122 may receive blocks of varying siZes. In alternative embodiments, any of the data portion of loads to be executed from load/ store unit virtual memory address space 210, physical memory address 124 via link 161 and convey the data portion of stores to space 220, L2 cache space 230, and L1 cache space 240 may load/store unit 124 via link 162. Load/store unit 124 may include more or feWer blocks than the number shoWn in FIG. receive the data portion of loads to be executed from L1 data 2 cache 126 via link 163 and convey the data portion of stores [0021] In one embodiment, block 221 may be reserved in to L1 data cache 126 via link 164. L1 data cache 126 may physical memory space 220 as microcode emulation memory. receive the data portion of loads from L2 data cache 130 via Further, block 231 of L2 cache space 230 may be permanently link 165 and convey the data portion of stores to L2 data cache reserved for caching the contents of microcode emulation 130 via link 166. L2 data cache 130 may receive the data memory. During operation, When processor 110 desires to portion of loads from and convey the data portion of stores to access microcode emulation memory, block 231 may be memory 150 via link 167. L1 TLB 128 is shoWn coupled to L1 cached in level 1 cache, such as in block 242, as shoWn in FIG. data cache 126 via link 171, to L2 data cache 130 via link 172, 2. HoWever, block 242 may not be permanently reserved for and to L2 TLB 140 via link 173. L2 TLB 140 is also shoWn the use of microcode emulation memory, as is block 231. The coupled to L2 data cache 130 via link 174. blocks that are cached in L1 may change from time to time, [0019] L1 data cache 126, L1 TLB 128, L2 data cache 130, depending on program execution. Accordingly, microcode and L2 TLB 140 may perform conventional address transla emulation memory may be evicted from L1 to L2, Where tion and caching functions. For example, Ll TLB 128 may block 231 is reserved for its use. In one embodiment, access cache mappings of virtual addresses to physical addresses. to microcode emulation memory by applications or processes When a memory access request occurs, Ll TLB 128 may be other than microcode may be prevented by disalloWing Ll checked to see if a mapping of the desired virtual address to a TLB re?lls involving block 221 of physical memory space. physical address is cached. Mappings cached in L1 TLB 128 [0022] FIG. 3 illustrates one embodiment of a process 300 may be used to determine if a desired cache line is present in for accessing a memory hierarchy including microcode emu L1 data cache 126. If a desired cache line is not present in L1 lation memory. A memory access may begin With a check for data cache 126, i.e., there is an L1 cache miss, L2 TLB 140 the presence of a microcode access signal (not shoWn) asso may be checked to see if a mapping of the desired virtual ciated With each instruction decoded by an execution unit address to a physical address is cached. Mappings cached in (decision block 310). For example, in one embodiment, a bit L2 TLB 140 may be used to determine if a desired cache line of each decoded instruction may be used as a microcode is present in L2 data cache 130. When a cache miss occurs in access signal. In an alternative embodiment, microcode L1 data cache 126, in order to make room for a neW entry, a instructions may have a special opcode that serves as a micro cache line may be evicted from L1 data cache 126 to L2 data code access signal and by Which they may be identi?ed as cache 130. A corresponding entry in L1 TLB 128 may be microcode. Any of a variety of alternative microcode access moved to L2 TLB 140. In order to make room for a neW entry signals may be conveyed from an execution unit to a cache in L2 data cache 130, it may be necessary to evict a cache line controller to indicate Whether or not an instruction is a micro from L2 data cache 130 to memory 150. A neW address code instruction. If a microcode access signal is detected, translation may be performed for the desired cache line and then access to the microcode emulation memory may be the result cached in L1 TLB 128, a process that may be alloWed (block 320) and the access is completed. US 2008/0301364 A1 Dec. 4, 2008

[0023] If the microcode access signal is not detected, pro reduced number of evicts 566. Level-2 data cache 560 may be cess 300 may proceed as folloWs. One or more TLBs may be further coupled to each level-l data cache 542. More speci? searched to ?nd an entry matching the cache line targeted by cally, level-2 data cache 560 may convey ?lls 562 to level-l the access (block 330). If a matching entry is found in an L1 data cache 542. Level-2 data cache 560 may also be bi TLB (decision block 340), then the targeted cache line may be directionally coupled to memory 530. accessed (block 390) and the access is completed. If a match [0027] During operation, core 540 may execute a stream of ing entry is not found in an L1 TLB but is found in an L2 TLB instructions that, When decoded, cause loads 586 from L1 (decision block 350), then the targeted cache line may be data cache 542 to load/store pipeline 546 and/or stores 580 moved from the L2 cache to the L1 cache (block 360), the from load/store pipeline 546 to store logic 544. The instruc targeted cache line may be accessed (block 390), and the tions executed by core 540 may include execution of micro access is completed. If a matching entry is not found in either code. When microcode execution requires access to a cache L1 or L2 cache, then an address translation may be performed line in microcode emulation memory 135, the targeted cache (block 370). If the result of the address translation produces a line may be accessed and, if necessary, moved from L2 data target address that is located in the microcode emulation cache 560 to L1 data cache 542 using the process described in memory (decision block 380), then the access may be pre FIG. 4 above. Once the targeted cache line is moved to L1 data vented (block 384) ending the access attempt. If the result of cache 542, it may be accessed via loads 586 and/or stores 580 the address translation produces a target address that is not and 584. located in the microcode emulation memory (decision block [0028] Although system 500, as shoWn, include tWo cores, 380), then a TLB re?ll may be performed (block 382), the in alternative embodiments more than tWo cores may be targeted cache line may be accessed (block 390), and the included and/ or each core may represent a cluster of execu access is completed. tion units. Additional level-2 caches may also be included in [0024] FIG. 4 illustrates one embodiment of a process 400 further alternative embodiments in Which more than tWo for accessing microcode emulation memory in a level-l cores are included. Further, although level-2 data cache 560 is cache. An access request targeted to microcode emulation shoWn coupled directly to memory 530 and memory 530 is memory may begin With a check to see if the targeted cache shoWn as off-processor memory, processor 510 may include a line is cached in an L1 cache (decision block 410). If so, memory controller and/ or on-processor memory. Altema access to the targeted cache line may be alloWed (block 420) tively, an off-processor memory controller may couple and the access is completed. If the targeted cache line is not level-2 data cache 560 to memory 530. A variety of processor cached in an L1 cache, then the reserved location of the core and memory con?gurations Will be apparent to one of targeted cache line in L2 cache may be obtained (block 430) ordinary skill in the art. The targeted cache line may then be moved from L2 cache to [0029] It is noted that the above-described embodiments L1 cache (block 440). Once the target cache line is moved to may comprise softWare. In such an embodiment, the program L1 cache, access may be alloWed (block 420) and the access instructions that implement the methods and/or mechanisms is completed. may be conveyed or stored on a computer accessible medium. [0025] Turning noW to FIG. 5 a block diagram of one Numerous types of media Which are con?gured to store pro embodiment of a computer system 500 including L2 data gram instructions are available and include hard disks, ?oppy cache 560 and microcode emulation memory 135 coupled to disks, CD-ROM, DVD, ?ash memory, Programmable ROMs a variety of system components is shoWn. In the depicted (PROM), random access memory (RAM), and various other system, processor 510 is shoWn coupled to peripherals 520 forms of volatile or non-volatile storage. Still other forms of and to a memory 530. Peripherals 520 may include any of a media con?gured to convey program instructions for access variety of devices such as netWork interfaces, timing circuits, by a computing device include terrestrial and non-terrestrial storage media, input/ output devices, etc. that may be found in communication links such as netWork, Wireless, and satellite a conventional computer system. Memory 530 may include links on Which electrical, electromagnetic, optical, or digital SDRAM, SRAM, ROM, DRAM and/or other conventional signals may be conveyed. Thus, various embodiments may memory devices. Processor 510 includes cores 540A and further include receiving, sending or storing instructions and/ 540B, Write coalescing cache 550, level-2 data cache 560, and or data implemented in accordance With the foregoing I/O interface 570. l/ O interface 570 may couple each of cores description upon a computer accessible medium. 540 to peripherals 520. Elements referred to herein by a [0030] Although the embodiments above have been reference numeral folloWed by a letter may be collectively described in considerable detail, numerous variations and referred to by the reference numeral alone. For example, modi?cations Will become apparent to those skilled in the art cores 540A and 540B may be referred to as cores 540 and an once the above disclosure is fully appreciated. It is intended unspeci?ed one of cores 540 may be referred to as a core 540. that the folloWing claims be interpreted to embrace all such variations and modi?cations. [0026] Each of cores 540 includes a level-l data cache 542, a store logic unit 544, and a load/store pipeline 546. Store What is claimed is: logic unit 544 (alternately referred to as “store unit”) may 1. A processor comprising: represent a portion of a load/ store unit, a separate logic unit, a cache hierarchy including at least a ?rst level-l cache and or a combination thereof. Store logic 544 is coupled to both a higher-level cache; level-l data cache 542 and Write coalescing cache 550 to Wherein the processor is con?gured to: enable core 540 to Write to either cache level. More speci? map a ?rst portion of a physical memory space to a ?rst cally, store logic 544 may convey stores 584 to level-l data portion of the higher-level cache; cache 542 and stores 582 to Write coalescing cache 550. Write execute instructions, at least some of Which comprise coalescing cache 550 may be further coupled to level-2 data microcode; cache 560 via ?lls 564 and evicts 566. Write coalescing cache alloW microcode to access the ?rst portion of the higher 550 may coalesce stores 582 With ?lls 564 to produce a level cache; and US 2008/0301364 A1 Dec. 4, 2008

prevent instructions that do not comprise microcode 9. A method comprising: from accessing the ?rst portion of the higher-level mapping a ?rst portion of a physical memory space to a ?rst cache. portion of the higher-level cache in a cache hierarchy of 2. The processor of claim 1, Wherein the higher-level cache a processor; is a level-2 cache. a ?rst processor core executing instructions, at least some 3. The processor of claim 1, Wherein the ?rst portion of the of Which comprise microcode; physical memory space is permanently allocated for use by the ?rst processor core alloWing microcode to access the microcode. ?rst portion of the higher-level cache; and 4. The processor of claim 1, Wherein the processor is fur the ?rst processor core preventing instructions that do not ther con?gured to: comprise microcode from accessing the ?rst portion of move one or more cache lines of the ?rst portion of the the higher-level cache. higher-level cache from the higher-level cache to a ?rst 10. The method of claim 9, Wherein the higher-level cache portion of the ?rst level-l cache; is a level-2 cache. alloW microcode to access the ?rst portion of the ?rst 11. The method of claim 9, further comprising perma level-l cache; and nently allocating the ?rst portion of the physical memory prevent instructions that do not comprise microcode from space for use by microcode. accessing the ?rst portion of the ?rst level-l cache. 12. The method of claim 9, further comprising: 5. The processor of claim 1, Wherein the processor is fur moving one or more cache lines of the ?rst portion of the ther con?gured to: higher-level cache from the higher-level cache to a ?rst detect a microcode access signal; portion of a ?rst level-l cache of the processor; prevent instructions from accessing the ?rst portion of the alloWing microcode to access the ?rst portion of the ?rst physical memory space if the microcode access signal is level-l cache; and not asserted; and preventing instructions that do not comprise microcode alloW instructions to access the ?rst portion of the physical from accessing the ?rst portion of the ?rst level-l cache. memory space if the microcode access signal is asserted. 13. The method of claim 9, further comprising: 6. The processor of claim 5, further comprising a transla tion lookaside buffer (TLB), Wherein to prevent instructions detecting a microcode access signal; that do not comprise microcode from accessing the ?rst por preventing instructions from accessing the ?rst portion of tion of the physical memory space the processor is further the physical memory space if the microcode access sig con?gured to disalloW TLB re?lls to the ?rst portion of the nal is not asserted; and physical memory space. alloWing instructions to access the ?rst portion of the 7. The processor of claim 1, further comprising at least a physical memory space if the microcode access signal is ?rst core and a second core, Wherein the second core is asserted. con?gured to: 14. The method of claim 13, Wherein preventing instruc map a second portion of the physical memory space to a tions from accessing the ?rst portion of the physical memory second portion of the higher-level cache; space if the microcode access signal is not asserted further execute instructions, at least some of Which comprise comprises disalloWing re?lls to the ?rst portion of the physi microcode; cal memory space from a translation lookaside buffer (TLB). alloW microcode to access the second portion of the higher 15. The method of claim 9, further comprising: level cache; and mapping a second portion of the physical memory space to prevent instructions that do not comprise microcode from a second portion of the higher-level cache; accessing the second portion of the higher-level cache. a second processor core executing instructions, at least 8. The processor of claim 7, Wherein the ?rst core includes some of Which comprise microcode; the ?rst level-l cache and the second core includes a second the second processor core alloWing microcode to access the level-l cache; second portion of the higher-level cache; and Wherein the ?rst core is further con?gured to: the second processor core preventing instructions that do move one or more cache lines that are mapped to the ?rst not comprise microcode from accessing the second por portion of the higher-level cache, from the higher tion of the higher-level cache. level cache to a portion of the ?rst level-l cache; 16. The method of claim 15, further comprising: alloW microcode to access the portion of the ?rst level-l moving one or more cache lines that are mapped to the ?rst cache; and portion of the higher-level cache, from the higher-level prevent instructions that do not comprise microcode cache to a portion of a ?rst level-l cache; from accessing the portion of the ?rst level-l cache; moving one or more cache lines that are mapped to the and second portion of the higher-level cache, from the Wherein the second core is further con?gured to: higher-level cache to a portion of a second level-l cache; move one or more cache lines that are mapped to the alloWing microcode to access the portion of the ?rst level-l second portion of the higher-level cache, from the cache and/ or the portion of the second level-l cache; higher-level cache to a portion of the second level-l preventing instructions that do not comprise microcode cache; from accessing the portion of the ?rst level-l cache; and alloW microcode to access the portion of the second preventing instructions that do not comprise microcode level-l cache; and from accessing the portion of the second level-l cache. prevent instructions that do not comprise microcode 17. A computer system comprising: from accessing the portion of the second level-l at least one processor coupled to a memory and one or more cache. peripheral devices; US 2008/0301364 A1 Dec. 4, 2008

wherein the at least one processor comprises a cache hier prevent instructions that do not comprise microcode from archy including at least a ?rst level-l cache and a higher accessing the ?rst portion of the ?rst level-l cache. level cache; 19. The computer system of claim 17, Wherein the at least Wherein the at least one processor is con?gured to: one processor is further con?gured to: map a ?rst portion of a physical memory space to a ?rst portion of the higher-level cache; detect a microcode access signal; execute instructions, at least some of Which comprise prevent instructions from accessing the ?rst portion of the microcode; physical memory space if the microcode access signal is alloW microcode to access the ?rst portion of the higher not asserted; and level cache; and alloW instructions to access the ?rst portion of the physical prevent instructions that do not comprise microcode memory space if the microcode access signal is asserted. from accessing the ?rst portion of the higher-level 20. The computer system of claim 17, Wherein the at least cache. one processor further comprises a translation lookaside buffer 18. The computer system of claim 17, Wherein the at least (TLB), Wherein to prevent instructions that do not comprise one processor is further con?gured to: microcode from accessing the ?rst portion of the physical move one or more cache lines of the ?rst portion of the memory space the at least one processor is further con?gured higher-level cache from the higher-level cache to a ?rst to disalloW TLB re?lls to the ?rst portion of the physical portion of the ?rst level-l cache; memory space. alloW microcode to access the ?rst portion of the ?rst level-l cache; and