A Performance Comparison of TCP/IP and MPI on FDDI, Fast Ethernet

Total Page:16

File Type:pdf, Size:1020Kb

A Performance Comparison of TCP/IP and MPI on FDDI, Fast Ethernet APerformance Comparison of TCPIP and MPI on FDDI Fast Ethernet and Ethernet Saurab Nog and David Kotz Department of Computer Science Dartmouth College Hanover NH saurabcsdartmouthedu dfkcsdartmouthedu Dartmouth Technical Rep ort PCSTR November Revised January Abstract Communication is a very imp ortant factor aecting distributed applications Getting a close handle on network p erformance b oth bandwidth and latency is thus crucial to un derstanding overall application p erformance Webenchmarked some of the metrics of net work p erformance using twosetsofexperiments namely roundtrip and datahose The tests were designed to measure a combination of network latency bandwidth and contention We rep eated the tests for two proto cols TCPIP and MPI and three networks Mbit FDDI Fib er Distributed Data Interface Mbit Fast Ethernet and Mbit Ethernet The p erformance results provided interesting insights into the b ehaviour of these networks under dierent load conditions and the software overheads asso ciated with an MPI imple mentation MPICH This do cument presents details ab out the exp eriments their results and our analysis of the p erformance Keywords Network Performance FDDI FastEthernet Ethernet MPI Revised January to emphasize our use of a particular MPI implementation MPICH Copyright 1995 by the authors INTRODUCTION Intro duction This do cument presents b enchmarking tests that measured and compared p erformance of TCPIP and MPI Message Passing Interface implementations on dierentnetworks and their results Wechose these proto cols TCPIP and MPI b ecause TCPIP Greater exibility and user control Higher p erformance Wide usage and supp ort MPI Programming ease A widely accepted standard for distributed computing applications Since our MPI implementation MPICH runs on top of P which in turn uses TCPIP a p erformance comparison of TCPIP and MPI givesagoodestimateoftheoverheads and advantages asso ciated with using the higher level abstraction of MPI as opp osed to TCPIP so ckets We also compared three dierentnetworks to understand the inherent hardware and soft ware limitations of our setup We rep eated the same set of exp eriments on Mbps FDDI Fib er Distributed Data Interface token ring Mbps Fast Ethernet Mbps Ethernet In most cases we crosschecked our results with results from the publicly available ttcp package The results seem to b e in very close agreement including the presence of spikes and other anomalies Setup Details We ran two dierent tests roundtrip and datahose on all six combinations of proto col TCPIP and MPI and network FDDI Fast Ethernet Ethernet Although our exp eri ments were not sp ecic to any implementation of the hardware or software standards the results were necessarily dep endent on the sp ecic implementations Other implementations mayhave dierent p erformance SETUP DETAILS Hardware Software The FDDI and Ethernet exp eriments used RSs running AIX at MHz The FDDI was an isolated network and the Ethernet exp eriments were run when the Ethernet was lightly loaded usually overnight The Fast Ethernet tests used Pentium based PCs with MB RAM running FreeBSD on an isolated network Both the RSs and PCs had MPICH version released July running on top of P Environment All the tests except those involving Ethernet were conducted in an isolated mo de For the Ethernet exp eriments we did not disconnect ourselves from the rest of the world so wewere careful to cho ose quiet times of the day for testing This minimized the risk of interference from external trac We rep eated the tests several times at least running a few thousand iterations of each test every time Wechose the b est values max for bandwidths and min for time as our nal result Thus our numb ers approximate b estcase p erformance results NODELAY option except the Fast Ethernet datahose All TCPIP tests used the TCP Normally the TCPIP proto col delays small packet transmission in the hop e of gaining advantage by coalescing a large numb er of small packets This delay results in articially high latency times for small packets We used TCP NODELAYtoovercome this b ehaviour and eliminate the wait p erio d We also set b oth the sending and receiving side kernel buers at K bytes maximum allowed on the RSs FreeBSD Pentiums allowupto K The increased buers were prompted by the observation thatkernel buers are the b ottlenecks for most network op erations For MPI we used the default conguration in all cases Performance Measures In these tests wewere interested in the following measures of network p erformance Total Bandwidth the sum of the individual bandwidths of concurrent pro cesses It signies the eective bandwidth usage for the set of all participating hosts BandwidthPair of pro cesses the average bandwidth each individual pair of pro cesses was able to use Timeiteration the average time it takes to complete one iteration of roundtrip or datahose FreeBSD often crashed when o o ded with small messages ROUNDTRIP Roundtrip The roundtrip test is designed to measure the following parameters network latency network contention overhead synchronization overheads All machines were connected to the same network but were paired for communication pur p oses Each host talks to its designated partner only There is a masterslave relationship between the two pro cess in each pair The master initiates the communication and then measures the time interval it takes for the slave to receive and send the message back This completes one roundtrip iteration Our test do es many roundtrip iterations in a burst to determine the average timeiteration and the network bandwidth achieved Many iterations are necessary to overcome clo ckgranularity cold cache eects and accuracy problems All pro cesses synchronize b efore switching to the next message size This serves twomajor purp oses Each message size is timed separately restricting timing and other errors to the phase in which they o ccured Synchronization prevents pro cesses from running ahead or lagging b ehind the group Roundtrip is a store and forward test Eachslave pro cess receives the complete message from its master and then sends it back Since at anygiven time only pro cess in a pair is writing data to the network there is no contention b etween the master and slave pro cesses of a pair We ran roundtrip on and pairs up to pairs on FreeBSD of pro cessors simulta neously to determine howcontention inuences network p erformance Results for various combinations of network and proto col are presented in the following graphs ROUNDTRIP The pseudoco de for roundtrip is as follows for all interesting message sizes set messagesize synchronize all master and slave processes if master I am the master starttiming Initialize timer do a large number of iterations foriterationcountiterationcountMAXITERATIONSiterationcount Initiate communication with slave writeslavemessagemessagesize Wait for reply from slave read slavebuffermessagesize stoptiming Stop timer else I am the slave do a large number of iterations foriterationcountiterationcountMAXITERATIONSiterationcount Wait for the master to initiate communication read masterbuffermessagesize Reply back to the master with the same message writemasterbuffermessagesize End ifelse End for ROUNDTRIP 100 ’roundtrip-tcp-fddi-4-totalbw’ ’roundtrip-tcp-fddi-3-totalbw’ ’roundtrip-tcp-fddi-2-totalbw’ 80 ’roundtrip-tcp-fddi-1-totalbw’ 60 40 Bandwidth (Mbits/sec) 20 0 1 10 100 1000 10000 100000 1e+06 1e+07 Message Size (bytes) Figure Roundtrip TCPIP FDDI Total Bandwidth 60 ’roundtrip-tcp-fddi-4-bw’ ’roundtrip-tcp-fddi-3-bw’ ’roundtrip-tcp-fddi-2-bw’ 50 ’roundtrip-tcp-fddi-1-bw’ 40 30 Bandwidth (Mbits/sec) 20 10 0 1 10 100 1000 10000 100000 1e+06 1e+07 Message Size (bytes) Figure Roundtrip TCPIP FDDI Bandwidth p er Pair of Pro cesses MasterSlave 1e+06 ’roundtrip-tcp-fddi-4-time’ ’roundtrip-tcp-fddi-3-time’ ’roundtrip-tcp-fddi-2-time’ ’roundtrip-tcp-fddi-1-time’ 100000 Averageg Time (micro-sec) 10000 1000 1 10 100 1000 10000 100000 1e+06 1e+07 Message Size (bytes) Figure Roundtrip TCPIP FDDI Time p er Iteration ROUNDTRIP 100 ’roundtrip-mpi-fddi-4-totalbw’ ’roundtrip-mpi-fddi-3-totalbw’ ’roundtrip-mpi-fddi-2-totalbw’ 80 ’roundtrip-mpi-fddi-1-totalbw’ 60 40 Bandwidth (Mbits/sec) 20 0 1 10 100 1000 10000 100000 1e+06 1e+07 Message Size (bytes) Figure Roundtrip MPI FDDI Total Bandwidth 60 ’roundtrip-mpi-fddi-4-bw’ ’roundtrip-mpi-fddi-3-bw’ ’roundtrip-mpi-fddi-2-bw’ 50 ’roundtrip-mpi-fddi-1-bw’ 40 30 Bandwidth (Mbits/sec) 20 10 0 1 10 100 1000 10000 100000 1e+06 1e+07 Message Size (bytes) Figure Roundtrip MPI FDDI Bandwidth p er Pair of Pro cesses MasterSlave 1e+06 ’roundtrip-mpi-fddi-4-time’ ’roundtrip-mpi-fddi-3-time’ ’roundtrip-mpi-fddi-2-time’ ’roundtrip-mpi-fddi-1-time’ 100000 Averageg Time (micro-sec) 10000 1000 1 10 100 1000 10000 100000 1e+06 1e+07 Message Size (bytes) Figure Roundtrip MPI FDDI Time p er Iteration ROUNDTRIP 100 ’roundtrip-tcp-fast-3-totalbw’ ’roundtrip-tcp-fast-2-totalbw’ ’roundtrip-tcp-fast-1-totalbw’ 80 60 40 Bandwidth (Mbits/sec) 20 0 1 10 100 1000 10000 100000 1e+06 1e+07 Message Size (bytes) Figure Roundtrip TCPIP Fast Ethernet Total Bandwidth 60 ’roundtrip-tcp-fast-3-bw’ ’roundtrip-tcp-fast-2-bw’ ’roundtrip-tcp-fast-1-bw’ 50 40 30 Bandwidth (Mbits/sec) 20 10 0 1 10 100 1000 10000 100000 1e+06 1e+07 Message Size (bytes) Figure Roundtrip TCPIP Fast Ethernet Bandwidth p er Pair of Pro cesses MasterSlave 1e+06 ’roundtrip-tcp-fast-3-time’ ’roundtrip-tcp-fast-2-time’
Recommended publications
  • Designing an Ultra Low-Overhead Multithreading Runtime for Nim
    Designing an ultra low-overhead multithreading runtime for Nim Mamy Ratsimbazafy Weave [email protected] https://github.com/mratsim/weave Hello! I am Mamy Ratsimbazafy During the day blockchain/Ethereum 2 developer (in Nim) During the night, deep learning and numerical computing developer (in Nim) and data scientist (in Python) You can contact me at [email protected] Github: mratsim Twitter: m_ratsim 2 Where did this talk came from? ◇ 3 years ago: started writing a tensor library in Nim. ◇ 2 threading APIs at the time: OpenMP and simple threadpool ◇ 1 year ago: complete refactoring of the internals 3 Agenda ◇ Understanding the design space ◇ Hardware and software multithreading: definitions and use-cases ◇ Parallel APIs ◇ Sources of overhead and runtime design ◇ Minimum viable runtime plan in a weekend 4 Understanding the 1 design space Concurrency vs parallelism, latency vs throughput Cooperative vs preemptive, IO vs CPU 5 Parallelism is not 6 concurrency Kernel threading 7 models 1:1 Threading 1 application thread -> 1 hardware thread N:1 Threading N application threads -> 1 hardware thread M:N Threading M application threads -> N hardware threads The same distinctions can be done at a multithreaded language or multithreading runtime level. 8 The problem How to schedule M tasks on N hardware threads? Latency vs 9 Throughput - Do we want to do all the work in a minimal amount of time? - Numerical computing - Machine learning - ... - Do we want to be fair? - Clients-server - Video decoding - ... Cooperative vs 10 Preemptive Cooperative multithreading:
    [Show full text]
  • Fiber Context As a first-Class Object
    Document number: P0876R6 Date: 2019-06-17 Author: Oliver Kowalke ([email protected]) Nat Goodspeed ([email protected]) Audience: SG1 fiber_context - fibers without scheduler Revision History . .1 abstract . .2 control transfer mechanism . .2 std::fiber_context as a first-class object . .3 encapsulating the stack . .4 invalidation at resumption . .4 problem: avoiding non-const global variables and undefined behaviour . .5 solution: avoiding non-const global variables and undefined behaviour . .6 inject function into suspended fiber . 11 passing data between fibers . 12 termination . 13 exceptions . 16 std::fiber_context as building block for higher-level frameworks . 16 interaction with STL algorithms . 18 possible implementation strategies . 19 fiber switch on architectures with register window . 20 how fast is a fiber switch . 20 interaction with accelerators . 20 multi-threading environment . 21 acknowledgments . 21 API ................................................................ 22 33.7 Cooperative User-Mode Threads . 22 33.7.1 General . 22 33.7.2 Empty vs. Non-Empty . 22 33.7.3 Explicit Fiber vs. Implicit Fiber . 22 33.7.4 Implicit Top-Level Function . 22 33.7.5 Header <experimental/fiber_context> synopsis . 23 33.7.6 Class fiber_context . 23 33.7.7 Function unwind_fiber() . 27 references . 29 Revision History This document supersedes P0876R5. Changes since P0876R5: • std::unwind_exception removed: stack unwinding must be performed by platform facilities. • fiber_context::can_resume_from_any_thread() renamed to can_resume_from_this_thread(). • fiber_context::valid() renamed to empty() with inverted sense. • Material has been added concerning the top-level wrapper logic governing each fiber. The change to unwinding fiber stacks using an anonymous foreign exception not catchable by C++ try / catch blocks is in response to deep discussions in Kona 2019 of the surprisingly numerous problems surfaced by using an ordinary C++ exception for that purpose.
    [Show full text]
  • Fiber-Based Architecture for NFV Cloud Databases
    Fiber-based Architecture for NFV Cloud Databases Vaidas Gasiunas, David Dominguez-Sal, Ralph Acker, Aharon Avitzur, Ilan Bronshtein, Rushan Chen, Eli Ginot, Norbert Martinez-Bazan, Michael Muller,¨ Alexander Nozdrin, Weijie Ou, Nir Pachter, Dima Sivov, Eliezer Levy Huawei Technologies, Gauss Database Labs, European Research Institute fvaidas.gasiunas,david.dominguez1,fi[email protected] ABSTRACT to a specific workload, as well as to change this alloca- The telco industry is gradually shifting from using mono- tion on demand. Elasticity is especially attractive to op- lithic software packages deployed on custom hardware to erators who are very conscious about Total Cost of Own- using modular virtualized software functions deployed on ership (TCO). NFV meets databases (DBs) in more than cloudified data centers using commodity hardware. This a single aspect [20, 30]. First, the NFV concepts of modu- transformation is referred to as Network Function Virtual- lar software functions accelerate the separation of function ization (NFV). The scalability of the databases (DBs) un- (business logic) and state (data) in the design and imple- derlying the virtual network functions is the cornerstone for mentation of network functions (NFs). This in turn enables reaping the benefits from the NFV transformation. This independent scalability of the DB component, and under- paper presents an industrial experience of applying shared- lines its importance in providing elastic state repositories nothing techniques in order to achieve the scalability of a DB for various NFs. In principle, the NFV-ready DBs that are in an NFV setup. The special combination of requirements relevant to our discussion are sophisticated main-memory in NFV DBs are not easily met with conventional execution key-value (KV) stores with stringent high availability (HA) models.
    [Show full text]
  • A Thread Performance Comparison: Windows NT and Solaris on a Symmetric Multiprocessor
    The following paper was originally published in the Proceedings of the 2nd USENIX Windows NT Symposium Seattle, Washington, August 3–4, 1998 A Thread Performance Comparison: Windows NT and Solaris on A Symmetric Multiprocessor Fabian Zabatta and Kevin Ying Brooklyn College and CUNY Graduate School For more information about USENIX Association contact: 1. Phone: 510 528-8649 2. FAX: 510 548-5738 3. Email: [email protected] 4. WWW URL:http://www.usenix.org/ A Thread Performance Comparison: Windows NT and Solaris on A Symmetric Multiprocessor Fabian Zabatta and Kevin Ying Logic Based Systems Lab Brooklyn College and CUNY Graduate School Computer Science Department 2900 Bedford Avenue Brooklyn, New York 11210 {fabian, kevin}@sci.brooklyn.cuny.edu Abstract Manufacturers now have the capability to build high performance multiprocessor machines with common CPU CPU CPU CPU cache cache cache cache PC components. This has created a new market of low cost multiprocessor machines. However, these machines are handicapped unless they have an oper- Bus ating system that can take advantage of their under- lying architectures. Presented is a comparison of Shared Memory I/O two such operating systems, Windows NT and So- laris. By focusing on their implementation of Figure 1: A basic symmetric multiprocessor architecture. threads, we show each system's ability to exploit multiprocessors. We report our results and inter- pretations of several experiments that were used to compare the performance of each system. What 1.1 Symmetric Multiprocessing emerges is a discussion on the performance impact of each implementation and its significance on vari- Symmetric multiprocessing (SMP) is the primary ous types of applications.
    [Show full text]
  • Concurrent Cilk: Lazy Promotion from Tasks to Threads in C/C++
    Concurrent Cilk: Lazy Promotion from Tasks to Threads in C/C++ Christopher S. Zakian, Timothy A. K. Zakian Abhishek Kulkarni, Buddhika Chamith, and Ryan R. Newton Indiana University - Bloomington, fczakian, tzakian, adkulkar, budkahaw, [email protected] Abstract. Library and language support for scheduling non-blocking tasks has greatly improved, as have lightweight (user) threading packages. How- ever, there is a significant gap between the two developments. In previous work|and in today's software packages|lightweight thread creation incurs much larger overheads than tasking libraries, even on tasks that end up never blocking. This limitation can be removed. To that end, we describe an extension to the Intel Cilk Plus runtime system, Concurrent Cilk, where tasks are lazily promoted to threads. Concurrent Cilk removes the overhead of thread creation on threads which end up calling no blocking operations, and is the first system to do so for C/C++ with legacy support (standard calling conventions and stack representations). We demonstrate that Concurrent Cilk adds negligible overhead to existing Cilk programs, while its promoted threads remain more efficient than OS threads in terms of context-switch overhead and blocking communication. Further, it enables development of blocking data structures that create non-fork-join dependence graphs|which can expose more parallelism, and better supports data-driven computations waiting on results from remote devices. 1 Introduction Both task-parallelism [1, 11, 13, 15] and lightweight threading [20] libraries have become popular for different kinds of applications. The key difference between a task and a thread is that threads may block|for example when performing IO|and then resume again.
    [Show full text]
  • The Impact of Process Placement and Oversubscription on Application Performance: a Case Study for Exascale Computing
    Takustraße 7 Konrad-Zuse-Zentrum D-14195 Berlin-Dahlem fur¨ Informationstechnik Berlin Germany FLORIAN WENDE,THOMAS STEINKE,ALEXANDER REINEFELD The Impact of Process Placement and Oversubscription on Application Performance: A Case Study for Exascale Computing ZIB-Report 15-05 (January 2015) Herausgegeben vom Konrad-Zuse-Zentrum fur¨ Informationstechnik Berlin Takustraße 7 D-14195 Berlin-Dahlem Telefon: 030-84185-0 Telefax: 030-84185-125 e-mail: [email protected] URL: http://www.zib.de ZIB-Report (Print) ISSN 1438-0064 ZIB-Report (Internet) ISSN 2192-7782 The Impact of Process Placement and Oversubscription on Application Performance: A Case Study for Exascale Computing Florian Wende, Thomas Steinke, Alexander Reinefeld Abstract: With the growing number of hardware components and the increasing software complexity in the upcoming exascale computers, system failures will become the norm rather than an exception for long-running applications. Fault-tolerance can be achieved by the creation of checkpoints dur- ing the execution of a parallel program. Checkpoint/Restart (C/R) mechanisms allow for both task migration (even if there were no hardware faults) and restarting of tasks after the occurrence of hard- ware faults. Affected tasks are then migrated to other nodes which may result in unfortunate process placement and/or oversubscription of compute resources. In this paper we analyze the impact of unfortunate process placement and oversubscription of compute resources on the performance and scalability of two typical HPC application workloads, CP2K and MOM5. Results are given for a Cray XC30/40 with Aries dragonfly topology. Our results indicate that unfortunate process placement has only little negative impact while oversubscription substantially degrades the performance.
    [Show full text]
  • And Computer Systems I: Introduction Systems
    Welcome to Computer Team! Noah Singer Introduction Welcome to Computer Team! Units Computer and Computer Systems I: Introduction Systems Computer Parts Noah Singer Montgomery Blair High School Computer Team September 14, 2017 Overview Welcome to Computer Team! Noah Singer Introduction 1 Introduction Units Computer Systems 2 Units Computer Parts 3 Computer Systems 4 Computer Parts Welcome to Computer Team! Noah Singer Introduction Units Computer Systems Computer Parts Section 1: Introduction Computer Team Welcome to Computer Team! Computer Team is... Noah Singer A place to hang out and eat lunch every Thursday Introduction A cool discussion group for computer science Units Computer An award-winning competition programming group Systems A place for people to learn from each other Computer Parts Open to people of all experience levels Computer Team isn’t... A programming club A highly competitive environment A rigorous course that requires commitment Structure Welcome to Computer Team! Noah Singer Introduction Units Four units, each with five to ten lectures Computer Each lecture comes with notes that you can take home! Systems Computer Guided activities to help you understand more Parts difficult/technical concepts Special presentations and guest lectures on interesting topics Conventions Welcome to Computer Team! Noah Singer Vocabulary terms are marked in bold. Introduction Definition Units Computer Definitions are in boxes (along with theorems, etc.). Systems Computer Parts Important statements are highlighted in italics. Formulas are written
    [Show full text]
  • Enabling Technologies for Distributed and Cloud Computing Dr
    Enabling Technologies for Distributed and Cloud Computing Dr. Sanjay P. Ahuja, Ph.D. Fidelity National Financial Distinguished Professor of CIS School of Computing, UNF Technologies for Network-Based Systems Multi-core CPUs and Multithreading Technologies CPU’s today assume a multi-core architecture with dual, quad, six, or more processing cores. The clock rate increased from 10 MHz for Intel 286 to 4 GHz for Pentium 4 in 30 years. However, the clock rate reached its limit on CMOS chips due to power limitations. Clock speeds cannot continue to increase due to excessive heat generation and current leakage. Multi-core CPUs can handle multiple instruction threads. Technologies for Network-Based Systems Multi-core CPUs and Multithreading Technologies LI cache is private to each core, L2 cache is shared and L3 cache or DRAM is off the chip. Examples of multi-core CPUs include Intel i7, Xeon, AMD Opteron. Each core can also be multithreaded. E.g. the Niagara II has 8 cores with each core handling 8 threads for a total of 64 threads maximum. Technologies for Network-Based Systems Hyper-threading (HT) Technology A feature of certain Intel chips (such as Xeon, i7) that makes one physical core appear as two logical processors. On an operating system level, a single-core CPU with Hyper- Threading technology will be reported as two logical processors, dual-core CPU with HT is reported as four logical processors, and so on. HT adds a second set of general, control and special registers. The second set of registers allows the CPU to keep the state of both cores, and effortlessly switch between them by switching the register set.
    [Show full text]
  • Eindhoven University of Technology MASTER Acceleration of A
    Eindhoven University of Technology MASTER Acceleration of a geodesic fiber-tracking algorithm for diffusion tensor imaging using CUDA van Aart, E. Award date: 2010 Link to publication Disclaimer This document contains a student thesis (bachelor's or master's), as authored by a student at Eindhoven University of Technology. Student theses are made available in the TU/e repository upon obtaining the required degree. The grade received is not published on the document as presented in the repository. The required complexity or quality of research of student theses may vary by program, and the required minimum study period may vary in duration. General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain Acceleration of a Geodesic Fiber-Tracking Algorithm for Diffusion Tensor Imaging using CUDA Evert van Aart June 2010 Graduation Supervisor Dr. Andrei Jalba Eindhoven University of Technology Department of Mathematics and Computer Science Visualization group Committee Members Dr. Andrei Jalba Dr. Anna Vilanova Eindhoven University of Technology Department of Biomedical Engineering Biomedical Image Analysis group Dr. Bart Mesman Eindhoven University of Technology Department of Electrical Engineering Electronic Systems group Contents 1 Introduction 3 1.1 Problem Description .
    [Show full text]
  • HPX-Agseries
    Digital Fiber-Optic Sensors Easy operation and high performance for a variety of applications HPX-AG Series Dual display shows incoming light level and preset value side by side. High sensitivity and ultra long distance (1,200mm with the standard HPF-T003 thru scan fiber in high power mode) Three types of auto-tuning: 2-point, BGS and % EXPLANATION OF MAJOR FUNCTIONS AND FEATURES Easy-to-use design Auto-tuning button Function selection button Dual display panel Preset value Incoming light level The digital dual display panel indicates incoming light level and preset value side by side, so it is easy to check current scanning status while setting the sensor. The button layout is especially designed to ensure easy operation of gang-mounted sensors. Output indicator +Button -Button Easy operation Digital manual tuning With controls that are as easy to operate as a conventional potentiometer, and with easy-to-read digital display, settings can be changed directly in RUN mode. Less wiring, fewer man-hours The new models offer a choice between cable lead-out, M8 connector for fast installation, and reduced wiring models that receive power directly from adjacent gang-mounted units. Up to 16 units can be gang-mounted, with only the main unit wired to the power supply. M8 connector type Reduced wiring type Units are designed so that connecting cable is not required. There are no worries about wiring mishaps when mounting or dismounting. NEW Wiring with an M8 connector cable Add 1 sensor— save 2 wires! Up to 16 units can be combined. Since power is supplied through the gang-mounting connectors, only an output wire is required for the expansion units.
    [Show full text]
  • Fibers Are Not (P)Threads the Case for Loose Coupling of Asynchronous Programming Models and MPI Through Continuations
    Fibers are not (P)Threads The Case for Loose Coupling of Asynchronous Programming Models and MPI Through Continuations Joseph Schuchart Christoph Niethammer José Gracia [email protected] [email protected] [email protected] Höchstleistungsrechenzentrum Höchstleistungsrechenzentrum Höchstleistungsrechenzentrum Stuttgart (HLRS) Stuttgart (HLRS) Stuttgart (HLRS) Stuttgart, Germany Stuttgart, Germany Stuttgart, Germany ABSTRACT multi- and many-core systems by exposing all available concur- Asynchronous programming models (APM) are gaining more and rency to a runtime system. Applications are expressed in terms of more traction, allowing applications to expose the available concur- work-packages (tasks) with well-defined inputs and outputs, which rency to a runtime system tasked with coordinating the execution. guide the runtime scheduler in determining the correct execution While MPI has long provided support for multi-threaded commu- order of tasks. A wide range of task-based programming models nication and non-blocking operations, it falls short of adequately have been developed, ranging from node-local approaches such supporting APMs as correctly and efficiently handling MPI com- as OpenMP [40] and OmpSs [13] to distributed systems such as munication in different models is still a challenge. Meanwhile, new HPX [27], StarPU [3], DASH [49], and PaRSEC [7]. All of them have low-level implementations of light-weight, cooperatively scheduled in common that a set of tasks is scheduled for execution by a set of execution contexts (fibers, aka user-level threads (ULT)) are meant to worker threads based on constraints provided by the user, either in serve as a basis for higher-level APMs and their integration in MPI the form of dependencies or dataflow expressions.
    [Show full text]
  • Use of High Perfo Nce Networks and Supercomputers Ime Flight Simulation
    USE OF HIGH PERFO NCE NETWORKS AND SUPERCOMPUTERS IME FLIGHT SIMULATION Jeff I. Cleveland EE Project Engineer 3 National Aeronautics and Space Ad I Langley Research Center Nampton, Virginia 23681-0001 ABSTRACT In order to meet the stringent time-critical requirements for real-time man-in-the-loop flight simulation, computer processing operations must be consistent in processing time and be completed in as short a time as possible. These operations include simulation mathematical model computation and data inputloutput to the shulators. En 1986, in response to increased demands for flight simulation performance, NASA's Langley Research Center (LaRC), working with the contractor, developed extensions to the Computer Automated Measurement and Control (CAMAC) technology which resulted in a factor of ten increase in the effective bandwidlla and reduced latency of modules necessary for simulator communication. This technology extension is being used by more than 80 leading technological developers in the United States, Canada, and Europe. Included among the commercial applications are nuclear process control, power grid analysis, process monitoring, real-lime simulation, and radar data acquisition. Personnel at LaRC are completing the development of the use of supercomputers for mathematical model computation to support real-time flight simulation. This includes the development of a real-time operating system and development of specialized software and hardwxe for the simulator network. This paper describes the data acquisition technology and the development of supek-eompu~ng for flight simulation. INTRODUCTION NASA's Langley Research Center (LaRC) has used real-time flight simulation to support aerodynmic, space, and hardware research for over forty years.
    [Show full text]