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Design of Digital FMCW Chirp Synthesizer Plls Using Continuous-Time Delta-Sigma Time-To-Digital Converters

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Design of Digital FMCW Chirp Synthesizer Plls Using Continuous-Time Delta-Sigma Time-To-Digital Converters Design of Digital FMCW Chirp Synthesizer PLLs Using Continuous-Time Delta-Sigma Time-to-Digital Converters by Daniel J. Weyer A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Electrical Engineering) in the University of Michigan 2018 Doctoral Committee: Professor Michael P. Flynn, Chair Professor Zhong He Associate Professor David D. Wentzloff Associate Professor Zhengya Zhang Daniel J. Weyer [email protected] ORCID iD: 0000-0002-8355-9402 © Daniel J. Weyer 2018 TABLE OF CONTENTS LIST OF FIGURES ..................................................................................................................v LIST OF TABLES .................................................................................................................. ix ABSTRACT...............................................................................................................................x CHAPTER 1 Introduction ........................................................................................................1 1.1 FMCW Radar ............................................................................................................1 1.2 PLL Design for FMCW Chirp Synthesis ....................................................................5 1.3 Research Contributions ..............................................................................................7 1.4 Outline of the Dissertation .........................................................................................9 CHAPTER 2 Review and Background Information ............................................................. 10 2.1 Overview of Phase Locked Loops ............................................................................ 10 2.1.1 Fundamental PLL Architecture and Operation ........................................... 10 2.1.2 Integer-N and Fractional-N PLLs .............................................................. 12 2.1.3 Analog and Digital PLLs ........................................................................... 13 2.2 Conventional TDC Design ....................................................................................... 16 2.3 State-of-the-Art High-Frequency and Chirp Synthesizer PLLs ................................. 18 ii CHAPTER 3 Analysis of PLL Bandwidth and Chirp Linearity for PLL-based FMCW Chirp Synthesis ....................................................................................................................... 19 3.1 PLL Bandwidth Optimization .................................................................................. 19 3.2 Model and Simulation Setup .................................................................................... 20 3.3 Approach for Result Evaluation ............................................................................... 23 3.4 Generation of Slow Chirps ....................................................................................... 25 3.5 Generation of Fast Chirps ........................................................................................ 28 CHAPTER 4 A 20GHz Digital 25-Segment Chirp Synthesizer using a Third-Order Noise- Shaping TDC ........................................................................................................................... 32 4.1 Application Background .......................................................................................... 32 4.2 Implementation of Noise-Shaping TDC ................................................................... 35 4.3 Synthesizer Architecture .......................................................................................... 37 4.4 Measurement Results ............................................................................................... 39 4.4.1 Synthesizer Measurements ........................................................................ 40 4.4.2 Radar Testbed ........................................................................................... 42 4.5 Conclusion ............................................................................................................... 46 CHAPTER 5 A 38GHz Digital Fractional-N FMCW Chirp Synthesizer PLL with a Continuous-Time Bandpass TDC ..................................................................................... 47 5.1 ADC-based Time-to-Digital Conversion in PLLs ..................................................... 48 5.2 PLL Reference Sampling and Phase Digitization ..................................................... 49 iii 5.2.1 Shortcomings of Direct ADC-based Phase Digitization ............................. 50 5.2.2 Reference Digitization with Digital Down-Conversion .............................. 51 5.3 Continuous-Time Bandpass Modulation ............................................................. 54 5.4 Bandpass TDC ................................................................................................... 56 5.5 Synthesizer Architecture .......................................................................................... 57 5.6 Feedback Divider Design ......................................................................................... 60 5.7 Circuit Implementation ............................................................................................ 64 5.7.1 Bandpass Modulator ............................................................................ 64 5.7.2 Voltage-Controlled Oscillator .................................................................... 66 5.7.3 High-Speed Divider Stages ........................................................................ 67 5.7.4 Pipelined Phase Interpolator ...................................................................... 68 5.8 Measurement Results ............................................................................................... 70 5.8.1 TDC Measurements ................................................................................... 71 5.8.2 Synthesizer Measurements ........................................................................ 74 5.9 Conclusion ............................................................................................................... 79 CHAPTER 6 Conclusion and Future Work .......................................................................... 80 BIBLIOGRAPHY ................................................................................................................... 83 iv LIST OF FIGURES Figure 1.1. FMCW radar waveforms for a triangular waveform profile .......................................3 Figure 1.2. Block schematic of an FMCW radar system ..............................................................4 Figure 1.3. Chirp generation based on feedback modulation in a fractional-N PLL ......................6 Figure 1.4. Effect of lower close-in phase noise and faster chirps on detection reliability ............6 Figure 2.1. Basic PLL architecture with core components ......................................................... 11 Figure 2.2. Conventional analog fractional-N PLL .................................................................... 14 Figure 2.3. Digital fractional-N PLL architecture ...................................................................... 15 Figure 2.4. Delay-line time-to-digital converter ......................................................................... 16 Figure 3.1. Phase-domain PLL model........................................................................................ 21 Figure 3.2. Bode plot of loop gain for a 1MHz loop bandwidth ................................................. 21 Figure 3.3. Phase/Frequency model of an FMCW chirp synthesizer PLL................................... 22 Figure 3.4. Model of an FMCW radar system with chirp synthesizer model .............................. 22 Figure 3.5. Simulated synthesizer output waveforms for too small PLL bandwidth (a), optimized PLL bandwidth (b), and too large PLL bandwidth (c) ................................................................ 24 Figure 3.6. FFT spectra for BWPLL = 1MHz, T = 2ms, R = 100m, v = 0km/h, and stepping rates of 1.0MS/s (10bit resolution) (a) and 8.2MS/s (13bit resolution) (b) ......................................... 26 Figure 3.7. SFDR in FFT spectrum as a function of PLL bandwidth and chirp modulation resolution for T = 2ms ............................................................................................................... 27 Figure 3.8. PLL bandwidth vs. stepping rate characteristic for constant SFDRs and T = 2ms ..... 28 v Figure 3.9. Chirp non-linearity as a function of PLL bandwidth and modulation frequency for a modulation resolution of 12bit (a), 10bit (b), and 14bit (c) ........................................................ 29 Figure 3.10. Result accuracy in the modulation frequency vs. PLL bandwidth design plane for a 500MHz chirp bandwidth and R = 100m ................................................................................... 30 Figure 4.1. MAST 240GHz radar architecture ........................................................................... 33 Figure 4.2. Chirp profile of transmitter output for MAST radar ................................................. 34 Figure 4.3. Two-step architecture of noise-shaping TDC [4]...................................................... 36 Figure 4.4. Continuous-time 3rd-order feedback architecture of modulator [4] ...................... 37 Figure 4.5. Block schematic of the 20GHz chirp synthesizer ....................................................
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