DOCSLIB.ORG

Arm HPC Ecosystem Hardware, Software and Tools

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Arm HPC Ecosystem Hardware, Software and Tools Arm HPC Ecosystem Hardware, Software and tools Srinath Vadlamani, Field Application Engineer SEA, April 8, 2019 Arm Technology Already Connects the World Arm is ubiquitous Partnership is key Choice is good 21 billion chips sold by We design IP, not One size is not always the partners in 2017 alone manufacture chips best fit for all Mobile/Embedded/IoT/ Partners build products HPC is a great fit for Automotive/Server/GPUs for their target markets co-design and collaboration 2 © 2019 Arm Limited Armv8-A Architecture Evolution RISC architecture § Only have 32 bits available for encoding all instructions § Supports the development of efficient implementations 64-bit capable since 2012 § Known as AArch64 (or AArch32 when run in a 32-bit mode) § 128-bit vector unit (aka NEON Advanced SIMD) • AArch64 execution state • Atomic memory ops • Half-precision float • Pointer authentication • A64 instruction set • Type2 hypervisor support • RAS support • Nested virtualization 3 © 2019 Arm Limited • Statistical profiling • Complex float Arm business model Business Development Arm develops technology that is licensed to Arm licenses technology to Partner semiconductor companies. Technology Arm receives an SemiCo upfront license fee Partner License Fee and a royalty on every chip that contains its technology. Per-Chip Royalty Partner OEM develops Customer chips OEM sells consumer products 4 © 2019 Arm Limited CPU Engagement Models With Arm Core License Architecture License Partner licenses complete Partner designs complete CPU microarchitecture design microarchitecture from scratch § Wide choices available • Clean room – no reference to Arm § Many different A, R & M products core designs Standard CPU Proprietary CPU CPU differentiation through: Freedom to develop any design § Flexible configuration options • Must conform to the rules & § Wide implementation envelope with Core license Architecture license programmers model of a given different process technologies architecture variant • Must pass Arm architecture Range of licensing & engagement validation to preserve software models possible compatibility Long term strategic investment 5 © 2019 Arm Limited HPC on Arm – What’s new in 2018/19 Powerful hardware for now and future • Marvell ThunderX2 now GA • Fujitsu announced details of A64FX (with SVE) for Post-K • Arm announces Neoverse brand for infrastructure and core IP roadmap (Ares, Zeus, Poseidon) with each generation delivering 30% perf boost. N1 platform details announced. Mature toolchains and ISV Software • Three mature toolchains available –Arm Commercial, GNU and Cray CE • ISVs start porting to Arm – Altair RADIOSS, ANSYS Fluent and LS-DYNA Deployments • New deployments across the EU and USA • USA - Sandia Astra (Top 500), Comanche Clusters • EU – Catalyst and Isambard in UK, GENCI and Dibona (MontBlanc 3) in France 6 © 2019 Arm Limited Arm Hardware for Infrastrucutre (including HPC) AWS Graviton by Amazon 8 © 2019 Arm Limited AWS Graviton by Amazon 9 © 2019 Arm Limited Huawei unveils KunPeng 920 CPU and TaiShan Servers Industry’s Highest Performance 2.6GHz 64-cores 7nm based ARM v8 Server SoC & Servers Big Data, Distributed Storage and Arm-Native applications TaiShan 2280 Balanced Server TaiShan 5280/5290 Storage Server TaiShan X6000 High-Density Server “Use ARM-based CPU in areas like cloud and servers where they are better.” – William XU, Chief Strategy Marketing Officer, Huawei 10 © 2019 Arm Limited The Cloud to Edge Infrastructure Foundation for a World of 1T Intelligent Devices Broad SoC system design options within Arm Ecosystem Arm IP High performance CPUs Arm Architectural design Data plane CPUs CMN Fabric Custom Arm High performance CPU Other IP Custom Fabric & IP Accelerators ML, on-die FPGA Networking, security, encryption Video, Custom Memory DDR, HBM, Flash, Storage Class memory IO PCIe, CCIX, 100G+ ethernet Foundry TSMC 7FF, Samsung 7LPP, UMC Common Software Platform and Ecosystem Arm Architecture v8.x-A © 2018 Arm Limited Arm IP : Commitment to Infrastructure segment 5nm 7nm+ Poseidon Platform 7nm Zeus Platform 16nm Ares (N1) Cosmos Platform 2021 Platform 2020 (A72, A75)~30% per Gen Faster Performance & New Features 2019 Today 13 © 2019 Arm Limited Neoverse N1 platform Accelerating the transformation to a scalable cloud to edge infrastructure Revolutionary compute performance Platform features specific to infrastructure Extreme range of scale and diversity of compute 14 Confidential © 2018 Arm Limited Neoverse N1 platform: Revolutionary compute performance 2.5x NGINX 1.7x 2.5x Java* MemcacheD Improved cloud to edge TCO through revolutionary workload performance 15 Confidential © 2018 Arm Limited Data shown for Neoverse N1 has been collected/projected from an array of platforms, and relative to Cortex A72 ”Cosmos” *Based on an industry standard Java-based benchmark Arm Hardware for HPC Arm Architecture Partner SoC for HPC Available or Announced in 2018-19 17 © 2019 Arm Limited HPC Software Ecosystem Arm HPC Ecosystem – Overview Job schedulers HPC Applications: and Resource Open-source, Owned, and Commercial ISV codes User-space Management: utilities, scripting, SLURM, IBM LSF, App/ISA specific optimizations, optimized libs and intrinsics: container, and Altair PBS Pro, Arm PL, BLAS, FFTW, etc. other packages: etc. Singularity, HPEBright, CMU, Parallelism HPC Programming Debug and Filesystems: Openstack, Tools: Management Cluster standards: Languages: performance BeeGFS, OpenHPC, OpenMP Fortran, C, C++ analysis tools: LUSTRE, ZFS, Python, NumPy, (omp / gomp), via Arm Forge, SciPy, etc. MPI, SHMEM GNU, LLVM, Arm Rogue Wave, HDFS, GPFS (see below) & OEMs TAU, etc. xCat , Communication Stacks and run-times: Warewulf Silicon Suppliers: Mellanox IB/OFED/HPC-X, OpenMPI, MPICH, MVAPICH2, OpenSHMEM, OpenUCX, HPE MPI Marvell, Fujitsu, Mellanox Linux OS Distro of choice: RHEL, SUSE, CENTOS,… OEM/ODM’s: Cray, HPE, ATOS-Bull, Fujitsu, Gigabyte, Inventec, Foxconn Arm Server Ready Platform: Standard OS compatible FW and RAS features 19 © 2019 Arm Limited Common HPC applications now available GROMACS LAMMPS CESM2 MrBayes Bowtie NAMD AMBER Paraview SIESTA UM Quantum WRF VASP MILC GEANT4 ESPRESSO OpenFOAM GAMESS VisIT DL-Poly NEMO BLAST NWCHEM Abinit BWA QMCPACK Build recipes online at https://gitlab.com/arm-hpc/packages/wikis/home 20 © 2019 ArmChem Limited /Phys Weather CFD Visualization Genomics ISVs codes on Arm Porting underway Available 21 © 2019 Arm Limited : Typical HPC packages available for Arm Functional Areas Components include OpenHPC is a community effort to provide a common, Base OS CentOS 7.5, SLES 12 SP3 verified set of open source packages for HPC Administrative Conman, Ganglia, Lmod, LosF, Nagios, pdsh, pdsh- Tools mod-slurm, prun, EasyBuild, ClusterShell, mrsh, deployments Genders, Shine, test-suite Provisioning Warewulf Arm and partners actively involved: Resource Mgmt. SLURM, Munge • Arm is a silver member of OpenHPC I/O Services Lustre client (community version) • Numerical/Scientific Boost, GSL, FFTW, Metis, PETSc, Trilinos, Hypre, Linaro is on Technical Steering Committee Libraries SuperLU, SuperLU_Dist,Mumps, OpenBLAS, • Arm-based machines in the OpenHPC build Scalapack, SLEPc, PLASMA, ptScotch I/O Libraries HDF5 (pHDF5), NetCDF (including C++ and Fortran infrastructure interfaces), Adios Compiler Families GNU (gcc, g++, gfortran), LLVM Status: 1.3.6 release out now MPI Families OpenMPI, MPICH Development Tools Autotools (autoconf, automake, libtool), Cmake, • Packages built on Armv8-A for CentOS and SUSE Valgrind,R, SciPy/NumPy, hwloc Performance Tools PAPI, IMB, pdtoolkit, TAU, Scalasca, Score-P, SIONLib 22 © 2019 Arm Limited Arm HPC Ecosystem website: www.arm.com/hpc Starting point for developers and end-users of Arm for HPC Latest events, news, blogs, and collateral including whitepapers, webinars, and presentations Links to HPC open-source & commercial SW packages Guides for porting HPC applications Quick-start guides to Arm tools Links to community collaboration sites Curated and moderated by Arm 23 © 2019 Arm Limited Arm HPC Community: community.arm.com/tools/hpc/ HPC Community-driven Content Blogs By Arm and our HPC community Calendar of upcoming events such as workshops and weBinars HPC Forum with questions & posts curated and moderated By Arm HPC technical specialists Ask, answer, share progress and expertise 24 © 2019 Arm Limited Arm HPC Packages wiki www.gitlab.com/arm-hpc/packages/wikis • Dynamic list of common HPC packages • Status and porting recipes • Community driven • Anyone can join and contribute • Provides focus for porting progress • Allows developers to share and learn 25 © 2019 Arm Limited Open source libraries for helping increase performance Arm Optimized Routines Perf-libs-tools https://github.com/ARM-software/optimized-routines https://github.com/ARM-software/perf-libs-tools These routines provide high performing Understanding an application’s needs for versions of many math.h functions BLAS, LAPACK and FFT calls • Algorithmically better performance than • Used in conjunction with Arm Performance standard library calls Libraries can generate logging info to help profile • No loss of accuracy applications for specific case breakdowns SLEEF library https://github.com/shibatch/sleef/ Vectorized math.h functions • Provided as an option for use in Arm Compiler Example visualization: DGEMM cases called 26 © 2019 Arm Limited Arm HPC deployments Deployments 28 © 2019 Arm Limited Arm Supercomputer Makes Top500 List! “Astra, the world’s fastest Arm-based supercomputer according to the
Load more

Recommended publications
  • Forge and Performance Reports Modules $ Module Load Intel Intelmpi $ Module Use /P/Scratch/Share/VI-HPS/JURECA/Mf/ $ Module Load Arm-Forge Arm-Reports
    Acting on Insight Tips for developing and optimizing scientific applications [email protected] 28/06/2019 Agenda • Introduction • Maximize application efficiency • Analyze code performance • Profile multi-threaded codes • Optimize Python-based applications • Visualize code regions with Caliper 2 © 2019 Arm Limited Arm Technology Already Connects the World Arm is ubiquitous Partnership is key Choice is good 21 billion chips sold by We design IP, we do not One size is not always the best fit partners in 2017 manufacture chips for all #1 in Infrastructure today with Partners build products for HPC is a great fit for 28% market shares their target markets co-design and collaboration 3 © 2019 Arm Limited Arm’s solution for HPC application development and porting Combines cross-platform tools with Arm only tools for a comprehensive solution Cross-platform Tools Arm Architecture Tools FORGE C/C++ & FORTRAN DDT MAP COMPILER PERFORMANCE PERFORMANCE REPORTS LIBRARIES 4 © 2019 Arm Limited The billion dollar question in “weather and forecasting” Is it going to rain tomorrow? 1. Choose domain 2. Gather Data 3. Create Mesh 4. Match Data to Mesh 5. Simulate 6. Visualize 5 © 2019 Arm Limited Weather forecasting workflow Deploy Production Staging environment Builds Scalability Performance Develop Fix Regressions CI Agents Optimize Commit Continuous Version Start CI job control integration Pull system framework • 24 hour timeframe 6 © 2019 Arm Limited • 2 to 3 test runs for 1 production run Application efficiency Scientist Developer System admin Decision maker • Efficient use of allocation • Characterize application • Maximize resource usage • High-level view of system time behaviour • Diagnose performance workload • Higher result throughput • Gets hints on next issues • Reporting figures and optimization steps analysis to help decision making 7 © 2019 Arm Limited Arm Performance Reports Characterize and understand the performance of HPC application runs Gathers a rich set of data • Analyses metrics around CPU, memory, IO, hardware counters, etc.
    [Show full text]
  • Adaptive Data Migration in Load-Imbalanced HPC Applications
    Louisiana State University LSU Digital Commons LSU Doctoral Dissertations Graduate School 10-16-2020 Adaptive Data Migration in Load-Imbalanced HPC Applications Parsa Amini Louisiana State University and Agricultural and Mechanical College Follow this and additional works at: https://digitalcommons.lsu.edu/gradschool_dissertations Part of the Computer Sciences Commons Recommended Citation Amini, Parsa, "Adaptive Data Migration in Load-Imbalanced HPC Applications" (2020). LSU Doctoral Dissertations. 5370. https://digitalcommons.lsu.edu/gradschool_dissertations/5370 This Dissertation is brought to you for free and open access by the Graduate School at LSU Digital Commons. It has been accepted for inclusion in LSU Doctoral Dissertations by an authorized graduate school editor of LSU Digital Commons. For more information, please [email protected]. ADAPTIVE DATA MIGRATION IN LOAD-IMBALANCED HPC APPLICATIONS A Dissertation Submitted to the Graduate Faculty of the Louisiana State University and Agricultural and Mechanical College in partial fulfillment of the requirements for the degree of Doctor of Philosophy in The Department of Computer Science by Parsa Amini B.S., Shahed University, 2013 M.S., New Mexico State University, 2015 December 2020 Acknowledgments This effort has been possible, thanks to the involvement and assistance of numerous people. First and foremost, I thank my advisor, Dr. Hartmut Kaiser, who made this journey possible with their invaluable support, precise guidance, and generous sharing of expertise. It has been a great privilege and opportunity for me be your student, a part of the STE||AR group, and the HPX development effort. I would also like to thank my mentor and former advisor at New Mexico State University, Dr.
    [Show full text]
  • Fairborn Camera & Video
    © 2006 The Dayton Microcomputer Association, Inc. V O L UM E 3 1 , I S S U E 6 P A G E 1 TM Volume 31 Issue 6 www.DMA.org November 2006 Association of PC User Groups (APCUG) Member Location for October 31 General Meeting Topic meeting & map inside ... Parking Permits Fairborn Camera & Video Available … Mike Petros - Guest Speaker As the holidays approach, the search be- for prints. RAW format allows the option of gins for the hottest items for Christmas. We manipulating details with photo-editing soft- generally look for some high-tech gadget ware on a PC. It’s a good thing that memory that could make our lives easier, more pro- cards hold more data than ever before. ductive, or just plain fun. The latest in cam- Mike Petros, Store Manager at Fairborn era equipment has always been a favorite Camera & Video, has agreed to demonstrate and the choices this year are impressive. several of this year’s latest digital cameras There seem to be a half dozen models for and help make sense of their many features. every application. Credit-card sized “point Mike draws from 30 years of experience in and shoot” cameras fit easily in a pocket and the business. He often gives presentations to travel well. Those best suited for sports pho- local organizations and once wrote articles tography are the ones marked “single-lens- for the Midwest PC Review magazine. reflex”. They tend to be more responsive Although he would not give away any de- and accept interchangeable lenses. Cameras tails on the specials they will be running this of all sizes offer digital viewfinders.
    [Show full text]
  • Performance Tuning Workshop
    Performance Tuning Workshop Samuel Khuvis Scientifc Applications Engineer, OSC February 18, 2021 1/103 Workshop Set up I Workshop – set up account at my.osc.edu I If you already have an OSC account, sign in to my.osc.edu I Go to Project I Project access request I PROJECT CODE = PZS1010 I Reset your password I Slides are the workshop website: https://www.osc.edu/~skhuvis/opt21_spring 2/103 Outline I Introduction I Debugging I Hardware overview I Performance measurement and analysis I Help from the compiler I Code tuning/optimization I Parallel computing 3/103 Introduction 4/103 Workshop Philosophy I Aim for “reasonably good” performance I Discuss performance tuning techniques common to most HPC architectures I Compiler options I Code modifcation I Focus on serial performance I Reduce time spent accessing memory I Parallel processing I Multithreading I MPI 5/103 Hands-on Code During this workshop, we will be using a code based on the HPCCG miniapp from Mantevo. I Performs Conjugate Gradient (CG) method on a 3D chimney domain. I CG is an iterative algorithm to numerically approximate the solution to a system of linear equations. I Run code with srun -n <numprocs> ./test_HPCCG nx ny nz, where nx, ny, and nz are the number of nodes in the x, y, and z dimension on each processor. I Download with: wget go . osu .edu/perftuning21 t a r x f perftuning21 I Make sure that the following modules are loaded: intel/19.0.5 mvapich2/2.3.3 6/103 More important than Performance! I Correctness of results I Code readability/maintainability I Portability -
    [Show full text]
  • Performance Tuning Workshop
    Performance Tuning Workshop Samuel Khuvis Scientific Applications Engineer, OSC 1/89 Workshop Set up I Workshop – set up account at my.osc.edu I If you already have an OSC account, sign in to my.osc.edu I Go to Project I Project access request I PROJECT CODE = PZS0724 I Slides are on event page: osc.edu/events I Workshop website: https://www.osc.edu/˜skhuvis/opt19 2/89 Outline I Introduction I Debugging I Hardware overview I Performance measurement and analysis I Help from the compiler I Code tuning/optimization I Parallel computing 3/89 Introduction 4/89 Workshop Philosophy I Aim for “reasonably good” performance I Discuss performance tuning techniques common to most HPC architectures I Compiler options I Code modification I Focus on serial performance I Reduce time spent accessing memory I Parallel processing I Multithreading I MPI 5/89 Hands-on Code During this workshop, we will be using a code based on the HPCCG miniapp from Mantevo. I Performs Conjugate Gradient (CG) method on a 3D chimney domain. I CG is an iterative algorithm to numerically approximate the solution to a system of linear equations. I Run code with mpiexec -np <numprocs> ./test HPCCG nx ny nz, where nx, ny, and nz are the number of nodes in the x, y, and z dimension on each processor. I Download with git clone [email protected]:khuvis.1/performance2019 handson.git I Make sure that the following modules are loaded: intel/18.0.3 mvapich2/2.3 6/89 More important than Performance! I Correctness of results I Code readability/maintainability I Portability - future systems
    [Show full text]
  • Best Practice Guide Modern Processors
    Best Practice Guide Modern Processors Ole Widar Saastad, University of Oslo, Norway Kristina Kapanova, NCSA, Bulgaria Stoyan Markov, NCSA, Bulgaria Cristian Morales, BSC, Spain Anastasiia Shamakina, HLRS, Germany Nick Johnson, EPCC, United Kingdom Ezhilmathi Krishnasamy, University of Luxembourg, Luxembourg Sebastien Varrette, University of Luxembourg, Luxembourg Hayk Shoukourian (Editor), LRZ, Germany Updated 5-5-2021 1 Best Practice Guide Modern Processors Table of Contents 1. Introduction .............................................................................................................................. 4 2. ARM Processors ....................................................................................................................... 6 2.1. Architecture ................................................................................................................... 6 2.1.1. Kunpeng 920 ....................................................................................................... 6 2.1.2. ThunderX2 .......................................................................................................... 7 2.1.3. NUMA architecture .............................................................................................. 9 2.2. Programming Environment ............................................................................................... 9 2.2.1. Compilers ........................................................................................................... 9 2.2.2. Vendor performance libraries
    [Show full text]
  • Arm in HPC the Future of Supercomputing Starts Now
    Arm in HPC The future of supercomputing starts now Marcin Krzysztofik and Eric Lalardie Arm © 2018 Arm Limited Arm’s business model (HPC focus) Armv8.x and extensions, Neoverse IP roadmap SVE Scalable Vector Extension © 2018 Arm Limited The Cloud to Edge Infrastructure Foundation for a World of 1T Intelligent Devices © 2018 Arm Limited Each generation brings faster performance and new infrastructure specific features 5nm 7nm+ 7nm Poseidon 16nm Zeus Platform Neoverse Platform Cosmos N1 Platform Platform 2021 2020 2019 Today 30% Faster System Performance per Generation + New Features Limited Arm © 2018 © The embargo for this content presented at Arm Tech Day will lift on Wednesday, Feb 20th at 6 a.m. Pacific Time. Corresponding UK time is: Wednesday, Feb 20th 2 p.m. BST World-class Neoverse Ecosystem AMPERE Tencent Cloud orange © 2018 Arm Limited Vanguard Astra by HPE (Top 500 system) • 2,592 HPE Apollo 70 compute nodes • Mellanox IB EDR, ConnectX-5 • 5,184 CPUs, 145,152 cores, 2.3 PFLOPs (peak) • 112 36-port edges, 3 648-port spine switches • Cavium Thunder-X2 ARM SoC, 28 core, 2.0 GHz • Red Hat RHEL for Arm • Memory per node: 128 GB (16 x 8 GB DR DIMMs) • HPE Apollo 4520 All–flash Lustre storage • Aggregate capacity: 332 TB, 885 TB/s (peak) • Storage Capacity: 403 TB (usable) • Storage Bandwidth: 244 GB/s © 2018 Arm Limited Arm HPC Software Ecosystem Job schedulers HPC Applications: and Resource Open-source, Owned, and Commercial ISV codes User-space Management: utilities, scripting, SLURM, IBM LSF, App/ISA specific optimizations, optimized libs and intrinsics: containers, and Altair PBS Pro, etc.
    [Show full text]
  • Debugging and Performance Analysis of Heterogenous HPC Applications
    DOI: 10.14529/jsfi200105 Tools for GPU Computing – Debugging and Performance Analysis of Heterogenous HPC Applications Michael Knobloch1, Bernd Mohr1 c The Authors 2020. This paper is published with open access at SuperFri.org General purpose GPUs are now ubiquitous in high-end supercomputing. All but one (the Japanese Fugaku system, which is based on ARM processors) of the announced (pre-)exascale systems contain vast amounts of GPUs that deliver the majority of the performance of these systems. Thus, GPU programming will be a necessity for application developers using high-end HPC systems. However, programming GPUs efficiently is an even more daunting task than tra- ditional HPC application development. This becomes even more apparent for large-scale systems containing thousands of GPUs. Orchestrating all the resources of such a system imposes a tremen- dous challenge to developers. Luckily a rich ecosystem of tools exist to assist developers in every development step of a GPU application at all scales. In this paper we present an overview of these tools and discuss their capabilities. We start with an overview of different GPU programming models, from low-level with CUDA over pragma- based models like OpenACC to high-level approaches like Kokkos. We discuss their respective tool interfaces as the main method for tools to obtain information on the execution of a kernel on the GPU. The main focus of this paper is on two classes of tools, debuggers and performance analysis tools. Debuggers help the developer to identify problems both on the CPU and GPU side as well as in the interplay of both.
    [Show full text]
  • High-Performance I/O Programming Models for Exascale Computing
    High-Performance I/O Programming Models for Exascale Computing SERGIO RIVAS-GOMEZ Doctoral Thesis Stockholm, Sweden 2019 KTH Royal Institute of Technology School of Electrical Engineering and Computer Science TRITA-EECS-AVL-2019:77 SE-100 44 Stockholm ISBN 978-91-7873-344-6 SWEDEN Akademisk avhandling som med tillstånd av Kungl Tekniska Högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i högprestan- daberäkningar fredag den 29 Nov 2019 klockan 10.00 i B1, Brinellvägen 23, Bergs, våningsplan 1, Kungl Tekniska Högskolan, 114 28 Stockholm, Sverige. © Sergio Rivas-Gomez, Nov 2019 Tryck: Universitetsservice US AB iii Abstract The success of the exascale supercomputer is largely dependent on novel breakthroughs that overcome the increasing demands for high-performance I/O on HPC. Scientists are aggressively taking advantage of the available compute power of petascale supercomputers to run larger scale and higher- fidelity simulations. At the same time, data-intensive workloads have recently become dominant as well. Such use-cases inherently pose additional stress into the I/O subsystem, mostly due to the elevated number of I/O transactions. As a consequence, three critical challenges arise that are of paramount importance at exascale. First, while the concurrency of next-generation su- percomputers is expected to increase up to 1000 , the bandwidth and access × latency of the I/O subsystem is projected to remain roughly constant in com- parison. Storage is, therefore, on the verge of becoming a serious bottleneck. Second, despite upcoming supercomputers expected to integrate emerging non-volatile memory technologies to compensate for some of these limitations, existing programming models and interfaces (e.g., MPI-IO) might not provide any clear technical advantage when targeting distributed intra-node storage, let alone byte-addressable persistent memories.
    [Show full text]
  • Arm® Forge User Guide Copyright © 2021 Arm Limited Or Its Affiliates
    Arm® Forge Version 21.0.2 User Guide Copyright © 2021 Arm Limited or its affiliates. All rights reserved. 101136_21.0.2_00_en Arm® Forge Arm® Forge User Guide Copyright © 2021 Arm Limited or its affiliates. All rights reserved. Release Information Document History Issue Date Confidentiality Change 2100-00 01 March 2021 Non-Confidential Document update to version 21.0 2101-00 30 March 2021 Non-Confidential Document update to version 21.0.1 2102-00 30 April 2021 Non-Confidential Document update to version 21.0.2 Non-Confidential Proprietary Notice This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of Arm. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated. Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents. THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, Arm makes no representation with respect to, and has undertaken no analysis to identify or understand the scope and content of, third party patents, copyrights, trade secrets, or other rights.
    [Show full text]
  • Arm® Forge User Guide Copyright © 2021 Arm Limited Or Its Affiliates
    Arm® Forge Version 21.0 User Guide Copyright © 2021 Arm Limited or its affiliates. All rights reserved. 101136_2100_00_en Arm® Forge Arm® Forge User Guide Copyright © 2021 Arm Limited or its affiliates. All rights reserved. Release Information Document History Issue Date Confidentiality Change 2100-00 01 March 2021 Non-Confidential Document update to version 21.0 Non-Confidential Proprietary Notice This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of Arm. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated. Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents. THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, Arm makes no representation with respect to, and has undertaken no analysis to identify or understand the scope and content of, third party patents, copyrights, trade secrets, or other rights. This document may include technical inaccuracies or typographical errors. TO THE EXTENT NOT PROHIBITED BY LAW, IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING OUT OF ANY USE OF THIS DOCUMENT, EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
    [Show full text]
  • Arm MAP and Performance Reports
    VI-HPS Tuning Workshop 2020 Arm MAP and Performance Reports Timothy Duthie & Ryan Hulguin 30th July 2020 © 2020 Arm Limited (or its affiliates) Agenda • 14:00 – Introduction • 14:15 – MAP & Performance Reports • 14:45 – Examples • 15:30 – (break) • 16:00 – Hands-On • 17:00 – (end of workshop) 2 © 2020 Arm Limited (or its affiliates) An Introduction to Arm Arm is the world's leading semiconductor intellectual property supplier We license to over 350 partners: present in 95% of smart phones, 80% of digital cameras, 35% of all electronic devices. Total of 60 billion Arm cores have been shipped since 1990* Our partners license: • Architectures and Technical Standards, e.g. Armv8-A or GIC-300 • Hardware Designs, e.g. Cortex-A72 • Software Development Tools, e.g. Arm Forge …and our IP extends beyond the CPU 3 © 2020 Arm Limited (or its affiliates) Allinea history 4 © 2020 Arm Limited (or its affiliates) Arm’s solution for HPC application development and porting Commercial tools for aarch64, x86_64, ppc64 and accelerators Cross-platform Tools Arm Architecture Tools FORGE C/C++ & FORTRAN DDT MAP COMPILER PERFORMANCE PERFORMANCE REPORTS LIBRARIES 5 © 2020 Arm Limited (or its affiliates) Arm’s solution for HPC application development and porting Commercial tools for aarch64, x86_64, ppc64 and accelerators Cross-platform Tools Arm Architecture Tools FORGE C/C++ & FORTRAN DDT MAP COMPILER PERFORMANCE PERFORMANCE REPORTS LIBRARIES 6 © 2020 Arm Limited (or its affiliates) Performance Reports © 2020 Arm Limited (or its affiliates) Hardware utilization 8 © 2020 Arm Limited (or its affiliates) Arm Performance Reports Characterize and understand the performance of HPC application runs Gathers a rich set of data • Analyses metrics around CPU, memory, IO, hardware counters, etc.
    [Show full text]