MC68HC08AZ60 Data Sheet

M68HC08 Microcontrollers

Rev. 1.1 MC68HC08AZ60/D July 14, 2005

freescale.com

MC68HC08AZ60 MC68HC08AZ48 Technical Data — Rev 1.1

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MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor 3

ehia aaMC68HC 4 Technical Data Freescale Semiconductor Freescale 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

List of Paragraphs

List of Paragraphs...... 3 Table of Contents ...... 5 List of Figures ...... 15 List of Tables ...... 21 Section 1. General Description ...... 25 Section 2. Memory Map ...... 37 Section 3. RAM ...... 49 Section 4. ROM-1 Memory ...... 51

Section 5. ROM-2 Memory ...... 53 Section 6. EEPROM-1 ...... 55 Section 7. EEPROM-2 ...... 67 Section 8. Central Processing Unit (CPU) ...... 79 Section 9. System Integration Module (SIM) ...... 97 Section 10. Clock Generation Module (CGM) ...... 121 Section 11. Mask Options...... 149 Section 12. Break Module (BRK) ...... 153 Section 13. Monitor ROM (MON) ...... 159 Section 14. Computer Operating Properly (COP) . . . .171 Section 15. Low Voltage Inhibit (LVI) ...... 177 Section 16. External Interrupt (IRQ) ...... 183

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor List of Paragraphs 5

6 List of Paragraphs Freescale Semiconductor Freescale MC68HC ofParagraphs List 6 Technical Data List ofParagraphs Revision History . Revision History . . Glossary. Section 28.Appendix:HC08AZ48 Section 27.Appendix:Future Section 26.Electrical Sp Section 25.Analog-to-Digital Section 24.Timer InterfaceModu Section 23.Keyboard Section 22.MSCANController(M . Section 21.Input/OutputPorts . . Section 20.ModuloTimer(TIM) Section 19.Timer InterfaceModu Section 18.Serial PeripheralIn Section 17.Serial Communicat Module (KBD). ..375 Module (KBD). . . ecifications. . ecifications. EPO eitr ..443 EEPROMRegisters Converter (ADC-15). ..417 Converter (ADC-15). terface (SPI). ..231 terface (SPI). ..191 ions Interface(SCI). eA(IA ..385 le A(TIMA) ..263 le B(TIMB) Memory Map. ..447 MemoryMap. CN8 ..325 SCAN08) . .299 . .289 . .461 . .471 . .429 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Table of Contents

List of Paragraphs

Table of Contents

List of Figures

List of Tables

Section 1. General Description 1.1 Contents ...... 25 1.2 Introduction...... 26

1.3 Features ...... 26 1.4 MCU Block Diagram ...... 27 1.5 Pin Assignments...... 29 1.6 Ordering Information...... 36

Section 2. Memory Map 2.1 Contents ...... 37 2.2 Introduction...... 37 2.3 I/O Section ...... 40

Section 3. RAM 3.1 Contents ...... 49 3.2 Introduction...... 49 3.3 Functional Description ...... 49

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Freescale Semiconductor Table of Contents 7

8 Table of Contents Freescale Semiconductor Freescale MC68HC Contents of Table 8 Technical Data Table ofContents 7.6 Low-Power Modes . Low-Power Modes 7.6 . FutureEEPROMMemory. 7.3 . Introduction. 7.2 . . Contents 7.1 . Low-PowerModes 6.6 . FutureEEPROMMemory. 6.3 . Introduction. 6.2 . . Contents 6.1 . Low-PowerModes 5.4 . FunctionalDescription 5.3 . Introduction. 5.2 . . Contents 5.1 . Low-PowerModes 4.4 . FunctionalDescription 4.3 . Introduction. 4.2 . . Contents 4.1 . ucinlDsrpin. FunctionalDescription 7.5 . Features 7.4 . FunctionalDescription 6.5 . Features 6.4 Section 5. ROM-2 Memory 5.ROM-2 Section Memory 4.ROM-1 Section Section 7. EEPROM-2 Section 6. EEPROM-1 ...... 68 . .56 . .67 . .55 . .53 . .51 . .67 . .55 . .53 . .51 . .78 . .66 . .54 . .52 . .68 . .56 . .53 . .51 . .68 . .56 08AZ60 — Rev 1.1 Rev — 08AZ60 Table of Contents

Section 8. Central Processing Unit (CPU) 8.1 Contents ...... 79 8.2 Introduction...... 79 8.3 Features ...... 80 8.4 CPU registers ...... 80 8.5 Arithmetic/logic unit (ALU) ...... 86 8.6 Low-power modes ...... 86 8.7 CPU during break interrupts ...... 87 8.8 Instruction Set Summary ...... 87 8.9 Opcode Map ...... 95

Section 9. System Integration Module (SIM) 9.1 Contents ...... 97

9.2 Introduction...... 98 9.3 SIM Bus Clock Control and Generation ...... 100 9.4 Reset and System Initialization...... 102 9.5 SIM Counter ...... 106 9.6 Program Exception Control...... 107 9.7 Low-Power Modes ...... 112

9.8 SIM Registers ...... 116

Section 10. Clock Generation Module (CGM) 10.1 Contents ...... 121 10.2 Introduction...... 122

10.3 Features ...... 122 10.4 Functional Description ...... 123 10.5 I/O Signals ...... 134

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Freescale Semiconductor Table of Contents 9

10 Table of Contents Freescale Semiconductor Freescale MC68HC Contents of Table 10 Technical Data Table ofContents 01 Acquisition/LockTimeSpec 10.10 CGM DuringBreakInterr 10.9 13.1 Contents . . . Contents 13.1 . Break ModuleRegisters 12.6 . . . Contents 12.1 . . Contents 11.1 . Low-PowerModes 10.8 Interrupts. 10.7 . . CGM Registers 10.6 34Fntoa ecito . FunctionalDescription 13.4 . Features 13.3 . Introduction. 13.2 . Low-PowerModes 12.5 . Functional Description 12.4 . Features 12.3 . Introduction. 12.2 . Mask OptionRegister 11.4 . Functional Description 11.3 . Introduction. 11.2 Section 12.BreakModule (BRK) Section 13.MonitorROM(MON) Section 11.MaskOptions Section ...... ps. upts . . . . ifications . ifications . . . . .142 . .160 . .153 . .159 . .153 . .149 . .136 . .159 . .153 . .149 . .157 . .143 . .142 . .156 . .150 . .143 08AZ60 — Rev 1.1 Rev — 08AZ60 . .160 . .154 . .149 Table of Contents

Section 14. Computer Operating Properly (COP) 14.1 Contents ...... 171 14.2 Introduction...... 171 14.3 Functional Description ...... 172 14.4 I/O Signals ...... 173 14.5 COP Control Register...... 175 14.6 Interrupts...... 175 14.7 Monitor Mode ...... 175 14.8 Low-Power Modes ...... 175 14.9 COP Module During Break Interrupts...... 176

Section 15. Low Voltage Inhibit (LVI) 15.1 Contents ...... 177 15.2 Introduction...... 177

15.3 Features ...... 177 15.4 Functional Description ...... 178 15.5 LVI Status Register...... 181 15.6 LVI Interrupts ...... 182 15.7 Low-Power Modes ...... 182

Section 16. External Interrupt (IRQ) 16.1 Contents ...... 183 16.2 Introduction...... 183 16.3 Features ...... 183 16.4 Functional Description ...... 184 16.5 IRQ Pin ...... 187 16.6 IRQ Module During Break Interrupts ...... 188 16.7 IRQ Status and Control Register ...... 189

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Freescale Semiconductor Table of Contents 11

12 Table of Contents Freescale Semiconductor Freescale MC68HC Contents of Table 12 Technical Data Table ofContents 18.1 Contents . . . . Contents 18.1 . I/O Registers. 17.9 . I/O Signals 17.8 SCI DuringBreakModuleInterrupts. 17.7 . . Contents 17.1 18.7 Error Conditions . Error Conditions 18.7 . Transmission Formats 18.6 . Functional Description 18.5 Pin NameandRegisterConv 18.4 . Features 18.3 . Introduction. 18.2 . Low-PowerModes 17.6 . FunctionalDescription 17.5 . Pin NameConventions. 17.4 . Features 17.3 . Introduction. 17.2 18.8 Interrupts. . Interrupts. 18.8 18.14 I/O Registers. . I/ORegisters. 18.14 . I/OSignals 18.13 SPIDuring BreakInterrupts 18.12 Queuing Transmissi 18.9 18.11 Low-Power Modes . Low-PowerModes 18.11 . ResettingtheSPI 18.10 Section 17. SerialCommun Section 18. SerialPeri . . nDt . on Data ...... pheral Interface(SPI) ications Interface(SCI) . . entions. ..233 entions. . . .212 . .252 . .232 . .192 . .255 . .231 . .191 . .247 . .213 . .232 . .192 . .243 . .248 . .249 . .211 . .193 . .251 . .250 . .238 08AZ60 — Rev 1.1 Rev — 08AZ60 . .234 . .193 . .212 Table of Contents

Section 19. Timer Interface Module B (TIMB) 19.1 Contents ...... 263 19.2 Introduction...... 264 19.3 Features ...... 264 19.4 Functional Description ...... 267 19.5 Interrupts...... 275 19.6 Low-Power Modes ...... 275 19.7 TIMB During Break Interrupts...... 276 19.8 I/O Signals ...... 276 19.9 I/O Registers...... 278

Section 20. Modulo Timer (TIM) 20.1 Contents ...... 289

20.2 Introduction...... 289 20.3 Features ...... 290 20.4 Functional Description ...... 290 20.5 TIM Counter Prescaler ...... 292 20.6 Low-Power Modes ...... 292 20.7 TIM During Break Interrupts ...... 293

20.8 I/O Registers...... 294

Section 21. Input/Output Ports 21.1 Contents ...... 299 21.2 Introduction...... 300

21.3 Port A ...... 301 21.4 Port B ...... 303 21.5 Port C ...... 306

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14 Table of Contents Freescale Semiconductor Freescale MC68HC Contents of Table 14 Technical Data Table ofContents 23.1 Contents . . . Contents 23.1 Programmer’sModelof 22.13 . MemoryMap. 22.12 . ClockSystem 22.11 . TimerLink. 22.10 . LowPowerModes 22.9 . Interrupts. 22.7 Identifier AcceptanceFilter 22.6 . . Contents 22.1 . PortH 21.10 . . Port G 21.9 . Port F 21.8 . Port E 21.7 . Port D 21.6 34Fntoa ecito . FunctionalDescription 23.4 . . Features 23.3 . Introduction. 23.2 Programmer’s Modelof 22.14 Protecti Protocol Violation 22.8 . Message Storage 22.5 External Pins.. . 22.4 . Features 22.3 . Introduction. 22.2 Section 22.MSCANController(MSCAN08) Section 23.KeyboardModule(KBD) ...... MsaeSoae. MessageStorage Control Registers Control Registers on. . on...... 355 . .344 . .321 . .319 . .316 . .312 . .309 . .375 . .327 . .375 . .338 . .325 . .349 . .375 . .328 . .326 . .345 . .329 . .339 . .334 . .349 08AZ60 — Rev 1.1 Rev — 08AZ60 . .340 . .376 Table of Contents

23.5 Keyboard Initialization...... 379 23.6 Low-Power Modes ...... 380 23.7 Keyboard Module During Break Interrupts ...... 380 23.8 I/O Registers...... 380

Section 24. Timer Interface Module A (TIMA) 24.1 Contents ...... 385 24.2 Introduction...... 386 24.3 Features ...... 386 24.4 Functional Description ...... 389 24.5 Interrupts...... 398 24.6 Low-Power Modes ...... 399 24.7 TIMA During Break Interrupts...... 399

24.8 I/O Signals ...... 400 24.9 I/O Registers...... 401

Section 25. Analog-to-Digital Converter (ADC-15) 25.1 Contents ...... 417 25.2 Introduction...... 418 25.3 Features ...... 418

25.4 Functional Description ...... 418 25.5 Interrupts...... 421 25.6 Low-Power Modes ...... 421 25.7 I/O Signals ...... 422 25.8 I/O Registers...... 423

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16 Table of Contents Freescale Semiconductor Freescale MC68HC Contents of Table 16 Technical Data Table ofContents 28.1 Contents . . . . Contents 28.1 EEDIV Non-volatile 27.3 EEDIVH andEEDIVLR 27.2 EEPROM TimebaseDivider 27.1 . . Contents 26.1 28.3 I/O Section . I/O Section 28.3 . Introduction. 28.2 Electrical Specifications 26.2 63Mcaia pcfctos. Mechanical Specifications 26.3 Section 27. Appendix: FutureEEPROMRegisters Section 28. Appendix: Section 26.ElectricalSpecifications Revision History Registers. . Registers. . . Glossary . . egisters . . . egisters . HC08AZ48 MemoryMap CnrlRgses. ControlRegisters . . .445 . .447 . .429 . .450 . .447 . .430 . .444 08AZ60 — Rev 1.1 Rev — 08AZ60 . .443 . .441 Technical Data — MC68HC08AZ60

List of Figures

Figure Title Page

1-1 MCU Block Diagram for the MC68HC08AZ60 (64-Pin QFP) . .28 1-2 MC68HC08AZ60 (64-Pin QFP) ...... 29 1-3 Power supply bypassing...... 30 2-1 Memory Map...... 38 2-2 Control, Status, and Data Registers ...... 41 6-1 EEPROM-1 Control Register (EECR1)...... 62 6-2 EEPROM-1 Nonvolatile Register (EENVR1) ...... 64 6-3 EEPROM-1 Array Control Register (EEACR1)...... 65 7-1 EEPROM-2 Control Register (EECR2)...... 74 7-2 EEPROM-2 Nonvolatile Register (EENVR2) ...... 76

7-3 EEPROM-2 Array Control Register (EEACR2)...... 77 8-1 CPU registers ...... 81 8-2 Accumulator (A) ...... 81 8-3 Index register (H:X)...... 82 8-4 Stack pointer (SP)...... 83 8-5 Program counter (PC)...... 83 8-6 Condition code register (CCR) ...... 84 9-1 SIM Block Diagram...... 99 9-2 SIM I/O Register Summary...... 99 9-3 CGM Clock Signals...... 101 9-4 External Reset Timing ...... 103 9-5 Internal Reset Timing ...... 103 9-6 Sources of Internal Reset ...... 104 9-7 POR Recovery ...... 105 9-8 Interrupt Entry...... 108 9-9 Interrupt Processing ...... 109 9-10 Interrupt Recovery ...... 110 9-11 Interrupt Recognition Example ...... 111 9-12 Wait Mode Entry Timing ...... 113

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor List of Figures 15

6Ls fFgrsFreescale Semiconductor MC68HC ListFigures of 16 Technical Data List of Figures 76SIRcie lc iga . SCI ReceiverBlock Diagram 17-6 SCI Transmitter 17-5 74SITasitr. . SCI Transmitter 17-4 . DataFormats. SCI 17-3 . SCI I/ORegisterSummary 17-2 71SIMdl lc iga . SCI ModuleBlock Diagram 17-1 IRQ Status andControl 16-3 62IQItrutFocat. IRQ InterruptFlowchart 16-2 PLL BandwidthControl 10-5 PLL ControlRegister(PC 10-4 CGM ExternalConnections 10-3 I/O RegisterSummar . 10-2 CGM BlockDiagram 10-1 SIMBreakFlagControlRegister(S 9-19 . (SRSR) Register SIMResetStatus 9-18 SIMBreakStatusRegist 9-17 StopModeRecoveryfr 9-16 . StopModeEntryTiming 9-15 WaitRecoveryfromInternalReset. 9-14 WaitRecoveryfromInterruptorBr 9-13 16-1 IRQ Block Diagram. . IRQ BlockDiagram. 16-1 . . LVI StatusRegister(LVISR). 15-3 LVI I/ORegisterSummary 15-2 I/O RegisterSummar 12-2 Break ModuleBlockDiagram 12-1 PLL ProgrammingRegister 10-6 51LIMdl lc iga . LVI ModuleBlockDiagram 15-1 . COP ControlRegister (COPCTL). 14-2 COP BlockDiagram 14-1 Monitor ModeEntryTiming 13-6 . Break Transaction. 13-5 . Read Transaction 13-4 . . Sample Monitor Waveforms 13-3 . Monitor DataFormat. 13-2 . Monitor ModeCircuit. 13-1 Break AddressRegist 12-4 Break StatusandControlRegister 12-3 Configuration Register 11-1 I/O RegisterSummar . . y . y r BK n RL . ers (BRKHandBRKL) om Interrupt or Break. om InterruptorBreak. CNI-). (CONFIG-1) eitr(BC . (PBWC) Register eitr(SR . . Register (ISCR) r(BR . er (SBSR) . . . . TL) . TL) ...... (PPG) . . . (PPG) . . . . a . eak . . (BSCR) . (BSCR) FR . BFCR) . . . . . y . y . . .125 . .155 . .163 . .161 . .196 . .164 . .198 . .186 . .184 . .136 . .134 . .115 . .180 . .195 . .124 . .169 . .164 . .189 . .115 . .116 . .154 . .140 . .179 . .150 . .138 08AZ60 — Rev 1.1 Rev — 08AZ60 . .181 . .173 . .158 . .194 . .118 . .114 . .113 . .175 . .163 . .202 . .199 . .119 . .157 List of Figures

17-7 SCI I/O Receiver Register Summary ...... 203 17-8 Receiver Data Sampling...... 205 17-9 Slow Data ...... 207 17-10 Fast Data ...... 208 17-11 SCI Control Register 1 (SCC1)...... 214 17-12 SCI Control Register 2 (SCC2)...... 217 17-13 SCI Control Register 3 (SCC3)...... 220 17-14 SCI Status Register 1 (SCS1) ...... 222 17-15 Flag Clearing Sequence ...... 225 17-16 SCI Status Register 2 (SCS2) ...... 226 17-17 SCI Data Register (SCDR) ...... 227 17-18 SCI Baud Rate Register (SCBR) ...... 228 18-1 SPI Module Block Diagram...... 235 18-2 Full-Duplex Master-Slave Connections ...... 236 18-3 Transmission Format (CPHA = 0) ...... 239 18-4 Transmission Format (CPHA = 1) ...... 240 18-5 Transmission Start Delay (Master) ...... 242 18-6 Missed Read of Overflow Condition ...... 244 18-7 Clearing SPRF When OVRF Interrupt Is Not Enabled ...... 245 18-8 SPI Interrupt Request Generation ...... 248 18-9 SPRF/SPTE CPU Interrupt Timing...... 249 18-10 CPHA/SS Timing ...... 254 18-11 SPI Control Register (SPCR) ...... 256 18-12 SPI Status and Control Register (SPSCR)...... 259 18-13 SPI Data Register (SPDR) ...... 262 19-1 TIMB Block Diagram...... 265 19-2 TIMB I/O Register Summary...... 266 19-3 PWM Period and Pulse Width ...... 271 19-4 TIMB Status and Control Register (TBSC)...... 278 19-5 TIMB Counter Registers (TBCNTH and TBCNTL) ...... 281 19-6 TIMB Counter Modulo Registers (TMODH and TMODL) . . . .282 19-7 TIMB Channel Status and Control Registers (TBSC0–TBSC1) ...... 283 19-8 CHxMAX Latency ...... 287 19-9 TIMB Channel Registers (TBCH0H/L–TBCH1H/L) ...... 288 1 TIM Block Diagram ...... 290 20-1 TIM I/O Register Summary...... 291 20-2 TIM Status and Control Register (TSC) ...... 294

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor List of Figures 17

8Ls fFgrsFreescale Semiconductor MC68HC ListFigures of 18 Technical Data List of Figures 25Quadruple 8-BitMaskabl 22-5 Dual 16-BitMaskableAcceptanceFilt 22-4 26Sleep Request/Acknowledge 22-6 Single 32-BitMaskable 22-3 User ModelforMessageBufferOrgani 22-2 21 Receive/TransmitMessageBuff 22-11 MessageBufferOrganiza 22-10 . MSCAN08 MemoryMap. 22-9 Segments withintheBit 22-8 . Clocking Scheme 22-7 . TheCAN System 22-1 PortHI/OCircuit.. 21-24 . DataDirectionRegisterH(DDRH) 21-23 PortHDataRegister(PTH 21-22 . PortGI/OCircuit 21-21 DataDirectionRegister 21-20 PortGDataRegister(PTG 21-19 . PortFI/OCircuit. 21-18 . DataDirectionRegisterF(DDRF) 21-17 PortFDataRegister(PTF 21-16 . PortEI/OCircuit. 21-15 DataDirectionRegister 21-14 PortEDataRegister(PTE 21-13 PortDI/OCircuit.. 21-12 . DataDirectionRegisterD(DDRD) 21-11 PortDDataRegister(PTD 21-10 Port CI/OCircuit.. . 21-9 Data DirectionRegister 21-8 Port CDataRegister(PTC 21-7 . Port BI/OCircuit. 21-6 Data DirectionRegisterB 21-5 Port BDataRegister(PTB 21-4 . Port AI/OCircuit. 21-3 Data DirectionRegisterA 21-2 CAN ProtocolI/OPort Port ADataRegister(PTA 21-1 1 TIM CounterModulo 20-4 TIM CounterRegister 20-3 Registers (TMODH–TMODL) TNHTNL . s (TCNTH–TCNTL) Register Summary . Register Summary ...... Identifier AcceptanceFi G (DDRG). . G (DDRG). . E (DDRE) . C (DDRC) ie. Time . e Acceptance Filters . e AcceptanceFilters in. . tion . (DDRB) . (DDRB) . (DDRA) ). . ). . ) . ) . ) ) . ) . ) . ) ) . ) . . Cycle . . Cycle er ExtendedIdentifier (IDRn) . . . ers. . ers. zation. ..332 zation. . .323 . .318 . .315 . .311 . .308 . .305 . .302 . .320 . .328 . .347 . .319 . .345 . .321 . .312 . .309 . .306 . .303 . .301 . .350 . .316 . .304 . .301 . .349 . .320 . .314 . .307 . .337 . .342 . .300 . .297 tr..335 lter 08AZ60 — Rev 1.1 Rev — 08AZ60 . .322 . .317 . .310 ..298 . .336 List of Figures

...... 351 22-12 Standard Identifier Mapping ...... 352 22-13 Transmit Buffer Priority Register (TBPR) ...... 354 22-14 MSCAN08 Control Register Structure ...... 355 22-15 Module Control Register 0 (CMCR0) ...... 357 22-16 Module Control Register (CMCR1)...... 359 22-17 Bus Timing Register 0 (CBTR0) ...... 360 22-18 Bus Timing Register 1 (CBTR1) ...... 361 22-19 Receiver Flag Register (CRFLG) ...... 363 22-20 Receiver Interrupt Enable Register (CRIER) ...... 365 22-21 Transmitter Flag Register (CTFLG) ...... 367 22-22 Transmitter Control Register (CTCR) ...... 368 22-23 Identifier Acceptance Control Register (CIDAC)...... 369 22-24 Receiver Error Counter (CRXERR) ...... 371 22-25 Transmit Error Counter (CTXERR)...... 371 22-26 Identifier Acceptance Registers (CIDAR0–CIDAR3) ...... 372 22-27 Identifier Mask Registers (CIDMR0–CIDMR3) ...... 373 23-1 Keyboard Module Block Diagram ...... 377 23-2 I/O Register Summary ...... 377 23-3 Keyboard Status and Control Register (KBSCR) ...... 381 23-4 Keyboard Interrupt Enable Register (KBIER) ...... 382 24-1 TIMA Block Diagram...... 388 24-2 TIMA I/O Register Summary...... 388 24-3 PWM Period and Pulse Width ...... 394 24-4 TIMA Status and Control Register (TASC)...... 401 24-5 TIMA Counter Registers (TCNTH and TCNTL) ...... 405 24-6 TIMA Counter Modulo Registers (TAMODH and TAMODL)...... 406 24-7 TIMA Channel Status and Control Registers (TACC0–TASC5) ...... 407 24-8 CHxMAX Latency ...... 412 24-9 TIMA Channel Registers (TACH0H/L–TACH3H/L)...... 413 25-1 ADC Block Diagram ...... 419 25-2 ADC Status and Control Register (ADSCR)...... 423 25-3 ADC Data Register (ADR) ...... 427 25-4 ADC Input Clock Register (ADICLK) ...... 427 26-1 SPI Master Timing Diagram ...... 436

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor List of Figures 19

0Ls fFgrsFreescale Semiconductor MC68HC ListFigures of 20 Technical Data List of Figures 73EEPROM-2 DividerHighNon-vo 27-3 EEPROM-2 DividerLow 27-2 EEPROM-2 DividerHigh 27-1 SPI SlaveTimingDiagram 26-2 74EEPROM-2 Divider 27-4 82Control, Status,andData 28-2 . Memory Map. 28-1 . . . . Low Non-volatileRe . Register (EEDIVL). . (EEDIVL). Register eitr(EIH . (EEDIVH) Register Registers . . . Registers . . . latile Regist gister (EEDIVLNVR) gister . .448 er (EEDIVHNVR) . .437 . .452 . .444 . .445 . .445 08AZ60 — Rev 1.1 Rev — 08AZ60 . .444 Technical Data — MC68HC08AZ60

List of Tables

Table Title Page

1-1 External Pins Summary ...... 34 1-2 Clock Source Summary ...... 36 1-3 MC Order Numbers ...... 36 2-1 Vector Addresses ...... 46 6-1 EEPROM Array Address Blocks...... 60 6-2 EEPROM Program/Erase Mode Select ...... 63 7-1 EEPROM Array Address Blocks...... 72 7-2 EEPROM Program/Erase Mode Select ...... 75 8-1 Instruction Set Summary ...... 87 8-2 Opcode Map ...... 96

9-1 I/O Register Address Summary ...... 100 9-2 Signal Name Conventions ...... 100 9-3 PIN Bit Set Timing ...... 102 10-1 I/O Register Address Summary ...... 125 10-2 Variable Definitions...... 130 10-3 VCO Frequency Multiplier (N) Selection...... 141 12-1 I/O Register Address Summary ...... 155 13-1 Mode Selection...... 162 13-2 Mode Differences ...... 163 13-3 READ (Read Memory) Command ...... 165 13-4 WRITE (Write Memory) Command...... 166 13-5 IREAD (Indexed Read) Command ...... 166 13-6 IWRITE (Indexed Write) Command ...... 167 13-7 READSP (Read Stack Pointer) Command...... 167 13-8 RUN (Run User Program) Command...... 168 15-1 LVIOUT Bit Indication ...... 181 16-1 IRQ I/O Register Summary...... 185 17-1 Pin Name Conventions...... 193 17-2 SCI I/O Register Address Summary...... 195

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor List of Tables 21

22 List of Tables Freescale Semiconductor Freescale MC68HC Tables of List 22 Technical Data List ofTables 18-4 SPI Interrupts . SPI Interrupts 18-4 22MSCAN08 vsCPUoperati 22-2 MSCAN08 InterruptVectorAddresses. 22-1 Port HPinFunctions 21-8 . Port GPinFunctions. 21-7 . SPI Configuration 18-5 . SPI I/ORegisterSummary 18-3 29Identifier AcceptanceM 22-9 . Time SegmentValues 22-8 . Baud RatePrescaler. 22-7 Synchronization JumpWidt 22-6 . Data LengthCodes. 22-5 CAN StandardCompliantBitTime 22-4 . Time segmentsyntax 22-3 . Port FPinFunctions 21-6 Port EPinFunctions 21-5 Port DPinFunctions 21-4 Port CPinFunctions 21-3 Port BPinFunctions 21-2 Port APinFunctions 21-1 . Selection. Prescaler 20-2 TIM I/ORegisterAddressSummary. 20-1 . Mode, Edge,andLevelSelection. 19-2 . Selection. Prescaler 19-1 . SPI MasterBaudRateSelection 18-6 . I/O RegisterAddresses. 18-2 . Pin NameConventions. 18-1 . SCIBaudRateSelectionExamples 17-11 . SCIBaudRateSelection 17-10 SCI BaudRatePrescaling 17-9 . Selection Format Character 17-8 . Stop BitRecovery. 17-7 . Data BitRecovery. 17-6 . Start BitVerification 17-5 SCI ReceiverI/OAddr 17-4 SCI Transmitter 17-3 31I/O Register AddressSumm 23-1 Identifier AcceptanceHit 22-10 / drs umr I/O Address Summary ...... s umr . ess Summary d etns. ode Settings ...... niain. . Indication . . ng modes . ng modes ...... h . ary . . ary . SegmentSettings ...... 199 . .247 . .255 . .361 . .296 . .280 . .206 . .206 . .321 . .318 . .233 . .354 . .348 . .233 . .229 . .228 . .234 . .362 . .360 . .203 . .370 . .370 . .377 . .341 08AZ60 — Rev 1.1 Rev — 08AZ60 . .323 . .315 . .311 . .308 . .305 . .303 . .205 . .286 . .261 . .216 . .291 . .339 . .230 ..348 List of Tables

24-1 Prescaler Selection...... 404 24-2 Mode, Edge, and Level Selection...... 411 25-1 Mux Channel Select ...... 425 25-2 ADC Clock Divide Ratio ...... 428 28-1 Vector Addresses ...... 457

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor List of Tables 23

24 List of Tables Freescale Semiconductor Freescale MC68HC Tables of List 24 Technical Data List ofTables 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 1. General Description

1.1 Contents

1.2 Introduction...... 1.226 1.3 Features...... 26 1.4 MCU Block Diagram ...... 27 1.5 Pin Assignments...... 29 1.5.1 Power Supply Pins (VDD and VSS) ...... 30 1.5.2 Oscillator Pins (OSC1 and OSC2)...... 30 1.5.3 External Reset Pin (RST) ...... 31 1.5.4 External Interrupt Pin (IRQ) ...... 31 1.5.5 Analog Power Supply Pin (VDDA) ...... 31

1.5.6 Analog Ground Pin (VSSA)...... 31 1.5.7 External Filter Capacitor Pin (CGMXFC) ...... 31 1.5.8 Port A Input/Output (I/O) Pins (PTA7–PTA0) ...... 31 1.5.9 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0) ...... 32 1.5.10 Port C I/O Pins (PTC5–PTC0) ...... 32 1.5.11 Port D I/O Pins (PTD7–PTD0/ATD8) ...... 32 1.5.12 Port E I/O Pins (PTE7/SPSCK–PTE0/TxD) ...... 32 1.5.13 Port F I/O Pins (PTF6–PTF0/TACH2)...... 33 1.5.14 Port G I/O Pins (PTG2/KBD2–PTG0/KBD0) ...... 33 1.5.15 Port H I/O Pins (PTH1/KBD4–PTH0/KBD3)...... 33 1.5.16 CAN Transmit Pin (CANTx) ...... 33 1.5.17 CAN Receive Pin (CANRx)...... 33 1.6 Ordering Information ...... 36 1.6.1 MC Order Numbers ...... 36

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor General Description 25

26 General Description Freescale Semiconductor Freescale MC68HC Description General 26 Technical Data 1.3 Features 1.2 Introduction General Description Features oftheMC modules, memorysizesandtypes,packagetypes. central processorunit(CPU08)and AllMCUsint strategy. design Family isbasedonthecustomer-spec M68HC08 Familyof8-bi The MC68HC08AZ60isame System ProtectionFeatures • (TIM) InterruptTimer Periodic • 16-Bit,6-ChannelTimer In • 8-Bit, 15-ChannelAnalog-to-D • Serial Communications In • Serial PeripheralInterfaceModule(SPI) • Clock GeneratorModule(CGM) • 2 KbyteofOn-ChipRAM • 1 KbyteofOn-ChipElectrical • 60KbytesofRead-OnlyMemory(ROM) • 8.4 MHzInternalBusFrequency • FullyUpward-CompatibleOb • High-Performance M • Illegal AddressDetect – Illegal Opcode Detect – Low-Voltage DetectionwithOptionalReset – Computer Operating Properly – Se Memorywith Only and M68HC05Families 68HC08AZ60 include: t microcontroller units t microcontroller 68HC08 Architecture curity Option(EEPROM) he familyusetheenhancedM68HC08 mber ofthelow-co ion withOptionalReset ion withOptionalReset terface Module (SCI) terface Module terface Module(TIMA-6) ly ErasableProgrammableRead- ject Codewith are availablewithavarietyof igital Converter (ADC-15) igital Converter ified integrated circuit(CSIC) integrated ified (COP)withOptionalReset (MCUs).TheM68HC08 st, high-performance M6805, M146805, 08AZ60 — Rev 1.1 Rev — 08AZ60 General Description MCU Block Diagram

• Low-Power Design (Fully Static with Stop and Wait Modes) • Master Reset Pin and Power-On Reset

Features of the CPU08 include:

• Enhanced HC05 Programming Model • Extensive Loop Control Functions • 16 Addressing Modes (Eight More Than the HC05) • 16-Bit Index Register and Stack Pointer • Memory-to-Memory Data Transfers • Fast 8 × 8 Multiply Instruction • Fast 16/8 Divide Instruction • Binary-Coded Decimal (BCD) Instructions • Optimization for Controller Applications • C Language Support

• 16-Bit, 2-Channel Timer Interface Module (TIMB) • 5-Bit Keyboard Interrupt Module • MSCAN Controller (Scalable CAN) implements CAN 2.0b Protocol as Defined in BOSCH Specification September 1991

1.4 MCU Block Diagram

Figure 1-1 shows the structure of the MC68HC08AZ60.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor General Description 27

28 General Description Freescale Semiconductor Freescale MC68HC Description General 28 Technical Data General Description

M68HC08 CPU PTA7–PTA0 PTA

VREFH DDRA CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) ANALOG-TO-DIGITAL MODULE PTB7/ATD7–PTB0/ATD0 PTB DDRB CONTROL AND STATUS REGISTERS — 62 BYTES BREAK MODULE PTC5–PTC3 PTC2/MCLK PTC USER ROM — 60 kBYTES DDRC PTC1–PTC0 LOW-VOLTAGE INHIBIT PTD7 MODULE PTD6/ATD14/TACLK USER RAM — 2048BYTES PTD5/ATD13 PTD4/ATD12/TBCLK PTD

COMPUTER OPERATING DDRD PTD3/ATD11 USER EEPROM — 1024 BYTES PROPERLY MODULE PTD2/ATD10 PTD1/ATD9–PTD0/ATD8 TIMER A 6 CHANNEL PTE7/SPSCK MONITOR ROM — 224 BYTES INTERFACE MODULE PTE6/MOSI PTE5/MISO TIMER B INTERFACE PTE4/SS USER ROM VECTOR SPACE — 52 BYTES

MODULE PTE PTE3/TACH1 DDRE OSC1 PTE2/TACH0 CLOCK GENERATOR SERIAL COMMUNICATIONS OSC2 PTE1/RxD MODULE INTERFACE MODULE CGMXFC PTE0/TxD PTF6 SERIAL PERIPHERAL PTF5/TBCH1–PTF4/TBCH0 SYSTEM INTEGRATION PTF3/TACH5-PTF2/TACH4 RST MODULE INTERFACE MODULE PTF PTF1/TACH3 DDRF PTF0/TACH2 IRQ IRQ MODULE KEYBOARD INTERRUPT MODULE PTG2/KBD2–PTG0/KBD0 PTG DDRG POWER-ON RESET MODULE PTH1/KBD4–PTH0/KBD3 PTH VSS DDRH VDD POWER CANRx V AVSS/VREFL MSCAN MODULE DDA V CANTx VSSA DDAREF 08AZ60 — Rev 1.1 Rev — 08AZ60

Figure 1-1. MCU Block Diagram for the MC68HC08AZ60 (64-Pin QFP) General Description Pin Assignments

1.5 Pin Assignments

Figure 1-2 shows the MC68HC08AZ60 pin assignments.

SSA DDA REFH PTC5 PTC3 PTC2/MCLK PTC1 PTC0 OSC1 OSC2 CGMXFC V V V PTD7 PTD6/ATD14/TACLK PTD5/ATD13 PTD4/ATD12/TBCLK PTH1/KBD4 49 64

PTC4 1 63 62 61 60 59 58 57 56 55 54 53 52 51 50 48 PTH0/KBD3

IRQ 2 47 PTD3/ATD11

RST 3 46 PTD2/ATD10

PTF0/TACH2 4 45 AVSS /VREFL

PTF1/TACH3 5 44 VDDAREF

PTF2/TACH4 6 43 PTD1/ATD9

PTF3/TACH5 7 42 PTD0/ATD8

PTF4/TBCH0 PTB7/ATD7

8 41

CANRx 9 40 PTB6/ATD6

CANTx 10 39 PTB5/ATD5

PTF5/TBCH1 11 38 PTB4/ATD4

PTF6 12 37 PTB3/ATD3

PTE0/TxD 13 36 PTB2/ATD2

PTE1/RxD 14 35 PTB1/ATD1

PTE2/TACH0 15 34 PTB0/ATD0

PTE3/TACH1 16 33 PTA7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 17 32 SS DD V V PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 PTA6 PTE4/SS PTE6/MOSI PTE5/MISO PTG0/KBD0 PTG1/KBD1 PTG2/KBD2 PTE7/SPSCK

Figure 1-2. MC68HC08AZ60 (64-Pin QFP)

NOTE: The following pin descriptions are just a quick reference. For a more detailed representation, see Input/Output Ports on page 299.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor General Description 29

30 General Description Freescale Semiconductor Freescale MC68HC Description General 30 Technical Data 1.5.2 Oscillator 1.5.1 PowerSupplyPins(V General Description NOTE: Pins (OSC1andOSC2) Serial PeripheralInterface(SPI) for theserialclockin V circuit. See The OSC1andOSC2 pins ar V V pins tosource hi bulk currentbypasscapacitor a high-frequencyresponseceramiccapa 1-3 care toprovidepowersupplyby demands onthepowersupply.Topreven Fast signaltransitionsonMCUpins from asinglepowersupply. SS DD SS . PlacetheC1bypasscapacitoras isalsothegroundfo mustbegroundedfor andV DD andV SS Clock GenerationModule (CGM) NOTE: Component valuesshown NOTE: Component arethepowersupplyand Figure 1-3.Powersupplybypassing SS gh currentlevels. ) V DD the serialperipheralinte V DD r theportoutputbuffer proper MCUoperation. e theconnectionsfor foruseinapplicationsthatrequiretheport MCU 0.1 + C2 C1 passing attheMCUasshownin µ F on page231. represent typica place high,short-durationcurrent close totheMCUaspossible.Use ground pins.TheMCUoperates citor forC1.C2isanoptional t noiseproblems,takespecial V SS rface module(SPI).See l applications. on page121. s andthegroundreturn the on-chiposcillator 08AZ60 — Rev 1.1 Rev — 08AZ60 Figure General Description Pin Assignments

1.5.3 External Reset Pin (RST)

A logic 0 on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. See System Integration Module (SIM) on page 97 for more information.

1.5.4 External Interrupt Pin (IRQ)

IRQ is an asynchronous external interrupt pin. See External Interrupt (IRQ) on page 183.

1.5.5 Analog Power Supply Pin (VDDA)

VDDA is the power supply pin for the analog portion of the chip. This pin will supply the clock generator module (CGM). See Clock Generation Module (CGM) on page 121.

1.5.6 Analog Ground Pin (VSSA)

The VSSA analog ground pin is used only for the ground connections for the analog sections of the circuit and should be decoupled as per the VSS digital ground pin. The analog sections consist of a clock generator module (CGM). See Clock Generation Module (CGM) on page 121.

1.5.7 External Filter Capacitor Pin (CGMXFC)

CGMXFC is an external filter capacitor connection for the CGM. See Clock Generation Module (CGM) on page 121

1.5.8 Port A Input/Output (I/O) Pins (PTA7–PTA0)

PTA7–PTA0 are general-purpose bidirectional I/O port pins. See Input/Output Ports on page 299.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor General Description 31

1.5.10 PortCI 32 General Description Freescale Semiconductor Freescale MC68HC Description General 32 Technical Data 1.5.12 PortEI/OPi 1.5.11 PortDI/O 1.5.9 PortBI/OPins General Description /O Pins(PTC5–PTC0) Pins (PTD7–PTD0/ATD8) ns (PTE7/SPSCK (PTB7/ATD7–PTB0/ATD0) PTC5 (ADC-15) analog-to-digital conv Port Bisan8-bitspecial interface module(SPI),andtwoofits of four (TIMA), interfacemodule timer Port Eisan8-bitspecialfunctionportt Input/Output Ports interface module(TIMB).See timer interfacemodule(TIMA),andone the analog-to-digitalc Port Disan8-bitspecial- page 299. Interface ModuleA(TIMA) on page191, interface module(SCI).See page 385, See the systemclockwhichhasafrequency port pins.PTC2/MCLKisaspecialfunc Input/Output Ports – PTC3 and on page417and Analog-to-Digital Serial PeripheralInterface(SPI) –PTE0/TxD)

PTC1 on page299. onverter module erter (ADC).See – PTC0 aregeneral-purpos function portthatshares function portthatsharessevenofitspinswith on page299. Input/Output Ports on page385,and Serial CommunicationsInterface(SCI) Converter (ADC-15) Timer InterfaceModuleA(TIMA) pins withtheseri itspinswiththe hat sharestwoofitspinswiththe (ADC-15), oneofit Analog-to-Digital Converter tion portthatshar more ofitspinswiththetimer equivalent tothesystemclock. Input/Output Ports on page231, on page299. alleightpinswiththe e bidirectionalI/O on page417and al communication serial peripheral 08AZ60 — Rev 1.1 Rev — 08AZ60 s pinswiththe es itspinwith Timer on on General Description Pin Assignments

1.5.13 Port F I/O Pins (PTF6–PTF0/TACH2)

Port F is a 7-bit special function port that shares its pins with the timer interface module (TIMB). Six of its pins are shared with the timer interface module (TIMA-6). See Timer Interface Module A (TIMA) on page 385, Modulo Timer (TIM) on page 289, and Input/Output Ports on page 299.

1.5.14 Port G I/O Pins (PTG2/KBD2–PTG0/KBD0)

Port G is a 3-bit special function port that shares all of its pins with the keyboard interrupt module (KBD). See Keyboard Module (KBD) on page 375 and Input/Output Ports on page 299.

1.5.15 Port H I/O Pins (PTH1/KBD4–PTH0/KBD3)

Port H is a 2-bit special-function port that shares all of its pins with the keyboard interrupt module (KBD). See Keyboard Module (KBD) on

page 375 and Input/Output Ports on page 299.

1.5.16 CAN Transmit Pin (CANTx)

This pin is the digital output from the CAN module (CANTx). See MSCAN Controller (MSCAN08) on page 325.

1.5.17 CAN Receive Pin (CANRx)

This pin is the digital input to the CAN module (CANRx). See MSCAN Controller (MSCAN08) on page 325.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor General Description 33

34 General Description Freescale Semiconductor Freescale MC68HC Description General 34 Technical Data General Description PTD4/ATD12/TBCLK ** ADCChannel PTD6/ATD14/TACLK **ADCChannel PTD3/ATD11–PTD0/ATD8 **ADC T5AD3* D hne General-Purpose I/O PTD5/ATD13 **ADCChannel PTF5/TBCH1–PTF4/TBCH0 PTB7/ATD7–PTB0/ATD0 PTE7/SPSCK PTE2/TACH0 PTE3/TACH1 T5PC GnrlProeIODa tt oInput Hi-Z No DualState General-Purpose I/O PTC5–PTC0 PTE5/MISO PTE6/MOSI T7PA eea-ups / ulSaeN Input Hi-Z No DualState I/O General-Purpose PTA7–PTA0 PTE1/RxD PTE0/TxD i aeFunction Pin Name Channels PTE4/SS T7GnrlProeIO ulSaeN Input Hi-Z No DualState I/O/ General Purpose PTD7 T6GnrlProeIODa tt oInput Hi-Z No DualState General-Purpose I/O PTF6 Table 1-1.ExternalPinsSummary General-Purpose I/O General-Purpose I/O General-Purpose I/O General-Purpose I/O General-Purpose I/O General-Purpose I/O General-Purpose I/O General-Purpose I/O General-Purpose I/O General-Purpose I/O General-Purpose I/O General-Purpose I/O I/O/Timer B Channel External Input ClockExternal ADC Channel/Timer External Input ClockExternal ADC Channel/Timer SCI TransmitData SCI Receive Data General-Purpose General-Purpose SPI Slave Select Timer Channel 0 Timer Channel 1 SPI Data Path SPI Data Path ADC Channel ADC Channel ADC Channel SPI Clock Open Drain Open Drain Open Drain Dual State ulSaeNo Dual State ulSaeN Input Hi-Z No Dual State Dual State ulSaeN Input Hi-Z No Dual State ulSaeN Input Hi-Z No Dual State Dual State Dual State ulSaeYsInput Hi-Z Yes Dual State ulSaeN Input Hi-Z No Dual State ulSaeYsInput Hi-Z Input Hi-Z Yes Input Hi-Z Yes Dual State Input Hi-Z Yes Dual State Yes Dual State Dual State Driver Type ytrssReset State Hysteresis e Input Hi-Z Yes e Input Hi-Z Yes e Input Hi-Z Yes No 08AZ60 — Rev 1.1 Rev — 08AZ60 Input Hi-Z Input Hi-Z General Description Pin Assignments

Table 1-1. External Pins Summary (Continued)

Driver Pin Name Function Hysteresis Reset State Type General-Purpose I/O PTF3/TACH5 Dual State Yes Input Hi-Z Timer A Channel 5 General-Purpose I/O PTF2/TACH4 Dual State Yes Input Hi-Z Timer A Channel 4 General-Purpose I/O PTF1/TACH3 Dual State Yes Input Hi-Z Timer A Channel 3 General-Purpose I/O PTF0/TACH2 Dual State Yes Input Hi-Z Timer A Channel 2 General-Purpose I/O/ PTG2/KBD2–PTG0/KBD0 Dual State Yes Input Hi-Z Keyboard Wakeup Pin General-Purpose I/O/ PTH1/KBD4 –PTH0/KBD3 Dual State Yes Input Hi-Z Keyboard Wakeup Pin

VDD Chip Power Supply N/A N/A N/A

VSS Chip Ground N/A N/A N/A ADC Power Supply/ AVDD/VDDAREF ADC Reference N/A N/A N/A

Voltage ADC Ground/ADC A /V N/A N/A N/A VSS REFL Reference Voltage A/D Reference V N/A N/A N/A REFH Voltage OSC1 External Clock In N/A N/A Input Hi-Z OSC2 External Clock Out N/A N/A Output CGMXFC PLL Loop Filter Cap N/A N/A N/A External Interrupt IRQ N/A N/A Input Hi-Z Request RST Reset N/A N/A Output Low CANRx CAN Serial Input N/A Yes Input Hi-Z CANTx CAN Serial Output Output No Output

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor General Description 35

36 General Description Freescale Semiconductor Freescale MC68HC Description General 36 Technical Data 1.6.1 MCOrderNumbers 1.6 OrderingInformation General Description This sectioncontainsinstructi MC68HC08AZ60MFU –40 –40 °C to+125 °C MC68HC08AZ60MFU MC68HC08AZ60VFU –40 –40 MC68HC08AZ60VFU C8C8Z0F –40 MC68HC08AZ60CFU EEPROM RC OSC or BusClock RCOSC EEPROM oueClock Source Module TIMA-6 Bus ClockPTD6/ATD14/TACLK or Bus TIMA-6 IBBusClockor PTD4/TBCLK TIMB CGM OSC1 and OSC1 OSC2 CGM O CGMXCLK COP CPU Bus Clock Bus or CGMOUT CGMXCLK or BusClock CGMXCLK CPU CAN ADC BRK Bus Clock Bus BRK IRQ Bus Clock Bus CGMOUTCGMXCLK and IRQ SIM TIM Bus Clock Bus TIM C CGMXCLK SCI P BusClock/SPSCK SPI LVI Bus Clock Bus LVI MC Order Number Table 1-2.Clock Source Summary Table 1-3.MC Order Numbers ons fororderingtheMC68HC08AZ60. Temperature Range Operating ° ° C to+ 105 C to + 85 08AZ60 — Rev 1.1 Rev — 08AZ60 ° ° C C Technical Data — MC68HC08AZ60

Section 2. Memory Map

2.1 Contents

2.2 Introduction...... 37 2.3 I/O Section...... 40

2.2 Introduction

The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes:

• 60 Kbytes of ROM

• 2048 Bytes of RAM • 1024 Bytes of EEPROM with Protect Option • 52 Bytes of User-Defined Vectors • 224 Bytes of Monitor ROM

The following definitions apply to the memory map representation of reserved and unimplemented locations.

• Reserved — Accessing a reserved location can have unpredictable effects on MCU operation. • Unimplemented — Accessing an unimplemented location causes an illegal address reset if illegal address resets are enabled.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Memory Map 37

8Mmr a Freescale Semiconductor MC68HC Memory Map 38 Technical Data Map Memory FF $FDFF $FDFF 0F $0DFF $0DFF F0 EEVD$FE04 RESERVED $FE02 RESERVED $FE01 FLAGCONTRO SIM BREAK $FE04 REGISTER(SRSR) SIM RESETSTATUS $FE03 SIM BREAKSTATUS $FE02 $FE01 $FE00 7F $7FFF $7FFF 0F $09FF $07FF $05FF $0E00 $04FF $0A00 $09FF $07FF $05FF $04FF 07 $057F $044F $004F $003F $057F $044F $004F $003F $0580 $0450 $0050 $0040 $0000 $0800 $0600 $0500 $8000 ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ Figure 2-1.MemoryMap CAN CONTROL AND MESSAGE I/O REGISTERS I/O REGISTERS (64 BYTES) I/O REGISTERS, 16BYTES REGISTERS, I/O EEPROM-1, 512BYTES EEPROM-1, 512BYTES EEPROM-2, BUFFERS, 128BYTES BUFFERS, ROM-2, 29,184BYTES ROM-1, 32,256BYTES RAM-2 ,1024 BYTES RAM-1, 1024 BYTES ROM-2, 128BYTES ROM-2, 176BYTES EITR(BR $FE00 (SBSR) REGISTER EITR(BC) $FE03 L REGISTER(SBFCR) 08AZ60 — Rev 1.1 Rev — 08AZ60 $0A00 $0E00 $0580 $0450 $0050 $0040 $0000 $0800 $0600 $0500 $8000 Memory Map Introduction

Figure 2-1. Memory Map (Continued)

$FE05 RESERVED $FE05 $FE06 UNIMPLEMENTED $FE06 $FE07 RESERVED $FE07 $FE08 RESERVED $FE08 $FE09 RESERVED $FE09 $FE0A RESERVED $FE0A $FE0B RESERVED) $FE0B $FE0C BREAK ADDRESS REGISTER HIGH (BRKH) $FE0C $FE0D BREAK ADDRESS REGISTER LOW (BRKL) $FE0D $FE0E BREAK STATUS AND CONTROL REGISTER (BSCR) $FE0E $FE0F LVI STATUS REGISTER (LVISR) $FE0F $FE10 RESERVED $FE10 $FE11 RESERVED $FE11 $FE12 $FE12 ↓↓UNIMPLEMENTED (5BYTES) $FE17 $FE17 $FE18 EEPROM NON-VOLATILE REGISTER (EENVR2) $FE18 $FE19 EEPROM CONTROL REGISTER (EECR2) $FE19

$FE1A RESERVED $FE1A $FE1B EEPROM ARRAY CONFIGURATION (EEACR2) $FE1B $FE1C EEPROM NON-VOLATILE REGISTER (EENVR1) $FE1C $FE1D EEPROM CONTROL REGISTER (EECR1) $FE1D $FE1E RESERVED $FE1E $FE1F EEPROM ARRAY CONFIGURATION (EEACR1) $FE1F $FE20 $FE20 ↓↓MONITOR ROM (224 BYTES) $FEFF $FEFF $FF00 $FF00 ↓ UNIMPLEMENTED (128 BYTES) ↓ $FF7F $FF7F $FF80 RESERVED $FF80 $FF81 RESERVED $FF81 $FF82 $FF82 ↓↓RESERVED (75 BYTES) $FFCB $FFCB $FFCC $FFCC ↓↓VECTORS (52BYTES) $FFFF $FFFF

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Memory Map 39

0Mmr a Freescale Semiconductor MC68HC Memory Map 40 Technical Data Section 2.3 I/O Map Memory Table 2-1 addresses: control, status,anddata Addresses $0000–$003F,shownin $FFFF(COPcontrolregister,COPCTL) • $FE1F(EEPROMarrayconfi • $FE1D(EEPROMcont • $FE1C(EEPROMnon-volati • $FE1B(EEPROMarrayconf • $FE19(EEPROMcontro • $FE18(EEPROMnon-volati • $FE0F(LVIstatus • $FE0E(breakstatusand • $FE0Cand$FE0D(bre • $FE09(configurationwrite- • $FE03(SIMbreakflag • $FE01(SIMresetstat • $FE00(SIMbreakst • isalistofvectorlocations. registers.Additional register,LVISR) atus register,SBSR) us register,SRSR) rol register,EECR1) rol control register,SBFCR) ak addressregister l register,EECR2) control register,BRKSCR) once register,CONFIG-2) le register,EENVR2) le register,EENVR1) iguration register,EEACR2) guration register,EEACR1) Figure 2-2 I/O registershavethese , containmostofthe s, BRKHandBRKL) 08AZ60 — Rev 1.1 Rev — 08AZ60 Memory Map I/O Section

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read: $0000 Port A Data Register (PTA) PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 Write: Read: $0001 Port B Data Register (PTB) PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 Write: Read: 0 0 $0002 Port C Data Register (PTC) PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 Write: Read: $0003 Port D Data Register (PTD) PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 Write: Data Direction Register A Read: $0004 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 (DDRA) Write: Data Direction Register B Read: $0005 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 (DDRB) Write: Data Direction Register C Read: 0 $0006 MCLKEN DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 (DDRC) Write: Data Direction Register D Read: $0007 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDR2 DDRD1 DDRD0 (DDRD) Write: Read: $0008 Port E Data Register (PTE) PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 Write:

Read: 0 $0009 Port F Data Register (PTF) PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 Write: Read: 0 0 0 0 0 $000A Port G Data Register (PTG) PTG2 PTG1 PTG0 Write: Read: 0 0 0 0 0 0 $000B Port H Data Register (PTH) PTH1 PTH0 Write: Data Direction Register E Read: $000C DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 (DDRE) Write: Data Direction Register F Read: 0 $000D DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 (DDRF) Write: Data Direction Register G Read: 0 0 0 0 0 $000E DDRG2 DDRG1 DDRG0 (DDRG) Write: Data Direction Register H Read: 0 0 0 0 0 0 $000F DDRH1 DDRH0 (DDRH) Write: Read: $0010 SPI Control Register (SPCR) SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE Write:

= Unimplemented R = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 6)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Memory Map 41

dr eitrNm i Bit0 1 2 3 4 5 6 Bit7 Name Register Addr. $001D 01 PLLControlRegister(PCTL) $001C $001E $001A $001B $001F $0011 $0022 $0021 BaudRateRegister(SCBR) SCI SCIDataRegister(SCDR) $0019 $0018 StatusRegister SCI 2(SCS2) $0017 StatusRegister SCI 1(SCS1) $0016 SCIControlRegister 3(SCC3) $0015 SCIControlRegister 2(SCC2) $0014 SCIControlRegister 1(SCC1) SPIDataRegister(SPDR) $0013 $0012 $0020 2Mmr a Freescale Semiconductor MC68HC Memory Map 42 Technical Data Map Memory Keyboard Statusand Control PLL ProgrammingRegister Timer AStatusand Control Keyboard InterruptEnable Timer ACounterRegister IRQ Statusand Control PLL Bandwidth Control SPI Statusand Control Mask OptionRegister Figure 2-2.Control,Status, and Register (SPSCR) Register (KBSCR) Register (PBWC) Register (TASC) High (TACNTH) Register (ISCR) Register (KBIE) (MOR) (PPG) ed SPRF Read: Read: Read: ed i 51 31 11 Bit 8 9 10 11 12 13 0 14 0 Bit15 Read: 0 Read: R0 RPF BKF R1 0 R2 R3 0 PE R4 FE 0 0 R5 NF 0 0 R6 OR R0 Read: 0 R7 IDLE R1 Read: SCRF 0 R2 TC Read: SCTE R3 Read: R8 R4 Read: R5 Read: R6 Read: R7 Read: ed VSO OSCLIS VPRSRCCPSSO COPD STOP COPRS SSREC LVIPWR 0 LVIRST ROMSEC LVISTOP Read: IRQF 0 Read: 0 0 0 Read: ed TOF Read: ed EF0 KEYF 0 0 0 0 Read: Write: Write: Write: Write: Write: Write: Write: T0 T1 T2 T3 T4 T5 T6 T0 T7 T1 Write: T2 Write: T3 Write: T4 Write: T5 Write: T6 T7 Write: Write:RRRRRRRRWrite: Write: Write: rt:0TRST 0 Write: OP NC XN AEIT E PTY PEN ILTY WAKE M TXINV ENSCI LOOPS CI CESREII ER W SBK RWU RE TE ILIE SCRIE TCIE SCTIE AUTO PLLIE U7ML U5ML R7VS R5VRS4 VRS5 VRS6 VRS7 MUL4 MUL5 MUL6 MUL7 ERRIE LOCK PLLF OETSTOP TOIE 8RROI EEFI PEIE FEIE NEIE ORIE R R T8 Data Registers(Sheet 2of6) LO BCS PLLON VFMD SPTE MODF OVRF C1SCP0 SCP1 ACQ BE BE BE BE KBIE0 KBIE1 KBIE2 KBIE3 KBIE4 XLD 00 1111 0000 MODFE ACKK C2SR SCR0 SCR1 SCR2 ACK1 S S PS0 PS1 PS2 N 08AZ60 — Rev 1.1 Rev — 08AZ60 MSKMODEK IMASKK MS1MODE1 IMASK1 P1SPR0 SPR1 Memory Map I/O Section

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Timer A Counter Register Read: Bit 7 6 5 4 3 2 1 Bit 0 $0023 Low (TACNTL) Write: Timer A Modulo Register Read: $0024 Bit 15 14 13 12 11 10 9 Bit 8 High (TAMODH) Write: Timer A Modulo Register Read: $0025 Bit 7 6 5 4 3 2 1 Bit 0 Low (TAMODL) Write: Timer A Channel 0 Status and Read: CH0F $0026 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Control Register (TASC0) Write: 0 Timer A Channel 0 Register Read: $0027 Bit 15 14 13 12 11 10 9 Bit 8 High (TACH0H) Write: Timer A Channel 0 Register Read: $0028 Bit 7 6 5 4 3 2 1 Bit 0 Low (TACH0L) Write: Timer A Channel 1 Status and Read: CH1F 0 $0029 CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX Control Register (TASC1) Write: 0 Timer A Channel 1 Register Read: $002A Bit 15 14 13 12 11 10 9 Bit 8 High (TACH1H) Write: Timer A Channel 1 Register Read: $002B Bit 7 6 5 4 3 2 1 Bit 0 Low (TACH1L) Write:

Timer A Channel 2 Status and Read: CH2F $002C CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX Control Register (TASC2) Write: 0 Timer A Channel 2 Register Read: $002D Bit 15 14 13 12 11 10 9 Bit 8 High (TACH2H) Write: Timer A Channel 2 Register Read: $002E Bit 7 6 5 4 3 2 1 Bit 0 Low (TACH2L) Write: Timer A Channel 3 Status and Read: CH3F 0 $002F CH3IE MS3A ELS3B ELS3A TOV3 CH3MAX Control Register (TASC3) Write: 0 Timer A Channel 3 Register Read: $0030 Bit 15 14 13 12 11 10 9 Bit 8 High (TACH3H) Write: Timer A Channel 3 Register Read: $0031 Bit 7 6 5 4 3 2 1 Bit 0 Low (TACH3L) Write: Timer A Channel 4 Status and Read: CH4F $0032 CH4IE MS4B MS4A ELS4B ELS4A TOV4 CH4MAX Control Register (TASC4) Write: 0 Timer A Channel 4 Register High Read: $0033 Bit 15 14 13 12 11 10 9 Bit 8 (TACH4H) Write: Timer A Channel 4 Register Low Read: $0034 Bit 7 6 5 4 3 2 1 Bit 0 (TACH4L) Write: Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 6)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Memory Map 43

dr eitrNm i Bit0 1 2 3 4 5 6 Bit7 Name Register Addr. $004B $004A $003A 04 rt:0 Write: $0048 $0047 $0046 $0045 $0039 $0044 $0038 $0035 $0049 $0043 $0042 $0041 $0040 $0037 $0036 4Mmr a Freescale Semiconductor MC68HC Memory Map 44 Technical Data Map Memory Timer BCH1Statusand Control Timer BCH0Statusand Control TIM StatusandControlRegister Analog-to-Digital DataRegister Timer BCounterRegisterHigh Timer BCounterRegisterLow Timer AChannel5 and Status Timer BModuloRegisterHigh Timer BModuloRegisterLow Analog-to-Digital InputClock Analog-to-Digital Status and Analog-to-Digital Status Timer AChannel5Register Timer AChannel5Register Timer BCH0RegisterHigh Timer BCH1RegisterHigh Timer BStatusand Control Timer BCH0RegisterLow Timer BCH1RegisterLow Control Register(ADSCR) Control Register(TASC5) Figure 2-2.Control,Status, and Register (ADICLK) Register (TBSCR) Register (TBSC1) Register (TBSC0) High (TACH5H) Low (TACH5L) (TBMODH) (TBMODL) (TBCNTH) (TBCH0H) (TBCH1H) (TBCNTL) (TBCH0L) (TBCH1L) (ADR) (TSC) ed CH1F Read: Read: Read: ed CH0F Read: Read: COCO Read: ed D D D D D D D AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Read: ed CH5F Read: ed TOF Read: Read: Read: ed i Bit0 1 2 3 4 5 6 Bit 7 Read: Read: Read: TOF Read: Read: ed i 51 31 11 Bit 8 9 10 11 12 13 14 Bit15 Read: Read: Write: Write: 0 Write: rt:0 Write: Write: R Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: DV DV DV ADICLK ADIV0 ADIV1 ADIV2 i 51 31 11 Bit 8 9 10 11 12 13 14 Bit 15 i 51 31 11 Bit 8 9 10 11 12 13 14 Bit 15 i 51 31 11 Bit 8 9 10 11 12 13 14 Bit 15 Bit 8 9 10 11 12 13 14 Bit 15 i Bit0 1 2 3 4 5 6 Bit 7 i Bit0 1 2 3 4 5 6 Bit 7 i Bit0 1 2 3 4 5 6 Bit 7 i Bit0 1 2 3 4 5 6 Bit 7 CH1IE HI SBM0 L0 L0 O0CH0MAX TOV0 ELS0A ELS0B MS0A MS0B CH0IE CH5IE INAC DH DH DH DH ADCH0 ADCH1 ADCH2 ADCH3 ADCH4 ADCO AIEN OETSTOP TOIE OETSTOP TOIE Data Registers(Sheet 4of6) 0 0 SAESBESATV CH1MAX TOV1 ELS1A ELS1B MS1A SAESBESATV CH5MAX TOV5 ELS5A ELS5B MS5A TRST TRST 00 00 0000 S S PS0 PS1 PS2 S S PS0 PS1 PS2 08AZ60 — Rev 1.1 Rev — 08AZ60 Memory Map I/O Section

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 TIM Counter Register High Read: Bit 15 14 13 12 11 10 9 Bit 8 $004C (TCNTH) Write: TIM Counter Register Low Read: Bit 7 6 5 4 3 2 1 Bit 0 $004D (TCNTL) Write: TIM Modulo Register High Read: $004E Bit 15 14 13 12 11 10 9 Bit 8 (TMODH) Write: TIM Modulo Register Low Read: $004F Bit 7 6 5 4 3 2 1 Bit 0 (TMODL) Write: SIM Break Status Register Read: $FE00 R R R R R R SBSW R (SBSR) Write: Read: POR PIN COP ILOP ILAD 0 LVI 0 $FE01 SIM Reset Status Register (SRSR) Write: SIM Break Flag Control Register Read: $FE03 BCFERRR RRRR (SBFCR) Write: Read: $FE09 RESERVED RRRRRRRR Write: Read: $FE0B RESERVED RRRRRRRR Write:

Break Address Register High Read: $FE0C Bit 15 14 13 12 11 10 9 Bit 8 (BRKH) Write: Break Address Register Low Read: $FE0D Bit 7 6 5 4 3 2 1 Bit 0 (BRKL) Write: Break Status and Control Read: 0 0 0000 $FE0E BRKE BRKA Register (BRKSCR) Write: Read: LVIOUT 0 0 0 0 0 0 0 $FE0F LVI Status Register (LVISR) Write: Read: $FE11 RESERVED RRRRRRRR Write: EEPROM Nonvolatile Register Read: EEPRTC $FE18 EERA CON2 CON1 EEBP3 EEBP2 EEBP1 EEBP0 (EENVR2) Write: T EEPROM Control Read: 0 0 $FE19 EEBCLK EEOFF EERAS1 EERAS0 EELAT EEPGM Register (EECR2) Write: Read: $FE1A Reserved RRRRRRRR Write: Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 6)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Memory Map 45

dr eitrNm i Bit0 1 2 3 4 5 6 Bit7 Name Register Addr. $FE1C $FE1D F1 Reserved $FE1E $FE1B FF COP ControlRegister(COPCTL) $FFFF $FE1F F8 RESERVED RESERVED $FF81 $FF80 6Mmr a Freescale Semiconductor MC68HC Memory Map 46 Technical Data Map Memory EEPROM ArrayControlRegister EEPROM EEPROM ArrayControlRegister EEPROM EEPROM NonvolatileRegister EEPROM Figure 2-2.Control,Status,and Register (EECR1) EEPROM Control EEPROM (EENVR1) (EEACR1) (EEACR2) Read: Read: Read: LOW BYTE OF RESET VECTOR LOWBYTEOFRESET Read: Read: Read: ed EACN CON1 CON2 EERA Read: ed EACN CON1 CON2 EERA Read: Read: rt:WRITING TO$FFFF CLEARS COPCOUNTER Write: Write: Write: Write: Write: Write: Write: Write: EEBCLK EACN CON1 CON2 EERA RRRRRRRR

Low 0 drs Vector Address FC TIMA Channel 5Vector (Low) $FFCD TIMA Channel 5Vector (High) $FFCC FC TIMA Channel 4Vector (High) $FFCE FC TIMA Channel 4Vector (Low) $FFCF Data Registers(Sheet6of6) FD ADC Vector (Low) Vector ADC (High) $FFD1 $FFD0 EF EA1ERS EELAT EERAS0 EERAS1 EEOFF Table 2-1.Vector Addresses EEPRTC EEPRTC EEPRTC T T T EP EP EP EEBP0 EEBP1 EEBP2 EEBP3 EP EP EP EEBP0 EEBP1 EEBP2 EEBP3 EP EP EP EEBP0 EEBP1 EEBP2 EEBP3 RRRR RRRR 08AZ60 — Rev 1.1 Rev — 08AZ60 0 EEPGM Memory Map I/O Section

Table 2-1. Vector Addresses (Continued)

Address Vector $FFD2 Keyboard Vector (High) $FFD3 Keyboard Vector (Low) $FFD4 SCI Transmit Vector (High) $FFD5 SCI Transmit Vector (Low) $FFD6 SCI Receive Vector (High) $FFD7 SCI Receive Vector (Low) $FFD8 SCI Error Vector (High) $FFD9 SCI Error Vector (Low) $FFDA CAN Transmit Vector (High) $FFDB CAN Transmit Vector (Low) $FFDC CAN Receive Vector (High) $FFDD CAN Receive Vector (Low) $FFDE CAN Error Vector (High) $FFDF CAN Error Vector (Low) $FFE0 CAN Wakeup Vector (High)

Priority $FFE1 CAN Wakeup Vector (Low) $FFE2 SPI Transmit Vector (High) $FFE3 SPI Transmit Vector (Low) $FFE4 SPI Receive Vector (High) $FFE5 SPI Receive Vector (Low) $FFE6 TIMB Overflow Vector (High) $FFE7 TIMB Overflow Vector (Low) $FFE8 TIMB CH1 Vector (High) $FFE9 TIMB CH1 Vector (Low) $FFEA TIMB CH0 Vector (High) $FFEB TIMB CH0 Vector (Low) $FFEC TIMA Overflow Vector (High) $FFED TIMA Overflow Vector (Low) $FFEE TIMA CH3 Vector (High) $FFEF TIMA CH3 Vector (Low) $FFF0 TIMA CH2 Vector (High) $FFF1 TIMA CH2 Vector (Low)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Memory Map 47

8Mmr a Freescale Semiconductor MC68HC Memory Map 48 Technical Data Map Memory addresses aredefined. when definingvectoraddresses.It – see default, befilledwiththeso Note thatallavailable Central ProcessingUnit(CPU)

High Priority ROM locationsnotdefined Table 2-1.Vector Addresses (Continued) drs Vector Address FF SWI Vector (Low) SWI Vector (High) $FFFD $FFFC FF ResetVector (High) $FFFE FF IRQVector (Low) $FFFB FF Reset Vector (Low) $FFFF FF IRQ Vector (High) $FFFA $FFF9 PLL Vector PLL (Low) Vector PLL (High) $FFF9 TIMVector(Low) $FFF8 TIM Vector(High) $FFF7 Vector TIMACH0 (Low) $FFF6 Vector CH0 TIMA (High) $FFF5 Vector TIMACH1 (Low) $FFF4 Vector CH1 TIMA (High) $FFF3 $FFF2 ftware interruptinstru isrecommendedthatallvector . Pleasetakethisintoaccount ction (SWI,opcode83) by theuserwill, 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 3. RAM

3.1 Contents

3.2 Introduction...... 49 3.3 Functional Description...... 49

3.2 Introduction

This section describes the 2048 bytes of random-access memory (RAM).

3.3 Functional Description

Addresses $0050 through $044F and $0A00 through $0DFF are RAM locations. The location of the stack RAM is programmable with the reset stack pointer instruction (RSP). The 16-bit stack pointer allows the stack RAM to be anywhere in the 64K-byte memory space.

NOTE: For correct operation, the stack pointer must point only to RAM locations.

Within page zero are 176 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for input/output (I/O) control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access all page zero RAM locations efficiently. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables.

Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor RAM 49

50 RAM Freescale Semiconductor Freescale MC68HC RAM 50 Technical Data RAM NOTE: NOTE: operation. data intheRAMduring Be carefulwhenusingnestedsubr increments duringpulls. the returnaddress.Thestackpo During asubroutinecall, stacked. For M68HC05,M6805,and a subroutineorduring the CPUusestwobytes M146805 compatibility,t inter decrementsduringpushesand outines. TheCPU the interruptstacking of thestacktostore he Hregisterisnot could overwrite 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 4. ROM-1 Memory

4.1 Contents

4.2 Introduction...... 51 4.3 Functional Description...... 51 4.4 Low-Power Modes ...... 52 4.4.1 WAIT Mode ...... 52 4.4.2 STOP Mode ...... 52

4.2 Introduction

This section describes the operation of the embedded ROM-1 memory.

4.3 Functional Description

The ROM memory physically consists of two independent arrays of 32K bytes with an additional 52 bytes of user vectors and two bytes of block protection. The address ranges for the user memory and vectors are:

• $8000–$FDFF • $FFCC–$FFFF (These locations are reserved for user-defined interrupt and reset vectors.)

NOTE: A security feature prevents viewing of the ROM contents.(1)

1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the ROM difficult for unauthorized users.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor ROM-1 Memory 51

52 ROM-1 Memory Freescale Semiconductor Freescale MC68HC Memory ROM-1 52 Technical Data 4.4.2 STOPMode 4.4.1 WAITMode 4.4 Low-PowerModes Memory ROM-1 be putintolowpowerstandby. When theMCUisputintost since activity memory affect theoperationofROMmemory whil Putting theMCUintowaitmode consumption standbymodes. The WAITandSTOPin the CPUisinactive. the structions putthe op mode,iftheROMis e theROMisinre directly,buttherewillnotbeany MCU inlowpower in readmode,itwill ad modedoesnot 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 5. ROM-2 Memory

5.1 Contents

5.2 Introduction...... 53 5.3 Functional Description...... 53 5.4 Low-Power Modes ...... 54 5.4.1 WAIT Mode ...... 54 5.4.2 STOP Mode ...... 54

5.2 Introduction

This section describes the operation of the embedded ROM-2 memory.

5.3 Functional Description

The ROM-2 memory is an array of up to 29,488 bytes. The address ranges for the user memory and the control register are: • $0450–$04FF • $0580–$05FF • $0E00–$7FFF

NOTE: A security feature prevents viewing of the ROM contents.(1)

1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the ROM difficult for unauthorized users.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor ROM-2 Memory 53

54 ROM-2 Memory Freescale Semiconductor Freescale MC68HC Memory ROM-2 54 Technical Data 5.4.2 STOPMode 5.4.1 WAITMode 5.4 Low-PowerModes Memory ROM-2 be putintolowpowerstandby. When theMCUisputintost since activity memory affect theoperationofROMmemory whil Putting theMCUintowaitmode consumption standbymodes. The WAITandSTOPin the CPUisinactive. the structions putthe op mode,iftheROMis e theROMisinre directly,buttherewillnotbeany MCU inlowpower in readmode,itwill ad modedoesnot 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 6. EEPROM-1

6.1 Contents

6.2 Introduction...... 55 6.3 Future EEPROM Memory ...... 56 6.4 Features...... 56 6.5 Functional Description...... 56 6.5.1 EEPROM Programming ...... 57 6.5.2 EEPROM Erasing ...... 58 6.5.3 EEPROM Block Protection ...... 60 6.5.4 MCU Configuration...... 60 6.5.5 MC68HC08AZ60 EEPROM Protection ...... 61 6.5.6 EEPROM Control Register...... 62 6.5.7 EEPROM Nonvolatile Register ...... 64 6.5.8 EEPROM Array Configuration Register ...... 65 6.6 Low-Power Modes ...... 66 6.6.1 Wait Mode ...... 66 6.6.2 Stop Mode ...... 66

6.2 Introduction

This section describes the electrically erasable programmable read-only memory (EEPROM). The 1024 bytes available on the MC68HC08AZ60 are physically located in two 512byte arrays. This chapter details the array covering the address range $0800 to $09FF. For information relating to the array covering address range $0600 to $07FF see EEPROM-2 on page 67.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor EEPROM-1 55

6EPO- Freescal MC68HC EEPROM-1 56 Technical Data 6.5 FunctionalDescription 6.4 Features 6.3 Future EEPROMMemory EEPROM-1 NOTE: register afterreset(EE programming/erasing. are providedtoprotectstored register (EENVR1)andar protection option.Theseoptionsar erase cycles.EEPROMcell external voltagesupply. The 512bytesofEEPROM-1canbe EEPROM featuresinclude: bytes mustbeerasedbeforereprogramming. This newsilicon algorithms arefullycompatible will simplifyprogramminganderas Design isunderwaytointroduce compatibility pleasecontac new timebasecontrolregisters.Ifmo EEPROM modulerequiresaconstant Registers identified bymaskset.Pleaseread Security Option • ChargePump On-Chip • Bits MCUConfiguration Nonvolatile • Blo Nonvolatile • Byte, Block,orBulkErasable • on page443forpreliminarydetails. will not allow multiplewr will notallow ck ProtectionOption ACR1) orareadofEEN TheEEPROMha e loadedintotheEEPROM t thefactory.Thesilic s areprotectedwith for Programming/Erasing data corruptionfromaccidental with thenewEEPRO an improvedEEPROMmodule,which e storedintheEEP e. Currentread,writeanderase Appendix: FutureEEPROM re informationisrequiredforcode programmed orerasedwithoutan timebasethroug ites beforeerase.EEPROM s alifetimeof10,000write- VR1. Hardwareinterlocks a nonvolatileblock on differenceswillbe arrayconfiguration M design.Thenew ROM nonvolatile h thesetupof 08AZ60 — Rev 1.1 Rev — 08AZ60 e Semiconductor EEPROM-1 Functional Description

6.5.1 EEPROM Programming

The EEPROM-1 array will leave the factory in the erased state: all addresses logic ‘1’ and bit 4 of the EENVR1 register programmed to ‘1’ such that the full array is available and unprotected.

The unprogrammed state is a logic 1. Programming changes the state to a logic 0. Only valid EEPROM bytes in the non-protected blocks and EENVR1 can be programmed. It is recommended that all bits should be erased before being programmed.

Follow this procedure to program a byte of EEPROM after first ensuring the block protect feature is not set on the address block of the byte to be programmed:

1. Clear EERAS1 and EERAS0 and set EELAT in the EECR1. (See note A and B.) 2. Write the desired data to any user EEPROM address. 3. Set the EEPGM bit. (See note C.)

4. Wait for a time, tEEPGM, to program the byte. 5. Clear EEPGM bit.

6. Wait for a time, tEEFPV, for the programming voltage to fall. 7. Clear EELAT bits. (See note D.) 8. Repeat steps 1 to 7 for more EEPROM programming.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor EEPROM-1 57

8EPO- Freescal MC68HC EEPROM-1 58 Technical Data 6.5.2 EEPROMErasing EEPROM-1 protect featureisnotse Use thisprocedureto the nonprotectedblocks The unprogrammedstateis a.EERAS1 andEERAS0mustbecleare .Setthe EEPGMbit.(SeenoteB.) 3. Writeanydatatothedesiredaddr 2. Clear/setEERAS1and 1. NOTES: address forbulkerase. address inthedesiredblockforbl and setEELATinEE .SettingEELATbitconfigurestheaddressanddatabusesto b. .AnyattempttoclearbothEEP d. .Toensureproperprogrammi c. valid EEPROMwriteoccurs EEPROM addresswillbelatch latch dataforprogrammingthear be will part the for removalofhighvolt single instructionwillonlyclear charge pumpisturnedoff. program voltageisremovedfrom user EEPROMarray. pump generatestheprogramvolt write hasoccurred.WhenEEPG cannot besetiftheEELATbi valid EEPROMwrite. EECR1 writestothe set, other other EEPROMdatawill override thepreviousaddressand eraseEEPROMafterfi t ontheaddressblockof and EENVR1canbeerased. inerasemode. CR1. (SeenoteA.) a logic1.Onlythe EERAS0 toselectby WhentheEEPGMbit age fromtheEEPROMarray. read thelatcheddat , thisaddres t isclearedandanon-EEPROM ng sequence,theEEPGMbit d forprogrammi ock erase,ortoanyarray ess forbyteerase,toany GM andEELATbitswitha willonlybe ed. Ifanotherconsecutive EEPGM. This istoallowtime EEPGM. This M isset,theonboardcharge thearrayandinternal age andapplie ray. Onlydatawithvalid data. Anyattemptstoread rst ensuringtheblock valid EEPROMbytesin the bytetobeerased: te/block/bulk erase, s anddatawill allowed aftera is cleared,the 08AZ60 — Rev 1.1 Rev — 08AZ60 ng. Otherwise, a. IfEELATis e Semiconductor s ittothe EEPROM-1 Functional Description

4. Wait for a time, tEEPGM,/tEEBLOCK/tEEBULK.. 5. Clear EEPGM bit.

6. Wait for a time, tEEFPV, for the erasing voltage to fall. 7. Clear EELAT bits. (See note C.) 8. Repeat steps 1 to 7 for more EEPROM byte/block erasing.

EEBPx bit must be cleared to erase EEPROM data in the corresponding block. If any EEBPx is set, the corresponding block can not be erased and bulk erase mode does not apply.

NOTES: a.Setting EELAT bit configures the address and data buses to latch data for erasing the array. Only valid EEPROM addresses with their data will be latched. If another consecutive valid EEPROM write occurs, this address and data will override the previous address and data. In block erase mode, any EEPROM address in the block may be used in step 2. All locations within this block will be erased. In bulk erase mode,

any EEPROM address may be used to erase the whole EEPROM. EENVR1 is not affected with block or bulk erase. Any attempts to read other EEPROM data will read the latched data. If EELAT is set, other writes to the EECR1 will only be allowed after a valid EEPROM write. b. The EEPGM bit cannot be set if the EELAT bit is cleared and a non-EEPROM write has occurred. This is to ensure proper erasing sequence. Once EEPGM is set, the type of erase mode cannot be modified. If EEPGM is set, the onboard charge pump generates the erase voltage and applies it to the user EEPROM array. When the EEPGM bit is cleared, the erase voltage is removed from the array and the internal charge pump is turned off. c. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM array.

All bits should be erased before being programmed.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor EEPROM-1 59

6.5.4 MCUConfiguration 0EPO- Freescal MC68HC EEPROM-1 60 Technical Data 6.5.3 EEPROMBl EEPROM-1 ock Protection EENVR1. array configurationwillta EENVR1 likeanorm The MCUconfigurationcanbecha all readstotheEEN correct systemrequir responsibility toerase the volatileEEPR regist special reset,this On memory. MCU which,forsafety purpose bitswhichcanbeusedto The EEPROMnonvolatileregister(E EENVR1 register. corresponding bitsintheEENVR1 protect configuration bits areeffectiveafteraresetor If EEBPxbitisset,thatcorrespondi shows theaddressranges allow theprogram/erasevoltage to programorerasememorylocations of theseblockscanbeseparatelyprot The 512bytesofEEPROMar lc ubr(EP)AddressRange Block Number (EEBPx) Table 6-1.EEPROM Array Address Blocks EP $0980–$09FF $0900–$097F $0880–$08FF $0800–$087F EEBP3 EEBP2 EEBP1 EEBP0 OM arrayconfigurationregi VR1 willreloadEEACR1. al EEPROM byte. byte. al EEPROM can bemodifiedby reasons, needtobecontro ements andverifyit and program the EENVR and program ke affectafterasystem within theblocks. e dividedintofour1 areadtoEENVR1 to beappliedthearray. ng addressblockis enable/disable func nged byprogramming/erasingthe register andthen er loadstheMCUco ENVR1) alsocontainsgeneral- withintheprotec ected byEEBPxbi Please notethatit erasing/programming the ster (EEACR1).Thereafter, priortouse. reset orareadofthe lled fromnonvolatile 28-byte blocks.Each 1 registertothe register. Theblock readingthe protected.These tions withinthe ted blockwillnot 08AZ60 — Rev 1.1 Rev — 08AZ60 nfiguration into t. Anyattempt e Semiconductor istheuser’s The new Table 6-1

EEPROM-1 Functional Description

6.5.5 MC68HC08AZ60 EEPROM Protection

The MC68HC08AZ60 has a special protection option which prevents program/erase access to memory locations $08F0 to $08FF. This protect function is enabled by programming the EEPRTCT bit in the EENVR to 0.

In addition to the disabling of the program and erase operations on memory locations $08F0 to $08FF the enabling of the protect option has the following effects.

• Bulk and block erase modes are disabled. • Programming and erasing of the EENVR is disabled. • Unsecure locations ($0800–$08EF) can be erased using the single byte erase function as normal. • Secured locations can be read as normal. • Writing to a secure location no longer qualifies as a “valid EEPROM write” as detailed in (see EEPROM Programming)

Note B and (see EEPROM Erasing) Note A.

NOTE: Once armed, the protect option is permanently enabled. As a consequence, all functions in the EENVR will remain in the state they were in immediately before the security was enabled.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor EEPROM-1 61

2EPO- Freescal MC68HC EEPROM-1 62 Technical Data 6.5.6 EEPROMC EEPROM-1 NOTE: NOTE: ontrol Register drs:$FE1D Address: the EEOFFbit. EEOFF —EEPROMPowerDown than 8MHz. internal chargepumpforapplications The EEPROMrequiresa It isrecommendedthatt EEBCLK —EEPROMBusClockEnable This read/writeregister Reset:00000000 Read: Write: This read/writebitdisablesth internal chargepumpforprogramming/ results. Resetclearsthisbit. consumption. Anyattemptstoa This read/writebitdeter 0 = Enable EEPROMarray 0 =Enable 1 =DisableEEPROMarray oscill RC 0 =Internal 1 =Busclockdriveschargepump EEBCLK Bit 7654321Bit 0 Figure 6-1.EEPROM-1Cont 0 Unimplemented = controls programming/ EF EA1ERS EELAT EERAS0 EERAS1 EEOFF he internalRCo recovery time,t mines whichclockwill ator driveschargepump e EEPROMmoduleforlowerpower ccess thearraywillgiveunpredictable thathaveabusfrequencyofless rol Register(EECR1) EEOFF scillator isusedtodrivethe erasing. Resetclearsthisbit. , tostabilizeafterclearing erasing ofthearray. be usedtodrivethe 08AZ60 — Rev 1.1 Rev — 08AZ60 e Semiconductor 0 EEPGM EEPROM-1 Functional Description

EERAS1 and EERAS0 — Erase Bits These read/write bits set the erase modes. Reset clears these bits. Table 6-2. EEPROM Program/Erase Mode Select

EEBPx EERAS1 EERAS0 MODE

000Byte Program

001Byte Erase

0 1 0 Block Erase

011Bulk Erase

1 X X No Erase/Program

X = don’t care

EELAT — EEPROM Latch Control This read/write bit latches the address and data buses for programming the EEPROM array. EELAT cannot be cleared if EEPGM is still set. Reset clears this bit. 1 = Buses configured for EEPROM programming 0 = Buses configured for normal read operation

EEPGM — EEPROM Program/Erase Enable This read/write bit enables the internal charge pump and applies the programming/erasing voltage to the EEPROM array if the EELAT bit is set and a write to a valid EEPROM location has occurred. Reset clears the EEPGM bit. 1 = EEPROM programming/erasing power switched on 0 = EEPROM programming/erasing power switched off

NOTE: Writing logic 0s to both the EELAT and EEPGM bits with a single instruction will clear EEPGM only to allow time for the removal of high voltage.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor EEPROM-1 63

4EPO- Freescal MC68HC EEPROM-1 64 Technical Data 6.5.7 EEPROMN EEPROM-1 NOTE: onvolatile Register drs:$FE1C Address: EEBP3–EEBP0 —EEPROMBl EEPRTCT —EEPROMProtection may notbedisabled. This featureisawrite-oncefeature. CON1— Unused CON2 —Unused CONx —MCUConf EERA —EEPROM The EEPROMnonvolatileregist ee:PV Reset: Read: Write: EEACR1. programmed orerased.Resetload These read/writebitsselectbl ($8F0–$8FF) from This one-timeprogramm the MCU.ResetloadsCONx These read/writebitscanbeused This bitisreservedforfutureus 0 =EEPROMarrayblock isunprotected 1 =EEPROMarrayblock isprotected 0 =EEPROMprot 1 =EEPROMprotec Figure 6-2.EEPROM-1Nonvol EACN O1EPTTEB3EB2EB1EEBP0 EEBP1 EEBP2 EEBP3 EEPRTCT CON1 CON2 EERA Bit 7 6 5 4 3 2 1 Bit 0 Bit 1 2 3 4 5 6 Bit 7 = Unimplemented PV = valueor1intheerased PV Programmed state. Unimplemented = Redundant Array iguration Bits iguration being erasedorprogrammed. ection enabled tion disabled able bitcanbeusedtoprotect16bytes fromEENVR1toEEACR1. ock ProtectionBits er (EENVR1)isshownin ocks ofEEPROMarrayfrombeing e andshoulda Once theprotectionisenabledit to enable/disablefunctionswithin atile Register(EENVR1) s EEBP[3:0]from lways beequalto0. EENVR1to 08AZ60 — Rev 1.1 Rev — 08AZ60 e Semiconductor Figure 6-2 . EEPROM-1 Functional Description

6.5.8 EEPROM Array Configuration Register The EEPROM array configration register (EEACR1) is shown in Figure 6-3.

Address: $FE1F Bit 7 6 5 4 3 2 1 Bit 0 Read: EERA CON2 CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0 Write: Reset: EENVR = Unimplemented Figure 6-3. EEPROM-1 Array Control Register (EEACR1)

EERA — EEPROM Redundant Array This bit is reserved for future use and should always be equal to 0.

CONx — MCU Configuration Bits These read/write bits can be used to enable/disable functions within

the MCU. Reset loads CONx from EENVR1 to EEACR1.

CON2 — Unused

CON1— Unused

NOTE: This feature is a write-once feature. Once the protection is enabled it may not be disabled.

EEPRTCT — EEPROM Protection This one-time programmable bit can be used to protect 16 bytes ($8F0–$8FF) from being erased or programmed. 1 = EEPROM protection disabled 0 = EEPROM protection enabled

EEBP3–EEBP0 — EEPROM Block Protection Bits These read/write bits select blocks of EEPROM array from being programmed or erased. Reset loads EEBP[3:0] from EENVR1 to EEACR1. 1 = EEPROM array block is protected 0 = EEPROM array block is unprotected

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor EEPROM-1 65

6EPO- Freescal MC68HC EEPROM-1 66 Technical Data 6.6.2 StopMode 6.6.1 WaitMode 6.6 Low-PowerModes EEPROM-1 result inunpr stop mode.Attemptstoaccessthe The modulerequiresa extended ifprogram/eraseisin turn will beautomatically When stopmodeisterminated,andif off.Howe turned will beautomatically If stopmodeisenteredwhileprogram/ voltage isturned minimum. TheSTOPinstructionshoul The STOPinstructionr before executingthe EEPROM isinactive,powercanbe program theEEPROMandput The WAITinstructiondoes consumption standbymodes. The WAITandSTOPinst edictable behavior. on (EEPGM=1). WAIT instruction. educes theEEPR recovery time,t ed backon.Program/erasetimewillneedtobe ructions canputth not affectthe theMCUinwaitmode.However,if terrupted byente array duringtherecoverytimewill reduced bysettingtheEEOFFbit ver, the EEPGM bit will remain set. EEPGMbitwillremain ver, the EEPGM isstillset,thehighvoltage erase isinprogress,highvoltage d notbeexecutedwhilethehigh EESTOP OM powerconsumptiontoa EEPROM. Itispossibleto e MCUinlowpower- , tostabilizeafterleaving ring stopmode. 08AZ60 — Rev 1.1 Rev — 08AZ60 e Semiconductor Technical Data — MC68HC08AZ60

Section 7. EEPROM-2

7.1 Contents

7.2 Introduction...... 67 7.3 Future EEPROM Memory ...... 68 7.4 Features...... 68 7.5 Functional Description...... 68 7.5.1 EEPROM Programming ...... 69 7.5.2 EEPROM Erasing ...... 70 7.5.3 EEPROM Block Protection ...... 72 7.5.4 MCU Configuration...... 72 7.5.5 MC68HC08AZ60 EEPROM Protection ...... 73 7.5.6 EEPROM Control Register...... 74 7.5.7 EEPROM Nonvolatile Register ...... 76 7.5.8 EEPROM Array Configuration Register ...... 77 7.6 Low-Power Modes ...... 78 7.6.1 Wait Mode ...... 78 7.6.2 Stop Mode ...... 78

7.2 Introduction

This section describes the electrically erasable programmable read-only memory (EEPROM). The 1024 bytes available on the MC68HC08AZ60 are physically located in two 512byte arrays. This chapter details the array covering the address range $0600 to $07FF. For information relating to the array covering address range $0800 to $09FF see EEPROM-1 on page 55.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor EEPROM-2 67

8EPO- Freescal MC68HC EEPROM-2 68 Technical Data 7.5 FunctionalDescription 7.4 Features 7.3 Future EEPROMMemory EEPROM-2 NOTE: register afterreset(EE programming/erasing. are providedtoprotectstored register (EENVR2)andar protection option.Theseoptionsar erase cycles.EEPROMcell external voltagesupply. The 512bytesofEEPROM-2canbe EEPROM featuresinclude: bytes mustbeerasedbeforereprogramming. This newsilicon algorithms arefullycompatible will simplifyprogramminganderas Design isunderwaytointroduce compatibility pleasecontac new timebasecontrolregisters.Ifmo EEPROM modulerequiresaconstant Registers identified bymaskset.Pleaseread Security Option • ChargePump On-Chip • Bits MCUConfiguration Nonvolatile • Blo Nonvolatile • Byte, Block,orBulkErasable • forpreliminarydetails. will not allow multiplewr will notallow ck ProtectionOption ACR2) orareadofEEN TheEEPROMha e loadedintotheEEPROM t thefactory.Thesilic s areprotectedwith for Programming/Erasing data corruptionfromaccidental with thenewEEPRO an improvedEEPROMmodule,which e storedintheEEP e. Currentread,writeanderase Appendix: FutureEEPROM re informationisrequiredforcode programmed orerasedwithoutan timebasethroug ites beforeerase.EEPROM s alifetimeof10,000write- VR2. Hardwareinterlocks a nonvolatileblock on differenceswillbe arrayconfiguration M design.Thenew ROM nonvolatile h thesetupof 08AZ60 — Rev 1.1 Rev — 08AZ60 e Semiconductor EEPROM-2 Functional Description

7.5.1 EEPROM Programming

The EEPROM-2 array will leave the factory in the erased state: all addresses logic ‘1’ and bit 4 of the EENVR2 register programmed to ‘1’ such that the full array is available and unprotected.

The unprogrammed state is a logic 1. Programming changes the state to a logic 0. Only valid EEPROM bytes in the non-protected blocks and EENVR2 can be programmed. It is recommended that all bits should be erased before being programmed.

Follow this procedure to program a byte of EEPROM after first ensuring the block protect feature is not set on the address block of the byte to be programmed:

1. Clear EERAS1 and EERAS0 and set EELAT in the EECR2. (See note A and B.) 2. Write the desired data to any user EEPROM address. 3. Set the EEPGM bit. (See note C.)

4. Wait for a time, tEEPGM, to program the byte. 5. Clear EEPGM bit.

6. Wait for a time, tEEFPV, for the programming voltage to fall. 7. Clear EELAT bits. (See note D.) 8. Repeat steps 1 to 7 for more EEPROM programming.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor EEPROM-2 69

0EPO- Freescal MC68HC EEPROM-2 70 Technical Data 7.5.2 EEPROMErasing EEPROM-2 protect featureisnotse Use thisprocedureto the nonprotectedblocks The unprogrammedstateis a.EERAS1 andEERAS0mustbecleare .Setthe EEPGMbit.(SeenoteB.) 3. Writeanydatatothedesiredaddr 2. Clear/setEERAS1and 1. NOTES: address forbulkerase. address inthedesiredblockforbl and setEELATinEE .SettingEELATbitconfigurestheaddressanddatabusesto b. .AnyattempttoclearbothEEP d. .Toensureproperprogrammi c. valid EEPROMwriteoccurs EEPROM addresswillbelatch latch dataforprogrammingthear be will part the for removalofhighvolt single instructionwillonlyclear charge pumpisturnedoff. program voltageisremovedfrom user EEPROMarray. pump generatestheprogramvolt write hasoccurred.WhenEEPG cannot besetiftheEELATbi valid EEPROMwrite. EECR2 writestothe set, other other EEPROMdatawill override thepreviousaddressand eraseEEPROMafterfi t ontheaddressblockof and EENVR2canbeerased. inerasemode. CR2. (SeenoteA.) a logic1.Onlythe EERAS0 toselectby WhentheEEPGMbit age fromtheEEPROMarray. read thelatcheddat , thisaddres t isclearedandanon-EEPROM ng sequence,theEEPGMbit d forprogrammi ock erase,ortoanyarray ess forbyteerase,toany GM andEELATbitswitha willonlybe ed. Ifanotherconsecutive EEPGM. This istoallowtime EEPGM. This M isset,theonboardcharge thearrayandinternal age andapplie ray. Onlydatawithvalid data. Anyattemptstoread rst ensuringtheblock valid EEPROMbytesin the bytetobeerased: te/block/bulk erase, s anddatawill allowed aftera is cleared,the 08AZ60 — Rev 1.1 Rev — 08AZ60 ng. Otherwise, a. IfEELATis e Semiconductor s ittothe EEPROM-2 Functional Description

4. Wait for a time, tEEPGM,/tEEBLOCK/tEEBULK.. 5. Clear EEPGM bit.

6. Wait for a time, tEEFPV, for the erasing voltage to fall. 7. Clear EELAT bits. (See note C.) 8. Repeat steps 1 to 7 for more EEPROM byte/block erasing.

EEBPx bit must be cleared to erase EEPROM data in the corresponding block. If any EEBPx is set, the corresponding block can not be erased and bulk erase mode does not apply.

NOTES: a.Setting EELAT bit configures the address and data buses to latch data for erasing the array. Only valid EEPROM addresses with their data will be latched. If another consecutive valid EEPROM write occurs, this address and data will override the previous address and data. In block erase mode, any EEPROM address in the block may be used in step 2. All locations within this block will be erased. In bulk erase mode,

any EEPROM address may be used to erase the whole EEPROM. EENVR2 is not affected with block or bulk erase. Any attempts to read other EEPROM data will read the latched data. If EELAT is set, other writes to the EECR2 will only be allowed after a valid EEPROM write. b. The EEPGM bit cannot be set if the EELAT bit is cleared and a non-EEPROM write has occurred. This is to ensure proper erasing sequence. Once EEPGM is set, the type of erase mode cannot be modified. If EEPGM is set, the onboard charge pump generates the erase voltage and applies it to the user EEPROM array. When the EEPGM bit is cleared, the erase voltage is removed from the array and the internal charge pump is turned off. c. Any attempt to clear both EEPGM and EELAT bits with a single instruction will only clear EEPGM. This is to allow time for removal of high voltage from the EEPROM array.

All bits should be erased before being programmed.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor EEPROM-2 71

7.5.4 MCUConfiguration 2EPO- Freescal MC68HC EEPROM-2 72 Technical Data 7.5.3 EEPROMBl EEPROM-2 ock Protection EENVR2. array configurationwillta EENVR2 likeanorm The MCUconfigurationcanbecha all readstotheEEN correct systemrequir responsibility toerase the volatileEEPR regist special reset,this On memory. MCU which,forsafety purpose bitswhichcanbeusedto The EEPROMnonvolatileregister(E EENVR2 register. corresponding bitsintheEENVR2 protect configuration bits areeffectiveafteraresetor If EEBPxbitisset,thatcorrespondi shows theaddressranges allow theprogram/erasevoltage to programorerasememorylocations of theseblockscanbeseparatelyprot The 512bytesofEEPROMar lc ubr(EP)AddressRange Block Number (EEBPx) Table 7-1.EEPROM Array Address Blocks EP $0780–$07FF $0700–$077F $0680–$06FF $0600–$067F EEBP3 EEBP2 EEBP1 EEBP0 OM arrayconfigurationregi VR2 willreloadEEACR2. al EEPROM byte. byte. al EEPROM can bemodifiedby reasons, needtobecontro ements andverifyit and program the EENVR and program ke affectafterasystem within theblocks. e dividedintofour1 areadtoEENVR2 to beappliedthearray. ng addressblockis enable/disable func nged byprogramming/erasingthe register andthen er loadstheMCUco ENVR2) alsocontainsgeneral- withintheprotec ected byEEBPxbi Please notethatit erasing/programming the ster (EEACR2).Thereafter, priortouse. reset orareadofthe lled fromnonvolatile 28-byte blocks.Each 2 registertothe register. Theblock readingthe protected.These tions withinthe ted blockwillnot 08AZ60 — Rev 1.1 Rev — 08AZ60 nfiguration into t. Anyattempt e Semiconductor istheuser’s The new Table 7-1

EEPROM-2 Functional Description

7.5.5 MC68HC08AZ60 EEPROM Protection

The MC68HC08AZ60 has a special protection option which prevents program/erase access to memory locations $08F0 to $08FF. This protect function is enabled by programming the EEPRTCT bit in the EENVR to 0.

In addition to the disabling of the program and erase operations on memory locations $08F0 to $08FF the enabling of the protect option has the following effects.

• Bulk and block erase modes are disabled. • Programming and erasing of the EENVR is disabled. • Unsecure locations ($0800–$08EF) can be erased using the single byte erase function as normal. • Secured locations can be read as normal. • Writing to a secure location no longer qualifies as a “valid EEPROM write” as detailed in (see EEPROM Programming)

Note B and (see EEPROM Erasing) Note A.

NOTE: Once armed, the protect option is permanently enabled. As a consequence, all functions in the EENVR will remain in the state they were in immediately before the security was enabled.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor EEPROM-2 73

4EPO- Freescal MC68HC EEPROM-2 74 Technical Data 7.5.6 EEPROMC EEPROM-2 NOTE: NOTE: ontrol Register drs:$FE19 Address: the EEOFFbit. EEOFF —EEPROMPowerDown than 8MHz. internal chargepumpforapplications The EEPROMrequiresa It isrecommendedthatt EEBCLK —EEPROMBusClockEnable This read/writeregister Reset:00000000 Read: Write: This read/writebitdisablesth internal chargepumpforprogramming/ results. Resetclearsthisbit. consumption. Anyattemptstoa This read/writebitdeter 0 = Enable EEPROMarray 0 =Enable 1 =DisableEEPROMarray oscill RC 0 =Internal 1 =Busclockdriveschargepump EEBCLK Bit 7654321Bit 0 Figure 7-1.EEPROM-2Cont 0 Unimplemented = controls programming/ EF EA1ERS EELAT EERAS0 EERAS1 EEOFF he internalRCo recovery time,t mines whichclockwill ator driveschargepump e EEPROMmoduleforlowerpower ccess thearraywillgiveunpredictable thathaveabusfrequencyofless rol Register(EECR2) EEOFF scillator isusedtodrivethe erasing. Resetclearsthisbit. , tostabilizeafterclearing erasing ofthearray. be usedtodrivethe 08AZ60 — Rev 1.1 Rev — 08AZ60 e Semiconductor 0 EEPGM EEPROM-2 Functional Description

EERAS1 and EERAS0 — Erase Bits These read/write bits set the erase modes. Reset clears these bits. Table 7-2. EEPROM Program/Erase Mode Select

EEBPx EERAS1 EERAS0 MODE

000Byte Program

001Byte Erase

0 1 0 Block Erase

011Bulk Erase

1 X X No Erase/Program

X = don’t care

EELAT — EEPROM Latch Control This read/write bit latches the address and data buses for programming the EEPROM array. EELAT cannot be cleared if EEPGM is still set. Reset clears this bit. 1 = Buses configured for EEPROM programming 0 = Buses configured for normal read operation

EEPGM — EEPROM Program/Erase Enable This read/write bit enables the internal charge pump and applies the programming/erasing voltage to the EEPROM array if the EELAT bit is set and a write to a valid EEPROM location has occurred. Reset clears the EEPGM bit. 1 = EEPROM programming/erasing power switched on 0 = EEPROM programming/erasing power switched off

NOTE: Writing logic 0s to both the EELAT and EEPGM bits with a single instruction will clear EEPGM only to allow time for the removal of high voltage.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor EEPROM-2 75

6EPO- Freescal MC68HC EEPROM-2 76 Technical Data 7.5.7 EEPROMN EEPROM-2 NOTE: onvolatile Register drs:$FE18 Address: EEBP3–EEBP0 —EEPROMBl EEPRTCT —EEPROMProtection may notbedisabled. This featureisawrite-oncefeature. CON1— Unused CON2 —Unused CONx —MCUConf EERA —EEPROM The EEPROMnonvolatileregist ee:PV Reset: Read: Write: EEACR2. programmed orerased.Resetload These read/writebitsselectbl ($8F0–$8FF) from This one-timeprogramm the MCU.ResetloadsCONx These read/writebitscanbeused This bitisreservedforfutureus 0 =EEPROMarrayblock isunprotected 1 =EEPROMarrayblock isprotected 0 =EEPROMprot 1 =EEPROMprotec Figure 7-2.EEPROM-2Nonvol EACN O1EPTTEB3EB2EB1EEBP0 EEBP1 EEBP2 EEBP3 EEPRTCT CON1 CON2 EERA Bit 7 6 5 4 3 2 1 Bit 0 Bit 1 2 3 4 5 6 Bit 7 = Unimplemented PV = valueor1intheerased PV Programmed state. Unimplemented = Redundant Array iguration Bits iguration being erasedorprogrammed. ection enabled tion disabled able bitcanbeusedtoprotect16bytes fromEENVR2toEEACR2. ock ProtectionBits er (EENVR2)isshownin ocks ofEEPROMarrayfrombeing e andshoulda Once theprotectionisenabledit to enable/disablefunctionswithin atile Register(EENVR2) s EEBP[3:0]from lways beequalto0. EENVR2to 08AZ60 — Rev 1.1 Rev — 08AZ60 e Semiconductor Figure 7-2 . EEPROM-2 Functional Description

7.5.8 EEPROM Array Configuration Register The EEPROM array configration register (EEACR2) is shown in Figure 7-3.

Address: $FE1B Bit 7 6 5 4 3 2 1 Bit 0 Read: EERA CON2 CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0 Write: Reset: EENVR = Unimplemented Figure 7-3. EEPROM-2 Array Control Register (EEACR2)

EERA — EEPROM Redundant Array This bit is reserved for future use and should always be equal to 0.

CONx — MCU Configuration Bits These read/write bits can be used to enable/disable functions within

the MCU. Reset loads CONx from EENVR2 to EEACR2.

CON2 — Unused

CON1— Unused

NOTE: This feature is a write-once feature. Once the protection is enabled it may not be disabled.

EEPRTCT — EEPROM Protection This one-time programmable bit can be used to protect 16 bytes ($8F0–$8FF) from being erased or programmed. 1 = EEPROM protection disabled 0 = EEPROM protection enabled

EEBP3–EEBP0 — EEPROM Block Protection Bits These read/write bits select blocks of EEPROM array from being programmed or erased. Reset loads EEBP[3:0] from EENVR2 to EEACR2. 1 = EEPROM array block is protected 0 = EEPROM array block is unprotected

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor EEPROM-2 77

8EPO- Freescal MC68HC EEPROM-2 78 Technical Data 7.6.2 StopMode 7.6.1 WaitMode 7.6 Low-PowerModes EEPROM-2 result inunpr stop mode.Attemptstoaccessthe The modulerequiresa extended ifprogram/eraseisin turn will beautomatically When stopmodeisterminated,andif off.Howe turned will beautomatically If stopmodeisenteredwhileprogram/ voltage isturned minimum. TheSTOPinstructionshoul The STOPinstructionr before executingthe EEPROM isinactive,powercanbe program theEEPROMandput The WAITinstructiondoes consumption standbymodes. The WAITandSTOPinst edictable behavior. on (EEPGM=1). WAIT instruction. educes theEEPR recovery time,t ed backon.Program/erasetimewillneedtobe ructions canputth not affectthe theMCUinwaitmode.However,if terrupted byente array duringtherecoverytimewill reduced bysettingtheEEOFFbit ver, the EEPGM bit will remain set. EEPGMbitwillremain ver, the EEPGM isstillset,thehighvoltage erase isinprogress,highvoltage d notbeexecutedwhilethehigh EESTOP OM powerconsumptiontoa EEPROM. Itispossibleto e MCUinlowpower- , tostabilizeafterleaving ring stopmode. 08AZ60 — Rev 1.1 Rev — 08AZ60 e Semiconductor Central Processing Unit (CPU) Contents

Technical Data — MC68HC08AZ60

Section 8. Central Processing Unit (CPU)

8.1 Contents

8.2 Introduction...... 79 8.3 Features...... 80 8.4 CPU registers ...... 80 8.4.1 Accumulator (A) ...... 81 8.4.2 Index register (H:X) ...... 82 8.4.3 Stack pointer (SP) ...... 82 8.4.4 Program counter (PC) ...... 83 8.4.5 Condition code register (CCR) ...... 84

8.5 Arithmetic/logic unit (ALU) ...... 86 8.6 Low-power modes ...... 86 8.6.1 WAIT mode ...... 86 8.6.2 STOP mode ...... 86 8.7 CPU during break interrupts ...... 87 8.8 Instruction Set Summary ...... 87 8.9 Opcode Map ...... 95

8.2 Introduction

This section describes the central processor unit (CPU8). The M68HC08 CPU is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Freescale document number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Central Processing Unit (CPU) 79

ehia aaMC68HC (C Unit CentralProcessing 80 Technical Data 8.4 CPUregisters 8.3 Features Central Processing Unit(CPU) the memory map. memory the Figure 8-1 Features oftheCPU Low-powerSTOPandWAITModes • Enhanced binary-codeddecim • Fast8-bitbymultiplyand • Memory-to-memory datamoveswithoutusingaccumulator • 16addressingmodes • 64Kbyteprogram/datamemoryspace • 8.4MHz CPUinternalbusfrequency • 16-bitindexregisterwithX-re • 16-bitstackpointerwithst • Fullupward,object- • showsthefiveCPU include thefollowing: code compatibilitywi registers. CPUregist ack manipulationinstructions U Freescale Semiconductor PU) gister manipulationinstructions al (BCD)datahandling 16-bit by8-bitdivideinstructions th M68HC05family ers arenotpartof 08AZ60 — Rev 1.1 Rev — 08AZ60 Central Processing Unit (CPU) CPU registers

7 0 ACCUMULATOR (A)

15 0 H X INDEX REGISTER (H:X)

15 0 STACK POINTER (SP)

15 0 PROGRAM COUNTER (PC)

70 V11HINZC CONDITION CODE REGISTER (CCR)

CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO’S COMPLEMENT OVERFLOW FLAG

Figure 8-1. CPU registers

8.4.1 Accumulator (A)

The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.

Bit 7654321Bit 0

Read: A Write:

Reset: Unaffected by reset Figure 8-2. Accumulator (A)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Central Processing Unit (CPU) 81

ehia aaMC68HC (C Unit CentralProcessing 82 Technical Data 8.4.3 Stackpointer(SP) 8.4.2 Indexregister(H:X) Central Processing Unit(CPU) H:X Reset:00000000XXXXXXXX Read: Write: conditional address stack. TheCPUusesthecontentsof stack pointercanfuncti In thestackpointer8-bi increments asdatais stack pointerdecrementsas significant byteto$FFanddoesnotaf $00FF. Theresetstackpointer(RSP location onthestack.Duringarese The stackpointerisa16-bi location. The indexregistercan index registertodeterminethe In theindexedaddressi lower byte.H:Xistheconc memory space.Histheupperbyteof The 16-bitindexregisterallowsi X = Indeterminate X = Bit 151413121110987654321 Figure 8-3.Index of theoperand. pulled fromthestack. also beusedasa on asanindexregister ng modes,theCPUuses t offsetand16-bitoffs t registerthatcontains atenated 16-bitindexregister. data ispushedontothestackand conditional addr ndexed addressingofa64Kbyte register (H:X) U Freescale Semiconductor PU) t, thestackpointerispresetto ) instructionsetstheleast the stackpointertodetermine theindexregist fect themostsignificantbyte.The temporary datastorage et addressing toaccessdataonthe ess oftheoperand. theaddressofnext the contentsof er andXisthe 08AZ60 — Rev 1.1 Rev — 08AZ60 modes, the Bit 0 Central Processing Unit (CPU) CPU registers

Bit Bit 1514131211109876543210

Read: SP Write:

Reset:0000000011111111 Figure 8-4. Stack pointer (SP)

NOTE: The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct address (page zero) space. For correct operation, the stack pointer must point only to RAM locations.

8.4.4 Program counter (PC)

The program counter is a 16-bit register that contains the address of the

next instruction or operand to be fetched.

Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.

During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.

Bit Bit 1514131211109876543210

Read: PC Write:

Reset: Loaded with vector from $FFFE and $FFFF Figure 8-5. Program counter (PC)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Central Processing Unit (CPU) 83

ehia aaMC68HC (C Unit CentralProcessing 84 Technical Data 8.4.5 Conditioncoderegister(CCR) Central Processing Unit(CPU) CCR Reset:X11X1XXX Read: Write: I —Interruptmask H —Half-carryflag V —Overflowflag functions ofthecond 5 aresetpermanentlyto‘1’. flags thatindicatethere The 8-bitconditioncoderegistercont cleared. WhenaCPUin disabled. CPUinterruptsareena When theinterruptmaskisset, before theinterrupt automatically aftert to determinethe operations. TheDAAinstru carry flagisrequiredforbinary- accumulator bits3and4duringan The CPUsetsthehalf-carryfl the overflowflag. occurs. Thesignedbranchinstructions The CPUsetstheoverfl X = Indeterminate X = 0 =Interruptsenabled disabled 1 =Interrupts 0 =Nocarrybetweenbits3and4 1 =Carrybetweenbits3and4 0 =Nooverflow 1 =Overflow Bit 7654321Bit0 V11HINZC Figure 8-6.Condition appropriate correctionfactor. ition coderegister. he CPUregistersaresa vector isfetched. sults oftheinstruction ow flagwhenatwo'scomplementoverflow terrupt occurs,theinterruptmaskisset The followingparagraphsdescribethe ction usesthestates code register(CCR) ag whenacarryoccursbetween U Freescale Semiconductor PU) coded decimal(BCD all maskableCPUinterruptsare bled whentheinterruptmaskis ains theinterruptmaskandfive ADDorADCo BGT,BGE,BLE,andBLTuse just executed.Bits6and ved onthestack,but oftheHandCflags peration. Thehalf- ) arithmetic 08AZ60 — Rev 1.1 Rev — 08AZ60 Central Processing Unit (CPU) CPU registers

NOTE: To maintain M6805 compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions.

After the I bit is cleared, the highest-priority interrupt request is serviced first.

A return from interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can only be cleared by the clear interrupt mask software instruction (CLI).

N — Negative flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result

Z — Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result

C — Carry/borrow flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions - such as bit test and branch, shift, and rotate - also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Central Processing Unit (CPU) 85

ehia aaMC68HC (C Unit CentralProcessing 86 Technical Data 8.6.2 STOPmode 8.6.1 WAITmode 8.6 Low-powermodes 8.5 Arithmetic/logicunit(ALU) Central Processing Unit(CPU) oscillator stabilizationdelay. After exitingSTOPmode,theC The STOPinstruction: The WAITinstruction: consumption standbymodes. The WAITandSTOPin CPU08RM/AD) foradescriptionof Refer tothe instruction set. The ALUperformsthearit modes andmoredetail Disables theCPUclock • theinterrupt mask(Ibit) clears • Disables theCPUclock • theinterruptmask(Ibit) clears • bit isset. external interrupt,theIbitremains enabling externalinterrupts.Af exit After bit remainsclear. enabling interrupts.Afterexitfrom CPU08 ReferenceManual about CPUarchitecture. structions putthe hmetic andlogicoperat PU clockbeginsrunningafterthe U Freescale Semiconductor PU) by reset,theIbitisset. the instructions intheconditioncoderegister, intheconditioncoderegister, ter exitfromSTOPmodeby (Freescaledocumentnumber WAITmodebyinterrupt,theI clear. Afterexit MCU inlow--power ions definedbythe andaddressing 08AZ60 — Rev 1.1 Rev — 08AZ60 by reset, theI by reset, Central Processing Unit (CPU) CPU during break interrupts

8.7 CPU during break interrupts

If the break module is enabled, a break interrupt causes the CPU to execute the software interrupt instruction (SWI) at the completion of the current CPU instruction. See Break Module (BRK) on page 153. The program counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor mode).

A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.

8.8 Instruction Set Summary

Table 8-1 provides a summary of the M68HC08 instruction set.

Table 8-1. Instruction Set Summary

Effect on

Source CCR Operation Description Form VHI NZC Address Mode Opcode Operand Cycles

ii A9 dd ADC #opr IMM B9 2 ADC opr DIR C9 hh 3 ll ADC opr EXT D9 ee 4 ADC opr,X ↕↕ ↕↕↕IX2 E9 4 ADC opr,X Add with Carry A ← (A) + (M) + (C) – IX1 F9 ff 3 ff ADC ,X IX 9E 2 ADC opr,SP SP1 E9 4 ADC opr,SP SP2 9E ff 5 ee D9 ff ii AB ADD #opr IMM BB dd 2 hh ADD opr DIR CB ll 3 ADD opr EXT DB 4 ADD opr,X IX2 EB ee 4 Add without Carry A ← (A) + (M) ↕↕– ↕↕↕ ff ADD opr,X IX1 FB ff 3 ADD ,X IX 9E 2 ADD opr,SP SP1 EB 4 ff ADD opr,SP SP2 9E ee 5 DB ff

AIS #opr Add Immediate Value (Signed) to ––––––IMM A7ii 2 SP SP ← (SP) + (16 « M) Add Immediate Value (Signed) to AIX #opr H:X H:X ← (H:X) + (16 « M) ––––––IMM AFii 2

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Central Processing Unit (CPU) 87

ehia aaMC68HC (C Unit CentralProcessing 88 Technical Data Central Processing Unit(CPU) BGT BHCC BHCC BIL BCC BCC AND AND AND ,X AND AND AND AND AND # AND BCS BCLR ASR ASR ASR ASRX ASRA ASR BHCS BHCS BGE BEQ ASL ASL ,X ASL ASLX ASLA ASL BHI BHI BHS BIH BIH Source Form rel rel rel opr opr opr opr rel opr opr opr opr rel rel opr opr opr opr opr opr opr rel opr n rel rel , ,SP ,X ,SP ,X ,X ,SP ,SP ,X ,X opr Operands) BranchThan (Signed ifGreater Branch if Half Carry Bit Clear PC PC BitClear Branch ifHalfCarry Branch ifIRQ BLO) Bit BranchSet (Same as if Carry PC BitClear Branch ifCarry Shift Arithmetic Right Logical AND A A Logical AND Clear Bit n in M Mn Mn Bit ninM Clear asLSL) (Same Shift Arithmetic Left Branch if Half Carry Bit Set PC PC BitSet Branch ifHalfCarry rnhi qa PC To (SignedOperands) BranchThan orEqual ifGreater Branch ifEqual rnhi ihrPC asBCC) (Same Branch orSame ifHigher Branch ifHigher Branch ifIRQ prto Description Operation Table 8-1.Instruction Pin Low PC PC PC PinLow PinHigh PC PC ← PC PC PC PC ← ← C (PC)+2 ← ← (PC) + 2 + +2 (PC) (PC)+2 ← ← ← ← ← ← (PC) +2 (PC) +2 (PC) +2 (PC) +2 (PC) + 2 + rel ? 3 (C) rr 24 ––––––REL = 0 (PC) +2 (PC) +2 (PC)+2 b7 b7 Set Summary (Continued) Set Summary ← ()&()0–– – 0 &(M) (A) rel 0 ← rel rel ?(Z) 0–––––– 0 rel rel rel rel rel rel rel ? (C) | (Z) 3 rr 22 ––––––REL = 0 ?(N ?IRQ ?IRQ ? 3 (H) rr 28 ––––––REL = 0 ? 3 (C) rr 25 ––––––REL = 1 ? 3 (H) rr 29 ––––––REL = 1 ? 3 (C) rr 24 ––––––REL = 0 ? 3 (Z) rr 27 ––––––REL = 1 b0 b0

| (N

⊕ U Freescale Semiconductor PU) V

⊕ = 0–––RL2 r3 rr 2E ––––––REL 3 rr = 2F ––––––REL 0 = 1 0 C ) = 0 ) V ) = H NZC VHI –––E 0r 3 rr 90 ––––––REL –––E 2r 3 rr 92 ––––––REL ↕ ↕ Effect on –– –– CCR ↕↕↕ ↕↕↕ ↕↕ – SP1 IX IX1 INH INH DIR (b7) DIR (b6) DIR (b5) DIR (b4) DIR (b3) DIR (b2) DIR (b1) DIR (b0) DIR SP1 IX IX1 INH INH DIR SP2 SP1 IX IX1 IX2 EXT DIR IMM

08AZ60 — Rev 1.1 Rev — 08AZ60 Address Mode 1D D4 D4 C4 9E 1B 9E 9E E4 9E E4 B4 A4 1F F4 67 77 67 57 47 37 19 17 15 13 11 68 78 68 58 48 38 Opcode ff ff dd dd dd dd dd dd dd dd dd ff ff dd ff ee ff ff ff ee ll hh dd ii Operand 5 3 4 1 1 4 4 4 4 4 4 4 4 4 5 3 4 1 1 4 5 4 2 3 4 4 3 2 Cycles Central Processing Unit (CPU) Instruction Set Summary

Table 8-1. Instruction Set Summary (Continued)

Effect on Source CCR Operation Description Form VHI NZC Address Mode Opcode Operand Cycles

A5 ii dd BIT #opr IMM B5 hh 2 BIT opr DIR C5 3 BIT opr EXT D5 ll 4 ee BIT opr,X Bit Test (A) & (M) 0 – – ↕↕– IX2 E5 ff 4 BIT opr,X IX1 F5 3 BIT ,X IX 9E ff 2 BIT opr,SP SP1 E5 ff 4 BIT opr,SP SP2 9E 5 D5 ee ff

BLE opr Branch if Less Than or Equal To PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = ––––––REL 93 rr 3 (Signed Operands) 1 BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3 BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 ––––––REL 23 rr 3 BLT opr Branch if Less Than (Signed ––––––REL 91 rr 3 Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) =1 BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 ––––––REL 2Crr 3 BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 ––––––REL 2Brr 3 BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? (I) = 1 ––––––REL 2Drr 3 BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 ––––––REL 26 rr 3 BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 ––––––REL 2Arr 3

BRA rel Branch Always PC ← (PC) + 2 + rel ––––––REL 20 rr 3 DIR dd (b0) rr DIR dd (b1) rr DIR 01 dd 5 (b2) 03 rr 5 DIR 05 dd 5 BRCLR Branch if Bit n in M Clear PC (PC) + 3 + rel ? (Mn) = 0 – – – – – ↕ (b3) 07 rr 5 n,opr,rel ← DIR 09 dd 5 (b4) 0B rr 5 DIR 0D dd 5 (b5) 0F rr 5 DIR dd (b6) rr DIR dd (b7) rr BRN rel Branch Never PC ← (PC) + 2 ––––––REL 21 rr 3 DIR dd (b0) rr DIR dd (b1) rr DIR 00 dd 5 (b2) 02 rr 5 DIR 04 dd 5 BRSET Branch if Bit n in M Set PC (PC) + 3 + rel ? (Mn) = 1 – – – – – ↕ (b3) 06 rr 5 n,opr,rel ← DIR 08 dd 5 (b4) 0A rr 5 DIR 0C dd 5 (b5) 0E rr 5 DIR dd (b6) rr DIR dd (b7) rr

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Central Processing Unit (CPU) 89

ehia aaMC68HC (C Unit CentralProcessing 90 Technical Data Central Processing Unit(CPU) CLC Clear Carry Bit C C Bit Carry Clear CLC CBEQ opr, CBEQ CBEQ opr, CBEQ # CBEQX # CBEQA BSET CPHX CPHX # L la nerp akI CLR CLR ,X Mask Clear Interrupt CLR CLRH CLRX CLRA CLR CLI BSR COM COM ,X COM COMX COMA COM CMP CMP CMP ,X CMP CMP CMP CMP CMP # opr,rel opr,rel Source SP X+ Form opr opr opr rel opr opr opr opr opr opr opr opr opr ,rel opr,rel n ,rel opr opr X+ , opr ,SP ,X opr ,SP ,SP ,X ,X ,SP ,X ,rel Clear Branch toSubroutine Compare andBranch ifEqual Compare Set Bit opr : ihM(H:X) –(M:M +1) M H:Xwith Compare Complement) (One’sComplement opr ihM(A) –(M) AwithM Compare n in M Mn Mn M in prto Description Operation Table 8-1.Instruction PC PC PC PC PC PC ← ← ← ← ← ← SP PC (PC) + 4 + rel ? (A) – (M) =$00 – (M) ?(A) rel + +4 (PC) (PC) + 2 + rel ? (A) – (M) =$00 – (M) ?(A) rel + +2 (PC) (PC) + 3 + rel ? (A) – (M) =$00 – (M) ?(A) rel + +3 (PC) (PC) + 3 + rel ? (X) – (M) =$00 – (M) ?(X) rel + +3 (PC) (PC) + 3 + rel ? (A) – (M) =$00 – (M) ?(A) rel + +3 (PC) (PC) + 3 + rel ? (A) – (M) =$00 – (M) ?(A) rel + +3 (PC) M M M M ← A X ← PC ← ← ← ← ← ← (SP) – 1; push (PCH) (SP) –1;push (PC) + 2; push (PCL) (PC)+ Set Summary (Continued) Set Summary SP (M (A (M (M (X (M M M M M H ← A X ← ) = $FF –(M) ) =$FF –(M) ) =$FF ) = $FF –(M) ) =$FF –(M) ) =$FF –(M) ) =$FF –(M) ) =$FF ← ← (PC) + (PC) ← ← ← ← ← (SP)–1 ← ← ← $00 $00 $00 $00 $00 $00 $00 0–0–IH9 2 9A ––0–––INH 0 0–––IH9 1 98 –––––0INH 0 1–––––– 1 rel U Freescale Semiconductor PU) H NZC VHI 0–– –––––– –––E Dr 4 AD rr ––––––REL ↕ 0––01– ↕ Effect on –– –– CCR ↕↕ ↕↕↕ ↕↕↕ 1 SP1 IX+ IX1+ IMM IMM DIR DIR IMM SP1 IX IX1 INH INH DIR (b7) DIR (b6) DIR (b5) DIR (b4) DIR (b3) DIR (b2) DIR (b1) DIR (b0) DIR SP1 IX IX1 INH INH INH DIR SP2 SP1 IX IX1 IX2 EXT DIR IMM

08AZ60 — Rev 1.1 Rev — 08AZ60 Address Mode 1C 8C D1 D1 C1 9E 9E 1E 1A 9E 9E E1 9E E1 B1 A1 6F 7F 6F 5F 4F 3F F1 61 71 61 51 41 31 75 65 63 73 63 53 43 33 18 16 14 12 10 Opcode ff rr rr ff rr rr ii rr ii rr dd dd ii+1 ii ff ff dd dd dd dd dd dd dd dd dd ff ff dd ff ee ff ff ff ee ll hh dd ii Operand 6 4 5 4 4 5 4 3 5 3 4 1 1 4 4 4 4 4 4 4 4 4 4 2 3 1 1 1 3 5 4 2 3 4 4 3 2 Cycles Central Processing Unit (CPU) Instruction Set Summary

Table 8-1. Instruction Set Summary (Continued)

Effect on Source CCR Operation Description Form VHI NZC Address Mode Opcode Operand Cycles

A3 ii dd CPX #opr IMM B3 hh 2 CPX opr DIR C3 3 CPX opr EXT D3 ll 4 ee CPX ,X Compare X with M (X) – (M) ↕ ––↕↕↕IX2 E3 ff 4 CPX opr,X IX1 F3 3 CPX opr,X IX 9E ff 2 CPX opr,SP SP1 E3 ff 4 CPX opr,SP SP2 9E 5 D3 ee ff

DAA Decimal Adjust A (A)10 U– – ↕↕↕INH 72 2 A (A) – 1 or M (M) – 1 or X (X) – DBNZ opr,rel ← ← ← DBNZA rel 1 DIR 3B dd 5 PC ← (PC) + 3 + rel ? (result) ≠ 0 4B rr 3 DBNZX rel Decrement and Branch if Not PC (PC) + 2 + rel ? (result) 0 INH 5B rr 3 DBNZ ← ≠ ––––––INH opr,X,rel Zero PC ← (PC) + 2 + rel ? (result) ≠ 0 IX1 6B rr 5 PC ← (PC) + 3 + rel ? (result) ≠ 0 7B ff rr 4 DBNZ X,rel PC (PC) + 2 + rel ? (result) 0 IX 9E rr 6 DBNZ ← ≠ SP1 opr,SP,rel PC ← (PC) + 4 + rel ? (result) ≠ 0 6B ff rr 3A DEC opr M ← (M) – 1 DIR dd 4 DECA A (A) – 1 INH 4A 1 ← 5A DECX Decrement X ← (X) – 1 ↕ ––↕↕– INH 6A 1 DEC opr,X M (M) – 1 IX1 ff 4 ← 7A DEC ,X M (M) – 1 IX 3 ← 9E DEC opr,SP M ← (M) – 1 SP1 6A ff 5 A (H:A)/(X) DIV Divide ← ––––↕↕INH 52 7 H ← Remainder A8 ii dd EOR #opr IMM B8 hh 2 EOR opr DIR C8 3 EOR opr EXT D8 ll 4 ee EOR opr,X Exclusive OR M with A 0––↕↕– IX2 E8 ff 4 EOR opr,X A ← (A ⊕ M) IX1 F8 3 EOR ,X IX 9E ff 2 EOR opr,SP SP1 E8 ff 4 EOR opr,SP SP2 9E 5 D8 ee ff 3C INC opr M ← (M) + 1 DIR 4C dd 4 INCA A ← (A) + 1 INH 1 INCX X (X) + 1 INH 5C 1 Increment ← ↕ ––↕↕– 6C INC opr,X M ← (M) + 1 IX1 7C ff 4 INC ,X M ← (M) + 1 IX 3 INC opr,SP M (M) + 1 SP1 9E ff 5 ← 6C dd JMP opr DIR BC hh 2 JMP opr EXT CC ll 3 JMP opr,X Jump PC ← Jump Address ––––––IX2 DC ee 4 JMP opr,X IX1 EC ff 3 JMP ,X IX FC ff 2

dd JSR opr DIR BD hh 4 PC ← (PC) + n (n = 1, 2, or 3) JSR opr Push (PCL); SP (SP) – 1 EXT CD ll 5 JSR opr,X Jump to Subroutine ← ––––––IX2 DD ee 6 JSR opr,X Push (PCH); SP ← (SP) – 1 IX1 ED ff 5 PC Unconditional Address JSR ,X ← IX FD ff 4

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Central Processing Unit (CPU) 91

ehia aaMC68HC (C Unit CentralProcessing 92 Technical Data Central Processing Unit(CPU) LDA LDA LDA ,X LDA LDA LDA LDA LDA # U nindmlil X:A Unsigned multiply MUL NSA Nibble Swap A A A 1 9D ––––––INH None Nibble Swap A No Operation NSA NOP NEG NEG ,X NEG NEGX NEGA NEG LDHX # LDHX LDX LDX LDX ,X LDX LDX LDX LDX LDX # LDX LSL LSLX LSLA LSL LSR LSR ,X LSR LSR LSR LSRA LSR LSL LSL ,X MOV X+ MOV # MOV MOV Source Form X opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr, opr,opr opr opr opr opr,opr ,X ,SP opr ,SP ,SP ,X ,X ,SP ,SP ,X ,X ,SP ,X ,opr ,SP ,X X+ Load A from M A A A M from Load Negate (Two’sNegate Complement) Load H:X from M H:X H:X H:X fromM Load Load X from M X X X M from Load Move Logical ShiftRight asASL) (Same Logical ShiftLeft prto Description Operation Table 8-1.Instruction H:X 0 C (M) M M M X A ← Destination b7 ← ← ← ← ← (H:X) +1(IX+D, DIX+) b7 Set Summary (Continued) Set Summary ← –(M) = $00 –(M) = $00 –(M) –(M) = $00 –(M) = $00 –(M) –(M) = $00 –(M) –(X) = $00 – (X) –(X)=$00 –(A) = $00 – (A) –(A)=$00 (A[3:0]:A[7:4]) 3 62 ––––––INH ← ( ← ← ← (X) M:M

()0–– – 0 (M) ()0–– – 0 (M) ← × (M)

( )–––IH4 5 42 –0–––0INH (A) + 1 b0 b0 Source ) U Freescale Semiconductor PU) C 0 H NZC VHI 0–– ↕ 0–– ↕ ↕ Effect on –– ––0 –– CCR ↕↕ ↕↕ ↕↕↕ ↕↕ ↕↕ ↕↕↕ ↕↕ – – – – IX+D IMD DIX+ DD SP1 IX IX1 INH INH DIR SP2 SP1 IX IX1 IX2 EXT DIR IMM DIR IMM SP2 SP1 IX IX1 IX2 EXT DIR IMM SP1 IX IX1 INH INH DIR SP1 IX IX1 INH INH DIR

08AZ60 — Rev 1.1 Rev — 08AZ60 Address Mode DE CE DE EE BE AE EE D6 D6 C6 FE 7E 6E 5E 4E 9E 9E E6 9E E6 B6 A6 9E 9E 9E 9E F6 60 70 60 50 40 30 55 45 68 78 68 58 48 38 64 74 64 54 44 34 Opcode dd dd ii dd dd dd ff ff dd ff ee ff ff ff ee ll hh dd ii dd jj ii ff ee ff ff ff ee ll hh dd ii ff ff dd ff ff dd Operand 4 4 4 5 5 3 4 1 1 4 5 4 2 3 4 4 3 2 4 3 5 4 2 3 4 4 3 2 5 3 4 1 1 4 5 3 4 1 1 4 Cycles Central Processing Unit (CPU) Instruction Set Summary

Table 8-1. Instruction Set Summary (Continued)

Effect on Source CCR Operation Description Form VHI NZC Address Mode Opcode Operand Cycles

AA ii dd ORA #opr IMM BA hh 2 ORA opr DIR CA 3 ORA opr EXT DA ll 4 ee ORA opr,X Inclusive OR A and M A (A) | (M) 0 – – ↕↕– IX2 EA ff 4 ORA opr,X ← IX1 FA 3 ORA ,X IX 9E ff 2 ORA opr,SP SP1 EA ff 4 ORA opr,SP SP2 9E 5 DA ee ff PSHA Push A onto Stack Push (A); SP ← (SP) – 1 ––––––INH 87 2 PSHH Push H onto Stack Push (H); SP ← (SP) – 1 ––––––INH 8B 2 PSHX Push X onto Stack Push (X); SP ← (SP) – 1 ––––––INH 89 2 PULA Pull A from Stack SP ← (SP + 1); Pull (A) ––––––INH 86 2 PULH Pull H from Stack SP ← (SP + 1); Pull (H) ––––––INH 8A 2 PULX Pull X from Stack SP ← (SP + 1); Pull (X) ––––––INH 88 2 39 ROL opr DIR dd 4 ROLA INH 49 1 59 ROLX Rotate Left through Carry C ↕ ––↕↕↕INH 69 1 ROL opr,X IX1 ff 4 ROL ,X b7 b0 IX 79 3 9E ROL opr,SP SP1 69 ff 5

36 ROR opr DIR dd 4 RORA INH 46 1 56 RORX Rotate Right through Carry C ↕ ––↕↕↕INH 66 1 ROR opr,X IX1 ff 4 ROR ,X b7 b0 IX 76 3 9E ROR opr,SP SP1 66 ff 5 RSP Reset Stack Pointer SP ← $FF ––––––INH 9C 1 SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) RTI Return from Interrupt SP ← (SP) + 1; Pull (X) ↕↕↕↕↕↕INH 80 7 SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) RTS Return from Subroutine SP ← SP + 1; Pull (PCH) ––––––INH 81 4 SP ← SP + 1; Pull (PCL) ii A2 dd SBC #opr IMM B2 2 SBC opr DIR C2 hh 3 ll SBC opr EXT D2 ee 4 SBC opr,X ↕ ↕↕↕IX2 E2 4 SBC opr,X Subtract with Carry A ← (A) – (M) – (C) –– IX1 F2 ff 3 ff SBC ,X IX 9E 2 SBC opr,SP SP1 E2 4 SBC opr,SP SP2 9E ff 5 ee D2 ff SEC Set Carry Bit C ← 1 –––––1INH 99 1 SEI Set Interrupt Mask I ← 1 ––1–––INH 9B 2

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Central Processing Unit (CPU) 93

ehia aaMC68HC (C Unit CentralProcessing 94 Technical Data Central Processing Unit(CPU) STA STA STA ,X STA STA STA STA STX STX STX ,X STX STX STX STX STHX W Software Interrupt SWI SUB SUB SUB ,X SUB SUB SUB SUB SUB # TXA Transfer X to A A A (SP) H:X X A Transfer H:X toSP CCR Transfer Xto A Transfer SP toH:X TXS TXA TSX TST TransferTST ,X toA CCR TST Transfer AtoX TSTX TransferTSTA AtoCCR TST TPA TAX TAP TPEnable IRQ STOP Source Form opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr opr ,SP ,SP ,X ,X ,SP ,X ,SP ,SP ,X ,X ,SP ,SP ,X ,X Store A in M M M Store AinM Subtract A Store X in M M M Store XinM Store H:X in M (M:M + (M:M 1) M Store H:Xin etfrNgtv rZr A 0 r()–$0o M 0 – – 0 or(X) –$00or (M)–$00 (A)–$00 Test for Negativeor Zero prto Description Operation Pn tpOclao I Pin;StopOscillator Table 8-1.Instruction PCH PCH PCL PCL SP SP PC PC SP SP ← ← SP ← ← ← Interrupt VectorInterrupt Byte High ← Interrupt Vector Interrupt Low Byte ← ← (SP) –1;Push(CCR) (SP) (SP) –1;Push(PCH) (PC) +1;Push(PCL) (PC) Set Summary (Continued) Set Summary 0;Stop 1 Oscillator 8E ––0–––INH ← (SP)–1;Push(A) (SP)–1;Push(X) (SP) –1;I (SP) ← ← ← ← (A) ← ← ← ← ( C )–––IH8 1 85 ––––––INH (CCR) ( P –––N 52 95 ––––––INH (SP)+ 1 ( : ) – 1–––IH9 2 94 ––––––INH (H:X) – 1 ← ( )–––IH9 1 9F ––––––INH (X) 1 97 ––––––INH (A) ← A – – 0 (A) X – – 0 (X) – (A) (M) (:)0–– – 0 (H:X) ← 1 U Freescale Semiconductor PU) H NZC VHI ↕ ↕↕↕↕↕↕ 9 83 ––1–––INH Effect on –– CCR ↕↕ ↕↕ ↕↕↕ ↕↕ ↕↕ – – – I 5d 4 dd 35 DIR – SP2 SP1 IX IX1 IX2 EXT DIR SP2 SP1 IX IX1 IX2 EXT DIR IMM SP2 SP1 IX IX1 IX2 EXT DIR SP1 IX IX1 2 INH INH DIR 84 INH

08AZ60 — Rev 1.1 Rev — 08AZ60 Address Mode DF CF DF D7 D7 C7 D0 D0 C0 EF EF BF 6D 7D 6D 5D 4D 3D 9E E7 9E E7 B7 9E E0 9E E0 B0 A0 9E 9E FF 9E F7 F0 Opcode ff ee ff ff ff ee ll hh dd ff ee ff ff ff ee ll hh dd ii ff ee ff ff ff ee ll hh dd ff ff dd Operand 5 4 2 3 4 4 3 5 4 2 3 4 4 3 2 5 4 2 3 4 4 3 4 2 3 1 1 3 Cycles Central Processing Unit (CPU) Opcode Map

Table 8-1. Instruction Set Summary (Continued)

Effect on Source CCR Operation Description Form VHI NZC Address Mode Opcode Operand Cycles

A Accumulatorn Any bit C Carry/borrow bitopr Operand (one or two bytes) CCRCondition code registerPC Program counter ddDirect address of operandPCH Program counter high byte dd rrDirect address of operand and relative offset of branch instructionPCL Program counter low byte DDDirect to direct addressing modeREL Relative addressing mode DIRDirect addressing moderel Relative program counter offset byte DIX+Direct to indexed with post increment addressing moderr Relative program counter offset byte ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingSP1 Stack pointer, 8-bit offset addressing mode EXTExtended addressing modeSP2 Stack pointer 16-bit offset addressing mode ff Offset byte in indexed, 8-bit offset addressingSP Stack pointer H Half-carry bitU Undefined H Index register high byteV Overflow bit hh llHigh and low bytes of operand address in extended addressingX Index register low byte I Interrupt maskZ Zero bit ii Immediate operand byte& Logical AND IMDImmediate source to direct destination addressing mode| Logical OR IMMImmediate addressing mode⊕ Logical EXCLUSIVE OR INHInherent addressing mode( ) Contents of IXIndexed, no offset addressing mode–( ) Negation (two’s complement) IX+Indexed, no offset, post increment addressing mode# Immediate value IX+DIndexed with post increment to direct addressing mode« Sign extend

IX1Indexed, 8-bit offset addressing mode← Loaded with IX1+Indexed, 8-bit offset, post increment addressing mode? If IX2Indexed, 16-bit offset addressing mode: Concatenated with MMemory location↕ Set or cleared N Negative bit— Not affected

8.9 Opcode Map

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Central Processing Unit (CPU) 95 ehia aaMC68HC Semiconductor Freescale (CPU) Unit Processing Central 96 Data Technical Central Processing Unit(CPU) Bit Manipulation Branch Read-Modify-Write Control Register/Memory DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX MSB 0 1 2 3 4 5 6 9E6 7 8 9 A B C D 9ED E 9EE F LSB 5 4 3 4 1 1 4 5 3 7 3 2 3 4 4 5 3 4 2 0 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG NEG RTI BGE SUB SUB SUB SUB SUB SUB SUB SUB 3DIR2DIR2REL2DIR1INH1INH2IX13 SP1 1IX 1INH2REL2IMM2DIR3EXT3IX24SP22IX13 SP1 1IX 5 4 3 5 4 4 5 6 4 4 3 2 3 4 4 5 3 4 2 1 BRCLR0 BCLR0 BRN CBEQ CBEQA CBEQX CBEQ CBEQ CBEQ RTS BLT CMP CMP CMP CMP CMP CMP CMP CMP 3DIR2DIR2REL3DIR3IMM3IMM3IX1+ 4 SP1 2IX+1INH2REL2IMM2DIR3EXT3IX24SP22IX13 SP1 1IX 5 4 3 5 7 3 2 3 2 3 4 4 5 3 4 2 2 BRSET1 BSET1 BHI MUL DIV NSA DAA BGT SBC SBC SBC SBC SBC SBC SBC SBC 3DIR2DIR2REL 1INH1INH1INH 1INH 2REL2IMM2DIR3EXT3IX24SP22IX13 SP1 1IX 5 4 3 4 1 1 4 5 3 9 3 2 3 4 4 5 3 4 2 3 BRCLR1 BCLR1 BLS COM COMA COMX COM COM COM SWI BLE CPX CPX CPX CPX CPX CPX CPX CPX 3DIR2DIR2REL2DIR1INH1INH2IX13 SP1 1IX 1INH2REL2IMM2DIR3EXT3IX24SP22IX13 SP1 1IX 5 4 3 4 1 1 4 5 3 2 2 2 3 4 4 5 3 4 2 4 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR LSR TAP TXS AND AND AND AND AND AND AND AND 3DIR2DIR2REL2DIR1INH1INH2IX13 SP1 1IX 1INH1INH2IMM2DIR3EXT3IX24SP22IX13 SP1 1IX 5 4 3 4 3 4 3 4 1 2 2 3 4 4 5 3 4 2 5 BRCLR2 BCLR2 BCS STHX LDHX LDHX CPHX CPHX TPA TSX BIT BIT BIT BIT BIT BIT BIT BIT 3DIR2DIR2REL2DIR3IMM2DIR3IMM 2DIR1INH1INH2IMM2DIR3EXT3IX24SP22IX13 SP1 1IX 5 4 3 4 1 1 4 5 3 2 2 3 4 4 5 3 4 2 6 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR ROR PULA LDA LDA LDA LDA LDA LDA LDA LDA 3DIR2DIR2REL2DIR1INH1INH2IX13 SP1 1IX 1INH 2IMM2DIR3EXT3IX24SP22IX13 SP1 1IX 5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2 7 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR ASR PSHA TAX AIS STA STA STA STA STA STA STA 3DIR2DIR2REL2DIR1INH1INH2IX13 SP1 1IX 1INH1INH2IMM2DIR3EXT3IX24SP22IX13 SP1 1IX 5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2 8 BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL LSL PULX CLC EOR EOR EOR EOR EOR EOR EOR EOR 3DIR2DIR2REL2DIR1INH1INH2IX13 SP1 1IX 1INH1INH2IMM2DIR3EXT3IX24SP22IX13 SP1 1IX 5 4 3 4 1 1 4 5 3 2 1 2 3 4 4 5 3 4 2 9 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL ROL PSHX SEC ADC ADC ADC ADC ADC ADC ADC ADC 3DIR2DIR2REL2DIR1INH1INH2IX13 SP1 1IX 1INH1INH2IMM2DIR3EXT3IX24SP22IX13 SP1 1IX 5 4 3 4 1 1 4 5 3 2 2 2 3 4 4 5 3 4 2 A BRSET5 BSET5 BPL DEC DECA DECX DEC DEC DEC PULH CLI ORA ORA ORA ORA ORA ORA ORA ORA 3DIR2DIR2REL2DIR1INH1INH2IX13 SP1 1IX 1INH1INH2IMM2DIR3EXT3IX24SP22IX13 SP1 1IX 5 4 3 5 3 3 5 6 4 2 2 2 3 4 4 5 3 4 2 B BRCLR5 BCLR5 BMI DBNZ DBNZA DBNZX DBNZ DBNZ DBNZ PSHH SEI ADD ADD ADD ADD ADD ADD ADD ADD 3DIR2DIR2REL3DIR2INH2INH3IX14 SP1 2IX 1INH1INH2IMM2DIR3EXT3IX24SP22IX13 SP1 1IX 5 4 3 4 1 1 4 5 3 1 1 2 3 4 3 2 C BRSET6 BSET6 BMC INC INCA INCX INC INC INC CLRH RSP JMP JMP JMP JMP JMP 3DIR2DIR2REL2DIR1INH1INH2IX13 SP1 1IX 1INH1INH 2DIR3EXT3IX2 2IX1 1IX 5 4 3 3 1 1 3 4 2 1 4 4 5 6 5 4 D BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST TST NOP BSR JSR JSR JSR JSR JSR 3DIR2DIR2REL2DIR1INH1INH2IX13 SP1 1IX 1INH2REL2DIR3EXT3IX2 2IX1 1IX 5 4 3 5 4 4 4 1 2 3 4 4 5 3 4 2 E BRSET7 BSET7 BIL MOV MOV MOV MOV STOP LDX LDX LDX LDX LDX LDX LDX LDX 3DIR2DIR2REL 3DD2DIX+ 3IMD 2IX+D 1INH * 2IMM2DIR3EXT3IX24SP22IX13 SP1 1IX 5 4 3 3 1 1 3 4 2 1 1 2 3 4 4 5 3 4 2 F BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR CLR WAIT TXA AIX STX STX STX STX STX STX STX 3DIR2DIR2REL2DIR1INH1INH2IX13 SP1 1IX 1INH1INH2IMM2DIR3EXT3IX24SP22IX13 SP1 1IX 08AZ60 — Rev 1.1 Rev — 08AZ60 INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset MSB IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset 0 High Byte of Opcode in Hexadecimal DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with LSB EXT Extended IX2 Indexed, 16-Bit Offset Post Increment 5 Cycles DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with Low Byte of Opcode in Hexadecimal 0 BRSET0 Opcode Mnemonic IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment 3DIRNumber of Bytes / Addressing Mode *Pre-byte for stack pointer indexed instructions Table 8-2. Opcode Map Technical Data — MC68HC08AZ60

Section 9. System Integration Module (SIM)

9.1 Contents

9.2 Introduction...... 98 9.3 SIM Bus Clock Control and Generation ...... 100 9.3.1 Bus Timing ...... 100 9.3.2 Clock Startup from POR or LVI Reset ...... 101 9.3.3 Clocks in Stop Mode and Wait Mode ...... 101 9.4 Reset and System Initialization...... 102 9.4.1 External Pin Reset ...... 102 9.4.2 Active Resets from Internal Sources ...... 103 9.4.2.1 Power-On Reset ...... 104

9.4.2.2 Computer Operating Properly (COP) Reset...... 105 9.4.2.3 Illegal Opcode Reset ...... 105 9.4.2.4 Illegal Address Reset...... 105 9.4.2.5 Low-Voltage Inhibit (LVI) Reset ...... 106 9.5 SIM Counter...... 106 9.5.1 SIM Counter During Power-On Reset...... 106 9.5.2 SIM Counter During Stop Mode Recovery ...... 107 9.5.3 SIM Counter and Reset States ...... 107 9.6 Program Exception Control...... 107 9.6.1 Interrupts...... 108 9.6.2 Reset ...... 111 9.6.3 Break Interrupts ...... 111 9.6.4 Status Flag Protection in Break Mode ...... 112 9.7 Low-Power Modes ...... 112 9.7.1 Wait Mode ...... 112 9.7.2 Stop Mode ...... 114 9.8 SIM Registers ...... 116 9.8.1 SIM Break Status Register...... 116

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor System Integration Module (SIM) 97 ehia aaMC68HC Semiconductor Freescale (SIM) Module Integration System 98 Technical Data 9.2 Introduction System IntegrationModule(SIM) that coordinatesCPUan the SIMinput/output(I/O)registers. diagram oftheSIMisshownin central processorunit(CPU),theSIM supports upto32externaland/orinte This sectiondescribes SIM BreakFlagControlRegister SIM ResetStatusRegister 9.8.3 9.8.2 Modular architectureexp • CPU enable/disable timing • Interrupt control: • Master resetcontrol,incl • Bus clockgenerationandcont • Vector addressgeneration – timing control Arbitration – Acknowledge timing – computer operatingpr Internal clockcontrol – Stop/wait/reset/bre – the systemintegration d exceptiontiming.TheSI operly (COP)timeout ak entryandrecovery uding power-onreset(POR)and andable to128interruptsources Figure 9-1 The SIMisasystemstatecontroller rol forCPUandperipherals controls allMCUactivities.Ablock rnal interrupts. . . Figure 9-2 . module (SIM),which M isresponsiblefor: Together withthe . isasummaryof 08AZ60 — Rev 1.1 Rev — 08AZ60 . 119 118 System Integration Module (SIM) Introduction

MODULE STOP MODULE WAIT STOP/WAIT CPU STOP (FROM CPU) CONTROL CPU WAIT (FROM CPU) SIMOSCEN (TO CGM)

SIM COP CLOCK COUNTER

CGMXCLK (FROM CGM) CGMOUT (FROM CGM)

÷ 2

CLOCK CONTROL CLOCK GENERATORS INTERNAL CLOCKS

RESET POR CONTROL LVI (FROM LVI MODULE) PIN LOGIC MASTER ILLEGAL OPCODE (FROM CPU) RESET PIN CONTROL RESET ILLEGAL ADDRESS (FROM ADDRESS CONTROL MAP DECODERS) SIM RESET STATUS REGISTER COP (FROM COP MODULE)

RESET

INTERRUPT CONTROL INTERRUPT SOURCES AND PRIORITY DECODE CPU INTERFACE

Figure 9-1. SIM Block Diagram

Register Name Bit 7 6 5 4 3 2 1 Bit 0

SIM Break Status Register (SBSR) RRRRRRSBSWR

SIM Reset Status Register (SRSR) POR PIN COP ILOP ILAD 0 LVI 0

SIM Break Flag Control Register (SBFCR)BCFERRRRRRR

R=Reserved Figure 9-2. SIM I/O Register Summary

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor System Integration Module (SIM) 99 ehia aaMC68HC Semiconductor Freescale (SIM) Module Integration System 100 Technical Data 9.3.1 BusTiming 9.3 SIMBusClockControl andGeneration System IntegrationModule(SIM) divided byfour.(See output (CGMXCLK)divided byfour In usermode Generation Module(CGM) from eitheranexternal incoming clock,CG peripherals ontheMCU.Thesyst The busclockgeneratorprovides Table 9-2 inlNm Description Signal Name GVL PLL Output CGMVCLK CGMXCLK CGMOUT PORRST Signal from the Power-On the SIM the from to Signal Module Reset PORRST IRST Internal Reset Signal Reset Internal IRST R/W IDB Internal Data Bus Data Internal IDB IAB Internal Address Bus Address Internal IAB showstheinternalsignalna , Table 9-1.I/ORegisterAddress Summary theinternalbusfr Address Register Table 9-2.SignalNameConventions PLL-Basedor OSC1-Based Clock Output from CGMModule Buffered Version Module Clock Generator from OSC1 of Read/Write SignalRead/Write MOUT, asshownin (Bus Clock = CGMOUT Divided by CGMOUT Two) = Clock (Bus (CGM) Clock Generation oscillator or from or oscillator F0 F0 $FE03 $FE01 $FE00 BRSS SBFCR SRSR SBSR on page121). equency iseithert em clocksaregeneratedfroman system clocksignal orthePLLoutput(CGMVCLK) mes usedinthissection. Figure 9-3 the on-chipPLL.(See Module (CGM) . Thisclockcancome he crystaloscillator s fortheCPUand 08AZ60 — Rev 1.1 Rev — 08AZ60 on page121). Clock System Integration Module (SIM) SIM Bus Clock Control and Generation

9.3.2 Clock Startup from POR or LVI Reset

When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after 4096 CGMXCLK cycles. The RST pin is driven low by the SIM during this entire period. The bus clocks start upon completion of the timeout.

CGMXCLK OSC1 SIM COUNTER

CLOCK A CGMOUT SELECT ÷ 2 ÷ 2 BUS CLOCK CGMVCLK CIRCUIT B S* GENERATORS *When S = 1, CGMOUT = B BCS PLL SIM

PTC3 MONITOR MODE

USER MODE

CGM

Figure 9-3. CGM Clock Signals

9.3.3 Clocks in Stop Mode and Wait Mode

Upon exit from stop mode by an interrupt, break, or reset, the SIM allows CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 CGMXCLK cycles. See Stop Mode on page 114.

In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor System Integration Module (SIM) 101 ehia aaMC68HC Semiconductor Freescale (SIM) Module Integration System 102 Technical Data 9.4.1 ExternalPinReset 9.4 ResetandSystemInitialization System IntegrationModule(SIM) 9-4 nor theLVIwassour for aminimumof67CG asRST register(SRSR)issetaslong of theSIMresetstatus Pulling theasynchronousRST corresponding bitintheSIMrese 106), butanexternal An internalresetclea returned tothei all registerstobereturnedthei monitor mode)andassert All oftheseresetsproducethe The MCUhastheseresetsources: Registers Low-voltageinhi • Computer operatingpr • Illegal address • Illegal opcode • External resetpin(RST • (POR) module reset Power-on • shows the relative timing. timing. therelative shows ee yeNumberof Cycles Required to Set PIN Reset Type on page116). l tes67 (64 +3) All others POR/LVI 4163 (4096 + 64 + 3) (4096 4163 POR/LVI r resetstates. Table 9-3.PINBitSetTiming rs theSIMcounter(see reset doesnot.Eachoftheresetssetsa bit module (LVI) module bit ce ofthereset.See MXCLK cycles,assumingt the internalresetsignal operly module(COP) ) pinlowhaltsallpr vector $FFFE–FFFF r defaultvaluesandallmodulestobe t statusregister(SRSR)(see Table 9-3 SIM Counter ocessing. ThePINbit (IRST).IRSTcauses hat neitherthePOR ($FEFE–FEFF in fordetails. 08AZ60 — Rev 1.1 Rev — 08AZ60 on page isheldlow SIM Figure System Integration Module (SIM) Reset and System Initialization

CGMOUT

RST

IAB PC VECT H VECT L

Figure 9-4. External Reset Timing

9.4.2 Active Resets from Internal Sources

All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (see Figure 9- 5). An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR (see Figure 9-6). Note that for LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles during which the SIM forces the RST pin low. The internal reset signal then follows the

sequence from the falling edge of RST shown in Figure 9-5.

The COP reset is asynchronous to the bus clock.

The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU.

IRST

RST RST PULLED LOW BY MCU

32 CYCLES 32 CYCLES CGMXCLK

IAB VECTOR HIGH

Figure 9-5. Internal Reset Timing

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor System Integration Module (SIM) 103 ehia aaMC68HC Semiconductor Freescale (SIM) Module Integration System 104 Technical Data 9.4.2.1 Power-OnReset System IntegrationModule(SIM) At power-on, the foll the At power-on, sequence tooccur. CPU andmemoriesarere 4096 CGMXCLKcycles.Anothersixty-f external resetpin(RST (POR) generatesapul When powerisfirstappliedtothe ThePOR bitoftheSIM • TheRST • Internal clockstothe CPUandm • TheSIM enablesCGMOUT. • Theinternal reset • A PORpulseisgenerated. • other bitsinthe CGMXCLK cyclestoal pinisdrivenlowduringth Figure 9-6.Sources ILLEGAL ADDRESSRST ILLEGAL OPCODE RST owing eventsoccur: register arecleared. se toindicatethatpow ) isheldlowwhilethe signal isasserted. leased fromresettoa COPRST low stabilizationoftheoscillator. POR reset statusregister LVI MCU, thepower-onresetmodule of InternalReset odules areheldi our CGMXCLKcycleslater,the e oscillatorstabilizationtime. INTERNAL RESET er-on hasoccurred.The SIM countercountsout llow theresetvector (SRSR) issetandall nactive for4096 08AZ60 — Rev 1.1 Rev — 08AZ60 System Integration Module (SIM) Reset and System Initialization

OSC1

PORRST

4096 32 32 CYCLES CYCLES CYCLES

CGMXCLK

CGMOUT

RST

IAB $FFFE $FFFF

Figure 9-7. POR Recovery

9.4.2.2 Computer Operating Properly (COP) Reset

The overflow of the COP counter causes an internal reset and sets the

COP bit in the SIM reset status register (SRSR) if the COPD bit in the CONFIG-1 register is at logic zero. See Computer Operating Properly (COP) on page 171.

9.4.2.3 Illegal Opcode Reset

The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset.

If the stop enable bit, STOP, in the MOR register is logic zero, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset.

9.4.2.4 Illegal Address Reset

An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor System Integration Module (SIM) 105 ehia aaMC68HC Semiconductor Freescale (SIM) Module Integration System 106 Technical Data 9.5.1 SIMCounter 9.5 SIMCounter System IntegrationModule(SIM) 9.4.2.5 Low-Voltage During Power-OnReset Inhibit (LVI)Reset V pin willbeheldlowunt counter overflowsuppliesthecl a prescalerforthecomputeroperati status register(SRSR)is At power-on,thePOR ci The power-onresetmodule (POR)dete counter is12bitslongandclo enabling theinternalbus(I stop moderecoverytoallowtheos The SIMcounterisusedbythepow See CPU isreleasedfromresettoallo and LVIRSTDbitsintheCONFIG-1re user’s responsibilitytocheck sizes maybehaveinadifferentman in illegaladdresses eventually shrunkintoa Extra careshouldbeexer generate areset. resetting theMCU.Adatafetch Also notethatsomeHC the V the illegal addresses. always checkrelevantdatabo with datafetches The low-voltageinhibitm DD risesaboveV Low VoltageInhibit(LVI) DD voltagefallstotheV LVIR under certaincircum being accessed.Devices . Anothersixty-fourCGMX il theSIMcounts4096CGMXCLKcyclesafter rcuit asserts the signal PORRST. Once the SIM SIM Oncethe PORRST. signal assertsthe rcuit set andachipresetis odule (LVI)assertsitsoutputtotheSIMwhen 08 devicesgenerateil BUS) clocks.TheSIMc smaller ROMsize.Code cised ifcoderunning LVII ock fortheCOPmodule.TheSIM voltage.TheLVIbi on page177. cked bythefallingedgeofCGMXCLK. from anunmappedaddressdoesnot oks andalwayschecktheircodefor their codefor w theresetvectorsequencetooccur. cillator timetostabilizebefore ng properlymodule er-on resetmodule(POR)andin gister areatlogiczero.TheRST ner inthisinst cts powerappli stances. User’sshould asserted iftheLVIPWRD illegal addresses. with smallerROM CLK cycleslater,the legal addressresets ounter alsoservesas in thesepartsis t intheSIMreset errorsmayresult ance. Isisthe (COP).TheSIM ed totheMCU. 08AZ60 — Rev 1.1 Rev — 08AZ60

System Integration Module (SIM) Program Exception Control

is initialized, it enables the clock generation module (CGM) to drive the bus clock state machine.

9.5.2 SIM Counter During Stop Mode Recovery

The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask option register. If the SSREC bit is a logic one, then the stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared.

9.5.3 SIM Counter and Reset States

External reset has no effect on the SIM counter. See Stop Mode on

page 114 for details. The SIM counter is free-running after all reset states. See Active Resets from Internal Sources on page 103 for counter control and internal reset recovery sequences.

9.6 Program Exception Control

Normal, sequential program execution can be changed in three different ways:

• Interrupts – Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) • Reset • Break interrupts

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor System Integration Module (SIM) 107 ehia aaMC68HC Semiconductor Freescale (SIM) Module Integration System 108 Technical Data 9.6.1 Interrupts System IntegrationModule(SIM) INTERRUPT MODULE I BIT R/W IDB IAB DUMMY DUMMY 9-9 until thelatchedinterruptisservic the SIM,nootherinterruptcantake uses todeterminewhichve of interruptprocessing. Interrupts arelatched, 9-10 processing canresume. regist CPU the recovers additional interrupts.At contents onthesta At thebeginningofan SP PC – 1[7:0] . showsinterruptrecoverytiming. SP – 1 Figure 9-8 PC –1[15:8] SP – 2 ck and sets the interrupt ma interrupt the sets ck and X . Interrupt Entry SP –3 interrupt,theCPUsa and arbitrationisperformedin The arbitrationresultis the endofaninterrupt er contentsfromthe Figure 9-8 A ctor tofetch.Oncean SP –4 ed (ortheIbitiscleared),see CCR showsinterruptentrytiming. precedence,regardlessofpriority, VECT H V DATA H ves theCPUregister VECT L VECT stack sothatnormal , theRTIinstruction a constantthattheCPU sk (Ibit) toprevent V DATA L interrupt islatchedby START ADDR theSIMatstart OPCODE 08AZ60 — Rev 1.1 Rev — 08AZ60 Figure Figure System Integration Module (SIM) Program Exception Control

FROM RESET

YES BREAKI BIT INTERRUPT? SET?

NO

YES I BIT SET?

NO

IRQ YES INTERRUPT?

NO STACK CPU REGISTERS. SET I BIT. (AS MANY INTERRUPTS LOAD PC WITH INTERRUPT VECTOR. AS EXIST ON CHIP)

FETCH NEXT INSTRUCTION.

SWI YES INSTRUCTION?

NO

RTI YES INSTRUCTION? UNSTACK CPU REGISTERS.

NO

EXECUTE INSTRUCTION.

Figure 9-9. Interrupt Processing

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor System Integration Module (SIM) 109 ehia aaMC68HC Semiconductor Freescale (SIM) Module Integration System 110 Technical Data System IntegrationModule(SIM) I BIT R/W IDB IAB INTERRUPT MODULE NOTE: SP – 4 it prior toexit it prior addressing mode,softwareshouldsa r service If theinterrupt Families theHregisteris To maintaincompatibilitywi Hardware Interrupts redundant operation. instructions. However,inthecase The LDAopcodeispr executed. routine, thependi interrupt ispendingupon demonstrates whathap execution, thehighestpriority If morethanone otherwise, thenextinstructionisfetchedandexecuted. enable bitisset,theSIMproceed clear intheconditioncoderegister all pendinghardwareinte instruction. Whenthecu of ahardwareinterrupt A hardwareinterruptdoesnotstopt CCR Figure 9-10.In SP – 3 A ing theroutine. SP – 2 interruptispendingatth X ng interruptisservicedbefor SP –1 terrupt Recovery outine modifiest notpushedonthestack efetched bybothth PC – 1 [7:0] – 1 PC beginsaftercomple pens whentwointerruptsarepending.Ifan rrent instructionisco th theM68HC rrupts. Ifinterrupts exit fromtheoriginalinterruptservice SP PC – 1[15:8] interrupt isservicedfirst. s withinterrup ), andifthecorr of theINT1RTIprefetch,thisisa ve theHregister he currentinstruction.Processing PC he Hregisteror OPCODE 05, M6805andM146805 e INT1andINT2RTI e endofaninstruction PC + 1 PC + tion ofthecurrent OPERAND are notmasked(Ibit mplete, theSIMchecks e theLDAinstructionis during interruptentry. t processing; esponding interrupt andthenrestore uses the indexed 08AZ60 — Rev 1.1 Rev — 08AZ60 Figure 9-11

System Integration Module (SIM) Program Exception Control

CLI

BACKGROUND LDA #$FF ROUTINE

INT1 PSHH

INT1 INTERRUPT SERVICE ROUTINE PULH RTI

INT2 PSHH

INT2 INTERRUPT SERVICE ROUTINE PULH RTI Figure 9-11. Interrupt Recognition Example

SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register.

NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC – 1, as a hardware interrupt does.

9.6.2 Reset

All reset sources always have higher priority than interrupts and cannot be arbitrated.

9.6.3 Break Interrupts

The break module can stop normal program flow at a software- programmable break point by asserting its break interrupt output. See Break Module (BRK) on page 153. The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor System Integration Module (SIM) 111 ehia aaMC68HC Semiconductor Freescale (SIM) Module Integration System 112 Technical Data 9.7.1 WaitMode 9.7 Low-PowerModes 9.6.4 StatusFlagPr System IntegrationModule(SIM) otection inBreakMode as normal. Upon leavingbreakmode, even whenthefirststep of oneregisterfollowedby Status flagswithatwo-stepcleari break mode,aflagremainscleared Setting theBCFEbite and writtenduringbreakmo code register,allowinginterruptstooccur. below. BothSTOPandWAITclearthe while inbreakmode.Thisprotection Protecting flagsinbreak break state. cycle aftertheWAITinstruction dur interrupt ifthe isenabled A modulethatisactiveduringwa clocks continuetorun. In waitmode,t non-clocked state.Theoperationofeac consumption modeforst Executing theWAITor enable bit(BCFE)int protected frombeingclea be clearedduringbreakm The SIMcontrolswhetherstatusfl subsection ofeachmodul he CPUclocksareinactivewh he SIMbreakflagcontro nables theclearingmechani Figure 9-12 STOP instructionputst is accomplishedpriorto mode ensuresthatsetflagswillnotbecleared andby situations.TheS red byproperlyinitiali e toseehoweac thereadorwriteof execution ofthesecond ode. Theusercansele de withoutlosingstat it modecanwake ng mechanism—forexample,aread . Stackingfortheinterrupt beginsone ags containedinot showsthetimingfo ing whichtheinte even whenbreakmodeisexited. allows registers interrupt mask(I)inthecondition h ofthesemode h moduleisaffe ile onesetofperipheral another —areprotected, l register(SBFCR). he MCU in a low power- power- he MCUinalow zing thebreakclearflag enteringbreakmode. IM holdstheCPUina us flaginformation. ct whetherflagsare sms. Onceclearedin step willcleartheflag up theCPUwithan rrupt occurred. to befreelyread her modulescan r waitmodeentry. 08AZ60 — Rev 1.1 Rev — 08AZ60 s isdescribed cted bythe System Integration Module (SIM) Low-Power Modes

Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.

Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the configuration register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode.

IAB WAIT ADDR WAIT ADDR + 1 SAME SAME

IDB PREVIOUS DATA NEXT OPCODE SAME SAME

R/W

NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.

Figure 9-12. Wait Mode Entry Timing

IAB $6E0B $6E0C $00FF $00FE $00FD $00FC

IDB $A6 $A6 $A6 $01 $0B $6E

EXITSTOPWAIT

NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt

Figure 9-13. Wait Recovery from Interrupt or Break

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor System Integration Module (SIM) 113 ehia aaMC68HC Semiconductor Freescale (SIM) Module Integration System 114 Technical Data 9.7.2 StopMode System IntegrationModule(SIM) NOTE: recovery period. instruction untilth The SIMcounterisheldinreset st (SBSW) intheSIMbreak A breakinterruptduring clearing theSSRECbit. External crystalapplicati fromstopmode. times applications usingcanned normal delayof4096CGMXCLKcycles usi isselectable time recovery CGMXCLK) instopmode,stopping The SIMdisablestheclockgene time haselapsed.Resetorbreakal mode. Stackingforinte disabled. Aninterruptrequestfroma In stopmode,theSIM register (MOR).IfS CGMXCLK RST IDB IAB $A6 Figure 9-14.WaitRecover $6E0B $A6 Figure 9-15 e beginningofstoprecovery.It SREC isset,stoprecovery counter isresetand rrupts beginsafterthe $A6 stop modesetstheSI ons shouldusethefull oscillators thatdono atus register(SBSR). showsstopmodeentrytiming. Cycles 32 ng the SSREC bit in SSRECbit ng the from theexecutionofSTOP rator moduleoutputs(CGMOUTand so causesanexitfromstopmode. the CPUandperi module cancauseanexitfromstop y fromInternalReset Cycles 32 downto32.Thisisidealfor the systemclocksare selected stoprecovery M breakstop/waitbit isreducedfromthe t requirelongstartup stop recoverytimeby isthenusedtotimethe RST VCT H VCT RST themaskoption pherals. Stop 08AZ60 — Rev 1.1 Rev — 08AZ60 RST VCT L VCT RST System Integration Module (SIM) Low-Power Modes

CPUSTOP

IAB STOP ADDR STOP ADDR + 1 SAME SAME

IDB PREVIOUS DATA NEXT OPCODE SAME SAME

R/W

NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction. Figure 9-15. Stop Mode Entry Timing

STOP RECOVERY PERIOD

CGMXCLK

INT/BREAK

IAB STOP +1 STOP + 2 STOP + 2 SP SP – 1 SP – 2 SP – 3

Figure 9-16. Stop Mode Recovery from Interrupt or Break

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor System Integration Module (SIM) 115 ehia aaMC68HC Semiconductor Freescale (SIM) Module Integration System 116 Technical Data 9.8.1 SIMBreakStatusRegister 9.8 SIMRegisters System IntegrationModule(SIM) drs:$FE00 Address: clears it. following codeisanexampleofthis modify thereturnaddressonst SBSW canbereadwithin SBSW —SIMBreakStop/Wait caused anexitfromst The SIMbreakstatus The SIMhasthreememorymappedregisters. ee:0 Reset: Read: rt:SeeNote Write: logic 0toit.ResetclearsSBSW. mode afterexitingfrom This statusbitisuseful 0 =Stopmodeorwait 1 =Stopmodeorwa Bit 7654321Bit 0 eevdNOTE:Writingalogic 0clearsSBSW Reserved = R RRRRRR Figure 9-17.SIMBreakSt op orwaitmode. register contains in applicationsrequiringa the breakstateSWIr it modewasexitedby a breakinterrupt.Clear modewasnotexitedbybreakinterrupt ack bysubtractin . WritingzerototheSBSWbit atus Register(SBSR) aflagtoindica outine. Theusercan breakinterrupt SBSWbywriting a return towaitorstop g onefromit.The te thatabreak 08AZ60 — Rev 1.1 Rev — 08AZ60 SBSW R System Integration Module (SIM) SIM Registers

; This code works if the H register has been pushed onto the stack in the break ; service routine software. This code should be executed at the end of the ; break service routine software. HIBYTE EQU 5 LOBYTE EQU 6 ; If not SBSW, do RTI BRCLR SBSW,SBSR, RETURN ; See if wait mode or stop mode was exited ; by break. TST LOBYTE,SP ; If RETURNLO is not zero, BNE DOLO ; then just decrement low byte. DEC HIBYTE,SP ; Else deal with high byte, too. DOLO DEC LOBYTE,SP ; Point to WAIT/STOP opcode. RETURN PULH ; Restore H register. RTI

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor System Integration Module (SIM) 117 ehia aaMC68HC Semiconductor Freescale (SIM) Module Integration System 118 Technical Data 9.8.2 SIMReset System IntegrationModule(SIM) Status Register drs:$FE01 Address: LVI —Low-VoltageI ILAD —IllegalAddressRese ILOP —IllegalOpcodeResetBit COP —ComputerOperati Bit PIN —ExternalReset ResetBit POR —Power-On sets thePORbitandclearsall status registerwillautomaticallycl This registercontainssix ed O I O LPIA V 0 LVI 0 ILAD ILOP COP PIN POR Read: Write: POR:10000000 0 =PORorreadofSRSR 1 =LastresetwascausedbytheLVIcircuit 0 =PORorreadofSRSR 1 =Lastresetcausedbyanopcode 0 =PORorreadofSRSR 1 =Lastresetcaused 0 =PORorreadofSRSR 1 =LastresetcausedbyCOPcounter 0 =PORorreadofSRSR 1 =Lastresetcausedbyexternalpin(RST of SRSR 0 =Read 1 =LastresetcausedbyPORcircuit Bit 7654321Bit 0 Figure 9-18.SIMReset = Unimplemented nhibit ResetBit flags thatshowthesource ng ProperlyResetBit by anillegalopcode t Bit(opcodefetchesonly) other bitsin ear afterreadingit.Apower-onreset Status Register(SRSR) fetch fromanillegaladdress the register. ofthelastreset.The ) 08AZ60 — Rev 1.1 Rev — 08AZ60 System Integration Module (SIM) SIM Registers

9.8.3 SIM Break Flag Control Register

The SIM break control register contains a bit that enables software to clear status bits while the MCU is in a break state.

Address: $FE03 Bit 7654321Bit 0 Read: BCFERRRRRRR Write: Reset: 0 0 R= Reserved Figure 9-19. SIM Break Flag Control Register (SBFCR)

BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set.

1 = Status bits clearable during break 0 = Status bits not clearable during break

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor System Integration Module (SIM) 119 ehia aaMC68HC Semiconductor Freescale (SIM) Module Integration System 120 Technical Data System IntegrationModule(SIM) 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 10. Clock Generation Module (CGM)

10.1 Contents

10.2 Introduction...... 122 10.3 Features...... 122 10.4 Functional Description...... 123 10.4.1 Crystal Oscillator Circuit ...... 123 10.4.2 Phase-Locked Loop Circuit (PLL)...... 126 10.4.2.1 Circuits ...... 126 10.4.2.2 Acquisition and Tracking Modes ...... 127 10.4.2.3 Manual and Automatic PLL Bandwidth Modes . . . . .128 10.4.2.4 Programming the PLL ...... 130 10.4.2.5 Special Programming Exceptions ...... 132 10.4.3 Base Clock Selector Circuit ...... 132 10.4.4 CGM External Connections ...... 133 10.5 I/O Signals ...... 134 10.5.1 Crystal Amplifier Input Pin (OSC1) ...... 134 10.5.2 Crystal Amplifier Output Pin (OSC2) ...... 134 10.5.3 External Filter Capacitor Pin (CGMXFC) ...... 134 10.5.4 Analog Power Pin (VDDA)...... 135 10.5.5 Oscillator Enable Signal (SIMOSCEN) ...... 135 10.5.6 Crystal Output Frequency Signal (CGMXCLK) ...... 135 10.5.7 CGM Base Clock Output (CGMOUT) ...... 135 10.5.8 CGM CPU Interrupt (CGMINT) ...... 135 10.6 CGM Registers ...... 136 10.6.1 PLL Control Register ...... 136 10.6.2 PLL Bandwidth Control Register ...... 138 10.6.3 PLL Programming Register...... 140 10.7 Interrupts...... 142 10.8 Low-Power Modes ...... 142

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Clock Generation Module (CGM) 121 ehia aaMC68HC Semiconductor Freescale (CGM) Module Generation Clock 122 Technical Data 10.3 Features 10.2 Introduction Clock Generation Module (CGM) Features oftheCGMinclude: loop (PLL)clock,CGMVCLK,divi is basedoneitherthecrystalclo signal, CGMOUT,fromwhichthe at thefrequencyofcrystal.The The CGMgeneratesthecrystalclocksi Reaction TimeCalculation 10.10.4 Choosing a 10.10.3 Acquisition/Lock 10.10 CGM DuringBreakInterrupts 10.9 Stop Mode Mode Wait 10.8.2 10.8.1 resonators. ThePLL generator designedforusewith1-MH Parametric In 10.10.2 Acquisition/Lock 10.10.1 using a32-MHzcrystal. • CPU Interrupt on Entry or or Entry Interrupton CPU • Automatic FrequencyLockDetector • Automatic BandwidthControl • Programmable HardwareVoltage-C • Phase-Locked Loopwith • Low-Jitter Operation Low-Jitter the CrystalReference can generatean8-MHz . . Filter Capacitor fluences onReactionTime Time Specifications Time Definitions Output FrequencyinIntegerMultiplesof Exit fromLockedCondition ck dividedbytwoorthephase-locked ded bytwo.TheP system clocksarederived.CGMOUT CGM alsogeneratesthebaseclock Mode forLow-Jitt . . z to8-MHzcrystalsorceramic gnal, CGMXCLK,whichoperates . . . ontrolled Oscillat bus frequencywithout . . LL isafrequency . . . . . er Operation . 08AZ60 — Rev 1.1 Rev — 08AZ60 or (VCO)for 146 143 142 147 143 145 143 143 Clock Generation Module (CGM) Functional Description

10.4 Functional Description

The CGM consists of three major submodules:

• Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency clock, CGMXCLK. • Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock CGMVCLK. • Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The system clocks are derived from CGMOUT.

Figure 10-1 shows the structure of the CGM.

10.4.1 Crystal Oscillator Circuit

The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2

pin is the output. The SIMOSCEN signal enables the crystal oscillator circuit.

The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.

CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related external components.

An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Clock Generation Module (CGM) 123 ehia aaMC68HC Semiconductor Freescale (CGM) Module Generation Clock 124 Technical Data Clock Generation Module (CGM) OSC1 CGMRDV DETECTOR DETECTOR GVVCGMVCLK CGMVDV PHASE LOCK LOCK V DDA CGMRCLK GXCV CGMXFC AUTO Figure 10-1.CGMBlockDiagram FREQUENCY BANDWIDTH MUL7–MUL4 CONTROL DIVIDER FILTER LOOP ACQ PLL ANALOG SS CIRCUIT SELECT CLOCK PLLIE BCS CONTROLLED OSCILLATOR INTERRUPT VRS7–VRS4 CONTROL VOLTAGE PLLF ÷

2 B A S* CGMINT *When S =1, *When CGMOUT = B CGMXCLK CGMOUT 08AZ60 — Rev 1.1 Rev — 08AZ60 USER MODE MONITOR MODE PTC3 Clock Generation Module (CGM) Functional Description

Register NameBit 7654321Bit 0 Read: PLLF 1111 PLLIE PLLON BCS PLL Control Register (PCTL) Write: Reset:00101111

Read: LOCK 0000 PLL Bandwidth Control Register AUTO ACQ XLD Write: (PBWC) Reset:00000000

Read: MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4 PLL Programming Register (PPG) Write: Reset:01100110

= Unimplemented

Figure 10-2. I/O Register Summary

Table 10-1. I/O Register Address Summary

Register PCTL PBWC PPG

Address $001C $001D $001E

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Clock Generation Module (CGM) 125 ehia aaMC68HC Semiconductor Freescale (CGM) Module Generation Clock 126 Technical Data 10.4.2.1 Circuits 10.4.2 Phase-LockedLoopCircuit(PLL) Clock Generation Module (CGM) reduces theVCOclockbyafactor, back throughaprogrammablemodul with thefinalreference The phasedetectorthencomparesth Programming thePLL clock,CGMVDV,r feedback based onthephasedi The VCO’soutputclock,CGMVCLK,running atafrequencyf at afrequencyf buffer. Thebufferoutputis frequency, f within thisrange. Modulating thevoltageonCG from roughlyone-halftotwice supply andCGMXFC frequencies andformaximumimmunity The operatingrangeoftheVCOis The PLLconsistsofthesecircuits: modes eitherautomat frequency. ThePLLcanchangebetw mode ortrackingmode, The PLLisafrequencygene CGMRCLK runsat clock, PLLreference CGMRCLK isthe Lockdetector • Loopfilter • Phase detector • Modulo VCOfr • Voltage-controlled • NOM RDV , (4.9152MHz)timesa Bydesign,f afrequency,f =f equency divider ically ormanually. noise. TheVCOfrequency fference betweenthetwo si RCLK clock, CGMRDV.A onpage130formo dependingonthea oscillator (VCO) thefinalreferencecl . unning at a frequency f atafrequency unning VRS rator thatcanoperate the center-of-rangefrequency,f isequaltothenom RCLK MXFC pinchangesthefrequency programmable forawiderangeof N. Thedivider’sout o divider.Themodulodivider e VCOfeedbackclock,CGMVDV, een acquisitionandtracking abufferedversio , andisfedtot toexternalnoise,including linear factorLor(L)f correction pulseisgenerated ccuracy oftheoutput re information. ock, CGMRDV,running is boundtoarange gnals. Theloopfilter VDV in eitheracquisition inal center-of-range he PLLthrougha n ofCGMXCLK. put istheVCO 08AZ60 — Rev 1.1 Rev — 08AZ60 =f VCLK VCLK NOM VRS /N. See . , isfed . Clock Generation Module (CGM) Functional Description

then slightly alters the dc voltage on the external capacitor connected to CGMXFC based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, as described in Acquisition and Tracking Modes on page 127. The value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the PLL.

The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final reference frequency, fRDV. The circuit determines the mode of the PLL and the lock condition based on this comparison.

10.4.2.2 Acquisition and Tracking Modes

The PLL filter is manually or automatically configurable into one of two operating modes:

• Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL

startup or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in the PLL bandwidth control register. See PLL Bandwidth Control Register on page 138. • Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected as the base clock source. See Base Clock Selector Circuit on page 132. The PLL is automatically in tracking mode when it’s not in acquisition mode or when the ACQ bit is set.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Clock Generation Module (CGM) 127 ehia aaMC68HC Semiconductor Freescale (CGM) Module Generation Clock 128 Technical Data 10.4.2.3 Manuala Clock Generation Module (CGM) nd AutomaticPLLBandwidthModes mode: These conditionsapplywhen action, dependingont suffered aseverenoise as thesourceforbaseclockand See bit isset,theVCOclocksafetouseassourceforbaseclock. startup, usually)orat are disabled,softwarecanpollthe CPU interruptrequestandthencheck CPU interruptrequests CGMOUT. See CGMVCLK,issafetous VCO clock, Automatic bandwidthc automatically switchesbetween In automaticbandwidth manually orautomatically. The PLLcanchangethebandwidthoroper TheLOCKbitissetwhentheVCO • TheACQ • TheACQ • TheLOCKbitisaread-onlyindica • Base ClockSelectorCircuit a certaintolerance, tolerance, PLL. certain tolerance, tolerance, Tracking Modes read-only indicatorofthemodefilter.See 430. 430. bitissetwhentheVCOfr bit(See10.6.2PLLBandwidth PLL BandwidthControlRegister ∆ ∆ Lock trk , andisclearedwhentheVCO periodic intervals. Inei intervals. periodic , andisclearedwhentheVCOfrequencyout of he application.See ontrol modealsoisus controlmode(AUTO= hitandthesoftwaremu are enabled,thesoftware on page127. ∆ unt ∆ unl . See thePLLisinautomaticbandwidthcontrol . See acquisition andtrackingmodes. Electrical S on page132.Ift LOCK bitcontinuously(duringPLL Electrical Specifications theLOCKbitis e asthesourceforbaseclock, the LOCKbit.If tor ofthelockedstate frequency iswithinacertain equency iswithinacertain Interrupts ational modeof ther case,whentheLOCK ed todetermi pecifications ControlRegister.)isa 1), thelockdetector st takeappropriate canwaitforaPLL frequencyisoutofa on page138.IfPLL he VCOisselected clear, thePLLhas on page142. Acquisition and CPUinterrupts 08AZ60 — Rev 1.1 Rev — 08AZ60 ne whenthe the loopfilter on page on page Clock Generation Module (CGM) Functional Description

• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling the LOCK bit. See PLL Control Register on page 136.

The PLL also can operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below fbusmax and require fast startup. The following conditions apply when in manual mode:

•ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. • Before entering tracking mode (ACQ = 1), software must wait a given time, tacq (see Electrical Specifications on page 430), after turning on the PLL by setting PLLON in the PLL control register (PCTL).

• Software must wait a given time, tal, after entering tracking mode before selecting the PLL as the clock source to CGMOUT (BCS = 1). • The LOCK bit is disabled. • CPU interrupts from the CGM are disabled.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Clock Generation Module (CGM) 129 ehia aaMC68HC Semiconductor Freescale (CGM) Module Generation Clock 130 Technical Data 10.4.2.4 ProgrammingthePLL Clock Generation Module (CGM) variables usedand Use this9-stepprocedure .CalculatetheVCOfrequency,f 4. Calculatethedesir 2. .Usingareferencefrequency,f 3. Choosethedesiredbusfrequency,f 1. f f VCLKDES nearest integer. calculate theVCOfrequencymultipli Example: f Example: f aibeDefinition Variable BUSDES f f f f f RCLK VCLK NOM VRS BUS Example: f Example: f VCLKDES VCLKDES BUSDES theirmeaning. Table 10-2.Variable Definitions Nominal VCO CenterFrequency ClockCalculated Bus Frequency Clock Calculated VCO Frequency Chosen ReferenceFrequency Crystal DesiredClock VCO Frequency ClockDesired Bus Frequency Shifted VCOCenter Frequency f VCLK VCLK ed VCOfrequency,f =8MHz toprogramthePLL. N =4 =4 =8 N = = =8 Nf × × × f ------32 MHz 8MHz=32 f VCLKDES 4 MHz 4 MHz = 32 MHz =32 4MHz f × BUSDES RCLK RCLK RCLK ------VCLK , equaltothecrystalfrequency, = . er, N.Roundtheresultto BUSDES VCLKDES The tablebelowliststhe . . 08AZ60 — Rev 1.1 Rev — 08AZ60 Clock Generation Module (CGM) Functional Description

5. Calculate the bus frequency, fBUS, and compare fBUS with fBUSDES.

f f = ------VCLK BUS 4

32 MHz Example: f =8------= MHz BUS 4

6. If the calculated fbus is not within the tolerance limits of your application, select another fBUSDES or another fRCLK.

7. Using the value 4.9152 MHz for fNOM, calculate the VCO linear range multiplier, L. The linear range multiplier controls the frequency range of the PLL.

fVCLK L= round------fNOM

32 MHz Example: L = ------= 7 4.9152 MHz

8. Calculate the VCO center-of-range frequency, fVRS. The center- of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL.

fVRS = L × fNOM

Example: fVRS = 7 × 4.9152 MHz = 34.4 MHz fNOM NOTE: For proper operation,f – f ≤ ------. VRS VCLK 2 Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU.

9. Program the PLL registers accordingly: a. In the upper four bits of the PLL programming register (PPG), program the binary equivalent of N. b. In the lower four bits of the PLL programming register (PPG), program the binary equivalent of L.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Clock Generation Module (CGM) 131 ehia aaMC68HC Semiconductor Freescale (CGM) Module Generation Clock 132 Technical Data 10.4.3 BaseClockSelectorCircuit 10.4.2.5 SpecialPr Clock Generation Module (CGM) ogramming Exceptions the PLL,sothat 0. Thisvaluewouldsetupacondition be selectedasthebaseclocksource selection ordeselection is selected.ThePLLcannotbetur if thePLLisnotturned CGMOUT. TheVCOclockc The BCSbitinthePLLcont CGMVCLK). or selected clock(CGMXCLK two inputclocksgothro VCO clock,CGMVCLK,as This circuitisusedtoselecteither exceptions: L ismeaninglesswhenusedintheeq 130, doesnotaccountfortw The programmingmethoddescribedin be forcedasthesourceofbaseclock. one-half ofthebaseclockfrequency,is to correctthedutycycle. stasis. Theoutputofthetransitionco one clocksourcetotheother.Duri three CGMXCLKcyclesandCG A 0valueforLdisabl • Nisinterpret for A 0value • source forthebaseclock.See page 132. PLL wouldbedisabledandth on.ThePLLcannot oftheVCOclock.The ugh atransitioncontrolci Therefore,thebusclo thesourceofba rol register(PCTL)sele es thePLLandprevents annot beselectedast o possibleexceptions.Avalueof0forNor ed thesameasavalueof1. ned onoroffsimultaneouslywiththe ng thistime,CGMOUTisheldin the crystalclock, uations given.Toaccountforthese ntrol circuitisthendividedbytwo Base ClockSelectorCircuit if thefactorLisprogrammedtoa inconsistent withtheoperationof MVCLK cyclestochangefrom Programming thePLL one-fourththe beturnedoffif VCOclockalsocannot se clock,CGMOUT.The ck frequency,whichis rcuit thatwaitsupto cts whichclockdrives he baseclocksource e crystalclockwould CGMXCLK, or the CGMXCLK, orthe its selectionasthe frequency ofthe 08AZ60 — Rev 1.1 Rev — 08AZ60 theVCOclock on page on Clock Generation Module (CGM) Functional Description

10.4.4 CGM External Connections

In its typical configuration, the CGM requires seven external components. Five of these are for the crystal oscillator and two are for the PLL.

The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 10-3. Figure 10-3 shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components:

• Crystal, X1

• Fixed capacitor, C1

• Tuning capacitor, C2 (can also be a fixed capacitor)

• Feedback resistor, RB

• Series resistor, RS (optional)

The series resistor (RS) may not be required for all ranges of operation, especially with high-frequency crystals. Refer to the crystal manufacturer’s data for more information.

Figure 10-3 also shows the external components for the PLL:

• Bypass capacitor, CBYP

• Filter capacitor, CF Routing should be done with great care to minimize signal cross talk and noise. (See Acquisition/Lock Time Specifications on page 143 for routing information and more information on the filter capacitor’s value and its effects on PLL performance).

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Clock Generation Module (CGM) 133 ehia aaMC68HC Semiconductor Freescale (CGM) Module Generation Clock 134 Technical Data 10.5.3 ExternalFilter 10.5.2 CrystalAmplif 10.5.1 CrystalAmplif 10.5 I/OSignals Clock Generation Module (CGM) NOTE: CapacitorPin(CGMXFC) ier OutputPin(OSC2) Pin(OSC1) ier Input of othersignalsacross theC CGMXFC pinaspossible withmini To preventnoiseproblems,C corrections. Asmallexternalcapac The CGMXFCpinisrequiredbythe The OSC2pinistheoutput The OSC1pinisaninputtothe The followingparagraphsdescribethe *R S can be 0 (shorted) when usedwithhigher-fr be0(shorted)when can SIMOSCEN

OSC1 C 1 R X Figure 10-3.CGMEx 1 B

OSC2 R C S 2 * ofthecrystal F F connection. shouldbeplacedasclosetothe CGMXCLK equency crystals. Refer to manufacturer’sdata. to equency crystals.Refer crystal oscillatoramplifier. mum routingdistances andnorouting

itor isconnectedtothispin. VSS ternal Connections loop filtertofi CGM input/output oscillator invertingamplifier.

lter outphase CGMXFC C F 08AZ60 — Rev 1.1 Rev — 08AZ60 (I/O)signals.

VDDA C BYP V DD Clock Generation Module (CGM) I/O Signals

10.5.4 Analog Power Pin (VDDA)

VDDA is a power pin used by the analog portions of the PLL. Connect the VDDA pin to the same voltage potential as the VDD pin.

NOTE: Route VDDA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package.

10.5.5 Oscillator Enable Signal (SIMOSCEN)

The SIMOSCEN signal enables the oscillator and PLL.

10.5.6 Crystal Output Frequency Signal (CGMXCLK)

CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fxclk) and comes directly from the crystal oscillator circuit. Figure 10-3 shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be unstable at startup.

10.5.7 CGM Base Clock Output (CGMOUT)

CGMOUT is the clock output of the CGM. This signal is used to generate the MCU clocks. CGMOUT is a 50% duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by two.

10.5.8 CGM CPU Interrupt (CGMINT)

CGMINT is the CPU interrupt signal generated by the PLL lock detector.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Clock Generation Module (CGM) 135 ehia aaMC68HC Semiconductor Freescale (CGM) Module Generation Clock 136 Technical Data 10.6.1 PLLControlRegister 10.6 CGMRegisters Clock Generation Module (CGM) drs:$001C Address: PLLIE —PLLInterruptEnableBit on/off switch,andthebase The PLLcontrolregistercontainst Three registerscontrolandm Reset:00101111 Read: Write: bit. PLLIE cannotbewrittenandreadsas the AUTObitinP request whentheLOCKbit This read/writebitenabl PLL programming • PLL bandwidthcont • PLL controlr • 0 =PLLCPUinterrupt 1 =PLLCPUinterr PLLIE Bit 7654321Bit 0 Figure 10-4.PLLCont Unimplemented = PLLF egister (PCTL) LO BCS PLLON LL bandwidthcontrolregist upt requestsenabled register (PPG) rol register(PBWC) es thePLLtogener clockselectorbit. requestsdisabled onitor operationoftheCGM: toggles, settingthePLLflag,PLLF.When he interruptenablea rol Register(PCTL) logic 0.ResetclearsthePLLIE 1111 ate aCPUinterrupt er (PBWC)isclear, nd flagbits,the 08AZ60 — Rev 1.1 Rev — 08AZ60 Clock Generation Module (CGM) CGM Registers

PLLF — PLL Flag Bit This read-only bit is set whenever the LOCK bit toggles. PLLF generates a CPU interrupt request if the PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit. 1 = Change in lock condition 0 = No change in lock condition

NOTE: Do not inadvertently clear the PLLF bit. Be aware that any read or read- modify-write operation on the PLL control register clears the PLLF bit.

PLLON — PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). See Base Clock Selector Circuit on page 132. Reset sets this bit so that the loop can stabilize as the MCU is powering up. 1 = PLL on

0 = PLL off

BCS — Base Clock Select Bit This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. See Base Clock Selector Circuit on page 132. Reset and the STOP instruction clear the BCS bit. 1 = CGMVCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT

NOTE: PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Clock Generation Module (CGM) 137 ehia aaMC68HC Semiconductor Freescale (CGM) Module Generation Clock 138 Technical Data 10.6.2 PLL Clock Generation Module (CGM)

Bandwidth Cont drs:$001D Address: The PLLbandwidthcontrolregister: register. See CGMVCLKrequire (PLLON =0),selecting PCTL3–PCTL0 —Unimplemented Reset:00000000 Read: Write: In manualoperation,forcesthe • In automaticbandwidthcontrolmode • Indicates whenthePLLislocked • Selects automaticormanual • These bitsprovidenofunction rol Register Figure 10-5.PLLBandwidth mode acquisition ortrackingmode control mode AUTO Bit 7654321Bit 0 Base ClockSelectorCircuit Unimplemented = LOCK ACQ XLD and alwaysread (software-controlled) bandwidth Control Register(PBWC) PLL intoacquisitionortracking s twowritestothePLLcontrol 0000 , indicateswhenthePLLisin on page132. as logic1s. 08AZ60 — Rev 1.1 Rev — 08AZ60 Clock Generation Module (CGM) CGM Registers

AUTO — Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit. 1 = Automatic bandwidth control 0 = Manual bandwidth control

LOCK — Lock Indicator Bit When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0 and has no meaning. Reset clears the LOCK bit. 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked

ACQ — Acquisition Mode Bit When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. 1 = Tracking mode 0 = Acquisition mode

XLD — Crystal Loss Detect Bit When the VCO output, CGMVCLK, is driving CGMOUT, this read/write bit can indicate whether the crystal reference frequency is active or not. 1 = Crystal reference not active 0 = Crystal reference active

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Clock Generation Module (CGM) 139 ehia aaMC68HC Semiconductor Freescale (CGM) Module Generation Clock 140 Technical Data 10.6.3 PLLProgrammingRegister Clock Generation Module (CGM) drs:$001E Address: hardware configurat the modulofeedbackdivider The PLLprogrammingregist Bits 3–0—ReservedforTest MUL7–MUL4 —MultiplierSelectBits Reset:01100110 Read: Write: 3. Read XLD. Read 3. WaitN 2. Writealogic1toXLD. 1. software shouldwrite0stobi software portabilityfr These bitsenabletestfunctionsnot always readsaslogic0. selecting CGMVCLKtodriveCG The crystallossdetectfunctionwor To checkthestatusofcryst Programming thePLL N.(See multiplier, VCOfrequency the These read/writebitscontrolthem value of6. thesebits Reset initializes of$1. value select bitsconfigures U7ML U5ML R7VS R5VRS4 VRS5 VRS6 VRS7 MUL4 MUL5 MUL6 MUL7 Bit 7654321Bit 0 Figure 10-6.PLLProgr × 4 cycles.NistheVC ion oftheVCO. om developmentsystemsto themodulofeedbackdi on page130).Avalueof$0 er containstheprogram andtheprogramming ts 3–0whenwrit al reference,dothefollowing: amming Register(PPG) O frequencymultiplier. MOUT. WhenBCSisclear,XLD odulo feedbackdividerthatselects available inuser ks onlywhentheBCSbitisset, to$6give Circuits vider thesameasa ing toPBWC. on page126and information forthe ming informationfor userapplications, mode.Toensure a default multiply inthemultiplier 08AZ60 — Rev 1.1 Rev — 08AZ60 Clock Generation Module (CGM) CGM Registers

Table 10-3. VCO Frequency Multiplier (N) Selection

MUL7:MUL6:MUL5:MUL4 VCO Frequency Multiplier (N)

0000 1

0001 1

0010 2

0011 3

1101 13

1110 14

1111 15

NOTE: The multiplier select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1).

VRS7–VRS4 — VCO Range Select Bits

These read/write bits control the hardware center-of-range linear multiplier L, which controls the hardware center-of-range frequency, fVRS. (See Circuits on page 126, Programming the PLL on page 130, and PLL Control Register on page 136.) VRS7–VRS4 cannot be written when the PLLON bit in the PLL control register (PCTL) is set. See Special Programming Exceptions on page 132. A value of $0 in the VCO range select bits disables the PLL and clears the BCS bit in the PCTL. (See Base Clock Selector Circuit on page 132 and Special Programming Exceptions on page 132 for more information.) Reset initializes the bits to $6 to give a default range multiply value of 6.

NOTE: The VCO range select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1) and prevents selection of the VCO clock as the source of the base clock (BCS = 1) if the VCO range select bits are all clear.

The VCO range select bits must be programmed correctly. Incorrect programming can result in failure of the PLL to achieve lock.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Clock Generation Module (CGM) 141 ehia aaMC68HC Semiconductor Freescale (CGM) Module Generation Clock 142 Technical Data 10.8.1 WaitMode 10.8 Low-Power Modes 10.7 Clock Generation Module (CGM)

Interrupts NOTE: changes state.ThePLLIE the PLLoutputwithout that requirethePLLto applications candisengage PLLON bitsinthePLLcontrolre software candisengageandturnoff The CGMremainsactiveinwaitm consumption standbymodes. The WAITandSTOPin should makesurethePLLislo source eveniftheP Software canselect the CGMVCLK stack limitations. service routinesfromimpedingso CPU interruptrequests precautions shouldbetaken.Ifthea PLL exitslock,theVCOclockfr selected astheCGMOUTsourceby the PLLenterslock,t see iftherequestwasdue Software shouldreadthe disabled andPLLFreadsaslogic0. When theAUTObitiscl PCTL, becomessetwhether CPU interruptrequestsfromthePLL. the PLLcangeneratea When theAUTObitissetinPLL LL isnotlocked(LOCK= he VCOclock,CGMVCLK, wake theMCUfromwait turning offthePLL. should bedisabledtopr structions putthe ear, CPUinterrupt CPU interruptrequestev LOCK bitafteraPLLC to anentryintolockor bit inthePLLcontrol the PLLwithoutturning CPUinterruptreques cked beforesettingtheBCSbit. equency iscorrupt,andappropriate gister (PCTL).Lesspower-sensitive ftware performanceorfromexceeding ode. Beforeenteringwaitmode, pplication isnotfr bandwidth control divided bytwoastheCGMOUT setting BCS in the PCTL. When the When BCS inthePCTL. setting the PLLbyclear PLLF,theinterr MCU inlowpower- requestsfromthePLLare 0). Therefore,software modealsocandeselect register (PCTL)enables event PLLinterrupt an exitfromlock.When PU interruptrequestto divided bytwocanbe ery timetheLOCKbit ts areenabledornot. it off.Applications equency sensitive, ing theBCSand upt flaginthe register (PBWC), 08AZ60 — Rev 1.1 Rev — 08AZ60 Clock Generation Module (CGM) CGM During Break Interrupts

10.8.2 Stop Mode

The STOP instruction disables the CGM and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT).

If CGMOUT is being driven by CGMVCLK and a STOP instruction is executed; the PLL will clear the BCS bit in the PLL control register, causing CGMOUT to be driven by CGMXCLK. When the MCU recovers from STOP, the crystal clock divided by two drives CGMOUT and BCS remains clear.

10.9 CGM During Break Interrupts

The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See Break Module (BRK) on page 153.

To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it

remains cleared when the MCU exits the break state.

To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit.

10.10 Acquisition/Lock Time Specifications

The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times.

10.10.1 Acquisition/Lock Time Definitions

Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance is usually specified as a percent of the

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Clock Generation Module (CGM) 143 ehia aaMC68HC Semiconductor Freescale (CGM) Module Generation Clock 144 Technical Data Clock Generation Module (CGM) acquisition andlocktimes acquisition orlocktime The discrepancyinthesedefinitionsma initial error. a certaintoleranceofthedesiredfr definition becausethe not evenberegistered. time variesaccordingtotheoriginal is thetimetakentore MHz andsuffersa–100kH operating at1 1MHz command instructsthe example, considerasystemwith5% constant inthisdefinit a percentofthefrequen step inputorwhentheou output towithinspecifiedtoleranc takes toreducetheerrorbetween Other systemsrefertoac of the100-kHzstepinput. acquisition timeistheta • Lock time, t Locktime, • Acquisition time,t • becomes setinthePLLbandwid (f Acquisition timeisbasedon more than than more time isbasedonanin frequency tolessthanthelo between theactualoutputfr Modes control mode(see frequency tolessthanthetra between theactualoutputfr ± des 0kz it kHz=5%ofthe1-MH kHz.Fifty 50 –f orig on page128),acquisi )/f ± Lock 100%. Inautomaticbandwidth des unfo 0 H o1MHz kHzto1 turn from900 , of not more than morethan , ofnot , isthetimePLLta ion, regardlessofthesi system requirestheout TypicalPLLapplicationsprefertousethis system tochangefrom for atypicalPLL.Therefor acq cy change.Therefore,t Manual andAutomatic quisition andlocktimesas tput settlestothedesi for thismoduleare: , isthetimePLLta itial frequencyerror,(f ken forthefrequencytoreach es. Therefore,the equency andthedesiredoutput equency andthedesiredoutput ck modeentrytolerance, equency regardlessofthesize the actualoutputanddesired an initialfrequencyerror, errorintheoutput cking modeentrytolerance, tion timeexpireswhentheACQ acquisitiontimetolerance.Ifa th controlregi ± kes itdifficult 100%. Inautomaticbandwidth z noisehit,theacquisitiontime z stepinput.Ifthesystemis kes toreducetheerror ze ofthestepinput.For put frequencytobewithin 0 Hz to 1 MHz, the MHz, to1 Hz 0 he reactiontimeis red valueplusorminus control mode, lock time locktime mode, control ± kes toreducetheerror PLLBandwidth e, thedefinitionsfor H.Fv kHz=5% Five kHz. 5 des thetimesystem acquisition orlock ster (PBWC). . Minor errors may errors . Minor to specifyan – f 08AZ60 — Rev 1.1 Rev — 08AZ60 orig )/f ∆ Lock des ∆ , ofnot . Lock trk . bit bit Clock Generation Module (CGM) Acquisition/Lock Time Specifications

expires when the LOCK bit becomes set in the PLL bandwidth control register (PBWC). (See Manual and Automatic PLL Bandwidth Modes on page 128).

Obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases.

10.10.2 Parametric Influences on Reaction Time

Acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time.

The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRDV. This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error.

Therefore, the slower the reference the longer it takes to make these corrections. This parameter is also under user control via the choice of crystal frequency fXCLK. Another critical parameter is the external filter capacitor. The PLL modifies the voltage on the VCO by adding or subtracting charge from this capacitor. Therefore, the rate at which the voltage changes for a given frequency error (thus a change in charge) is proportional to the capacitor size. The size of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL may not be able to adjust the voltage in a reasonable time. See Choosing a Filter Capacitor on page 146.

Also important is the operating voltage potential applied to VDDA. The power supply potential alters the characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. Noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the PLL.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Clock Generation Module (CGM) 145 ehia aaMC68HC Semiconductor Freescale (CGM) Module Generation Clock 146 Technical Data 10.10.3 Choosing Clock Generation Module (CGM) a FilterCapacitor For acceptablevaluesofC equation: operation, theexternalfiltercapacit with supplypotentialandreferenc tolerance ( PLL maybecomeunstable.Also,alwa supply voltage.Thevalue time ofthePLL.The lower sizemayseemattractivefor different sizes,choosethehigherva size, soroundtot This equationdoes the middleof MCU isoperating.Ifthepowersupply 430). ForthevalueofV 145, theexternalfiltercapacitor,C As describedin board, andevenhum filter capacitor,capacitor the PLL.Thesefactorsincludenoise External factors,however,cancaus specified aslongtheseinfluences the electricalcharacteristicsof Temperature andprocessingalsocanaf ± 20% orbetter)andlowdissipation. Parametric InfluencesonReactionTime range ofpossible he nearestavailablesize.If not alwaysyieldacommonl PLLisalsodependent idity orcircuit DDA of thecapacitormust C fact , choosethevoltagepot F , (see leakage, strayimpedanc = the PLLchange.Thepartoperatesas C F e frequencyinmi acquisition timeimpr fact supplyvalues. , iscriticaltot or mustbechosenaccordingtothis board contamination. e drasticchangesintheoperationof lue forbetterstability.Choosingthe Electrical staywithinthespecifiedlimits. injected intot   ys chooseacapacitorwithtight is variable,choo ------V f rdv DDA fect acquisitiontimebecause - on referencefrequencyand the valueisbetweentwo Specifications , therefore,bechosen y availablecapacitor he stabilityandreaction he PLLthroughthe nd. Forproper ential atwhichthe ovement, butthe es onthecircuit se avaluenear 08AZ60 — Rev 1.1 Rev — 08AZ60 on page on page Clock Generation Module (CGM) Acquisition/Lock Time Specifications

10.10.4 Reaction Time Calculation

The actual acquisition and lock times can be calculated using the equations below. These equations yield nominal values under the following conditions:

• Correct selection of filter capacitor, CF (see Choosing a Filter Capacitor on page 146). • Room temperature operation • Negligible external leakage on CGMXFC • Negligible noise

The K factor in the equations is derived from internal PLL parameters. Kacq is the K factor when the PLL is configured in acquisition mode, and Ktrk is the K factor when the PLL is configured in tracking mode. (See Acquisition and Tracking Modes on page 127).

V 8 t = ------DDA- ------acq f K RDV ACQ

VDDA 4 tal = ------fRDV KTRK

tLock = tACQ + tAL

Note the inverse proportionality between the lock time and the reference frequency.

In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the reference frequency. (See Manual and Automatic PLL Bandwidth Modes on page 128). A certain number of clock cycles, nACQ, is required to ascertain that the PLL is within the tracking mode entry tolerance, ∆TRK, before exiting acquisition mode. A certain number of clock cycles, nTRK, is required to ascertain that the PLL is within the lock mode entry tolerance, ∆Lock. Therefore, the

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Clock Generation Module (CGM) 147 ehia aaMC68HC Semiconductor Freescale (CGM) Module Generation Clock 148 Technical Data Clock Generation Module (CGM) since theaveragefrequencyovert t be withinthespecifiedtole acquisition tolocktime,t on ReactionTime on page132),becausethefactorsdescribedin t In manualmode,itisus acquisition time,t Lock Lock beforeselecting ascalculatedabove. ACQ on page145,mayslowthelocktimeconsiderably. , isanintegermultipleofn the PLLclock(see ually necessarytowait AL rance, thetotaltime , isanintegermultipleofn he entiremeasurem Base ClockSelectorCircuit considerably longerthan usually islongerthan Parametric Influences ACQ /f RDV TRK ent periodmust 08AZ60 — Rev 1.1 Rev — 08AZ60 , andthe /f RDV . Also, Technical Data — MC68HC08AZ60

Section 11. Mask Options

11.1 Contents

11.2 Introduction...... 149 11.3 Functional Description...... 149 11.4 Mask Option Register...... 150

11.2 Introduction

This section describes use of mask options by custom-masked ROMs and the mask option register in the MC68HC08AZ60.

11.3 Functional Description

The mask options are hard-wired connections, specified at the same time as the ROM code, which allow the user to customise the MCU. The options control the enable or disable ability of the following functions:

• ROM security(1) • Resets caused by the LVI module • Power to the LVI module • Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles) • COP timeout period (218 – 24 CGMXCLK cycles or 213 – 24 CGMXCLK cycles) • Stop instruction

1. No security feature is absolutely secure. However, Motoroola’s strategy is to make reading or copying the ROM data dificult for unauthorized users.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Mask Options 149

150 Mask Options Freescale Semiconductor Freescale MC68HC Options Mask 150 Technical Data 11.4 MaskOptionRegister Mask Options LVIRST —LVIResetEnableBit ROMSEC —ROMSecurityBit LVISTOP —LVIStop effect onMCUoperation. (MC68HC908AZ60), awriteto options. Forfreecompatibilit The maskoptionregister ee:UnaffectedbyReset Reset: ed VSO OSCLIS VPRSRCCPSSO COPD STOP COPRS SSREC LVIPWR LVIRST ROMSEC LVISTOP Read: Write:RRRRRRRR LVIRST enablestheresetsignal to unauthorize prevents readingofthe ROMSEC enablestheRMsecurity Inhibit (LVI) Voltage Inhibit(LVI) LVISTOP enablestheLVIm Computer operatingpr • 0 =ROMsecuritydisabled 1 =ROMsecurityenabled 0 =LVIdisabledduringstopmode 1 =LVIenabledduringstopmode 0 =LVImoduleresetsdisabled 1 =LVImoduleresetsenabled Bit 7654321Bit 0 Figure 11-1.Configurati R=Reserved on page177). d usersofcustome Mode EnableBit on page177). ($001F) isusedinthe ROM contentsAcccesstotheisdenied y withtheemulatorOTP operly module(COP) $001F intheMC68HC08AZ60hasno odule instopmode.(See on Register(CONFIG-1) fromtheLVImodule.(See r-specified software. feature. SettingtheROMSECbit itialization ofvarious 08AZ60 — Rev 1.1 Rev — 08AZ60 Low Voltage Low Mask Options Mask Option Register

LVIPWR — LVI Power Enable Bit LVIPWR enables the LVI module. (See Low Voltage Inhibit (LVI) on page 177). 1 = LVI module power enabled 0 = LVI module power disabled

SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay. (See Stop Mode on page 143). 1 = Stop mode recovery after 32 CGMXCLK cycles 0 = Stop mode recovery after 4096 CGMXCLK cycles

NOTE: If using an external crystal oscillator, do not set the SSREC bit.

COPL — COP Long Timeout COPL enables the shorter COP timeout period. (See Computer Operating Properly (COP) on page 171). 1 = COP timeout period is 213 – 24 CGMXCLK cycles 0 = COP timeout period is 218 – 24 CGMXCLK cycles

STOP — STOP Instruction Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode

COPD — COP Disable Bit COPD disables the COP module. (See Computer Operating Properly (COP) on page 171). 1 = COP module disabled 0 = COP module enabled

Extra care should be exercised when selecting mask option registers since other HC08 family parts may have different register options. If in doubt, check with your local field applications representative.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Mask Options 151

152 Mask Options Freescale Semiconductor Freescale MC68HC Options Mask 152 Technical Data Mask Options 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 12. Break Module (BRK)

12.1 Contents

12.2 Introduction...... 153 12.3 Features...... 153 12.4 Functional Description...... 154 12.4.1 Flag Protection During Break Interrupts ...... 155 12.4.2 CPU During Break Interrupts ...... 156 12.4.3 TIM During Break Interrupts ...... 156 12.4.4 COP During Break Interrupts ...... 156 12.5 Low-Power Modes ...... 156 12.5.1 Wait Mode ...... 156 12.5.2 Stop Mode ...... 157 12.6 Break Module Registers...... 157 12.6.1 Break Status and Control Register...... 157 12.6.2 Break Address Registers...... 158

12.2 Introduction

The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.

12.3 Features

• Accessible I/O Registers during Break Interrupts • CPU-Generated Break Interrupts • Software-Generated Break Interrupts • COP Disabling during Break Interrupts

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Break Module (BRK) 153 ehia aaMC68HC Freescale Semiconductor BreakModule (BRK) 154 Technical Data 12.4 FunctionalDescription Break Module(BRK) operation. routine endsthebreak current instruction.Areturn-from-inter address registers,th When aCPU-generatedaddre The followingeventscancausea and $FEFDinmonitormode). instruction. Theprogr (SWI)afte instruction interrupt CPU. TheCPUthen address registers,thebr When theinternaladdressbusmatches Software writesalogic1tothe • A CPU-generatedaddress(theaddr • IAB[15:0] control register. matches thecontentsofth Figure 12-1 Figure 12-1.Break IAB[15:8] IAB[7:0] e breakinterruptbeginsaf BREAK ADDRESSREGISTERHIGH BREAK ADDRESSREGISTERLOW loads theinstruct am countervectorsto showsthestructure interrupt andreturns eak moduleissuesabreakpointsignaltothe 8-BIT COMPARATOR 8-BIT COMPARATOR r completion ofthecurrentCPU r completion ss matchesthecontentsofbreak e breakaddressregisters. Module BlockDiagram break interrupttooccur: BRKA bitinthe rupt instruction(R ion registerwithasoftware thevaluewritteninbreak ess intheprogramcounter) $FFFCand$FFFD($FEFC of thebreakmodule. the MCUtonormal ter theCPUcompletesits CONTROL break statusand 08AZ60 — Rev 1.1 Rev — 08AZ60 TI) inthebreak BREAK Break Module (BRK) Functional Description

Register NameBit 7654321Bit 0 Read: Break Address Register High Bit 15 14 13 12 11 10 9 Bit 8 Write: (BRKH) Reset:00000000

Read: Break Address Register Low Bit 7654321Bit 0 Write: (BRKL) Reset:00000000

Read: 000000 Break Status and Control Register BRKE BRKA Write: (BSCR) Reset:00000000

= Unimplemented R = Reserved

Figure 12-2. I/O Register Summary

Table 12-1. I/O Register Address Summary

Register BRKH BRKL BSCR

Address $FE0C $FE0D $FE0E

12.4.1 Flag Protection During Break Interrupts

The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Break Module (BRK) 155 ehia aaMC68HC Freescale Semiconductor BreakModule (BRK) 156 Technical Data 12.5.1 WaitMode 12.5 Low-Power Modes 12.4.2 CPUDuringBreakInterrupts Break Module(BRK) 12.4.4 COPDuringBreakInterrupts 12.4.3 TIMDuring BreakInterrupts Integration Module(SIM) address onthestackbys wait wasexitedbyabreakinterrupt.If bit(SBSW)in stop/wait If enabled,thebreakmoduleisacti tion standbymodes. The WAITandSTOPinst RST The breakinterruptbegins The CPUstartsabr a CPUinstruction,thebreak progress. Ifthebreakaddressregister The COPisdisabledduring A breakinterruptstops Loadingtheprogramcounterwi • Loadingtheinstructionregist • pin. in monitormode) eak interruptby: thetimercounter. the SIMbreakstatusregi ructions puttheMCU ubtracting onefromit.(See on page97). after completionoft a breakinterruptwhenV interrupt beginsimmediately. er withtheSWIinstruction ve inwaitmode.TheSIMbreak so,theusercanmodifyreturn th $FFFC:$FFFD matchoccursonthelastcycleof he CPUinstructionin in lowpower-consump- ster indicateswhether Hi System ispresentonthe ($FEFC:$FEFD 08AZ60 — Rev 1.1 Rev — 08AZ60 Break Module (BRK) Break Module Registers

12.5.2 Stop Mode

The break module is inactive in stop mode. The STOP instruction does not affect break module register states. A break interrupt will cause an exit from stop mode and sets the SBSW bit in the SIM break status register.

12.6 Break Module Registers

These registers control and monitor operation of the break module:

• Break address register high (BRKH) • Break address register low (BRKL) • Break status and control register (BSCR)

12.6.1 Break Status and Control Register

The break status and control register contains break module enable and

status bits.

Address: $FE0E

Bit 7654321Bit 0

Read: 000000 BRKE BRKA Write:

Reset:00000000

= Unimplemented Figure 12-3. Break Status and Control Register (BSCR)

BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled on 16-bit address match

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Break Module (BRK) 157 ehia aaMC68HC Freescale Semiconductor BreakModule (BRK) 158 Technical Data 12.6.2 BreakAddr Break Module(BRK) ess Registers eitr RHBRKL BRKH Register: drs:$EC$FE0D $FE0C Address: desired breakpointaddress.Resetcl The breakaddressregisterscontai BRKA —BreakActiveBit Reset:00000000Reset:00000000 Read: Read: Write: Write: Reset clearstheBRKAbit. writingal Clear BRKAby match occurs.Writingalogic1to This read/writestatus Figure 12-4.BreakAddr 0 =(Whenread)No 1 =(Whenread)Br Bit 15 14 13 12 11 10 9 Bit 8 Bit 9 10 11 12 13 14 Bit 15 BitBit 7654321Bit 7654321Bit 0 0 eak addressmatch and controlbitisse break addressmatch ogic 0toitbeforeexit ess Registers n thehighandlowbytesof BRKAgeneratesabr ears thebreakaddressregisters. t whenabreakaddress (BRKH andBRKL) ing thebreakroutine. 08AZ60 — Rev 1.1 Rev — 08AZ60 eak interrupt. Technical Data — MC68HC08AZ60

Section 13. Monitor ROM (MON)

13.1 Contents

13.2 Introduction...... 159 13.3 Features...... 160 13.4 Functional Description...... 160 13.4.1 Entering Monitor Mode ...... 162 13.4.2 Data Format ...... 163 13.4.3 Echoing ...... 164 13.4.4 Break Signal ...... 164 13.4.5 Commands ...... 165 13.4.6 Baud Rate ...... 168

13.4.7 Security ...... 169

13.2 Introduction

This section describes the monitor ROM (MON). The monitor ROM allows complete testing of the MCU through a single-wire interface with a host computer.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Monitor ROM (MON) 159 ehia aaMC68HC Freescale Semiconductor MonitorROM (MON) 160 Technical Data 13.4 FunctionalDescription 13.3 Features Monitor ROM (MON) MC68HC08AZ60 has configuration andrequire between PTA0andthehostcomputer. the PTA0pin.Alevel-shiftingand All communicationbetweenthehost while allMCUpinsexceptPTA0reta In monitormode,the of customerspecifiedsoftware(see verify ROMcontent.Accesstoth viewing ofthecontentsROM.Pr While simplemonitorco communicate withahostcomputer Figure 13-1 Monitor ROMreceivesandexecutes Features ofthemo Execution ofCodeinRAM. • Up to28.8kBaud • Standard Mark/SpaceNon-Retu • One PinDedicatedtoSerial • Normal User-ModePinFunctionality • with HostComputer with ROM andHostComputer showsasamplecircuitus nitor ROMinclude: MCU canexecutehost-co a ROMsecurityfeature Communicationwi mmands canaccessany s apullupresistor. e ROMisdeniedtounauthorizedusers multiplexing interfaceisrequired oper proceduresmustbefollowedto Communication betweenMonitor via astandardRS-232interface. in normaloperati Security commandsfromahostcomputer. computer andt rn-to-Zero (NRZ ed toentermonitormodeand PTA0 isusedinawired-OR th HostComputer on page169). to preventexternal mputer codeinRAM memory address,the he MCUisthrough ng modefunctions. ) Communication 08AZ60 — Rev 1.1 Rev — 08AZ60 Monitor ROM (MON) Functional Description

VDD 68HC08 10 kΩ

RST 0.1 µF

VHI

10 Ω IRQ

VDDA VDDA/VDDAREF

CGMXFC 0.1 µF 1 20 MC145407 + + 10 µF 10 µF 3 18 OSC1 X1 20 pF 10 MΩ 4 17 4.9152 MHz OSC2 + V 10 µF 10 µF DD + 20 pF 2 19

VSSA DB-25 VSS 2 5 16

3 6 15 VDD VDD 7 0.1 µF

VDD 1 14 VDD MC74HC125 2 3 10 kΩ PTA0 6 5

4 PTC3 VDD VDD

7 10 kΩ 10 kΩ

A PTC0 (SEE PTC1 NOTE.) B NOTE: Position A — Bus clock = CGMXCLK ÷ 4 or CGMVCLK ÷ 4 Position B — Bus clock = CGMXCLK ÷ 2 Figure 13-1. Monitor Mode Circuit

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Monitor ROM (MON) 161 ehia aaMC68HC Freescale Semiconductor MonitorROM (MON) 162 Technical Data 13.4.1 EnteringMonitorMode Monitor ROM (MON) NOTE: (SIM) (SIM) either theIRQ 5.0 VoltDCElectri The alternatevectorsareinthe$FE Monitor modeusesalternat that itisreadyto break signal(10co a 50%dutycycleat generates internalbus clocks.Inth equal totheCGMXCLKfrequency, of adivide-by-twostageatthe Holding thePTC3pinlowwhenent code. TheCOPmoduleisdisabled allow codeexecutionfromtheinternal (see Once outofreset,the Enter monitormodebyeither Table 13-1 1. For V 1. For page 430. page V Applying alogic0andt • Executing asoftwareinte • V HI HI Security (1) (1) IRQ Pin on page97formoreinformati HI , 5.0 Volt DC Electric 5.0 VoltDC showsthepinconditions 1010Monitor CGMXCLK1011Monitor or PTC0 Pin pin or the RESET pin. (See pinortheRESETpin.(See on page169).Afterthesecuri

receiveacommand. PTC1 Pin nsecutive logic0s)tot cal Characteristics PTA0 Pin maximum busfrequency. Table 13-1.ModeSelection MCU waitsforthehostto PTC3 Pin al Characteristics al Characteristics oeCGMOUT Mode e vectors forreset,SW hen alogic1totheRST oscillator. TheCGMOUTfrequencyis rrupt instruction(SWI)or ering monitormodecausesabypass ------CGMXCLK is case,theOSC1signal musthave in monitormodeaslongV and theOSC1i on modesofoperation). pageinsteadof for enteringmonitormode. monitorfirmwareinsteadofuser 2 on page 432, and and 432, page on on page432),isappliedto he hostcomputer,indicating System IntegrationModule ty bytes,theMCUsendsa send eightsecuritybytes ------CGMVCLK I, andbreakinterrupt. nput directly 2 the$FFpageand Maximum Ratings Ratings Maximum pin. 08AZ60 — Rev 1.1 Rev — 08AZ60 Frequency ------CGMOUT ------CGMOUT Bus HI 2 2 (see on Monitor ROM (MON) Functional Description

Table 13-2 is a summary of the differences between user mode and monitor mode.

Table 13-2. Mode Differences

Functions

Modes Reset Reset Break Break SWI SWI COP Vector Vector Vector Vector Vector Vector High Low High Low High Low

User Enabled $FFFE $FFFF $FFFC $FFFD $FFFC $FFFD

Monitor Disabled(1) $FEFE $FEFF $FEFC $FEFD $FEFC $FEFD

1. If the high voltage (VHI) is removed from the IRQ/VPP pin while in monitor mode, the SIM asserts its COP enable output. The COP is a mask option enabled or disabled by the COPD bit in the configuration register. See 5.0 Volt DC Electrical Characteristics on page 432.

13.4.2 Data Format

Communication with the monitor ROM is in standard non-return-to-zero

(NRZ) mark/space data format. (See Figure 13-2 and Figure 13-3.)

The data transmit and receive rate can be anywhere from 4800 baud to 28.8 kBaud. Transmit and receive baud rates must be identical.

NEXT START START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT BIT

Figure 13-2. Monitor Data Format

NEXT START START $A5 BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT BIT START STOP BREAK BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT NEXT START BIT

Figure 13-3. Sample Monitor Waveforms

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Monitor ROM (MON) 163 ehia aaMC68HC Freescale Semiconductor MonitorROM (MON) 164 Technical Data 13.4.4 BreakSignal 13.4.3 Echoing Monitor ROM (MON) MONITOR SENT TO ECHO 0 READ 1 2 the durationoftw When themonitorreceivesabreaksign A startbitfollowedby command. Any resultofacommand received bytebacktothePT As shownin 3 MISSING STOP BIT READ 4 Figure 13-5.BreakTransaction Figure 13-4.Re 5 Figure 13-4 6 ADDR. HIGH 7 o bitsbeforeechoi ninelowbitsisabreaksignal.(See ad Transaction ADDR. HIGH , themonitorROMimmediatelyechoeseach appears aftertheec A0 pinforerrorchecking. TWO-STOP-BITDELAY BEFORE ZERO ECHO 0 ADDR. LOW ng thebreaksignal. 1 al, itdrivesthePTA0pinhighfor 2 3 ADDR. LOW ho ofthelast 4 5 6 08AZ60 — Rev 1.1 Rev — 08AZ60 RESULT DATA Figure 13-5 7 byteofthe ). Monitor ROM (MON) Functional Description

13.4.5 Commands

The monitor ROM uses these commands:

• READ, read memory • WRITE, write memory • IREAD, indexed read • IWRITE, indexed write • READSP, read stack pointer • RUN, run user program

A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map.

Table 13-3. READ (Read Memory) Command

Description Read byte from memory Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of specified address Opcode $4A Command Sequence

SENT TO MONITOR

READ READ ADDR. HIGH ADDR. HIGH ADDR. LOW ADDR. LOW DATA

ECHO RESULT

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Monitor ROM (MON) 165 ehia aaMC68HC Freescale Semiconductor MonitorROM (MON) 166 Technical Data Monitor ROM (MON) poe$1A Command Sequence Specifies 2-byte addresshighin byte:low byte order contents of Returns next two addresses Opcode Readnext 2bytesData inme Returned Operand Description $49 Command Sequence Specifies 2-byte addresshighin byte:low bytelow byte order; followed by databyte None Opcode byte memory to Write Data Returned Operand Description MONITOR SENT TO ECHO WRITE WRITE MONITOR SENT TO Table 13-4.WRITE (Write Memory)Command Table 13-5.IREAD(I ECHO ADDR. HIGH IREAD ADDR. HIGH mory fromlast addressmory accessed IREAD ndexed Read) Command ADDR. LOW DATA ADDR. LOW DATA RESULT DATA 08AZ60 — Rev 1.1 Rev — 08AZ60 DATA Monitor ROM (MON) Functional Description

Table 13-6. IWRITE (Indexed Write) Command

Description Write to last address accessed + 1 Operand Specifies single data byte Data Returned None Opcode $19 Command Sequence

SENT TO MONITOR

IWRITE IWRITE DATA DATA

ECHO

Table 13-7. READSP (Read Stack Pointer) Command

Description Reads stack pointer

Operand None Data Returned Returns stack pointer in high byte:low byte order Opcode $0C Command Sequence

SENT TO MONITOR

READSP READSP SP HIGH SP LOW

ECHO RESULT

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Monitor ROM (MON) 167 ehia aaMC68HC Freescale Semiconductor MonitorROM (MON) 168 Technical Data 13.4.6 BaudRate Monitor ROM (MON) poe$28 Command Sequence None None Opcode Executes RTIData Returned instruction Operand Description Table 13-8.RUN (RunU baud ratesettingcan resultin Care shouldbetaken whensetting range ofcrystalsandhow 16MHz crystal.Thetable the MSCANmodule,whichisgenerally a 4MHzcrystal(ormultip either a4.1952MHzcrystalclocksour The partfeaturesamoni .12H 943 421 8143 .90.50 0.49 4430 8861 4452.17 8904.35 4.9152MHz .9Mz79.339.178 8010 1.08 1.08 3840 7680 3798.91 7597.83 4.194MHz lc rqPC= T31PC= T31PC= PTC3=1 PTC3=0 PTC3=1 PTC3=0 PTC3=1 PTC3=0 Clock freq 6H 88.11427 80 40 .40.64 0.64 14400 28800 14492.75 28985.51 16MHz 2H 79 89 762. .40.63 0.64 28.8 57.6 28.98 57.97 32kHz Mz74.732.970 6006 0.64 0.64 0.64 0.64 0.64 0.64 3600 1800 900 7200 3600 3623.19 1800 1811.59 7246.37 905.80 3623.19 4MHz 1811.59 2MHz 1MHz Mz1427 263 40 2006 0.64 0.64 7200 14400 7246.37 14492.72 8MHz MONITOR SENT TO ECHO Baud rate Closest PC baud PC Error % Error Closest PCbaud PC rate Baud RUN ser Program) Command tor modewhichisopti les of4MHz).Thissupp below outlinestheavai theycanmatchtoaPCbaudrate. RUN communicationsfailure. ce (ormultiplesof4.1952MHz)or the baudratesinceincorrect clockedfroma4MHz,8MHzor mised tooperatewith orts designswhichuse lable baudratesfora 08AZ60 — Rev 1.1 Rev — 08AZ60 Monitor ROM (MON) Functional Description

13.4.7 Security

A security feature discourages unauthorized reading of ROM locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain user- defined data.

NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons, enter data at locations $FFF6–$FFFD even if they are not used for vectors.

During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PA0.

VDD

4096 + 32 CGMXCLK CYCLES

RST

24 CGMXCLK CYCLES

PA7

256 CGMXCLK CYCLES (ONE BIT TIME) Byte 1 Byte 2 Byte 8 Byte Command FROM HOST

PA0 1 4 1 1 2 4 1 FROM MCU Break

NOTE: 1 = Echo delay (2 bit times) 1 Byte Echo 2 Byte Echo 8 Byte Echo 2 = Data return delay (2 bit times) 4 = Wait 1 bit time before sending next byte. Echo Command

Figure 13-6. Monitor Mode Entry Timing

If the received bytes match those at locations $FFF6–$FFFD, the host bypasses the security feature and can read all ROM locations and execute code from ROM. Security remains bypassed until a power-on reset occurs. After the host bypasses security, any reset other than a power-on reset requires the host to send another eight bytes. If the reset

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Monitor ROM (MON) 169 ehia aaMC68HC Freescale Semiconductor MonitorROM (MON) 170 Technical Data Monitor ROM (MON) NOTE: endless loopofillega fails tobypasssecurity,anyresetotherthanapower-oncausesan execute codefromROMcausesanill the eightsecuritybytes. The MCUdoesnottransmit a breakcharactersigna After receivingtheeightsecurityby mode, butreadingROMlo the hostfailstobypasssecurity If thereceivedbytesdonotma the datathat was notapower-onreset,thesecuri the hostsends. l addressresets. lling thatitisready cations returnsundefined a breakcharacterunti tch thedataatlocations$FFF6–$FFFD, feature. TheMCUremainsinmonitor tes fromthehost,MCUtransmits ty remainsbypassedregardlessof egal addressreset. toreceiveacommand. l afterthehostsends data,andtryingto 08AZ60 — Rev 1.1 Rev — 08AZ60 Afterthehost Technical Data — MC68HC08AZ60

Section 14. Computer Operating Properly (COP)

14.1 Contents

14.2 Introduction...... 171 14.3 Functional Description...... 172 14.4 I/O Signals ...... 173 14.4.1 CGMXCLK ...... 173 14.4.2 STOP Instruction ...... 173 14.4.3 COPCTL Write...... 174 14.4.4 Power-On Reset ...... 174 14.4.5 Internal Reset ...... 174 14.4.6 Reset Vector Fetch...... 174

14.4.7 COPD ...... 174 14.4.8 COPL ...... 174 14.5 COP Control Register...... 175 14.6 Interrupts...... 175 14.7 Monitor Mode ...... 175 14.8 Low-Power Modes ...... 175 14.8.1 Wait Mode ...... 175 14.8.2 Stop Mode ...... 176 14.9 COP Module During Break Interrupts...... 176

14.2 Introduction

The COP module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by periodically clearing the COP counter.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Computer Operating Properly (COP) 171 ehia aaMC68HC Freescale Semiconductor ComputerOperating Properly (COP) 172 Technical Data 14.3 FunctionalDescription Properly Operating Computer (COP) NOTE: NOTE: at V In monitor mode, theCO mode, monitor In COP bitintheresetst stages 4–12oftheSIMcounter. overflow occurspreventsaCOPre ms.Writingany period of53.3 1, a4.9152-MH = CONFIG-1. WhenCOPL cycles, dependingonthestate properly. from generatingareset interrupt subroutine.Su Place COPclearinginstructionsin RST A COPresetpullsthe counter overflow. exiting stopmodetoguaranteethema Service theCOPimmediatelyafterre generates anasynchr prescaler. Ifnotclea The COPcounterisafree-running6- Hi uigtebeksae V . Duringthebreakstate, red bysoftware,theCO onous resetafter2 atus register(RSR). ch aninterruptsubrout even whilethemainpr P isdisablediftheRST pinlowfor32CGM of theCOPlongtimeout value tolocation$FFFFbeforean Hi ontheRST themainprogram set byclearingtheCOPcounterand bit counterprecededbya12-bit set andbeforeenteringorafter ximum timebeforethefirstCOP 13 z crystalgivesaCOPtimeout –2 P counteroverflowsand XCLK cyclesandsetsthe pindisablestheCOP. ine couldkeeptheCOP 4 pinortheIRQ ogram isnotworking or2 18 andnotinan bit,COPL,inthe –2 08AZ60 — Rev 1.1 Rev — 08AZ60 4 CGMXCLK pinisheld Computer Operating Properly (COP) I/O Signals

14.4 I/O Signals

The following paragraphs describe the signals shown in Figure 14-1.

12-BIT COP PRESCALER

CGMXCLK CLEAR ALL STAGES STOP INSTRUCTION CLEAR STAGES 4–12 INTERNAL RESET SOURCES RESET VECTOR FETCH

COPCTL WRITE RESET

RESET STATUS REGISTER 6-BIT COP COUNTER

COPD FROM MOR

RESET CLEAR COP COPCTL WRITE COUNTER

COPRS FROM MOR

Figure 14-1. COP Block Diagram

14.4.1 CGMXCLK

CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.

14.4.2 STOP Instruction

The STOP instruction clears the COP prescaler.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Computer Operating Properly (COP) 173 ehia aaMC68HC Freescale Semiconductor ComputerOperating Properly (COP) 174 Technical Data 14.4.8 COPL 14.4.7 COPD 14.4.6 ResetVectorFetch 14.4.5 InternalReset 14.4.4 Power-OnReset 14.4.3 COPCTLWrite Properly Operating Computer (COP) the maskoptionregister.(See The COPLsignalreflectst MOR register.(See The COPDsignalreflec bus. Aresetvectorfetch A resetvectorfetchoccurswhen An internalresetclearstheCO CGMXCLK cyclesafterpower-up. The power-onreset(POR)circuit register returnstheresetvector. stages 12through4of Control Register Writing anyvaluetotheCOPc on page175),clearst Mask Options the COPprescaler.Re ts thestateofCOPdi clears the COPprescaler. the clears he stateoftheCOPrate Mask Options P prescalerand ontrol register(COPCTL)(see the vectoraddres clears theCOPprescaler4096 on page149). he COPcounterandclears ading theCOPcontrol on page149). the COPcounter. sable bit(COPD)inthe s appearsonthedata select bit.COPRSin 08AZ60 — Rev 1.1 Rev — 08AZ60 COP Computer Operating Properly (COP) COP Control Register

14.5 COP Control Register

The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.

Address: $FFFF

Bit 7654321Bit 0

Read: Low Byte of Reset Vector

Write: Clear COP Counter

Reset: Unaffected by Reset Figure 14-2. COP Control Register (COPCTL)

14.6 Interrupts

The COP does not generate CPU interrupt requests.

14.7 Monitor Mode

The COP is disabled in monitor mode when VHi is present on the IRQ pin or on the RST pin.

14.8 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consump- tion standby modes.

14.8.1 Wait Mode

The COP remains active in wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Computer Operating Properly (COP) 175 ehia aaMC68HC Freescale Semiconductor ComputerOperating Properly (COP) 176 Technical Data 14.9 COPModuleDu 14.8.2 StopMode Properly Operating Computer (COP) RST The COPisdisabledduring instruction, disableth CO prescaler. Servicethe Stop modeturnsofftheCGMXCLKi instruction. Toprevent The STOPbitinthemaskoptionr stop mode. stop modetoensureafull ring BreakInterrupts pin. e STOPinstructionby inadvertently turningof P immediatelybeforeent COPtimeoutperioda a breakinterruptwhenV egister (MOR)enablestheSTOP nput totheCOPa clearing theSTOPbit. f theCOPwithaSTOP fter enteringorexiting ering orafterexiting Hi nd clearstheCOP ispresentonthe 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 15. Low Voltage Inhibit (LVI)

15.1 Contents

15.2 Introduction...... 177 15.3 Features...... 177 15.4 Functional Description...... 178 15.4.1 Polled LVI Operation ...... 180 15.4.2 Forced Reset Operation...... 180 15.4.3 False Reset Protection...... 180 15.5 LVI Status Register...... 181 15.6 LVI Interrupts ...... 181

15.7 Low-Power Modes ...... 182 15.7.1 Wait Mode ...... 182 15.7.2 Stop Mode ...... 182

15.2 Introduction

This section describes the low-voltage inhibit module, which monitors

the voltage on the VDD pin and can force a reset when the VDD voltage falls to the LVI trip voltage.

15.3 Features

Features of the LVI module include:

• Programmable LVI Reset • Programmable Power Consumption

• Digital Filtering of VDD Pin Level

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Low Voltage Inhibit (LVI) 177 ehia aaMC68HC Freescale Semiconductor Low VoltageInhibit (LVI) 178 Technical Data 15.4 FunctionalDescription Low Voltage Inhibit (LVI) NOTE: above avoltage,LVI Note thatshortV An LVIresetalsodrivestheRST LVIOUT flagintheLVI below thatlevelfornineor protection toexternalperipheraldevices. on page180).Theoutputofthecomparat resetoccurs,the anLVI Once in theMORregister.(See monitor thevoltagelevelonV when theSTOPinstructionisimpl LVISTOP, enablestheLVImodule guaranteed. operating voltagerangeifnormalmi responsibility to a resetwhenV voltage. TheLVIresetbit,LVIRST, comparator. TheLVIpower out ofreset.TheLVImodulecont Figure 15-1 conditions. addresses beingprogrammedrece responsibility oftheusertoensur allowed toensuretheintegrityand memory, thenadequatepr If alowvoltageinterrupt(LVI)o CPU cycletobringtheMC showsthestructur DD falls below a ensure acleanV DD TRIPR spikesmaynottrip status register(LVISR). U outofreset.(See . V Mask Options ogramming timema bit,LVIPWR,enables more consecutiveCPUcycles. DD DD MCU remains in resetuntilV in MCU remains e oftheLVImodule. voltage, LVI ccurs duringprogrammingofEEPROM mustbeaboveLVI . LVIPWR,LVISTOP, pinlowtoprovidelow-voltage e thatintheeventofanLVIany ains abandgapreferencecircuitand emented, theLVIw ive specificationprogramming retention ofthe during stopmode.Thiswillensure enables theLVImoduletogenerate DD crocontroller operationistobe signalwithin on page149). or controlsth theLVI.Itisuser’s TRIPF Forced ResetOperation y maynothavebeen , andremainsator the LVItomonitorV data. Itisthe TRIPR TheLVIisenabled thespecified ill continueto andLVIRSTare e stateofthe 08AZ60 — Rev 1.1 Rev — 08AZ60 foronlyone DD rises DD

Low Voltage Inhibit (LVI) Functional Description

VDD

LVIPWR FROM MOR

CPU CLOCK FROM MOR LVIRST V LOW V VDD > LVITRIP = 0 DD LVI RESET DD DIGITAL FILTER DETECTOR VDD < LVITRIP = 1

Stop Mode Filter Bypass ANLGTRIP LVIOUT

LVISTOP FROM MOR

Figure 15-1. LVI Module Block Diagram

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Low Voltage Inhibit (LVI) 179

15.4.2 ForcedResetOperation ehia aaMC68HC Freescale Semiconductor Low VoltageInhibit (LVI) 180 Technical Data 15.4.3 FalseResetProtection 15.4.1 PolledLVIOperation Low Voltage Inhibit (LVI) F0 V ttsRgse LIR LVIOUT StatusRegister(LVISR) LVI $FE0F Addr. RegisterName Bit 7654321Bit 0 remain atorbelowtheLVI enabling LVIresetsallowsthe In applications the LVIRSTbitmust register, theLVIPWR MCU outofreset. cycles. V supply noise.Inorderforthe The V enable LVIresets. and LVIRSTbitsmustbeatlogic more consecutiveCPUcycl theLVI to falls In applicationsthat software canmonitorV Figure 15-2.LVII/ DD pinlevelisdigitallyfilteredtoreducefalseresets duetopower DD mustbeaboveLVI TRIPF that requireV canoperateatV Unimplemented = levelandremainsatorbel beatlogic0todisableLVIresets. bitmustbeatlogic1to O RegisterSummary DD bypollingtheLVIOUT TRIPF es. Inthemaskoption DD LVI moduletoresettheMCU,V TRIPR toremainabovetheLVI levelfornineormoreconsecutiveCPU 1 toenabletheLVImoduleand module toreset foronlyoneCPUcycletobringthe DD levelsbelowtheLVI enabletheLVImodule,and ow thatlevelfornineor bit. Inthemaskoption register, theLVIPWR the MCUwhenV 08AZ60 — Rev 1.1 Rev — 08AZ60 TRIPF TRIPF DD level,

must level, level, DD

Low Voltage Inhibit (LVI) LVI Status Register

15.5 LVI Status Register

The LVI status register flags VDD voltages below the LVITRIPF level.

Address: $FE0F

Bit 7654321Bit 0

Read: LVIOUT 0000000

Write:

Reset:00000000

= Unimplemented Figure 15-3. LVI Status Register (LVISR)

LVIOUT — LVI Output Bit

This read-only flag becomes set when the VDD voltage falls below the LVITRIPF voltage for 32 to 40 CGMXCLK cycles. (See Table 15-1). Reset clears the LVIOUT bit.

Table 15-1. LVIOUT Bit Indication

VDD For Number of LVIOUT At Level: CGMXCLK Cycles:

VDD > LVITRIPR Any 0

VDD < LVITRIPF < 32 CGMXCLK Cycles 0 Between 32 and 40 V < LVI 0 or 1 DD TRIPF CGMXCLK Cycles

VDD < LVITRIPF > 40 CGMXCLK Cycles 1

LVITRIPF < VDD < LVITRIPR Any Previous Value

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Low Voltage Inhibit (LVI) 181 ehia aaMC68HC Freescale Semiconductor Low VoltageInhibit (LVI) 182 Technical Data 15.7.2 StopMode 15.7.1 WaitMode 15.7 Low-Power Modes 15.6 LVIInterrupts Low Voltage Inhibit (LVI) to anyapplicationV of themicrocontroller mode. the LVImodulec lower thanthespecifi level. Isisnotintended Note thattheLVIfeatureisin STOP instruction. and theLVISTOPbitat With theLVIPWRbitinmaskopt out ofstop. trip mustbypassthedigi instruction. BecauseCPUclocksare programmed toalogic1, With theLVISTOPandLVIPWRbits With theLVIRSTbitinmaskopti the LVImoduleisactive With theLVIPWRbitinmaskopti consumption standbymodes. The WAITandSTOPin The LVImoduledoesnotgener an generatearesetandbring DD ed operatingvoltage,V alogic0,theLVImodule structions putthe and thusprotectionofre voltagecollapsingcom tal filtertogeneratea after aWAITinstruction. thatusersoperatet theLVImodulewillbe tended toprovideth ate interruptrequests. on registerprogramm inthemaskoptionregister ion registerprogr disabled duringstopmode,theLVI on registerprogrammedtologic1, MCU inlowpower- reset andbringtheMCU he microcontrollerat the MCUoutofwait activeafteraSTOP DD will beinactiveaftera pletely toanunsafe lated circuitryprior e safeshutdown ammed tologic1 08AZ60 — Rev 1.1 Rev — 08AZ60 ed tologic1, Technical Data — MC68HC08AZ60

Section 16. External Interrupt (IRQ)

16.1 Contents

16.2 Introduction...... 183 16.3 Features...... 183 16.4 Functional Description...... 184 16.5 IRQ Pin...... 187 16.6 IRQ Module During Break Interrupts ...... 188 16.7 IRQ Status and Control Register...... 189

16.2 Introduction

This section describes the nonmaskable external interrupt (IRQ) input.

16.3 Features

Features include:

• Dedicated External Interrupt Pin (IRQ) • Hysteresis Buffer • Programmable Edge-Only or Edge- and Level-Interrupt Sensitivity • Automatic Interrupt Acknowledge

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor External Interrupt (IRQ) 183 ehia aaMC68HC Semiconductor Freescale (IRQ) Interrupt External 184 Technical Data 16.4 FunctionalDescription External Interrupt(IRQ)

INTERNAL ADDRESS BUS IRQ DECODER VECTOR FETCH ACK1 interrupt latchremainssetuntilon Interrupt signalsontheIRQ request. A logic0appliedtotheex Software clear—Softwarecan • Vector fetch—Avectorau • Reset —Aresetautomatically • V MODE1 DD to theappropriateackn fetch. acknowledge signalthatclearst IRQ latch. IRQ control register(ISCR).Writinga Figure 16-1.IRQBlockDiagram Figure 16-1 DQ CK LATCH CLR IRQ showsthestructur ternal interruptpinca pinarelatchedinto IMASK1 owledge bitinthe e ofthefollowingactionsoccurs: SYNCHRO- VOLTAGE DETECT NIZER HIGH clears bothinterruptlatches. tomatically generatesaninterrupt he latchthatcausedthevector logic 1totheA e oftheIRQmodule. an interrupt latch by writing bywriting latch interrupt an n latchaCPUinterrupt the IRQlatch.An terrupt statusand IRQF CK1 bitclearsthe 08AZ60 — Rev 1.1 Rev — 08AZ60 LOGIC SELECT TO MODE REQUEST INTERRUPT IRQ INSTRUCTIONS BIL/BIH TO CPUFOR External Interrupt (IRQ) Functional Description

Table 16-1. IRQ I/O Register Summary

Addr.Register Name Bit 7654321Bit 0

Read: 0000IRQF0 $001A IRQ Status/Control Register (ISCR) IMASK1 MODE1 Write:RRRRRACK1

R= Reserved

The external interrupt pin is falling-edge triggered and is software- configurable to be both falling-edge and low-level triggered. The MODE1 bit in the ISCR controls the triggering sensitivity of the IRQ pin.

When an interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software clear, or reset occurs.

When an interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both of the following occur:

• Vector fetch or software clear

• Return of the interrupt pin to logic 1

The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE1 control bit, thereby clearing the interrupt even if the pin stays low.

When set, the IMASK1 bit in the ISCR masks all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the corresponding IMASK bit is clear.

NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. (See Figure 16-2).

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor External Interrupt (IRQ) 185 ehia aaMC68HC Semiconductor Freescale (IRQ) Interrupt External 186 Technical Data External Interrupt(IRQ) YES INSTRUCTION? INSTRUCTION? INSTRUCTION. Figure 16-2.IRQInterruptFlowchart FROM RESET INTERRUPT? FETCH NEXT I BIT SET? SWI RTI NO NO NO NO YES YES YES LOAD PC WITH INTERRUPT VECTOR.WITH INTERRUPT LOAD PC UNSTACK CPU REGISTERS. EXECUTE INSTRUCTION. STACK CPUREGISTERS. SET IBIT. 08AZ60 — Rev 1.1 Rev — 08AZ60 External Interrupt (IRQ) IRQ Pin

16.5 IRQ Pin

A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch.

If the MODE1 bit is set, the IRQ pin is both falling-edge sensitive and low-level sensitive. With MODE1 set, both of the following actions must occur to clear the IRQ latch:

• Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK1 bit in the interrupt status and control register (ISCR). The ACK1 bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK1 bit can also prevent spurious interrupts due to noise. Setting ACK1 does not affect subsequent transitions on the IRQ pin. A falling edge on

IRQ/VPP that occurs after writing to the ACK1 bit latches another interrupt request. If the IRQ mask bit, IMASK1, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. • Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, the IRQ latch remains set.

The vector fetch or software clear and the return of the IRQ pin to logic 1 can occur in any order. The interrupt request remains pending as long as the IRQ pin is at logic 0. A reset will clear the latch and the MODE1 control bit, thereby clearing the interrupt even if the pin stays low.

If the MODE1 bit is clear, the IRQ pin is falling-edge sensitive only. With MODE1 clear, a vector fetch or software clear immediately clears the IRQ latch.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor External Interrupt (IRQ) 187 ehia aaMC68HC Semiconductor Freescale (IRQ) Interrupt External 188 Technical Data 16.6 IRQModuleDu External Interrupt(IRQ) NOTE: break flagcontrolregist bit. WithBCFEatlogic0(itsdefault To protectthelatchduringbreakst remains clearedwhentheM logic 1totheBCFEbit. To allowsoftwaretocleartheIRQla 119 during thebreakstate.(See latch canbecleareddu The systemintegrationmodule(SIM)c masking interrupt When usingthelevel-sensit Use theBIHorBILin it usefulinapplications interrupts. TheIRQFbit The IRQFbitintheI IRQ statusandcontrolregi the IRQlatch. ring BreakInterrupts requests intheinterruptroutine. SCR registercanbeus struction toreadthe wherepolling er (SBFCR)enablessoftware ring thebreakstate.The If alatchiscleareddur is notaffectedbythe ster duringthebreak ive interrupttrigger,av SIM BreakFlagControlRegister CU exitsthebreakstate. state), writingtot tch duringabreakinterrupt,write is preferred. ontrols whethert ate, writealogi logic levelontheIRQ ed tocheckforpending IMASK1 bit,whichmakes ing thebreakstate,it state hasnoeffecton BCFE bitintheSIM oid falseinterruptsby toclearthelatches he ACK1bitinthe c 0totheBCFE he IRQinterrupt 08AZ60 — Rev 1.1 Rev — 08AZ60 on page pin. External Interrupt (IRQ) IRQ Status and Control Register

16.7 IRQ Status and Control Register

The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR has these functions:

• Shows the state of the IRQ interrupt flag • Clears the IRQ interrupt latch • Masks IRQ interrupt request • Controls triggering sensitivity of the IRQ interrupt pin

Address: $001A

Bit 7654321Bit 0

Read: 0000IRQF0 IMASK1 MODE1 Write:RRRRRACK1

Reset:00000000

R= Reserved

Figure 16-3. IRQ Status and Control Register (ISCR)

IRQF — IRQ Flag Bit This read-only status bit is high when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending

ACK1 — IRQ Interrupt Request Acknowledge Bit Writing a logic 1 to this write-only bit clears the IRQ latch. ACK1 always reads as logic 0. Reset clears ACK1.

IMASK1 — IRQ Interrupt Mask Bit Writing a logic 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK1. 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor External Interrupt (IRQ) 189 ehia aaMC68HC Semiconductor Freescale (IRQ) Interrupt External 190 Technical Data External Interrupt(IRQ) MODE1 — IRQ Edge/ —IRQ MODE1 Reset clearsMODE1. This read/writebitcont 1 =IRQ 0 =IRQ interruptrequests interruptrequestsonfa Level SelectBit rols thetriggeringse on fallingedgesonly lling edgesandlowlevels nsitivity oftheIRQ 08AZ60 — Rev 1.1 Rev — 08AZ60 pin. Technical Data — MC68HC08AZ60

Section 17. Serial Communications Interface (SCI)

17.1 Contents

17.2 Introduction...... 192 17.3 Features...... 192 17.4 Pin Name Conventions...... 193 17.5 Functional Description...... 193 17.5.1 Data Format ...... 196 17.5.2 Transmitter ...... 196 17.5.2.1 Character Length ...... 196 17.5.2.2 Character Transmission ...... 196 17.5.2.3 Break Characters ...... 200

17.5.2.4 Idle Characters ...... 200 17.5.2.5 Inversion of Transmitted Output ...... 201 17.5.2.6 Transmitter Interrupts ...... 201 17.5.3 Receiver ...... 202 17.5.3.1 Character Length ...... 204 17.5.3.2 Character Reception ...... 204 17.5.3.3 Data Sampling ...... 204 17.5.3.4 Framing Errors ...... 207 17.5.3.5 Baud Rate Tolerance ...... 207 17.5.3.6 Receiver Wakeup ...... 209 17.5.3.7 Receiver Interrupts ...... 210 17.5.3.8 Error Interrupts ...... 210 17.6 Low-Power Modes ...... 211 17.6.1 Wait Mode ...... 211 17.6.2 Stop Mode ...... 211 17.7 SCI During Break Module Interrupts...... 212 17.8 I/O Signals ...... 212 17.8.1 PTE0/SCTxD (Transmit Data) ...... 212 17.8.2 PTE1/SCRxD (Receive Data) ...... 213

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 191 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 192 Technical Data 17.3 Features 17.2 Introduction Serial Communications Interface(SCI) The SCImodule’sfeaturesinclude: and otherMCUs. The SCIallowsasynchronouscommuni I/O Registers 17.9 17.9.4 SCI Status Register1 SCI SCI ControlRegister3 SCI ControlRegister2 17.9.4 SCI ControlRegister1 17.9.3 17.9.2 17.9.1 796SCI DataRegister SCI StatusRegister2 17.9.6 17.9.5 797SCI BaudRateRegister 17.9.7 Interrupt-Driven Operation • Two ReceiverWakeupMethods: • Programmable TransmitterOutputPolarity • Separate ReceiverandTransmi • Separately EnabledTr • Programmable 8-Bitor • 32ProgrammableBaudRates • Standard Mark/SpaceNon-Re • FullDuplexOperation • Idle Receiver Input – Receiver Full – Transmission Complete – Transmitter Empty – MarkWakeup Address – Idle LineWakeup – . ansmitter andReceiver 9-BitCharacterLength . with EightInterruptFlags: . . turn-to-Zero (NRZ)Format . . . . . tter CPUInte cations withperipheraldevices . . rrupt Requests ...... 08AZ60 — Rev 1.1 Rev — 08AZ60 213 220 216 213 222 226 227 228 Serial Communications Interface (SCI) Pin Name Conventions

– Receiver Overrun – Noise Error – Framing Error – Parity Error • Receiver Framing Error Detection • Hardware Parity Checking • 1/16 Bit-Time Noise Detection

17.4 Pin Name Conventions

The generic names of the SCI input/output (I/O) pins are:

• RxD (receive data) • TxD (transmit data)

SCI I/O lines are implemented by sharing parallel I/O port pins. The full

name of an SCI input or output reflects the name of the shared port pin. Table 17-1 shows the full names and the generic names of the SCI I/O pins.The generic pin names appear in the text of this section.

Table 17-1. Pin Name Conventions

Generic Pin Names RxD TxD

Full Pin Names PTE1/SCRxD PTE0/SCTxD

17.5 Functional Description

Figure 17-1 shows the structure of the SCI module. The SCI allows full- duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the SCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 193 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 194 Technical Data Serial Communications Interface(SCI) RxD CGMXCLK SCRIE SCTIE RWU TCIE SBK ILIE RE TE SHIFT REGISTER REGISTER SCI DATA RECEIVE ÷ 4 CONTROL WAKEUP Figure 17-1.SCIM SCRF SCTE SCALER IDLE ENSCI TC PRE- GENERATOR BAUD RATE ÷ CONTROL RECEIVE 16

TRANSMITTER INTERRUPT INTERNAL BUS CONTROL odule BlockDiagram LOOPS RPF BKF RECEIVER DATA SELECTION CONTROL INTERRUPT OR NF PE FE FLAG

CONTROL CONTROL

ERROR WAKE ILTY PEN LOOPS PTY INTERRUPT ENSCI M CONTROL TRANSMIT CONTROL SHIFT REGISTER TXINV ORIE NEIE PEIE FEIE R8 T8 TRANSMIT REGISTER SCI DATA 08AZ60 — Rev 1.1 Rev — 08AZ60 TxD Serial Communications Interface (SCI) Functional Description

Register NameBit 7654321Bit 0 Read: LOOPS ENSCI TXINV M WAKE ILTY PEN PTY SCI Control Register 1 (SCC1) Write: Reset:00000000 Read: SCTIE TCIE SCRIE ILIE TE RE RWU SBK SCI Control Register 2 (SCC2) Write: Reset:00000000 Read: R8 T8 R R ORIE NEIE FEIE PEIE SCI Control Register 3 (SCC3) Write: Reset:UU000000 Read: SCTE TC SCRF IDLE OR NF FE PE SCI Status Register 1 (SCS1) Write: Reset:11000000 Read: BKF RPF SCI Status Register 2 (SCS2) Write: Reset:00000000 Read: R7 R6 R5 R4 R3 R2 R1 R0 SCI Data Register (SCDR) Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Unaffected by Reset Read: SCP1 SCP0 R SCR2 SCR1 SCR0 SCI Baud Rate Register (SCBR) Write: Reset:00000000

= Unimplemented U = Unaffected R = Reserved Figure 17-2. SCI I/O Register Summary

Table 17-2. SCI I/O Register Address Summary

Register SCC1 SCC2 SCC3 SCS1 SCS2 SCDR SCBR

Address $0013 $0014 $0015 $0016 $0017 $0018 $0019

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 195 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 196 Technical Data 17.5.2.2 CharacterTransmission 17.5.2.1 CharacterLength 17.5.2 Transmitter 17.5.1 DataFormat Serial Communications Interface(SCI) an SCItransmission: between theinternaldatabusandtr out totheTxDpin.TheSCI control SCI in Mbit the During anSCItransmission, the ninthbi When transmitting9-bitdata, The transmittercanaccommod Figure 17-4 illustrated in The SCIusesthestandard .Clearthe SCItransmit 3. Enable thetransmitterbywriti 2. EnabletheSCIbywritingalogi 1. START START BIT BIT bit (TE)inSCIcont in SCIcontrolr BIT 0 BIT 0 t (bit 8). t (bit showsthestructureof Figure 17-3 BIT 1 BIT 1 BIT BIT 2 BIT 2 Figure 17-3.SCIDataFormats egister 1(SCC1). register 1(SCC1)deter BIT 3 BIT 3 . rol register2(SCC2). (BIT M IN SCC1 CLEAR) SCC1 IN M (BIT dataregister(SCDR)is 9-BIT DATAFORMAT 8-BIT DATAFORMAT (BIT M IN SCC1 SET) IN SCC1 M (BIT non-return-to-zero mark ter emptybit(SCTE) the transmitshiftregist bitT8inSCIcontrol BIT 4 BIT 4 ate either8-bitor9- theSCItransmitter. BIT 5 BIT 5 ng alogic1tothetransmitterenable c 1totheenableSCIbit(ENSCI) ansmit shiftregister.Toinitiate BIT 6 BIT 6 OR DATA PARITY BIT 7 BIT 7 BIT mines characterlength. OR DATA by firstreadingSCI PARITY register 3(SCC3)is bit data.Thestateof thewrite-onlybuffer STOP BIT 8 er shiftsacharacter BIT BIT /space dataformat 08AZ60 — Rev 1.1 Rev — 08AZ60 START STOP NEXT BIT BIT START NEXT BIT Serial Communications Interface (SCI) Functional Description

status register 1 (SCS1) and then writing to the SCDR. 4. Repeat step 3 for each subsequent transmission.

At the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. After the preamble shifts out, control logic transfers the SCDR data into the transmit shift register. A logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit position.

The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a transmitter CPU interrupt request.

When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition, logic 1. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver relinquish control of the port E pins.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 197 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 198 Technical Data Serial Communications Interface(SCI)

CGMXCLK SCR0 SCR2 SCR1 SCP0 SCP1 ÷ 4

TRANSMITTER CPU INTERRUPT REQUEST SCALER PRE- DIVIDER BAUD PEN PTY TXINV Figure 17-4.SCITransmitter ÷ GENERATION 16 PARITY TCIE TC SCTIE SCTE T8 M

H876543210L STOP MSB SCTIE SCTE TCIE TC SCI DATA REGISTER SHIFT REGISTER LOAD FROM SCDR INTERNAL BUS TRANSMIT 11-BIT CONTROL LOGIC TRANSMITTER SHIFT ENABLE

PREAMBLE (ALL ONES) LOOPS ENSCI SBK TE BREAK (ALL ZEROS) START 08AZ60 — Rev 1.1 Rev — 08AZ60 TxD Serial Communications Interface (SCI) Functional Description

Register NameBit 7654321Bit 0 Read: LOOPS ENSCI TXINV M WAKE ILTY PEN PTY SCI Control Register 1 (SCC1) Write: Reset:00000000 Read: SCTIE TCIE SCRIE ILIE TE RE RWU SBK SCI Control Register 2 (SCC2) Write: Reset:00000000 Read: R8 T8 R R ORIE NEIE FEIE PEIE SCI Control Register 3 (SCC3) Write: Reset:UU000000 Read: SCTE TC SCRF IDLE OR NF FE PE SCI Status Register 1 (SCS1) Write: Reset:11000000 Read: R7 R6 R5 R4 R3 R2 R1 R0 SCI Data Register (SCDR) Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Unaffected by Reset Read: SCP1 SCP0 R SCR2 SCR1 SCR0 SCI Baud Rate Register (SCBR) Write: Reset:00000000

= Unimplemented U = Unaffected R = Reserved

Figure 17-5. SCI Transmitter I/O Register Summary

Table 17-3. SCI Transmitter I/O Address Summary

Register SCC1 SCC2 SCC3 SCS1 SCDR SCBR

Address $0013 $0014 $0015 $0016 $0018 $0019

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 199 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 200 Technical Data 17.5.2.3 BreakCharacters Serial Communications Interface(SCI) 17.5.2.4 IdleCharacters Writing alogic1tothe on theMbitinSCC1.As 0s andhasnostart,stop, shift registerwithabreakcharacter. setting theTEbitduri after completionofth If theTEbitisclear synchronizing idlecharacter Idle characterlengthdependsontheM An idlecharactercontains Receiving abreakcharacterhasthe eight orninelogic0data The SCIrecognizesabreakcharacte recognition ofthestart automatic logic1attheendofa last breakcharacterandthentr software clearstheSBKbit,shif continuously loadsbreakcharactersin sent afterthecharacter May settheoverrun(OR),noise • Sets thebreakflag • Clears theR8bitinSCC3 • Clears theSCIdat • Sets theSCIreceiver • Sets theframingerro • reception inprog ed duringatransmission,th e transmissioninprog ng atransmissionqueuesanid send breakbit, ress flag (RPF) bits (RPF) ress flag bit ofthenex currently beingtransmitted. bitsandalogic0where a register(SCDR) bit (BKF) in SCS2 in (BKF) bit long asSBKisatlogi orparitybit.Break all logic1sandhasnost r bit(FE)inSCS1 full bit(SCRF)inSCS1 that beginseverytransmission. ansmits atleastonelogic1.The break character Abreakcharactercontainsalllogic t registerfinishestransmittingthe t character. following effectsonSCIregisters: r whenastartbitisfollowedby to thetransmitshif SBK, in SCC2 loads thetransmit SBK, inSCC2loads flag (NF), parity error (PE), or (NF),parityerror(PE), flag bit inSCC1.Th ress. Clearingandthen characterlengthdepends c 1,transmitterlogic e TxDpinbecomesidle the stopbitshouldbe. guarantees the art, stop,orparitybit. le charactertobe e preambleisa 08AZ60 — Rev 1.1 Rev — 08AZ60 t register.After Serial Communications Interface (SCI) Functional Description

NOTE: When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current character shifts out to the TxD pin. Setting TE after the stop bit appears on TxD causes data previously written to the SCDR to be lost.

A good time to toggle the TE bit for a queued idle character is when the SCTE bit becomes set and just before writing the next byte to the SCDR.

17.5.2.5 Inversion of Transmitted Output

The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the polarity of transmitted data. All transmitted values, including idle, break, start, and stop bits, are inverted when TXINV is at logic 1. (See SCI Control Register 1.)

17.5.2.6 Transmitter Interrupts

The following conditions can generate CPU interrupt requests from the SCI transmitter:

• SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request. Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate transmitter CPU interrupt requests. • Transmission complete (TC) — The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 201 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 202 Technical Data 17.5.3 Receiver Serial Communications Interface(SCI) CGMXCLK

ERROR CPU INTERRUPT REQUEST

CPU INTERRUPT REQUEST SCP0 SCP1 ÷ 4 WAKE SCALER ILTY PEN RPF PTY BKF PRE- M Figure 17-6 Figure 17-6.SCIReceiver BlockDiagram RxD DIVIDER BAUD ALL ZEROS CHECKING WAKEUP PEIE PE FEIE FE NEIE NF ORIE OR SCRIE SCRF ILIE IDLE PARITY LOGIC showsthestructure RECOVERY SCR0 SCR2 SCR1 DATA ÷ 16 INTERNAL BUS

ALL ONES

MSB H876543210L STOP of theSCIreceiver. RECEIVE SHIFT REGISTER SCI DATAREGISTER 11-BIT SCRIE SCRF ORIE NEIE PEIE FEIE IDLE ILIE OR PE NF FE R8 08AZ60 — Rev 1.1 Rev — 08AZ60

RWU START Serial Communications Interface (SCI) Functional Description

Register NameBit 7654321Bit 0 SCI Control Register 1 (SCC1) Read: LOOPS ENSCI TXINV M WAKE ILTY PEN PTY Write: Reset:00000000 SCI Control Register 2 (SCC2) Read: SCTIE TCIE SCRIE ILIE TE RE RWU SBK Write: Reset:00000000 SCI Control Register 3 (SCC3) Read: R8 T8 R R ORIE NEIE FEIE PEIE Write: Reset:UU000000 SCI Status Register 1 (SCS1) Read: SCTE TC SCRF IDLE OR NF FE PE Write: Reset:11000000 SCI Status Register 2 (SCS2) Read: BKF RPF Write: Reset:00000000 SCI Data Register (SCDR) Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0 Reset: Unaffected by Reset SCI Baud Rate Register (SCBR) Read: SCP1 SCP0 R SCR2 SCR1 SCR0 Write: Reset:00000000

= Unimplemented U = Unaffected R = Reserved

Figure 17-7. SCI I/O Receiver Register Summary

Table 17-4. SCI Receiver I/O Address Summary

Register SCC1 SCC2 SCC3 SCS1 SCS2 SCDR SCBR

Address $0013 $0014 $0015 $0016 $0017 $0018 $0019

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 203 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 204 Technical Data 17.5.3.2 CharacterReception 17.5.3.1 CharacterLength Serial Communications Interface(SCI) 17.5.3.3 DataSampling possible startbitoccurs,theRT During anSCIre bit (bit7). ninth bit(bit8).Whenrece When receiving9-bitdata,bitR8in M bitinSCIcontrolregister1 The receivercanaccommodat for alogic0precededby in SCC2isalsoset,theSCRFbi received bytecanberead.IftheSCI from theRxDpin.TheSCIdataregist To locatethestartbit, (see times an internalsignalwith The receiversamplestheRxDpinat request. SCRF, inSCIstatusregi character the portion of into shifts character After acomplete between theinternaldatabusand baud ratemismatch,theRTclockis After thereceiverdetectsadata • After everystartbit • RT10 samplesreturnsavalidlogic0) returns avalidlogic1 (after themajority Figure 17-8 ception, thereceiveshiftregi afrequency16timesthe data recovery ): transfers to theSCDR.TheSCIreceiverfullbit, transfers to of databitsamplesat ster 1(SCS1)becomesse threelogic1s.When iving 8-bitdata,bitR8 and themajorityoft (SCC1) determinescharacterlength. e either8-bitor9-bi clockbeginstocount16. t generatesareceiverCPUinterrupt the receiveshiftregister. SCI controlregister2(SCC2)isthe receiveinterruptenablebit,SCRIE, logic doesanasyn resynchronizedat thereceiveshift the RTclockrate.Theis er (SCDR)ist bit changefroml ster shiftscharactersin RT8,RT9,andRT10 the fallingedgeofa baud rate.Toadjustfor he nextRT8,RT9,and is acopyoftheeighth t data.Thestateofthe t, indicatingthatthe he read-onlybuffer register, thedata chronous search thefollowing ogic 1tologic0 08AZ60 — Rev 1.1 Rev — 08AZ60 Serial Communications Interface (SCI) Functional Description

START BIT LSB RxD

START BIT START BIT DATA SAMPLES QUALIFICATION VERIFICATION SAMPLING

RT CLOCK RT CLOCK

STATE RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT CLOCK RESET Figure 17-8. Receiver Data Sampling

To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 17-5 summarizes the results of the start bit verification samples.

Table 17-5. Start Bit Verification

RT3, RT5, and RT7 Samples Start Bit Verification Noise Flag

000 Yes 0

001 Yes 1

010 Yes 1

011 No 0

100 Yes 1

101 No 0

110 No 0

111 No 0

If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 205 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 206 Technical Data Serial Communications Interface(SCI) NOTE: samples. RT8, RT9,andRT10. To verifyastopbitandto the receiverassumesthat following asuccessfulstartbitverifica any oralloftheRT8, The RT8,RT9,andRT10samp results ofthedatabitsamples. takes samplesatR To determinethevalueof T,R9 n T0SmlsDt i eemnto Noise Flag DataBit Determination RT8,and RT9,Samples RT10 RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag Noise Flag Error Framing RT9, andRT10RT8, Samples 1 0 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 111 110 101 100 011 010 001 000 1 0 1 1 1 1 1 0 1 0 0 0 1 0 1 1 1 111 110 101 100 011 010 001 000 T8, RT9,andRT10. Table 17-7.StopBitRecovery Table 17-6.DataBitRecovery RT9,andRT10startbit Table 17-7 detect noise,recovery thebitisastartbit. a databitandtodetect les donotaffectstar summarizestheresu tion, thenoiseflag(NF)issetand Table 17-6 samples arelogic1s logic takessamplesat noise, recoverylogic summarizesthe t bitverification.If lts ofthestopbit 08AZ60 — Rev 1.1 Rev — 08AZ60 Serial Communications Interface (SCI) Functional Description

17.5.3.4 Framing Errors

If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character has no stop bit. The FE bit is set at the same time that the SCRF bit is set.

17.5.3.5 Baud Rate Tolerance

A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur.

As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization

within characters corrects misalignments between transmitter bit times and receiver bit times.

Slow Data Tolerance Figure 17-9 shows how much a slow received character can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10.

MSB STOP

RECEIVER RT CLOCK RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 DATA SAMPLES Figure 17-9. Slow Data

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 207 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 208 Technical Data Serial Communications Interface(SCI) Fast DataTolerance data samplesatR stop bitendsatRT10insteadofRT16 misaligned withoutcausing Figure 17-10 transmitter countofaslow9- The maximumpercentdifferencebetwe eiei 0bittimes device is10 counts 170RTcyclesatthepointw With themisalignedcharactershownin bittimes 10 For a9-bitcharacter,datasampling transmitter countofaslow8- The maximumpercentdifferencebetwe bit times device is 9 counts 154RTcyclesatthepointw With themisalignedcharactershownin bit times 9 For an8-bitcharacter, RT CLOCK RECEIVER ×

RT1 × 6R yls+1 Tcce 5 Tcycles. RT 154 = cycles RT 10 + cycles RT 16 showshowmuchafast 6R yls+1 Tcce 7 Tcycles. RT 170 = cycles RT 10 + cycles RT 16 RT2

RT3 T8, RT9,andRT10. 5 147 154 ------7 163 170 ------× Figure 17-10.FastData ×

RT4 cycles. RT 147 = cycles RT 3 + cycles RT 16 data samplingofthestop 154 170 6R yls+3R yls=13R cycles. RT 163 = cycles RT 3 + cycles RT 16 STOP – – ------RT5 ------a noiseerrororfr - - bit characterwithnoerrorsis RT6 bit characterwithnoerrorsis × × 100 RT7 100 SAMPLES hen thecountoftransmitting RT8 hen thecountoftransmitting of thestopbittakesreceiver DATA = = butisstillthereforthestopbit received charactercanbe en thereceivercountand RT9 en thereceivercountand 4.54% 4.12% Figure 17-9 Figure 17-9 RT10

RT11 IDLE ORNEXTCHARACTER aming error.Thefast bit takesthereceiver RT12 , thereceiver , thereceiver

08AZ60 — Rev 1.1 Rev — 08AZ60 RT13

RT14

RT15

RT16 Serial Communications Interface (SCI) Functional Description

For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 17-10, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times × 16 RT cycles = 160 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is 154– 160 ------× 100 = 3.90%. 154

For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 17-10, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times × 16 RT cycles = 176 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 170– 176 ------× 100 = 3.53%. 170

17.5.3.6 Receiver Wakeup

So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the receiver into a standby state during which receiver interrupts are disabled.

Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the receiver out of the standby state:

• Address mark — An address mark is a logic 1 in the most significant bit position of a received character. When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing the RWU bit. The address mark also sets the SCI receiver full bit, SCRF. Software can then compare the character containing the address mark to the user-defined address of the receiver. If they are the same, the receiver remains awake and

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 209 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 210 Technical Data 17.5.3.8 ErrorInterrupts 17.5.3.7 ReceiverInterrupts Serial Communications Interface(SCI) NOTE: requests: The followingreceivererrorflagsin receiver: The followingsourcescangene idle maycausethereceiver With theWAKEbitclear Receiver overrun(OR)— TheOR • Idle input(IDLE)—The • SCI receiver full( • Idle inputlinecondition—When • start bitorafterthestopbit. receiver beginscountinglogic1s full bit,SCRF.Theidlelinetypebi character wasreadfrom the shift registershiftedinanew CPU interruptrequests. interrupt enablebit,ILIE,inSCC2 consecutive logic1sshiftedin SCRF bittogeneraterece SCI receiveinterrupt SCRF cangenerateareceiverCP the receiveshiftregisterhastran receiver doesnotsetthe state byclearingthe character ontheRxDpinwakes standby state. software cansetthe processes thecharactersthatfo SCRF) — The SCRF bitin SCRF SCRF) —The , settingtheRWUbitafte RWU bit.Theidlechar RWU bitandputtherece enable bit,S towakeupimmediately. IDLEbitinSCS1i receiver idlebit,IDLE rate CPUinterruptre iver CPUinterrupts. SCDR. Thepreviouscharacter SCS1cangenerat character before from theRxDpi llow. Iftheyarenotthesame, sferred acharacte the receiverfromstandby enablestheIDLEbittogenerate the WAKEbitisclear,anidle as idlecharacterbitsafterthe t, ILTY,determineswhetherthe CRIE, inSCC2enablesthe U interruptrequest.Settingthe bit indicatesthatthereceive r theRxDpinhasbeen ndicates that10or11 acter thatwakesthe SCS1indicatesthat quests fromtheSCI , ortheSCIreceiver theprevious n. Theidleline iver backintothe e CPUinterrupt 08AZ60 — Rev 1.1 Rev — 08AZ60 r to the SCDR. theSCDR. r to Serial Communications Interface (SCI) Low-Power Modes

remains in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI error CPU interrupt requests. • Noise flag (NF) — The NF bit is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate SCI error CPU interrupt requests. • Framing error (FE) — The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI error CPU interrupt requests. • Parity error (PE) — The PE bit in SCS1 is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU interrupt requests.

17.6 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power- consumption standby modes.

17.6.1 Wait Mode

The SCI module remains active in wait mode. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode.

If SCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction.

17.6.2 Stop Mode

The SCI module is inactive in stop mode. The STOP instruction does not affect SCI register states. SCI module operation resumes after the MCU exits stop mode.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 211 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 212 Technical Data 17.8.1 PTE0/SCTxD 17.8 I/OSignals 17.7 SCIDuringBr Serial Communications Interface(SCI) (Transmit Data) (Transmit DDRE2 bitindatadirect enabled, thePTE0/SCTxDpinisanout The SCIsharesthePTE0/SCTxDpin The PTE0/SCTxDpinistheserialdat are: Port Esharestwoofitspinswith status bitshaveatwo-stepread/wr I/O registersduringthebreakstatewi bit. WithBCFEatlogic0(itsdefaul To protectstatusbitsdu remains clearedwhentheM logic 1totheBCFE To allowsoftwaretoclearstatusbi page 153). to clearstatusbitsdur The BCFEbitinthebreak mode duringanSCItransmissionor Because theinternalclockisinacti does thefirststeponsu doing thesecondstepcl during thebreakstateaslongBCF eak ModuleInterrupts PTE1/SCRxD —Receive data • PTE0/SCTxD —Transmitdata • bit. Ifastatusbi ing thebreakstate.(See ch abitbeforethebr ring thebreakstate,writ ion registerE(DDRE). ears thestatusbit. flag controlregister CU exitsthebreakstate. the SCI module. The two SCI I/O pins I/Opins twoSCI The module. SCI the ve duringstopm ts duringabreak t state),softwarecanreadandwrite ite clearingproce t isclearedduring reception resultsininvaliddata. a outputfromtheSCItransmitter. thout affecting status bits. Some Some statusbits. affecting thout with portE.W E isatlogic0.Afterthebreak, put regardlessofthestate eak, thebitcannotchange (BFCR) enablessoftware Break Module(BRK) e alogic0totheBCFE ode, enteringstop hen theSCIis interrupt, write a interrupt, writea dure. Ifsoftware he breakstate,it 08AZ60 — Rev 1.1 Rev — 08AZ60 on Serial Communications Interface (SCI) I/O Registers

17.8.2 PTE1/SCRxD (Receive Data)

The PTE1/SCRxD pin is the serial data input to the SCI receiver. The SCI shares the PTE1/SCRxD pin with port E. When the SCI is enabled, the PTE1/SCRxD pin is an input regardless of the state of the DDRE1 bit in data direction register E (DDRE).

17.9 I/O Registers

The following I/O registers control and monitor SCI operation:

• SCI control register 1 (SCC1) • SCI control register 2 (SCC2) • SCI control register 3 (SCC3) • SCI status register 1 (SCS1) • SCI status register 2 (SCS2) • SCI data register (SCDR)

• SCI baud rate register (SCBR)

17.9.1 SCI Control Register 1

SCI control register 1:

• Enables loop mode operation • Enables the SCI • Controls output polarity • Controls character length • Controls SCI wakeup method • Controls idle character detection • Enables parity function • Controls parity type

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 213 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 214 Technical Data Serial Communications Interface(SCI) NOTE: drs:$0013 Address: TXINV —TransmitInversionBit ENSCI — Enable SCIBit ENSCI —Enable start, andstopbits. Setting theTXINVbitinve LOOPS —LoopModeSelectBit Reset:00000000 Read: Write: clears theTXINVbit. This read/writebit and disablestransmitterinterrupt Clearing ENSCIsetsthe This read/writebitenabl enabled touseloopmode.Re into thereceiverinput.Both RxD pinisdisconnectedfromtheSCI, This read/writebitenabl 0 =Transmitterout 1 =Transmitter 0 =SCIdisabled 1 =SCIenabled 0 =Normaloperationenabled 1 =Loopmodeenabled OP NC XN AEILYPNPTY PEN ILLTY WAKE M TXINV ENSCI LOOPS Bit 7654321Bit 0 Figure 17-11.SCICont reverses thepolarityof output inverted put not inverted put not rts all transmitted values transmitted rts all es theSCIandSC es loopmodeoperatio SCTE and TC bits in SC in bits TC and SCTE set clearstheLOOPSbit. transmitter andthereceivermustbe rol Register1(SCC1) s. ResetclearstheENSCIbit. andthetransmitteroutputgoes transmitteddata.Reset I baudrategenerator. n. Inloopmodethe , includingidle,break, I statusregister1 08AZ60 — Rev 1.1 Rev — 08AZ60 Serial Communications Interface (SCI) I/O Registers

M — Mode (Character Length) Bit This read/write bit determines whether SCI characters are eight or nine bits long. (See Table 17-8).The ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears the M bit. 1 = 9-bit SCI characters 0 = 8-bit SCI characters

WAKE — Wakeup Condition Bit This read/write bit determines which condition wakes up the SCI: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the RxD pin. Reset clears the WAKE bit. 1 = Address mark wakeup 0 = Idle line wakeup

ILTY — Idle Line Type Bit This read/write bit determines when the SCI starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. Reset clears the ILTY bit. 1 = Idle character bit count begins after stop bit 0 = Idle character bit count begins after start bit

PEN — Parity Enable Bit This read/write bit enables the SCI parity function. (See Table 17-8). When enabled, the parity function inserts a parity bit in the most significant bit position. (See Table 17-7). Reset clears the PEN bit. 1 = Parity function enabled 0 = Parity function disabled

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 215 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 216 Technical Data 17.9.2 SCICont Serial Communications Interface(SCI) NOTE: rol Register2 SCI controlregister2: generate aparityerror. Changing thePTYbitinmiddleof PTY —ParityBit PEN:PTY M 118Od111Bits 11Bits 10Bits 1 10Bits 1 Odd 1 11Bits Even 10Bits 1 8 Odd 1 8 Even 1 7 1 None 7 1 None 1 9 11 1 8 10 1 11 1 1 10 1 0X 0 0X 0 1 0 Enables thefollowing • bit. for oddparityor This read/writebitdeterminesw oto isCharacter Format Control Bits 0 =Evenparity 1 =Oddparity Enables theIDLEbittogene – Enables theSCRF bittogener – Enables theTCbi – Enables theSCTEbittogener – requests requests requests requests Table 17-8.Character even parity.(See Start Bits t togeneratetransmi CPU interrupt requests: interrupt CPU Data Bits hether theSCIgeneratesandchecks Table 17-8 atransmissionor FormatSelection rate receiverCPUinterrupt Parity ate transmitter ate receiverCPUinterrupt ). ResetclearsthePTY tter CPUinterrupt Stop Bits CPU interrupt 08AZ60 — Rev 1.1 Rev — 08AZ60 receptioncan Character Length Serial Communications Interface (SCI) I/O Registers

• Enables the transmitter • Enables the receiver • Enables SCI wakeup • Transmits SCI break characters

Address: $0014

Bit 7654321Bit 0

Read: SCTIE TCIE SCRIE ILIE TE RE RWU SBK Write:

Reset:00000000 Figure 17-12. SCI Control Register 2 (SCC2)

SCTIE — SCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Setting the SCTIE bit in SCC3 enables the

SCTE bit to generate CPU interrupt requests. Reset clears the SCTIE bit. 1 = SCTE enabled to generate CPU interrupt 0 = SCTE not enabled to generate CPU interrupt

TCIE — Transmission Complete Interrupt Enable Bit This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears the TCIE bit. 1 = TC enabled to generate CPU interrupt requests 0 = TC not enabled to generate CPU interrupt requests

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 217 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 218 Technical Data Serial Communications Interface(SCI) NOTE: TE —Transmitt ILIE —IdleLine clear. ENSCIisinSCI Writing totheTEbitis SCRIE —SCIReceive transmitted. ResetclearstheTEbit. an idlecharactertobesentaf (logic 1).Clearingandthensetti transmission inprogressbeforetheTx TxD pin.IfsoftwareclearstheTE preamble of10or11logi Setting thisread/writebitbegin Rese requests. interrupt This read/writebitenables bit. SCRF bittogenerateC CPU interruptrequests. This read/writebi 0 =Transmitt 1 =Transmitt 0 =IDLEnotenabl 1 =IDLEenabledtogenerate 0 =SCRFnotenabledto 1 =SCRFenabledtogener er EnableBit Interrupt EnableBit er disabled er enabled t enablestheSCRFbitto controlregister1. notallowedwhentheenab Interrupt EnableBit ed togenerateCP PU interruptrequests. t clearstheILIEbit. Setting theSCRIEbitin c 1sfromthetransmit the IDLEbittogener generate CPUinterrupt ter thecharactercurrentlybeing ate CPUinterrupt s thetransmissionbysendinga ng TEduringatransmissionqueues CPUinterruptrequests bit, thetransmi D returnstotheidlecondition U interruptrequests generateSCIreceiver Reset clearstheSCRIE ate SCIreceiverCPU le SCIbit(ENSCI)is shift registertothe SCC3enablesthe tter completesany 08AZ60 — Rev 1.1 Rev — 08AZ60 Serial Communications Interface (SCI) I/O Registers

RE — Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled

NOTE: Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is clear. ENSCI is in SCI control register 1.

RWU — Receiver Wakeup Bit This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the RWU bit. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation

SBK — Send Break Bit

Setting and then clearing this read/write bit transmits a break character followed by a logic 1. The logic 1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter continuously transmits break characters with no logic 1s between them. Reset clears the SBK bit. 1 = Transmit break characters 0 = No break characters being transmitted

NOTE: Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the SCI to send a break character instead of a preamble.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 219 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 220 Technical Data 17.9.3 SCICont Serial Communications Interface(SCI) rol Register3 drs:$0015 Address: SCI controlregister3: T8 —TransmittedBit8 Bit8 R8 —Received Reset:UU000000 ed R8 Read: Write: Enables thefoll • Stores theninthSCIdatabitrece • the transmit shift register. Re shiftregister. transmit the transmit shiftregisterat ninth bit(bit8)of When theSCIistransmi bit (bit7).Resethas When theSCIisreceiving8-bitcharac receiv SCDR the that bit (bit8)ofthereceivedcharacte When theSCIisreceiving9-bitchar be transmitted. Parity errorinterrupts – errorinterrupts Framing – Noise errorinterrupts – Receiver overruninterrupts – Bit 7654321Bit 0 Figure 17-13.SCICont nmlmne eevdU=Unaffected Reserved = R Unimplemented = 8RROI EEFI PEIE FEIE NEIE ORIE R R T8 the transmittedcharacter. owing interrupts: no effectontheR8bit. es theother8bits. thesametimethatSCDRisloadedinto tting 9-bitcharacters set hasnoeffectontheT8bit. rol Register3(SCC3) r. R8is receivedatthesametime ived andtheninth acters, R8istheread-onlyninth ters, R8isacopyoftheeighth T8isloadedintothe , T8istheread/write 08AZ60 — Rev 1.1 Rev — 08AZ60 SCI data bit to to bit data SCI Serial Communications Interface (SCI) I/O Registers

ORIE — Receiver Overrun Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR. 1 = SCI error CPU interrupt requests from OR bit enabled 0 = SCI error CPU interrupt requests from OR bit disabled

NEIE — Receiver Noise Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE. Reset clears NEIE. 1 = SCI error CPU interrupt requests from NE bit enabled 0 = SCI error CPU interrupt requests from NE bit disabled

FEIE — Receiver Framing Error Interrupt Enable Bit This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE. Reset clears FEIE. 1 = SCI error CPU interrupt requests from FE bit enabled 0 = SCI error CPU interrupt requests from FE bit disabled

PEIE — Receiver Parity Error Interrupt Enable Bit

This read/write bit enables SCI receiver CPU interrupt requests generated by the parity error bit, PE. Reset clears PEIE. 1 = SCI error CPU interrupt requests from PE bit enabled 0 = SCI error CPU interrupt requests from PE bit disabled

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 221 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 222 Technical Data StatusRegister1 SCI 17.9.4 Serial Communications Interface(SCI) drs:$0016 Address: SCTE —SCITransmi SCI statusregister1co Reset:11000000 ed CET CFIL RN EPE FE NF OR IDLE SCRF TC SCTE Read: Write: Parity error • Framing error • Noisy data • Receiver overrun • Receiver inputidle • Transfer ofreceiveshiftr • Transmission complete • Transfer ofSCDRdatatotrans • This clearable,read-onlybitis then writing to SCDR.Re operation, cleartheSCT SCTE generatesanSCItransmitter transmitter CPUinterrupt character tothetransmitshift 0 =SCDRdatanottransferredto 1 =SCDRdatatransferredto Bit 7654321Bit 0 Figure 17-14.SCIStatus Unimplemented = tter EmptyBit ntains flagstosignal E bitbyreadingSC request. When theSCTIE request.When set setstheSCTEbit. egister datatoSCDRcomplete register. SCTEcangenerateanSCI set whentheSCDR transmitshiftregister mit shiftregister complete Register1(SCS1) CPU interruptr transmitshiftregister the followingconditions: S1 withSCTEsetand transfersa equest. Innormal bit in SCC2 isset, bit inSCC2 08AZ60 — Rev 1.1 Rev — 08AZ60 Serial Communications Interface (SCI) I/O Registers

TC — Transmission Complete Bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates an SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set. TC is cleared automatically when data, preamble, or break is queued and ready to be sent. There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. Reset sets the TC bit. 1 = No transmission in progress 0 = Transmission in progress

SCRF — SCI Receiver Full Bit This clearable, read-only bit is set when the data in the receive shift register transfers to the SCI data register. SCRF can generate an SCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is set the SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF. 1 = Received data available in SCDR

0 = Data not available in SCDR

IDLE — Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. IDLE generates an SCI error CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the IDLE bit. 1 = Receiver input idle 0 = Receiver input active (or idle since the IDLE bit was cleared)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 223 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 224 Technical Data Serial Communications Interface(SCI) Software latencymayallowanoverr data register. routine canchecktheOR important toknowwhichbyteislost In applicationsthat caused theoverrunandislost.The clear theORbitbecausewasno a delayedflag-clearing and SCDRintheflag Bit Overrun —Receiver OR byte 3intheSCDR normal flag-clearingse with ORsetandthen already intheSCDRis bit inSCC3isalsoset. The ORbitgeneratesanSCIerrorCPU SCDR beforethereceiveshiftregist This clearable,read-onlybitisse 0 = Noreceiveroverrun 1 =ReceiveshiftregisterfullandSCRF aresubjecttosoftwarela instead ofbyte2. -clearing sequence. quence andanexampleof sequence. Thedelayed reading theSCDR.Rese The dataintheshiftregist not affected.Clearthe bit inasecondreadof duetoanoverrun, un tooccurbetween t whensoftwarefailstoreadthe next flag-clearing t setwhenSCS1 er receivesthenextcharacter. Figure 17-15 interruptrequestiftheORIE tency orinwhichitis read ofSCDRdoesnot OR bitbyreadingSCS1 SCS1afterreadingthe t clearstheORbit. an overruncausedby er islost,butthedata sequence reads was read.Byte2 the flag-clearing showsthe 08AZ60 — Rev 1.1 Rev — 08AZ60 readsofSCS1 Serial Communications Interface (SCI) I/O Registers

NORMAL FLAG CLEARING SEQUENCE SCRF = 1 = SCRF 0 = SCRF 1 = SCRF 0 = SCRF SCRF = 1 SCRF = 0

BYTE 1 BYTE 2 BYTE 3 BYTE 4

READ SCS1 READ SCS1 READ SCS1 SCRF = 1 SCRF = 1 SCRF = 1 OR = 0 OR = 0 OR = 0 READ SCDR READ SCDR READ SCDR BYTE 1 BYTE 2 BYTE 3

DELAYED FLAG CLEARING SEQUENCE SCRF = SCRF 1 OR = 1 = SCRF 0 OR = 1 = SCRF 0 OR = 0 OR = 1 OR = SCRF = SCRF 1 SCRF = SCRF 1

BYTE 1 BYTE 2 BYTE 3 BYTE 4

READ SCS1 READ SCS1 SCRF = 1 SCRF = 1 OR = 0 OR = 1 READ SCDR READ SCDR BYTE 1 BYTE 3 Figure 17-15. Flag Clearing Sequence

NF — Receiver Noise Flag Bit This clearable, read-only bit is set when the SCI detects noise on the RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears the NF bit. 1 = Noise detected 0 = No noise detected

FE — Receiver Framing Error Bit This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit. 1 = Framing error detected 0 = No framing error detected

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 225 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 226 Technical Data 17.9.5 SCIStatusRegister2 Serial Communications Interface(SCI) drs:$0017 Address: BKF —BreakFlagBit SCI statusregister2co ParityErrorBit PE —Receiver Reset:00000000 Read: Write: BKF bit. on theRxDpinfollowedbyanotherbr cleared, BKFcanbecomesetagain reading SCS2with BKF doesnotgenerate set. In9-bitcharacter character ontheRxDpin. This clearable,read-onlybitis Incoming data • Break characterdetected • PE setandthenreadi PEIE bitinSCC3isal in incomingdata.PEgeneratesa This clearable,read-only 0 =Nobreakch 1 =Breakcharacterdetected 0 =Noparityerrordetected 1 = Parityerrordetected Bit 7654321Bit 0 Figure 17-16.SCIStatus Unimplemented = aracter detected BKF setandthenreadi ntains flagstosignal ng theSCDR. transmissions, theR8bi so set.ClearthePE a CPUinterruptr bit issetwhentheSCI InSCS1,theFEand set whentheSCI PE CPUinterrupt Register2(SCS2) Reset clears only afterlogic1sagainappear eak character.Resetclearsthe equest. ClearBKFby the followingconditions: ng theSCDR.Once bit byreadingSCS1with t inSCC3iscleared. detectsaparityerror SCRF bitsarealso detects abreak the PEbit. request ifthe 08AZ60 — Rev 1.1 Rev — 08AZ60 K RPF BKF Serial Communications Interface (SCI) I/O Registers

RPF — Reception in Progress Flag Bit This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character. Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress. 1 = Reception in progress 0 = No reception in progress

17.9.6 SCI Data Register

The SCI data register is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the SCI data register.

Address: $0018

Bit 7654321Bit 0

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Reset: Unaffected by Reset Figure 17-17. SCI Data Register (SCDR)

R7/T7:R0/T0 — Receive/Transmit Data Bits Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018 writes the data to be transmitted, T7:T0. Reset has no effect on the SCI data register.

NOTE: Do not use read-modify-write instructions on the SCI data register.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 227 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 228 Technical Data 17.9.7 SCIBaudRateRegister Serial Communications Interface(SCI) drs:$0019 Address: SCP1 andSCP0—SCIBaudRatePrescalerBits transmitter. The baudrateregisterselectsthebau Reset:00000000 Read: Write: in These read/writebitsselectthebaud Table 17-9 C[:]Prescaler Divisor (PD) SCP[1:0] Bit 7654321Bit 0 113 4 3 1 11 10 01 00 Figure 17-18.SCIBaud nmlmne =Reserved R Unimplemented = Table 17-9.SCIBaudRatePrescaling . ResetclearsSCP1andSCP0. C1SP C2SR SCR0 SCR1 SCR2 R SCP0 SCP1 Rate Register(SCBR) d rateforbothth rate prescalerdivisorasshown e receiverandthe 08AZ60 — Rev 1.1 Rev — 08AZ60 Serial Communications Interface (SCI) I/O Registers

SCR2 – SCR0 — SCI Baud Rate Select Bits These read/write bits select the SCI baud rate divisor as shown in Table 17-10. Reset clears SCR2–SCR0.

Table 17-10. SCI Baud Rate Selection

SCR[2:1:0] Baud Rate Divisor (BD)

000 1

001 2

010 4

011 8

100 16

101 32

110 64

111 128

Use the following formula to calculate the SCI baud rate:

f Baud rate = ------Crystal------64× PD× BD

where: fCrystal = crystal frequency PD = prescaler divisor BD = baud rate divisor

Table 17-11 shows the SCI baud rates that can be generated with a 4.9152-MHz crystal.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Communications Interface (SCI) 229 ehia aaMC68HC Freescale Semiconductor Serial CommunicationsInterface (SCI) 230 Technical Data Serial Communications Interface(SCI) SCP[1:0] 11 1 2 46 92 185 369 739 1477 128 2954 64 5908 32 150 16 300 111 8 600 110 4 1200 101 2 2400 100 1 13 4800 011 128 13 9600 010 64 13 19,200 001 32 13 11 000 200 16 13 11 111 400 8 13 11 110 800 4 13 11 101 1600 2 13 3200 11 100 1 4 6400 11 011 4 128 11 010 12,800 64 4 11 001 25,600 32 4 10 000 600 16 4 10 111 1200 8 4 10 110 2400 4 4 10 101 4800 2 4 9600 10 100 1 3 10 011 19,200 3 128 10 010 38,400 64 3 10 001 76,800 32 3 01 000 16 3 01 111 8 3 01 110 4 3 01 101 2 3 01 100 1 1 01 011 1 01 010 1 01 001 1 00 000 1 00 1 00 1 00 1 00 00 00 00 Table 17-11.SCIBaudRateSelectionExamples Prescaler Divisor (PD) SCR[2:1:0] Baud Rate Divisor (BD) (f Crystal Baud Rate 08AZ60 — Rev 1.1 Rev — 08AZ60 =4.9152MHz) Technical Data — MC68HC08AZ60

Section 18. Serial Peripheral Interface (SPI)

18.1 Contents

18.2 Introduction...... 232 18.3 Features...... 232 18.4 Pin Name Conventions and I/O Register Addresses. . . . .233 18.5 Functional Description...... 234 18.5.1 Master Mode ...... 236 18.5.2 Slave Mode ...... 237 18.6 Transmission Formats ...... 238 18.6.1 Clock Phase and Polarity Controls...... 238

18.6.2 Transmission Format When CPHA = ‘0’...... 239 18.6.3 Transmission Format When CPHA = ‘1’...... 240 18.6.4 Transmission Initiation Latency ...... 241 18.6.5 Error Conditions ...... 243 18.6.6 Overflow Error ...... 243 18.6.7 Mode Fault Error...... 245 18.7 Interrupts...... 247 18.8 Queuing Transmission Data ...... 248

18.9 Resetting the SPI ...... 250 18.10 Low-Power Modes ...... 251 18.10.1 WAIT Mode ...... 251 18.10.2 STOP Mode ...... 251 18.11 SPI During Break Interrupts...... 251 18.12 I/O Signals ...... 252 18.12.1 MISO (MasterIn/Slave Out) ...... 253 18.12.2 MOSI (Master Out/Slave In) ...... 253

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Peripheral Interface (SPI) 231 ehia aaMC68HC Freescale Semiconductor Serial PeripheralInterface (SPI) 232 Technical Data 18.3 Features 18.2 Introduction Serial Peripheral Interface(SPI) Features oftheSPImodu peripheral devices. which allowsfull-duplex,synchr This sectiondescribesth VSS (ClockGround) 18.12.5 SS (SlaveSelect) 18.12.4 SPSCK (SerialClock) 18.12.3 81 I/ORegisters 18.13 81. SPI Data 18.13.3 SPI StatusandCo 18.13.2 SPI ControlRegister(SPCR) 18.13.1 •I Programmable wired-OR mode • Overflow error flagwith • Mode faulterrorflagwi • Two separatelyenabledinte • Serial clockwithprogram • Maximum slavemodefrequency=bus • Fourmastermodefrequencie • Double-buffered operationwith • Master andslavemodes • Full-duplexoperation • SPTE (SPItransmitterempty) – SPRF (SPIreceiverfull) – registers 2 C (inter-integratedci Register (SPDR) . e serialperipheralin le includethefollowing: rcuit) compatibility . ntrol Register(SPSCR) th CPUinterruptcapability CPUinterruptcapability mable polarityandphase . onous, serialcommunicationswith . rrupts withCPUservice: mxmm=busfrequency = s (maximum . . separate transmitandreceive . terface module(SPI), ...... 08AZ60 — Rev 1.1 Rev — 08AZ60 ÷ 2) 254 253 255 255 262 258 256 Serial Peripheral Interface (SPI) Pin Name Conventions and I/O Register Addresses

18.4 Pin Name Conventions and I/O Register Addresses

The generic names of the SPI input/output (I/O) pins are:

•SS (slave select) • SPSCK (SPI serial clock) • MOSI (master out slave in) • MISO (master in slave out)

The SPI shares four I/O pins with a parallel I/O port. The full name of an SPI pin reflects the name of the shared port pin. Table 18-1 shows the full names of the SPI I/O pins. The generic pin names appear in the text that follows.:

Table 18-1. Pin Name Conventions

SPI Generic Pin Names: MISO MOSI SS SCK VSS Full SPI Pin Names: SPI PTE5/MISO PTE6/MOSI PTE4/SS PTE7/SPSCK CGND

Table 18-2. I/O Register Addresses

Register name Register address

SPI Control Register (SPICR) $0010

SPI Status and Control Register (SPISCR) $0011

SPI Data Register (SPIDR) $0012

The generic pins names appear in the text that follows.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Peripheral Interface (SPI) 233 ehia aaMC68HC Freescale Semiconductor Serial PeripheralInterface (SPI) 234 Technical Data 18.5 FunctionalDescription Serial Peripheral Interface(SPI) SPI StatusSPI and ControlRegister SPI Control Register (SPCR) SPI Control SPI Data Register (SPDR) SPI Data Register name R/W Bit 7 6 5 4 3 2 1 Bit 0 Bit 1 2 3 4 5 6 7 Bit R/W name Register (SPSCR) structure oftheSPImodule. Figure 18-1 Figure 18-1.SPII/O Reset:00101000 Reset:00001000 ee:Unaffected by reset Reset: ed SPRF Read: Read: Read:R7R6R5R4R3R2R1R0 Write: rt:T 6T 4T 2T T0 T1 T2 T3 T4 T5 T6 T7 Write: Write: summarizestheSP PI PSRCO PASWMSESPTIE SPE SPWOM CPHA CPOL SPMSTR R SPRIE R=Reserved ERRIE Register Summary VFMD SPTE MODF OVRF I I/Oregistersand Unimplemented = Figure 18-2 OFNSR SPR0 SPR1 MODFEN 08AZ60 — Rev 1.1 Rev — 08AZ60 showthe Serial Peripheral Interface (SPI) Functional Description

INTERNAL BUS

TRANSMIT DATA REGISTER

SHIFT REGISTER BUS CLOCK 76543210 MISO

÷ 2 MOSI CLOCK ÷ 8 RECEIVE DATA REGISTER DIVIDER ÷ 32 PIN ÷ 128 CONTROL LOGIC

CLOCK SPSCK SPMSTR SPE SELECT CLOCK M LOGIC S SS SPR1 SPR0

SPMSTR CPHA CPOL

MODFEN SPWOM TRANSMITTER CPU INTERRUPT REQUEST ERRIE SPI CONTROL SPTIE SPRIE RECEIVER/ERROR CPU INTERRUPT REQUEST

SPE

SPRF SPTE OVRF MODF Figure 18-2. SPI Module Block Diagram

The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt- driven. All SPI interrupts can be serviced by the CPU.

The following paragraphs describe the operation of the SPI module.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Peripheral Interface (SPI) 235 ehia aaMC68HC Freescale Semiconductor Serial PeripheralInterface (SPI) 236 Technical Data 18.5.1 MasterMode Serial Peripheral Interface(SPI) NOTE: register. Iftheshiftregist the transmissionfroma Only amasterSPImodul on page256. SPI beforedisablingt Enable themasterSPI Configure theSPImodules set. The SPIoperatesinmast the shiftregister,setti Software clearsSPRFbyreadingtheSP register. Innormaloperation,SPR becomes set,thebyte the receiverfullbit, in fromtheslaveonmaster’s As thebyteshiftsout of themasteralsocontrolssh (SPSCR) the speedofsh The SPR1andSPR0bitscontrolt See begins shiftingoutontheMOSIpinunder Figure 18-3 onpage258.ThroughtheSPSCKpi . ift register.See SPRF, becomes set.Att SPRF, becomes he masterSPI.See on theMOSIpinofma ng theSPItransmitterem from theslavetransfers before enablingtheslaveSPI.Disable master SPImodulebywr er isempty,thebyte er modewhentheSPIma e caninitiatetransmi asmasterandslav MISO pin.Thetransmissionendswhen ift registeroft he baudrategeneratoranddetermine F signalstheendof SPI StatusandC I statusandcontro SPI ControlRegi the controlofserialclock. he same time that SPRF thatSPRF time he same n, thebaudrategenerator immediately transfersto ssions. Softwarebegins tothereceivedata e beforeenablingthem. he slaveperipheral. pty bit,SPTE.Thebyte ster, anotherbyteshifts iting totheSPIdata ster bit,SPMSTR,is ontrol Register atransmission. 08AZ60 — Rev 1.1 Rev — 08AZ60 l registerwith ster (SPCR) Serial Peripheral Interface (SPI) Functional Description

SPRF set and then reading the SPI data register. Writing to the SPI data register clears the SPTIE bit.

MASTER MCU SLAVE MCU

MISO MISO SHIFT REGISTER

MOSI MOSI SHIFT REGISTER

SPSCK SPSCK

BAUD RATE GENERATOR SS SS VDD

Figure 18-3. Full-duplex Master-Slave Connections

18.5.2 Slave Mode

The SPI operates in slave mode when the SPMSTR bit is clear. In slave mode the SPSCK pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave MCU must be at logic ‘0’. SS must remain low until the transmission is complete. See Mode Fault Error on page 245.

In a slave SPI module, data enters the shift register under the control of the serial clock from the master SPI module. After a byte enters the shift register of a slave SPI, it transfers to the receive data register, and the SPRF bit is set. To prevent an overflow condition, slave software must then read the SPI data register before another byte enters the shift register.

The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed (which is twice as fast as the fastest master SPSCK clock that can be generated). The frequency of the SPSCK for an SPI configured as a slave does not have to correspond to any particular SPI baud rate. The baud rate only controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Peripheral Interface (SPI) 237 ehia aaMC68HC Freescale Semiconductor Serial PeripheralInterface (SPI) 238 Technical Data 18.6.1 ClockPhaseandPolarityControls Formats 18.6 Transmission Serial Peripheral Interface(SPI) NOTE: in theshiftregisterfrom If thewritetodataregisteris transmission. See or lowclockandhasno significant polarity isspecifiedby the CPOLcont and polarityusingtwobitsintheSPI Software canselectanyoffourcomb amultiple-m indicate a masterSPIdevice,theslavesele devices thatarenotsele sele allowsindividual select line synchronizes shiftingandsamplingon out serially)andreceived(shifted During anSPItransmission, prevent SPSCKfrom SPSCK mustbeinthepr a transmission.WhenCPHAis When theclockphasebit(CPHA)is a bufferuntiltheend data register.Theslavemust register withanewbyteforthenext register beginsshifting When themasterSPIstartsatransm frequency lessthanorequa frequency ofthe Data writtentotheslav the bytealreadyin one buscyclebeforethemasterstarts SPSCK foranSPIconfigur Transmission Formats aster bus of thetransmission. appearing asaclockedge. e shiftregisterduringa slave shiftregistershif out ontheMISOpin.Thesl theprevioustransmission. cted donotinterferewith oper idlestatebefore l tothebusspeed. dataissimultaneously writetoitstransmit contention. clear,thefallingedgeofSS ction ofaslaveSPIdevice; late, theSPItransmitsdataalready in serially).Aserialclockline effectonthetransmission format. transmission bywritin transmission ct linecanoptional inations ofserialclock(SCK)phase set, thefirstedgeofSPSCKstarts control register rol bit,whichselectsan activehigh ission, thedatain thenexttransmission.Otherwise the twoserialdatalines.Aslave on page238. ed asaslavecanbeany ts outontheMISOpin. a transmissionremainsin the slaveisenabledto SPIbusactivities.On data registeratleast ave canloaditsshift transmitted (shifted (SPCR). Theclock ly beusedto theslaveshift 08AZ60 — Rev 1.1 Rev — 08AZ60 g toitstransmit startsa Serial Peripheral Interface (SPI) Transmission Formats

The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.

NOTE: Before writing to the CPOL bit or the CPHA bit, the SPI should be disabled by clearing the SPI enable bit (SPE).

18.6.2 Transmission Format When CPHA = ‘0’

Figure 18-4 shows an SPI transmission in which CPHA is ‘0’. The figure should not be used as a replacement for data sheet parametric information.Two waveforms are shown for SCK: one for CPOL = ‘0’ and another for CPOL = ‘1’. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at logic ‘0’, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general purpose I/O not affecting the SPI. See Mode Fault Error on page 245. When CPHA = ‘0’, the first SPSCK edge is the MSB capture strobe. Therefore the slave must begin driving its data before the first SPSCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low again between each byte transmitted.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Peripheral Interface (SPI) 239 ehia aaMC68HC Freescale Semiconductor Serial PeripheralInterface (SPI) 240 Technical Data = ‘1’ 18.6.3 TransmissionFormatWhenCPHA Serial Peripheral Interface(SPI) (FOR REFERENCE) CAPTURE STROBE (FROM MASTER) SCK (CPOL =’0’)SCK (CPOL SS SCK (CPOL =1) (FROM SLAVE) SCK CYCLE# (TO SLAVE) MISO MOSI Figure 18-4.Transmission selected slavedrives remain lowbetweentransmissions.Thi uses thefirstSPSCKedgeasa begins drivingitsMOSIpinonthe SPI. See high ormustbereconf shown but isassumed output onlywhenitsslav is theslaveselectinputtosl the slave,andMOSI between themasterand (MISO), andmasterout/slavein(M slave timingdiagramsincetheserial another forCPOL=‘1’.The information. TwowaveformsareshownforSCK:oneCPOL=‘0’and should notbeusedasa Figure 18-5 MSB MSB 12345678 Mode FaultError BIT 6 BIT 6 shows an SPI transmission in showsanSPItransmission BIT 5 BIT 5 to themaster.TheSS igured asgeneral-purpose to beinactive.TheSS signalistheoutputfrommaster.TheSS e selectinput(SS replacement fordata BIT 4 BIT 4 Format(CPHA=‘0’) onpage245.When diagram maybeinterpretedasamasteror slave. TheMISOsignal start transmissionsignal.TheSS ave. TheslaveSPI BIT 3 BIT 3 first SPSCKedge.Ther OSI) pinsaredi clock (SCK),masterin/slaveout s formatmaybe BIT 2 BIT 2 ) is at logic‘0’, ) isat which CPHA is ‘1’. Thefigure CPHAis‘1’. which pinofthemasterisnot pinofthemastermustbe sheetparametric CPHA=‘1’,themaster BIT 1 BIT 1 I/Onotaf rectly connected drives itsMISO istheoutputfrom 08AZ60 — Rev 1.1 Rev — 08AZ60 sothatonlythe LSB LSB preferable in efore theslave fecting the pincan line Serial Peripheral Interface (SPI) Transmission Formats

systems having only one master and only one slave driving the MISO data line.

SCK CYCLE # (FOR REFERENCE) 12345678

SCK (CPOL =’0’)

SCK (CPOL =1)

MOSI MSB (FROM MASTER) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

MISO (FROM SLAVE) MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

SS (TO SLAVE)

CAPTURE STROBE

Figure 18-5. Transmission Format (CPHA = ‘1’)

18.6.4 Transmission Initiation Latency

When the SPI is configured as a master (SPMSTR = ‘1’), transmissions are started by a software write to the SPDR. CPHA has no effect on the delay to the start of the transmission, but it does affect the initial state of the SCK signal. When CPHA = ‘0’, the SCK signal remains inactive for the first half of the first SCK cycle. When CPHA = ‘1’, the first SCK cycle begins with an edge on the SCK line from its inactive to its active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and the start of the SPI transmission. See Figure 18-6. The internal SPI clock in the master is a free-running derivative of the internal MCU clock. It is only enabled when both the SPE and SPMSTR bits are set to conserve power. SCK edges occur halfway through the low time of the internal MCU clock. Since the SPI clock is free-running, it is uncertain where the write to the SPDR will occur relative to the slower SCK. This uncertainty causes the variation in the initiation delay shown in Figure 18-6. This delay will be no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Peripheral Interface (SPI) 241 ehia aaMC68HC Freescale Semiconductor Serial PeripheralInterface (SPI) 242 Technical Data Serial Peripheral Interface(SPI) SCK CYCLE (CPHA = ‘1’) (CPHA = (CPHA =’0’) NUMBER CLOCK SCK SCK CLOCK CLOCK CLOCK CLOCK BUS BUS BUS BUS BUS MOSI

Figure 18-6.Transmissi TO SPDR  TO SPDR TO SPDR TO SPDR WRITE

WRITE TO SPDR WRITE

WRITE

WRITE 



ALETLATEST LATEST LATEST EARLIEST EARLIEST EARLIEST EARLIEST 





 INITIATIONBEGINWRITE SPDRTOTRANSFERFROM DELAY LATEST  (SCK =INTERNAL CLOCK (SCK = INTERNAL CLOCK (SCK = 128 POSSIBLESTARTPOINTS) INITIATION DELAY INITIATION (SCK = INTERNAL CLOCK (SCK = (SCK = INTERNAL CLOCK 32 POSSIBLE START POINTS)32 POSSIBLESTART 2 POSSIBLE START POINTS) 8 POSSIBLE START POINTS) MSB BIT 6 BIT MSB 12 on StartDelay(Master) ÷ ÷ ÷ ÷ 128; 32; 2; 8; 08AZ60 — Rev 1.1 Rev — 08AZ60 BIT 5 BIT 3 Serial Peripheral Interface (SPI) Transmission Formats

18.6.5 Error Conditions

The following flags signal SPI error conditions:

• Overflow (OVRF) — failing to read the SPI data register before the next byte enters the shift register results in the OVRF bit becoming set. The new byte does not transfer to the receive data register, and the unread byte still can be read by accessing the SPI data register. OVRF is in the SPI status and control register. • Mode fault error (MODF) — the MODF bit indicates that the voltage on the slave select pin (SS) is inconsistent with the mode of the SPI. MODF is in the SPI status and control register.

18.6.6 Overflow Error

The overflow flag (OVRF) becomes set if the SPI receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. See Figure 18-4 and Figure 18-5. If an overflow occurs, the data being received is not transferred to the receive data register so that the unread data can still be read. Therefore, an overflow error always indicates the loss of data.

OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. MODF and OVRF can generate a receiver/error CPU interrupt request. See Figure 18-9. It is not possible to enable only MODF or OVRF to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set.

If an end-of-block transmission interrupt was meant to pull the MCU out of wait, having an overflow condition without overflow interrupts enabled causes the MCU to hang in wait mode. If the OVRF is enabled to generate an interrupt, it can pull the MCU out of wait mode instead.

If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition. Figure 18-7 shows how it is possible to miss an overflow.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Peripheral Interface (SPI) 243 ehia aaMC68HC Freescale Semiconductor Serial PeripheralInterface (SPI) 244 Technical Data Serial Peripheral Interface(SPI) READ SPSCR READ SPDR OVRF SPRF 4 3 2 1 CPU READS SPSCR WITH SPRF BITSET READS SPSCRWITH CPU CLEARING SPRF BIT. SPDR, READSBYTE1IN CPU BITCLEAR. OVRF AND 1 SETSBYTE SPRFBIT. BYTE 2SETSSPRF BIT. YE1BT YE3BYTE4 BYTE3 BYTE2 BYTE 1 Figure 18-7.MissedRead In thiscase,anoverflowcaneas between SPSCRand second transmissionexample,theOVRF problems. without SPRF the clear to The firstpartof interrupts canbegenerat bit. second SPSCRread,enable interrupt. was clearedandthatfuturetransmi the SPDR.Thisensures another readofthe To preventthis,theOVRFinterrupt obvious thatbytesarebeinglostas 1 2 3 Figure 18-8 Figure 18-7 4 SPSCR shouldbeca illustrates thisprocess. SPDR beingread. that theOVRFwasnot ed untilthisOVRFisse of OverflowCondition 7 6 5 8 showshowtoread 5 the OVRFtoCPU OVRF BITISSET.BYTE4LOST. BYTE 4FAILSTOSETSPRFBITBECAUSE NOTOVRFBIT. BUT CLEARINGSPRF READS BYTE 2INSPDR, CPU BYTE 3SETSOVRF BIT.BYTE ISLOST. 3 BITCLEAR. OVRF AND READS SPSCRW WITHCPU SPRFBITSET 6 ily bemissed.Sinc 7 moretransmissionsarecompleted. ssions willterminatewithanSPRF should beenabled,or However,asil rried outfollowin flagcanbesetintheinterval 8 Generally, toavoidthis the SPSCR and SPDR SPSCR and the setbeforetheSPRF rviced, itwillnotbe by settingtheERRIE lustrated bythe e nomoreSPRF 08AZ60 — Rev 1.1 Rev — 08AZ60 g thereadof alternatively Serial Peripheral Interface (SPI) Transmission Formats

BYTE 1 BYTE 2 BYTE 3 BYTE 4 SPI RECEIVE 1 5 7 11 COMPLETE

SPRF

OVRF

READ SPSCR 2 4 6 9 12 14

READ SPDR 3 8 10 13

1 BYTE 1 SETS SPRF BIT. 8 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. 2 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. 9 CPU READS SPSCR AGAIN 3 CPU READS BYTE 1 IN SPDR, TO CHECK OVRF BIT. CLEARING SPRF BIT. 10 CPU READS BYTE 2 SPDR, 4 CPU READS SPSCR AGAIN CLEARING OVRF BIT. TO CHECK OVRF BIT. 11 BYTE 4 SETS SPRF BIT. 5 BYTE 2 SETS SPRF BIT. 12 CPU READS SPSCR. 6 CPU READS SPSCR WITH SPRF BIT SET 13 CPU READS BYTE 4 IN SPDR, AND OVRF BIT CLEAR. CLEARING SPRF BIT. 7 BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. 14 CPU READS SPSCR AGAIN TO CHECK OVRF BIT. Figure 18-8. Clearing SPRF When OVRF Interrupt is Not Enabled

18.6.7 Mode Fault Error

For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared.

MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. MODF and OVRF can generate a receiver/error CPU interrupt request. See Figure 18-9. It is not possible to enable only MODF or OVRF to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Peripheral Interface (SPI) 245 ehia aaMC68HC Freescale Semiconductor Serial PeripheralInterface (SPI) 246 Technical Data Serial Peripheral Interface(SPI) NOTE: NOTE: NOTE: ‘0’) andlaterdeselected(SS begins whenSS goes highduringatransmission. receiver/error CPUinterr =‘0’), (MSTR aslaveSPI In transmission wasneverbegun. no transmissionoccurri When CPHA=‘1’,aslav transmission (MISOdrivenoutwithth When CPHA=‘0’,aMODFoccurs Formats to itsIDLElevelfollowingthe SS = ‘1’,thetransmissionbeginswhen back toitsidlelevelfollowingthe When configuredasaslave(SPMSTR= occurred ineithermast Reading SPMSTRwhenMO MODFflag(SPSCR)d Setting the shared portpins. error, clearalldatadirect To preventbuscontentionwithanother SPI causesthefollowingeventstooccur: fault flag(MODF)issetifSS In amasterSPIwithth that slave.Thi Thedatadirectionregi • TheSPIstatecounteriscleared. • TheSPTEbitisset. • TheSPEbitiscleared. • If ERRIE=‘1’,t • isalreadylow.The port drivers. request. interrupt onpage238. s happensbecauseSS goeslowandendsonce he SPIgeneratesan e modefaultenablebit(M er modeorslavemode. transmission continuesunt ng. Therefore,MODF e canbeselectedandthen upt requestiftheERRIE ion register(DDR) ster ofthesharedI/O isatlogic‘1’)even the MODFbitgenerates anSPI shift ofthelastdatabit.See goestologic‘0’.A F=1 willindicateaMODEfaulterror = DF shift oftheeighthdatabit.WhenCPHA When CPHA=‘0’,atransmission oes notcleartheSPMSTRbit. if aslaveisselected(SS the SPSCKleavesitsidleleveland at logic ‘0’indica logic at e valueof MSB) master SPIafteramodefault ‘0’), theMODFfl theincomingSPSCKgoes bitsassociatedwiththeSPI does notoccursincea receiver/error CPU ODFEN) set,themode mode faultinamaster if noSPSCKissentto port regainscontrolof bit isset.TheMODF il theSPSCKreturns later deselectedwith tes thestartof for CPHA = ‘0’. for CPHA=‘0’. 08AZ60 — Rev 1.1 Rev — 08AZ60 Transmission ag issetifSS isatlogic

Serial Peripheral Interface (SPI) Interrupts

bit does not clear the SPE bit or reset the SPI in any way. Software can abort the SPI transmission by toggling the SPE bit of the slave.

NOTE: A logic ‘1’ on the SS pin of a slave SPI puts the MISO pin in a high impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if a transmission has begun.

To clear the MODF flag, read the SPSCR and then write to the SPCR register. This entire clearing procedure must occur with no MODF condition existing or else the flag will not be cleared.

18.7 Interrupts

Four SPI status flags can be enabled to generate CPU interrupt requests:

Table 18-3. SPI Interrupts

Flag Request

SPTE (Transmitter Empty) SPI Transmitter CPU Interrupt Request (SPTIE = 1)

SPRF (Receiver Full) SPI Receiver CPU Interrupt Request (SPRIE = 1)

OVRF (Overflow) SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1)

MODF (Mode Fault) SPI Receiver/Error Interrupt Request (SPRIE = 1, ERRIE = 1, MODFEN = ‘1’)

The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU interrupt requests.

The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt requests, provided that the SPI is enabled (SPE = 1).

The error interrupt enable bit (ERRIE) enables both the MODF and OVRF flags to generate a receiver/error CPU interrupt request.

The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF flag is enabled to generate receiver/error CPU interrupt requests.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Peripheral Interface (SPI) 247 ehia aaMC68HC Freescale Semiconductor Serial PeripheralInterface (SPI) 248 Technical Data 18.8 QueuingTr Serial Peripheral Interface(SPI) ERRIE MODF OVRF ansmission Data Figure 18-9.SPIInterr has CPHA:CPOL=1:0). back-to-back tr withdoing associated register onlywhent transmit databufferisreadytoacce completed. TheSP data byteistransmittedimmediately queued andtransmitted.ForanSPI The double-bufferedtransmit requests: interrupt Two sourcesintheSPIstatusand SPI transmitter empty(SPTE) • (SPRF) bit full receiver SPI • SPTE time a byte transfers from the tr the from transfers a byte time SPRF cangenerateanSPIreceiv register. IftheSPIreceiverinterr sh the from transfers abyte time SPTE cangeneratean register. IftheSPItrans SPRIE SPTIE SPRF SPE I transmitteremptyflag he SPTEbitishigh. upt RequestGeneration mit interruptenablebit, data registerallows — theSPRFbitbec control register CPUinterruptrequest. pt newdata.Writ — theSPTEbitbecomessetevery after theprevioustransmissionhas configured as ansmissions with ansmissions ansmit dataregist upt enablebit,SPRIE,isalsoset, ift registertothereceivedata CPU INTERRUPT CPU INTERRUPT REQUEST SPI TRANSMITTER Figure 18-10 er/error CPUinterruptrequest. CPU INTERRUPT REQUEST CPU INTERRUPT SPI RECEIVER/ERROR (SPTE) indicateswhenthe a databytetobe can generateCPU a master,queued SPTIE, isalsoset, e totheSPIdata showsthetiming omes setevery the SPI(SPSCK the 08AZ60 — Rev 1.1 Rev — 08AZ60 er totheshift Serial Peripheral Interface (SPI) Queuing Transmission Data

WRITE TO SPDR 1 3 8

SPTE 2 5 10

PSCK (CPHA:CPOL =‘1’:0)

MOSI MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT 6 5 4 3 2 1 6 5 4 3 2 1 6 5 4 BYTE 1 BYTE 2 BYTE 3

SPRF 4 9

READ SPSCR 6 11

READ SPDR 7 12

1 CPU WRITES BYTE 1 TO SPDR, CLEARING 7 CPU READS SPDR, CLEARING SPRF BIT. SPTE BIT. 8 CPU WRITES BYTE 3 TO SPDR, QUEUEING 2 BYTE 1 TRANSFERS FROM TRANSMIT DATA BYTE 3 AND CLEARING SPTE BIT. REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 9 SECOND INCOMING BYTE TRANSFERS FROM SHIFT 3 CPU WRITES BYTE 2 TO SPDR, QUEUEING REGISTER TO RECEIVE DATA REGISTER, SETTING BYTE 2 AND CLEARING SPTE BIT. SPRF BIT. 4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT 10 BYTE 3 TRANSFERS FROM TRANSMIT DATA REGISTER TO RECEIVE DATA REGISTER, SETTING REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. SPRF BIT. 5 BYTE 2 TRANSFERS FROM TRANSMIT DATA 11 CPU READS SPSCR WITH SPRF BIT SET. REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 12 CPU READS SPDR, CLEARING SPRF BIT. 6 CPU READS SPSCR WITH SPRF BIT SET.

Figure 18-10. SPRF/SPTE CPU Interrupt Timing

For a slave, the transmit data buffer allows back-to-back transmissions to occur without the slave having to time the write of its data between the transmissions. Also, if no new data is written to the data buffer, the last value contained in the shift register will be the next data word transmitted.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Peripheral Interface (SPI) 249 ehia aaMC68HC Freescale Semiconductor Serial PeripheralInterface (SPI) 250 Technical Data 18.9 ResettingtheSPI Serial Peripheral Interface(SPI) By notresettingtheSPR SPE issetbackhighfo between transmissionswit By notresettingthecontrolbitswhen The followingitemsarerese following occurs: whenever theSPIenable Any systemresetcompletelyresets the MODFEN bit set. bit MODFEN the by amodefaultoccurring disable theSPIbywriting‘0’tot service theseinterruptsafterthe ThestatusflagsSPRF,OVRF,andMODF • SPSCR All controlbitsinthe • All controlbitsintheSPCRregister • All theSPIportlogi • TheSPIstatecounteriscleared, • Theshiftregisteriscleared • Any transmissioncurrently • TheSPTEflagisset • and SPR0) I/O. complete transmission r thenexttransmission. F, OVRF,andMODFflags c isdefaultedbackto in anSPIthatwasconf bit (SPE)islow.WheneverSPElow,the hout havingtosetallc t onlybyasystemreset: he SPEbit.TheSPIca inprogressisaborted SPI hasbeendisabl register (MODFEN, theSPI.Partialresetsoccur SPE islow,theusercanclear makingitreadyforanew beinggeneralpurpose igured asamasterwith ontrol bitsagainwhen , theusercanstill ed. Theusercan n alsobedisabled ERRIE,SPR1, 08AZ60 — Rev 1.1 Rev — 08AZ60 Serial Peripheral Interface (SPI) Low-Power Modes

18.10 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power- consumption standby modes.

18.10.1 WAIT Mode

The SPI module remains active after the execution of a WAIT instruction. In WAIT mode the SPI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can bring the MCU out of WAIT mode.

If SPI module functions are not required during WAIT mode, power consumption can be reduced by disabling the SPI module before executing the WAIT instruction.

To exit WAIT mode when an overflow condition occurs, the OVRF bit should be enabled to generate CPU interrupt requests by setting the error interrupt enable bit (ERRIE). See Interrupts on page 247.

18.10.2 STOP Mode

The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. SPI operation resumes after an external interrupt. If STOP mode is exited by reset, any transfer in progress is aborted, and the SPI is reset.

18.11 SPI During Break Interrupts

The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See SIM Break Flag Control Register on page 119.

To allow software to clear status bits during a break interrupt, a ‘1’ should be written to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Peripheral Interface (SPI) 251 ehia aaMC68HC Freescale Semiconductor Serial PeripheralInterface (SPI) 252 Technical Data 18.12 I/OSignals Serial Peripheral Interface(SPI) bidirectional pinfromtheI communication, theMO V when theSPWOMbitin communicate withI software support)asamasterin The SPIhaslimitedinte The SPImodulehasfiveI/O status bitshaveatwo-stepread/wr I/O registersduringthebreakstatewi BCFE bit.Withat‘0’(itsdefau To protectstatusbitsdur I/O port. does thefirststeponsu has noeffect. cleared, awritetotheda Since theSPTEbitcannotbecleared second stepclears during thebreakstateaslongBCF Therefore, awritetot transmission, norwillthisdatabetr DD •V •SS SPSCK —serial clock • MOSI —datatransmitted • MISO —datareceived • . SS —slaveselect —clockground 2 the statusbit. C peripherals,MOSIbecom he SPDRinbreakmode ch abitbeforethebr SI andMISOpinsareconnectedtoa r-integrated circuit(I theSPIcontrolregi ing thebreakstate,a‘0 ta registerinbreakm 2 C peripheralandthrough pins andsharesfourof a single-masterenvironment.To ite clearingproce ansferred intotheshiftregister. lt state),software thout affecting status bits. Some Some statusbits. affecting thout E isa‘0’.Afterthebreak, during abreakwiththeBCFEbit ster isset.InI 2 eak, thebitcannotchange C) capability(requiring with theBCFEbitcleared ode willnot ’ shouldbewrittentothe es anopen-drainoutput them withaparallel dure. Ifsoftware a pullupresistorto canreadandwrite 08AZ60 — Rev 1.1 Rev — 08AZ60 2 initiate a C Serial Peripheral Interface (SPI) I/O Signals

18.12.1 MISO (MasterIn/Slave Out)

MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI simultaneously receives data on its MISO pin and transmits data from its MOSI pin.

Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is configured as a slave when its SPMSTR bit is logic ‘0’ and its SS pin is at locic ‘0’. To support a multiple- slave system, a logic ‘1’ on the SS pin puts the MISO pin in a high- impedance state.

When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction register of the shared I/O port.

18.12.2 MOSI (Master Out/Slave In)

MOSI is one of the two SPI module pins that transmits serial data. In full

duplex operation, the MOSI pin of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI simultaneously transmits data from its MOSI pin and receives data on its MISO pin.

When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction register of the shared I/O port.

18.12.3 SPSCK (Serial Clock)

The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles.

When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Peripheral Interface (SPI) 253 ehia aaMC68HC Freescale Semiconductor Serial PeripheralInterface (SPI) 254 Technical Data 18.12.4 SS Serial Peripheral Interface(SPI) (SlaveSelect) NOTE: MASTER SS MISO/MOSI (CPHA =‘1’) (CPHA =’0’) SLAVE SS SLAVE SS 18-11 low throughoutthetransmissionfo each bytetransmittedfor For CPHA = ‘0’, the SS For CPHA=‘0’,the register ofthesharedI/O port.With be usedasageneralpurposeI/Ounder Ifthe beset. must SS the MOSI andSPSCK.See conjunction withtheMODF When anSPIisconfigur even iftransmissionhasalreadybegun. impedance state.TheslaveSPIignor SS A logic‘1’onthe and ControlRegister(SPSCR) prevent thestateofSS state oftheMODFENcontrolbit. as aninput.Itcannotbeuseda When anSPIisconfigur start ofatran Transmission Formats SPI. ForanSPIconfigur The SS . pin to set the MODF flag, the MO the MODF flag, setthe to pin pinhasvariousfunc smission, theSS BYTE 1 MODFEN bitislowforanSPImaster,theSS Figure 18-11.CPHA/SS pinofaslaveSPIputs isusedtodefinethest Mode FaultError ed asamaster,theSS ed asaslave,theSS onpage238.Sinceit ed asaslave,theSS the CPHA=‘0’format.Ho fromcreatinga flagtopreventmultip tions dependingonthecu mustbetoggledhi onpage258. However, the MODFEN bit can still MODFENbitcan However, the general purposeI/Oregardlessofthe r theCPHA=‘1’format.See BYTE 2 MODFEN high,itis es allincomingSPSCKclocks, DFEN bitinthe the controlofdatadirection onpage245.Forthestateof MODF error.See Timing the MISOpininahigh- art ofatransmission.See isusedtoselectaslave. pinisalwaysconfigured is usedtoindicatethe inputcanbeusedin le masters from driving fromdriving le masters gh andlo wever, it canremain aninput-onlypin rrent stateofthe BYTE 3 SPSCK register 08AZ60 — Rev 1.1 Rev — 08AZ60 w between SPI Status pincan Figure Serial Peripheral Interface (SPI) I/O Registers

to the SPI regardless of the state of the data direction register of the shared I/O port.

The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the data register. See Table 18- 4.

Table 18-4. SPI Configuration

SPE SPMSTR MODFEN SPI CONFIGURATION STATE OF SS LOGIC

General-purpose I/O; SS 0 X X Not Enabled ignored by SPI

1 0 X Slave Input-only to SPI

General-purpose I/O; SS 1 1 0 Master without MODF ignored by SPI

1 1 1 Master with MODF Input-only to SPI

X = don’t care

18.12.5 VSS (Clock Ground)

VSS is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. To reduce the ground return path loop and minimize radio frequency (RF) emissions, connect the ground pin of the slave to the VSS pin.

18.13 I/O Registers

Three registers control and monitor SPI operation:

• SPI control register (SPCR) • SPI status and control register (SPSCR) • SPI data register (SPDR)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Peripheral Interface (SPI) 255 ehia aaMC68HC Freescale Semiconductor Serial PeripheralInterface (SPI) 256 Technical Data 18.13.1 SPIContro Serial Peripheral Interface(SPI) SPCR Reset:00101000 Read: Write: l Register(SPCR) SPMSTR — SPI Master —SPI SPMSTR Enable SPRIE —SPIReceiverInterrupt The SPIcontrolregister PI PSRCO PASWMSESPTIE SPE SPWOM CPHA CPOL SPMSTR R SPRIE operation. ResetsetstheSPMSTRbit. This read/writebitsele register tothereceivedatar SPRF bit.Thebitissetwhen This read/writebi Enables theSPImodule • Configures theSPSCK,MOSI, • Selects serialclockpolarityandphase • Configures theSPImodul • Selects CPUinterruptrequests • Enables SPImodul • Bit 7 6 5 4 3 2 1 Bit 0 Bit 1 2 3 4 5 6 Bit 7 R= Reserved 0 =Slavemode 1 =Mastermode 1 =SPRFCPUinterr 0 =SPRFCPUinterr outputs Figure 18-12.SPICont t enablesCPUinterruptre doesthefollowing: cts mastermodeoper e interruptrequests upt requestsdisabled upt requestsenabled rol Register(SPCR) egister. Resetclear e asmasterorslave and MISOpinsasopen-drain a bytetransfersfromtheshift quests generatedbythe ation orslavemode s theSPRIEbit. 08AZ60 — Rev 1.1 Rev — 08AZ60 Serial Peripheral Interface (SPI) I/O Registers

CPOL — Clock Polarity This read/write bit determines the logic state of the SPSCK pin between transmissions. See Figure 18-4 and Figure 18-5. To transmit data between SPI modules, the SPI modules must have identical CPOL bits. Reset clears the CPOL bit.

CPHA — Clock Phase This read/write bit controls the timing relationship between the serial clock and SPI data. See Figure 18-4 and Figure 18-5. To transmit data between SPI modules, the SPI modules must have identical CPHA bits. When CPHA = ‘0’, the SS pin of the slave SPI module must be set to logic one between bytes. See Figure 18-11. Reset sets the CPHA bit. When CPHA =’0’ for a slave, the falling edge of SS indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the data register. Therefore, the slave data register must be

loaded with the desired transmit data before the falling edge of SS. Any data written after the falling edge is stored in the data register and transferred to the shift register at the current transmission. When CPHA = ‘1’ for a slave, the first edge of the SPSCK indicates the beginning of the transmission. The same applies when SS is high for a slave. The MISO pin is held in a high-impedance state, and the incoming SPSCK is ignored. In certain cases, it may also cause the MODF flag to be set. See Mode Fault Error on page 245. A logic ‘1’ on the SS pin does not affect the state of the SPI state machine in any way.

SPWOM — SPI Wired-OR Mode This read/write bit disables the pull-up devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs. 1 = Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Peripheral Interface (SPI) 257 ehia aaMC68HC Freescale Semiconductor Serial PeripheralInterface (SPI) 258 Technical Data 18.13.2 SPIStatusandCo Serial Peripheral Interface(SPI) SPTIE— SPI Transmit Interrupt Enable Interrupt Transmit SPI SPTIE— conditions: The SPIstatusandcontrolregistercont SPE —SPIEnable register totheshif SPTE bit.isset This read/writebi Transmit datar • Inconsistent logiclevelonSS • FailuretoclearSPRF • Receive data registerfull • clears theSPEbit. partial resetoftheSPI.See This read/writebi ntrol Register(SPSCR) 0 =SPTECPUinterr 1 =SPTECPUinterr 0 =SPImoduledisabled 1 =SPImoduleenabled error) t enablesCPUinterruptre t enablestheSPImodule. t register.Resetcl egister empty when abytetransfersfr upt requestsdisabled upt requestsenabled bitbeforenextbyteisreceived(overflow Resetting theSPI pin(modefaulterror) ears theSPTIEbit. ains flagstosignalthefollowing quests generatedbythe Clearing SPEcausesa om thetransmitdata onpage250.Reset 08AZ60 — Rev 1.1 Rev — 08AZ60 Serial Peripheral Interface (SPI) I/O Registers

The SPI status and control register also contains bits that perform the following functions:

• Enable error interrupts • Enable mode fault error detection • Select master SPI baud rate

Bit 7654321Bit 0

SPSCR Read: SPRF OVRF MODF SPTE MODFE ERRIE SPR1 SPR0 Write: N

Reset:00001000

R= Reserved = Unimplemented Figure 18-13. SPI Status and Control Register (SPSCR)

SPRF — SPI Receiver Full This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. SPRF generates a CPU

interrupt request if the SPRIE bit in the SPI control register is set also. During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Any read of the SPI data register clears the SPRF bit. Reset clears the SPRF bit. 1 = Receive data register full 0 = Receive data register not full

ERRIE — Error Interrupt Enable This read-only bit enables the MODF and OVRF flags to generate CPU interrupt requests. Reset clears the ERRIE bit. 1 = MODF and OVRF can generate CPU interrupt requests 0 = MODF and OVRF cannot generate CPU interrupt requests

OVRF — Overflow Flag This clearable, read-only flag is set if software does not read the byte in the receive data register before the next byte enters the shift register. In an overflow condition, the byte already in the receive data

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Peripheral Interface (SPI) 259 ehia aaMC68HC Freescale Semiconductor Serial PeripheralInterface (SPI) 260 Technical Data Serial Peripheral Interface(SPI) NOTE: SPTE —SPITrans MODF —ModeFault high. The SPIdataregistershou the SS the high duringatransmission.Inmast SPTE CPUinterruptrequest is setalso. register transfersaby This clearable,read-onlyflagis This clearable,ready-onlyflagis and thenreadingtheSPI OVRF bitbyreadingtheSPIstatus Reset setstheSPTEbit. occur. register isnotpossible.TheSPTE completed. Thisimpliesthataback- load oftheshiftregistercannot to queueupa16-bi empties buffer transmit the transmit buffer,theSPTEwillbeset For anidlemasteror SPI dataregister.Rese SPI statusandcontrolregisterwi register isunaffected,andt 0 =Transmitdatar 1 =Transmitdata 0 =SS 0 =Nooverflow 1 =Overflow 1 =SS pingoeslowatanytime.Clear pinatappropria pinatinappropriatelogiclevel mitter Empty mitter t valuetosend. idleslavethathas register empty egister notempty te intotheshiftregi t clearstheMODFbit. ld notbewrittentounl data register.Reset te logiclevel he bytethatshiftedin into theshiftregister if theSPTIEbitint occuruntilthetransmissionis set eachtimet set inaslaveSPIiftheSS th MODFsetandthenwritingtothe indicateswhenthenextwritecan and controlregisterwithOVRFset For analreadyactiveslave,the again withintwobuscyclessince to-back writetothetransmitdata er SPI, the MODF flag is set if setif is flag MODF er SPI,the theMODFbit no dataloadedintoits ster. SPTEgeneratesan clears theOVRFflag. he SPIcontrolregister ess theSPTEbitis he transmitdata . Thisallowstheuser last islost.Clearthe 08AZ60 — Rev 1.1 Rev — 08AZ60 by readingthe pingoes Serial Peripheral Interface (SPI) I/O Registers

MODFEN — Mode Fault Enable This read/write bit, when set to ‘1’, allows the MODF flag to be set. If the MODF flag is set, clearing the MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low, then the SS pin is available as a general purpose I/O. If the MODFEN bit is set, then this pin is not available as a general purpose I/O. When the SPI is enabled as a slave, the SS pin is not available as a general purpose I/O regardless of the value of MODFEN. See SS (Slave Select) on page 254. If the MODFEN bit is low, the level of the SS pin does not affect the operation of an enabled SPI configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents the MODF flag from being set. It does not affect any other part of SPI operation. See Mode Fault Error on page 245.

SPR1 and SPR0 — SPI Baud Rate Select In master mode, these read/write bits select one of four baud rates as shown in Table 18-5. SPR1 and SPR0 have no effect in slave mode.

Reset clears SPR1 and SPR0.

Table 18-5. SPI Master Baud Rate Selection

SPR1:SPR0 Baud rate divisor (BD)

00 2

01 8

10 32

11 128

The following formula is used to calculate the SPI baud rate:

CGMOUT Baud rate = ------2BD×

where:

CGMOUT = base clock output of the clock generator module (CGM) BD = baud rate divisor

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Serial Peripheral Interface (SPI) 261 ehia aaMC68HC Freescale Semiconductor Serial PeripheralInterface (SPI) 262 Technical Data 18.13.3 SPIData Serial Peripheral Interface(SPI) NOTE: SPDR Register (SPDR) Reset: Indeterminate after reset after Indeterminate Reset: Read: Write: R7:R0/T7:T0 —Receive/ Figure 18-2 registers areseparatebuffersthat from thereceivedataregister into thetransmitdatar and thetransmitdataregiste the bufferreadis Do notuseRead-modify-writeinstruct The SPIdataregisterist Bit 7654321Bit0 7R 5R 3R 1R0 R1 R2 R3 R4 R5 R6 R7 7T 5T 3T 1T0 T1 T2 T3 T4 T5 T6 T7 Figure 18-14.SPIData . not thesameasbufferwritten. egister. ReadingtheSPIda he read/writebufferfort Transmit DataBits r. WritingtotheSPIdat . Thetransmitdataandreceive Register(SPDR) cancontaindifferentvalues.See ions ontheSPIdataregistersince he receivedataregister ta registerreadsdata a registerwritesdata 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 19. Timer Interface Module B (TIMB)

19.1 Contents

19.2 Introduction...... 264 19.3 Features...... 264 19.4 Functional Description...... 266 19.4.1 TIMB Counter Prescaler...... 266 19.4.2 Input Capture ...... 267 19.4.3 Output Compare ...... 268 19.4.3.1 Unbuffered Output Compare...... 268 19.4.3.2 Buffered Output Compare...... 269 19.4.4 Pulse Width Modulation (PWM) ...... 270 19.4.4.1 Unbuffered PWM Signal Generation ...... 271

19.4.4.2 Buffered PWM Signal Generation...... 272 19.4.4.3 PWM Initialization ...... 272 19.5 Interrupts...... 274 19.6 Low-Power Modes ...... 274 19.6.1 Wait Mode ...... 274 19.6.2 Stop Mode ...... 274 19.7 TIMB During Break Interrupts ...... 275

19.8 I/O Signals ...... 275 19.8.1 TIMB Clock Pin (PTD4/ATD12/TBLCK) ...... 275 19.8.2 TIMB Channel I/O Pins (PTF5/TBCH1–PTF4/TBCH0) . .276 19.9 I/O Registers ...... 276 19.9.1 TIMB Status and Control Register ...... 277 19.9.2 TIMB Counter Registers ...... 279 19.9.3 TIMB Counter Modulo Registers...... 280 19.9.4 TIMB Channel Status and Control Registers...... 281 19.9.5 TIMB Channel Registers ...... 285

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module B (TIMB) 263 ehia aaMC68HC Semiconductor Freescale (TIMB) B Module Interface Timer 264 Technical Data 19.3 Features 19.2 Introduction Timer InterfaceModuleB(TIMB) Features oft please consulttheHC08Time For furtherinformationregardingti block diagram output compareandpulsewid 2-channel timerthatprov This sectiondescribesthetimerinte • TIMB Counter Stop and ResetBits Stopand TIMB Counter • Toggle Any ChannelPinonOverflow • Free-Running orModuloUp-CountOperation • Programmable TIMBClockInput • Buffered andUnbufferedPulse • Two InputCapture/Ou • External TIMBClockInput – 7 FrequencyInternalBusClockPrescalerSelection – Generation Set, ClearorToggleOu – Rising-Edge, Falling-Edgeor – he TIMBinclude: of theTIMB. ides atimingreferenc tput CompareChannels th modulationfunctions. r ReferenceManual,TIM08RM/AD. tput CompareAction mers onM68HC08familydevices, rface module(TIMB).TheTIMBisa (4MHzMaximumFrequency) Width Modulation(PWM)Signal Any-Edge InputCaptureTrigger e withinputcapture, Figure 19-1 08AZ60 — Rev 1.1 Rev — 08AZ60 isa Timer Interface Module B (TIMB) Features

TCLK PTD4/ATD12/TBLCK INTERNAL PRESCALER SELECT BUS CLOCK PRESCALER

TSTOP PS2 PS1 PS0 TRST

16-BIT COUNTER TOF INTER- RUPT TOIE LOGIC 16-BIT COMPARATOR TMODH:TMODL

CHANNEL 0 ELS0B ELS0A TOV0 16-BIT COMPARATOR CH0MAX PTF4 PTF4/TBCH0 LOGIC TCH0H:TCH0L CH0F INTER- 16-BIT LATCH RUPT CH0IE LOGIC MS0A MS0B CHANNEL 1 ELS1B ELS1A TOV1 16-BIT COMPARATOR CH1MAX PTF5 PTF5/TBCH1 LOGIC TCH1H:TCH1L CH1F INTER- 16-BIT LATCH RUPT LOGIC MS1A CH1IE

Figure 19-1. TIMB Block Diagram

Figure 19-2. TIMB I/O Register Summary

Addr.Register Name Bit 7654321Bit 0 R: TOF 00 $0040 TIMB Status/Control Register (TBSC) TOIE TSTOP PS2 PS1 PS0 W: 0TRSTR R: Bit 15 14 13 12 11 10 9 Bit 8 $0041 TIMB Counter Register High (TBCNTH) W: RRRRRRRR R: Bit 7654321Bit 0 $0042 TIMB Counter Register Low (TBCNTL) W: RRRRRRRR TIMB Counter Modulo Reg. High R: $0043 Bit 15 14 13 12 11 10 9 Bit 8 (TBMODH) W: TIMB Counter Modulo Reg. Low R: $0044 Bit 7654321Bit 0 (TBMODL) W: TIMB Ch. 0 Status/Control Register R: CH0F $0045 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX (TBSC0) W: 0 R: $0046 TIMB Ch. 0 Register High (TBCH0H) Bit 15 14 13 12 11 10 9 Bit 8 W:

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module B (TIMB) 265 ehia aaMC68HC Semiconductor Freescale (TIMB) B Module Interface Timer 266 Technical Data 19.4.1 TIMBCounterPrescaler 19.4 FunctionalDescription Timer InterfaceModuleB(TIMB) 04 TIMBCh.1RegisterLow(TBCH1L) $004A $0048 TIMBCh.0RegisterLow(TBCH0L) $0047 04 TIMBCh.1RegisterHigh(TBCH1H) $0049 Addr. RegisterName Bit 7654321Bit 0 TIMB Ch. 1Status/ControlRegister in theTIMBstatusand clock ratesfromtheinternalbusclo TIMB clockpin,PTD4/ATD12/TBL The TIMBclocksourcecanbeoneof capture oroutputcomparechannels. The twoTIMBchannelsareprogra any timewithoutaffect value oftheTIMBcount counter moduloregisters,TBMO reference fortheinputcaptureand counter oramoduloup-c TIMB isthe16-bitcounter Figure 19-1 Figure 19-2.TIMBI/ORegisterSummary (TBSC1) W: W: W: W: showstheTIMBstructure. R: R: R: R: CH1F i 51 31 11 Bit 8 9 10 11 12 13 14 Bit 15 BitBit 7654321Bit 7654321Bit 0 0 R= Reserved 0R ing thecountingsequence. CH1IE control registerselect er. Softwarecanreadthe ounter. TheTIMBcounter 0 thatcanoperate DH–TBMODL, controlthemodulo CK. Theprescale ck. Theprescalerselectbits,PS[2:0], output comparefunctions.TheTIMB mmable independentlyasinput SAESBESATV CH1MAX TOV1 ELS1A ELS1B MS1A the sevenprescaleroutputsor The centralcomponentofthe the TIMBclocksource. TIMB countervalueat as afree-running provides thetiming r generatesseven 08AZ60 — Rev 1.1 Rev — 08AZ60 Timer Interface Module B (TIMB) Functional Description

19.4.2 Input Capture

An input capture function has three basic parts: edge select logic, an input capture latch and a 16-bit counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The polarity of the active edge is programmable. The level transition which triggers the counter transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TBSC0 through TBSC1 control registers with x referring to the active channel number). When an active edge occurs on the pin of an input capture channel, the TIMB latches the contents of the TIMB counter into the TIMB channel registers, TBCHxH–TBCHxL. Input captures can generate TIMB CPU interrupt requests. Software can determine that an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit.

The free-running counter contents are transferred to the TIMB channel register (TBCHxH–TBCHxL, see TIMB Channel Registers on page 285) on each proper signal transition regardless of whether the TIMB

channel flag (CH0F–CH1F in TBSC0–TBSC1 registers) is set or clear. When the status flag is set, a CPU interrupt is generated if enabled. The value of the count latched or “captured” is the time of the event. Because this value is stored in the input capture register 2 bus cycles after the actual event occurs, user software can respond to this event at a later time and determine the actual time of the event. However, this must be done prior to another input capture on the same pin; otherwise, the previous time value will be lost.

By recording the times for successive edges on an incoming signal, software can determine the period and/or pulse width of the signal. To measure a period, two successive edges of the same polarity are captured. To measure a pulse width, two alternate polarity edges are captured. Software should track the overflows at the 16-bit module counter to extend its range.

Another use for the input capture function is to establish a time reference. In this case, an input capture function is used in conjunction with an output compare function. For example, to activate an output signal a specified number of clock cycles after detecting an input event

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module B (TIMB) 267 ehia aaMC68HC Semiconductor Freescale (TIMB) B Module Interface Timer 268 Technical Data 19.4.3.1 Unbuffer 19.4.3 OutputCompare Timer InterfaceModuleB(TIMB) ed OutputCompare Channel Registers output compareva Use thefollowingmethodstosynch pass thenewvaluebef compare valuemaycaus using aTIMBoverflowinterruptrout value preventsanycompareduringthat counter reachestheold counter overflowperiods.Forexampl output comparevaluecouldcause An unsynchronizedwritetothe the newvalueoverol unbuffered becausechangingtheoutput pulses asdescribedin Any outputcomparechannelcan CPUinterruptrequests. generate TIMB the TIMBcanset,clear pulse withaprogr With theoutputcomparefunction, (TBCHxH–TBCHxL). Reset doesnotaffectthecontentsof latencies. software delay canbecontrolledtothereso output comparesarerefe this capturedvalueandstoredto edge occurred.Anumberco (edge), usetheinputcapturefunction counter reachesthevalueinr ammable polarity,duration lue onchannelx: on page285).Becausebothinputcapturesand Output Compare ore itiswritten. or togglethec value butafterthec d valuecurrentlyinth renced tothesame16-bitmodulocounter, e thecomparetobe rresponding tothedesir TIMB channelregisterstochangean egisters ofanoutput an outputcompareregister(see generate unbufferedoutputcompare theTIMBcan lution ofthecounterindependent incorrect operati ronize unbufferedchangesinthe ine towriteanew e, writinganew the inputcapture hannel pin.Outputcomparescan to recordthetimeatwhich counteroverflowperiod.Also, compare valuerequireswriting on page268.Thepulsesare ounter reachesthenew andfrequen e TIMBchannelregisters. missed. TheTIMBmay generate aperiodic ed delayisaddedto on foruptotwo comparechannel, , smalleroutput value beforethe channel register 08AZ60 — Rev 1.1 Rev — 08AZ60 cy. Whenthe TIMB Timer Interface Module B (TIMB) Functional Description

• When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. • When changing to a larger output compare value, enable TIMB overflow interrupts and write the new value in the TIMB overflow interrupt routine. The TIMB overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period.

19.4.3.2 Buffered Output Compare

Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the PTF4/TBCH0 pin. The TIMB channel registers of the linked pair alternately control the output.

Setting the MS0B bit in TIMB channel 0 status and control register (TBSC0) links channel 0 and channel 1. The output compare value in the TIMB channel 0 registers initially controls the output on the PTF4/TBCH0 pin. Writing to the TIMB channel 1 registers enables the TIMB channel 1 registers to synchronously control the output after the TIMB overflows. At each subsequent overflow, the TIMB channel registers (0 or 1) that control the output are the ones written to last. TBSC0 controls and monitors the buffered output compare function and TIMB channel 1 status and control register (TBSC1) is unused. While the MS0B bit is set, the channel 1 pin, PTF5/TBCH1, is available as a general-purpose I/O pin.

NOTE: In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module B (TIMB) 269 ehia aaMC68HC Semiconductor Freescale (TIMB) B Module Interface Timer 270 Technical Data 19.4.4 PulseWidt Timer InterfaceModuleB(TIMB) h Modulation(PWM) 256 increments.Writing produces adutycycl the PWMoutput.Thepuls The valueintheTIMBchannelregist value is$000(see period of256timesthein $00FF (255)totheTIMB frequency ofan8-bitPWMsignalisva prescaler outputdeterminesthe The valueintheTIMBcounterm pulse islogic0. between overflowandoutput registers determinest As signal. modulo registers.Thetimebetweenov pin toggleswhenthecounterreaches modulo registersdetermi pulse islogic1.Program TIMB toclearthechannel the TIMBcangenerate By usingthetoggle-on-overflowf PTEx/TCHx Figure 19-3 VRLWOEFO OVERFLOW OVERFLOW OVERFLOW Figure 19-3.PWMPeri shows,theoutputcompare WIDTH PULSE TIMB Statusand PERIOD e of128/256or50%. he pulsewidthofthe COMPARE a PWMsignal.Thevaluein OUTPUT $0080 (128)totheTIMB nes theperiodofth countermoduloregi the TIMBtosetpin pinonoutputcompareif ternal busclockperiodif e widthofan8-bitPWM compareisthepulse eature withanoutputcomparechannel, frequency ofthePWMoutput.The odulo registersand ers determinesthepulsewidthof od andPulseWidth Control Register thevalueinTIMBcounter riable in256 erflows istheperiodofPWM PWM signal.Thetime e PWMsignal.Thechannel value intheTIMBchannel COMPARE OUTPUT sters producesaPWM if thestateofPWM channelregisters thestateofPWM theprescalerselect width.Programthe signal isvariablein theTIMBcounter theselected crements. Writing ). 08AZ60 — Rev 1.1 Rev — 08AZ60 COMPARE OUTPUT Timer Interface Module B (TIMB) Functional Description

19.4.4.1 Unbuffered PWM Signal Generation

Any output compare channel can generate unbuffered PWM pulses as described in Pulse Width Modulation (PWM) on page 270. The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the value currently in the TIMB channel registers.

An unsynchronized write to the TIMB channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIMB overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIMB may pass the new value before it is written to the TIMB channel registers.

Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:

• When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. • When changing to a longer pulse width, enable TIMB overflow interrupts and write the new value in the TIMB overflow interrupt routine. The TIMB overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period.

NOTE: In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module B (TIMB) 271 ehia aaMC68HC Semiconductor Freescale (TIMB) B Module Interface Timer 272 Technical Data 19.4.4.3 PWM 19.4.4.2 BufferedPWMSignalGeneration Timer InterfaceModuleB(TIMB) NOTE: Initialization PWM signals,usethefollow To ensurecorrectoperationwhengen to thecurrentlyactive In bufferedPWMsignalgener TIMB channel1regist initially controlthepulsewidthon (TBSC0) linkschannel Setting theMS0BbitinTIMBchanne the linkedpairalternatelycontro output appearsonthe Channels 0and1canbe generating unbuffer channel. Writingtotheactivec currently activechanneltoprevent pin. the channel1pin,PTF5/ status andcontrolregister(TBSC1)is 1) thatcontrolthepul period. Ateachsubsequentoverflow, synchronously controlthepulsewidth controls andmonitorsthebuffer .In theTIMBstatusand 1. .IntheTIMBchannel 3. IntheTIMBcountermodulo 2. value fortherequ the valuefor .Reset the TIMBcounterandpr b. StoptheTIMBcounterbysett a. reset bit,TRST. reset ed PWMsignals. se widtharetheones channel registers.Userso ers enablestheTIMB PTF4/TBCH0 pin.TheTIMB required PWMperiod. 0 andchannel1. ired pulse width. pulse ired TBCH1, isavailable linked toformabufferedPWMchannelwhose xregisters(TBCHxH ing initializat control register(TBSC): ation, donotwritenewpulsewidthvalues hannel registersis ed PWMfunction,and l thepulsewidthofoutput. the PTF4/TBCH0pin. registers (TBMO writing anewvaluetotheactive unused.WhiletheMS0Bbitisset, l 0statusandcontrolregister at thebeginningofnextPWM the TIMBchannelregisters(0or erating unbufferedorbuffered The TIMBchannel0registers ion procedure: ing theTIMBstopbit,TSTOP. escaler bysettingtheTIMB written tolast.TBSC0 channel 1regi as ageneral-purposeI/O –TBCHxL) writethe ftware shouldtrackthe thesameas channelregistersof DH–TBMODL) write TIMB channel1 08AZ60 — Rev 1.1 Rev — 08AZ60 Writing tothe Writing sters to Timer Interface Module B (TIMB) Functional Description

4. In TIMB channel x status and control register (TBSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB–MSxA (see Table 19-2). b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB–ELSxA. The output action on compare must force the output to the complement of the pulse width level (see Table 19-2).

NOTE: In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.

5. In the TIMB status control register (TBSC) clear the TIMB stop bit, TSTOP.

Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIMB channel 0 registers (TBCH0H–TBCH0L) initially control the buffered PWM output. TIMB status control register 0 (TBSC0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A.

Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIMB overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output.

Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output (see TIMB Channel Status and Control Registers on page 281).

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module B (TIMB) 273 ehia aaMC68HC Semiconductor Freescale (TIMB) B Module Interface Timer 274 Technical Data 19.6.2 StopMode 19.6.1 WaitMode 19.6 Low-Power Modes 19.5 Interrupts Timer InterfaceModuleB(TIMB) TIMB counter.oper do STOP instruction The TIMBisinactiveaf consumption bystoppi If TIMBfunctionsarenotrequir wait mode. enabled CPUinterruptreque wait mode,theTIMBr The TIMBremainsactiveaf consumption standbymodes. The WAITandSTOPin The followingTIMBsourcescan instruction. TIMB overflowflag(TOF)—TheTO • TIMB channelflags(CH1F–CH0F) • interrupt enablebit,CHxIE. CPUinterruptr TIMB input captureoroutputcompar TIMB overflowCPUin registers. TheTIMBoverflowin counter valuereaches TIMB statusandcontrolregister. es notaffectregistercond egisters arenotaccessib ng theTIMBbeforeex ter theexecutionofa structions putthe ation resumeswhent equests arecontrolled ter theexecutionofa terrupt requests.TOFan st fromtheTIMBcan the valueinT ed duringwaitmode,reducepower generate interruptrequests: e occursonchannelx.Channelx terrupt enablebi —TheCHxFbitissetwhenan MCU inlowpower- F bitissetwhentheTIMB STOP instruction.The ecuting theWAIT itions orthestateof he MCUexitsstopmode. IMB countermodulo le by the CPU. Any le bythe WAIT instruction.In bring theMCUoutof by thechannelx d TOIEareinthe t, TOIE,enables 08AZ60 — Rev 1.1 Rev — 08AZ60 Timer Interface Module B (TIMB) TIMB During Break Interrupts

19.7 TIMB During Break Interrupts

A break interrupt stops the TIMB counter and inhibits input captures.

The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state (see SIM Break Flag Control Register on page 119).

To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state.

To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the

second step clears the status bit.

19.8 I/O Signals

Port D shares one of its pins with the TIMB. Port F shares two of its pins with the TIMB. PTD4/ATD12/TBLCK is an external clock input to the TIMB prescaler. The two TIMB channel I/O pins are PTF4/TBCH0 and PTF5/TBCH1.

19.8.1 TIMB Clock Pin (PTD4/ATD12/TBLCK)

PTD4/ATD12/TBLCK is an external clock input that can be the clock source for the TIMB counter instead of the prescaled internal bus clock. Select the PTD4/ATD12/TBLCK input by writing logic 1s to the three prescaler select bits, PS[2:0] (see TIMB Status and Control Register). The minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is: 1 ------+ t bus frequency SU

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module B (TIMB) 275

19.8.2 TIMBChan ehia aaMC68HC Semiconductor Freescale (TIMB) B Module Interface Timer 276 Technical Data 19.9 I/ORegisters Timer InterfaceModuleB(TIMB) nel I/OPins(PTF5/TBCH1–PTF4/TBCH0) capture pinoranoutput Each channelI/Opinisprogr of thestate PTD4/ATD12/TBLCK pinist channel whennotused can beconfiguredasbufferedoutput PTD4/ATD12/TBLCK isavailableas These I/Oregisterscontrol The maximumTCLKfrequencyisthe TIMB channelregisters(T • TIMB channelstatusandcontro • TIMB countermoduloregi • TIMB controlregist • TIMB statusandcont • DDRD4 bitindatadi astheTIMBcl compare pin.PTF4/TBCH0 ers (TBCNTH–TBCNTL) and monitorTIMBoperation: rol register(TBSC) he TIMBclockinput,it ammable independently BCH0H–TBCH0L, TBCH1H–TBCH1L) sters (TBMODH–TBMODL) ageneral-purpose compareorbufferedPWMpins. least: 4MHzor l registers(T ock input.Whenthe rection registerD. is aninputregardless BSC0 andTBSC1)

and busfrequency asaninput 08AZ60 — Rev 1.1 Rev — 08AZ60 I/O pinorADC

PTF5/TBCH1 ÷ 2. Timer Interface Module B (TIMB) I/O Registers

19.9.1 TIMB Status and Control Register

The TIMB status and control register:

• Enables TIMB overflow interrupts • Flags TIMB overflows • Stops the TIMB counter • Resets the TIMB counter • Prescales the TIMB counter clock

Address: $0040 Bit 7654321Bit 0 Read: TOF 00 TOIE TSTOP PS2 PS1 PS0 Write: 0 TRST R Reset:00100000 R= Reserved

Figure 19-4. TIMB Status and Control Register (TBSC)

TOF — TIMB Overflow Flag Bit This read/write flag is set when the TIMB counter reaches the modulo value programmed in the TIMB counter modulo registers. Clear TOF by reading the TIMB status and control register when TOF is set and then writing a logic 0 to TOF. If another TIMB overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect. 1 = TIMB counter has reached modulo value 0 = TIMB counter has not reached modulo value

TOIE — TIMB Overflow Interrupt Enable Bit This read/write bit enables TIMB overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIMB overflow interrupts enabled 0 = TIMB overflow interrupts disabled

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module B (TIMB) 277 ehia aaMC68HC Semiconductor Freescale (TIMB) B Module Interface Timer 278 Technical Data Timer InterfaceModuleB(TIMB) NOTE: NOTE: PS[2:0] — Prescaler SelectBits PS[2:0] —Prescaler counter atavalueof$0000. Setting theTSTOPandTRSTbits Bit —TIMBReset TRST until TSTOPiscleared. is configuredforinput required toexitwaitm Do notsettheTSTOPbitbeforeenter TSTOP —TIMBStopBit as one ofthesevenprescaleroutputsas These read/writebitsselecteit counter isresetandalwaysreads as automaticallyTIMB afterTRST iscleared the resumes from$0000. registers.effect Counting prescaler. Setting onanyother TRSThasno Setting this write-only bit resets the TIMB counter and the TIMB counter untilsoftware TSTOP iscleared.Resetsetst This read/writebitstop 0 =Noeffect 1 =PrescalerandTIMBcountercleared 0 =TIMBcounteractive 1 =TIMBcounterstopped Table 19-1 S20 TIMBClock Source PS[2:0] 1 PTD4/ATD12/TBLCK Clock Bus Internal Clock Bus Internal Clock Bus Internal Clock Bus Internal Clock Bus Internal Clock Bus Internal 111 110 101 100 011 010 001 000 Internal Bus Clock Bus Internal 000 shows.Resetclear Table 19-1.Pres ode. Also,whentheTSTOP capture operation, clears theTSTOPbit. s theTIMBcounter. her thePTD4/ATD12/TBLCKpinor he TSTOPbit,stoppingtheTIMB simultaneouslystopstheTIMB s thePS[2:0]bits. caler Selection ing wait mode if the TIMB is is TIMB the if mode ing wait logic 0. Reset clears the TRST bit. the TRST clears logic 0.Reset theinputtot inputcaptures Counting resumeswhen bit issetandthetimer he TIMBcounter ÷ ÷ ÷ ÷ ÷ ÷ ÷ 08AZ60 — Rev 1.1 Rev — 08AZ60 areinhibited 64 32 16 4 1 8 2 Timer Interface Module B (TIMB) I/O Registers

19.9.2 TIMB Counter Registers

The two read-only TIMB counter registers contain the high and low bytes of the value in the TIMB counter. Reading the high byte (TBCNTH) latches the contents of the low byte (TBCNTL) into a buffer. Subsequent reads of TBCNTH do not affect the latched TBCNTL value until TBCNTL is read. Reset clears the TIMB counter registers. Setting the TIMB reset bit (TRST) also clears the TIMB counter registers.

NOTE: If TBCNTH is read during a break interrupt, be sure to unlatch TBCNTL by reading TBCNTL before exiting the break interrupt. Otherwise, TBCNTL retains the value latched during the break.

Register Name and Address TBCNTH — $0041

Bit 7654321Bit 0

Read: BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8

Write:RRRRRRRR

Reset:00000000

Register Name and Address TBCNTL — $0042

Bit 7654321Bit 0

Read: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

Write:RRRRRRRR

Reset:00000000

RR = Reserved Figure 19-5. TIMB Counter Registers (TBCNTH and TBCNTL)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module B (TIMB) 279 ehia aaMC68HC Semiconductor Freescale (TIMB) B Module Interface Timer 280 Technical Data 19.9.3 TIMBCounterModuloRegisters Timer InterfaceModuleB(TIMB) NOTE: registers. Reset theTIMBcounterbeforewr (TBMODH) inhibitstheTO counting from$0000att overflow flag(TOF)becomesse TIMB counter.Whenthecounter The read/writeTIMBmodulo (TBMODL) iswritten.Resetsets Reset:11111111 Reset:11111111 Read: Read: Write: Write: eitrNm n drs TBMODL —$0044 Register NameandAddress TBMODH —$0043 Register NameandAddress Figure 19-6.TIMB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT BIT9 BIT10 BIT11 BIT12 BIT13 BIT14 BIT 15 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT BIT 7 Bit 7654321BitBit 7654321Bit 0 0 CounterModuloR he nexttimerclock.Wr F bitandoverflowinterr registers containthe TBMODL) t andtheTIMBcounterresumes iting totheTIMB the TIMBcounter reachesthem egisters (TBMODHand iting tothehighbyte countermodulo upts untilthelowbyte modulo valueforthe modulo registers. odulo value,the 08AZ60 — Rev 1.1 Rev — 08AZ60 Timer Interface Module B (TIMB) I/O Registers

19.9.4 TIMB Channel Status and Control Registers

Each of the TIMB channel status and control registers:

• Flags input captures and output compares • Enables input capture and output compare interrupts • Selects input capture, output compare or PWM operation • Selects high, low or toggling output on output compare • Selects rising edge, falling edge or any edge as the active input capture trigger • Selects output toggling on TIMB overflow • Selects 0% and 100% PWM duty cycle • Selects buffered or unbuffered output compare/PWM operation

Register Name and Address TBSC0 — $0045

Bit 7654321Bit 0

Read: CH0F CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Write: 0

Reset:00000000

Register Name and Address TBSC1 — $0048

Bit 7654321Bit 0

Read: CH1F 0 CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX Write: 0 R

Reset:00000000

RR = Reserved Figure 19-7. TIMB Channel Status and Control Registers (TBSC0–TBSC1)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module B (TIMB) 281 ehia aaMC68HC Semiconductor Freescale (TIMB) B Module Interface Timer 282 Technical Data Timer InterfaceModuleB(TIMB) MSxB —ModeSelectBitB CHxIE —ChannelxIn CHxF —Chann Reset clearstheMSxBbit. reverts TBCH1to Setting MS0Bdisablesthechannel MSxB existsonlyin This read/writebitsele Reset clearstheCHxIEbit. This read/writebitenabl Reset clearstheCHxFbit. interrupt requestcannotbelostdue complete, thenwritingl another interruptrequestoccurs control registerwithCHxFset,a When CHxIE=1,clearCHxFbyre counter registersmatche an outputcomparechannel,CHxFis when anactiveedgeoccursonthe When channelxisaninpu 0 =Bufferedoutputcompar 1 =Bufferedoutputcom 0 =ChannelxCPUinterr 1 =ChannelxCPUinte 0 =Noinputcaptureor 1 =Inputcaptureorout el xFlagBit general-purpose I/O. theTIMBchannel0. terrupt EnableBit cts bufferedoutputco ogic 0toCHxFhasno es TIMBCPUinterruptsonchannelx. s thevalueinTI put compareonchannelx Writingalogic1to rrupt requestsenabled output compareonchannelx t capturechannel,this pare/PWM operationenabled upt requestsdisabled e/PWM operationdisabled nd thenwritingalogi before theclearingsequenceis ading TIMBchannelxstatusand channel xpin.Whenis 1 statusandcontrolregister to inadvertent set whenthevalueinTIMB mpare/PWM operation. MB channelxregisters. CHxFhasnoeffect. effect. Therefore,an read/write bitisset clearing ofCHxF. 08AZ60 — Rev 1.1 Rev — 08AZ60 c 0toCHxF.If Timer Interface Module B (TIMB) I/O Registers

MSxA — Mode Select Bit A When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation (see Table 19-2). 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TBCHx pin once PWM, input capture or output compare operation is enabled (see Table 19-2). Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high

NOTE: Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIMB status and control register (TBSC).

ELSxB and ELSxA — Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x.

When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to port F and pin PTFx/TBCHx is available as a general-purpose I/O pin. However, channel x is at a state determined by these bits and becomes transparent to the respective pin when PWM, input capture, or output compare mode is enabled. Table 19-2 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module B (TIMB) 283 ehia aaMC68HC Semiconductor Freescale (TIMB) B Module Interface Timer 284 Technical Data Timer InterfaceModuleB(TIMB) NOTE: NOTE: channel xoutputcompareifbot When TOVxisset,aTIMBcounter TOVx —Toggle-On-OverflowBit make surethatthePTFx/TBCHxpinis Before enablingaTIMB SBMx Lx:Lx oeConfiguration Mode ELSxB:ELSxA MSxB:MSxA effect. Reset clear effect. Reset overflows. Whenchannelxisani controls thebehaviorofchannel When channelxisanoutputcompar 0 =Channelxpindoesnottoggl 1 =ChannelxpintogglesonTIMBcounteroverflow. 100 X1 000 X0 X0 Buffered 01 1X 1X 11 Set Output on Compare on Output Set Compare on Output Clear 11 10 1X 1X 00 11 Capture on Rising or Falling CaptureonRising Edge CaptureonFalling EdgeOnly 01 11 10 01 01 00 00 00 01 11 Set Output on Compare on Output Set Compare on Output Clear 11 10 01 01 Table Edge, 19-2.Mode, s theTOVxbit. channel registerforinputcaptureoperation, or Bufferedor Compare Compare Compare or PWM or Capture h occuratthesametime. Output Output Output Preset Output Output PWM Input overflowtakesprecedenceovera nput capturechannel,TOVxhasno andLevel Selection e onTIMBcounteroverflow. stableforatleasttwobusclocks. xoutputwhentheTIMBcounter e channel,thisread/writebit Pin under PortControl; Capture onEdge Rising Only Pin under PortControl; Toggle Compare on Output Toggle Compare on Output Output LevelLow Initialize Timer Output LevelHigh Initialize Timer 08AZ60 — Rev 1.1 Rev — 08AZ60 Timer Interface Module B (TIMB) I/O Registers

CHxMAX — Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 19-8 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.

OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW

PERIOD

PTEx/TCHx

OUTPUT OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE COMPARE

CHxMAX

Figure 19-8. CHxMAX Latency

19.9.5 TIMB Channel Registers

These read/write registers contain the captured TIMB counter value of the input capture function or the output compare value of the output compare function. The state of the TIMB channel registers after reset is unknown.

In input capture mode (MSxB–MSxA = 0:0) reading the high byte of the TIMB channel x registers (TBCHxH) inhibits input captures until the low byte (TBCHxL) is read.

In output compare mode (MSxB–MSxA ≠ 0:0) writing to the high byte of the TIMB channel x registers (TBCHxH) inhibits output compares and the CHxF bit until the low byte (TBCHxL) is written.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module B (TIMB) 285 ehia aaMC68HC Semiconductor Freescale (TIMB) B Module Interface Timer 286 Technical Data Timer InterfaceModuleB(TIMB) ee:Indeterminateafter Reset Indeterminateafter Reset Reset: Indeterminateafter Reset Reset: Indeterminateafter Reset Reset: Reset: Read: Read: Read: Read: Write: Write: Write: Write: Register Name and Address TBCH1L —$004A TBCH1L Register NameandAddress TBCH1H —$0049 Register NameandAddress —$0047 TBCH0L Register NameandAddress TBCH0H —$0046 Register NameandAddress Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 9 Bit 10 Bit Bit11 Bit12 Bit13 Bit14 Bit 15 8 Bit 9 Bit 10 Bit Bit11 Bit12 Bit13 Bit14 Bit 15 BitBit 7Bit 7654321BitBit 6BitBit 5Bit 7654321BitBit 0 7Bit 4Bit 7654321BitBit 0 6Bit 3Bit 5Bit 2Bit 7654321Bit 0 4Bit 1Bit 0 3Bit 0 2Bit 1Bit 0 Figure 19-9.TIMB (TBCH0H/L–TBCH1H/L) ChannelRegisters 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 20. Programmable Interrupt Timer (PIT)

20.1 Contents

20.2 Introduction...... 289 20.3 Features...... 290 20.4 Functional Description...... 290 20.5 PIT Counter Prescaler ...... 291 20.6 Low-Power Modes ...... 292 20.6.1 Wait Mode ...... 292 20.6.2 Stop Mode ...... 292 20.7 PIT During Break Interrupts...... 292

20.8 I/O Registers ...... 293 20.8.1 PIT Status and Control Register ...... 293 20.8.2 PIT Counter Registers ...... 296 20.8.3 PIT Counter Modulo Registers ...... 297

20.2 Introduction

This section describes the Programmable Interrupt Timer (PIT) which is a periodic interrupt timer whose counter is clocked internally via software programmable options. Figure 20-1 is a block diagram of the PIT.

For further information regarding timers on M68HC08 family devices, please consult the HC08 Timer Reference Manual, TIM08RM/AD.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Programmable Interrupt Timer (PIT) 289 ehia aaMC68HC Semiconductor Freescale (PIT) Timer Interrupt Programmable 290 Technical Data 20.4 FunctionalDescription 20.3 Features Programmable InterruptTimer(PIT) BUS CLOCK INTERNAL CSTOP CRST 16-BIT COMPARATOR 16-BIT COUNTER PMODH:PMODL sequence. read thecountervalue PMODH–PMODL, controlthemodulova reference fortheinte counter oramoduloup-counter.The the PITis16-bit Figure 20-1 Features ofthePITinclude: PRESCALER PIT CounterStopandResetBits • Free-Running orModuloUp-CountOperation • Programmable PITClockInput • Figure 20-1.PITBlockDiagram showsthestructureof PPS2 PIT counterthatcano rrupt. ThePITcounter PRESCALER SELECT at anytimewithoutaffectingthecounting PPS1 PPS0 counter providesthetiming PIT. Thecentralcomponentof lue ofthecounter.Softwarecan perate asafree-running moduloregisters, POIE POF 08AZ60 — Rev 1.1 Rev — 08AZ60 INTER- LOGIC RUPT Programmable Interrupt Timer (PIT) PIT Counter Prescaler

Register NameBit 7654321Bit 0 Read: POF 00 PIT Status and Control Register POIE PSTOP PPS2 PPS1 PPS0 Write: 0 PRST (PSC) Reset:00100000 Read: Bit 15 14 13 12 11 10 9 Bit 8 PIT Counter Register High Write: (PCNTH) Reset:00000000 Read: Bit 7 654321Bit 0 PIT Counter Register Low Write: (PCNTL) Reset:00000000 Read: PIT Counter Modulo Register High Bit 15 14 13 12 11 10 9 Bit 8 Write: (PMODH) Reset:11111111 Read: PIT Counter Modulo Register Low Bit 7654321Bit 0 Write: (PMODL) Reset:11111111

=Unimplemented

Figure 20-2. PIT I/O Register Summary

Table 20-1. PIT I/O Register Address Summary

Register PSC PCNTH PCNTL PMODH PMODL

Address $004B $004C $004D $004E $004F

20.5 PIT Counter Prescaler

The clock source can be one of the seven prescaler outputs. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PPS[2:0], in the status and control register select the PIT clock source.

The value in the PIT counter modulo registers and the selected prescaler output determines the frequency of the periodic interrupt. The PIT overflow flag (POF) is set when the PIT counter value reaches the

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Programmable Interrupt Timer (PIT) 291

20.6.2 StopMode ehia aaMC68HC Semiconductor Freescale (PIT) Timer Interrupt Programmable 292 Technical Data 20.7 PITDuring 20.6.1 WaitMode 20.6 Low-Power Modes Programmable InterruptTimer(PIT) BreakInterrupts external interrupt. external counter. PIToperationresumeswhen instruction doesno The PITisinactiveaftertheexecuti consumption bystoppingthePITbefor If PITfunctionsarenotrequired interrupt request from request interrupt on page119). status bitsduring the SIMbreakflagcontro other modulescanbeclearedduringth The systemintegrationmodule(SIM)c A breakinterruptst mode thePITregisters The PITremainsactiveaftertheexecuti tion standbymodes. The WAITandSTOPinst POF andPOIEareinthePIT interrupt enablebit,POIE,enablesPIT modulo valueprogrammed the breakstate(see t affectregisterconditions ops thePITcounter. the PITcanbring are notaccessibleby l register(SBFCR)enabl ructions puttheMCU in thePITcounterm status andcontrolregister. during waitmode, on ofaSTOPinstruction.The SIM BreakFlagControlRegister the MCUexitsstopmodeafteran e executingtheWAITinstruction. overflow CPUinte ontrols whetherstatusbitsin e breakstate.TheBCFEbitin on ofaWAITinstruction.Inwait the CPU.AnyenabledCPU MCU outofwaitmode. orthestateofPIT odulo registers.ThePIT in lowpower-consump- es software to clear clear to es software reducepower 08AZ60 — Rev 1.1 Rev — 08AZ60 rrupt requests. Programmable Interrupt Timer (PIT) I/O Registers

To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state.

To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit.

20.8 I/O Registers

The following I/O registers control and monitor operation of the PIT:

• PIT status and control register (PSC) • PIT counter registers (PCNTH–PCNTL)

• PIT counter modulo registers (PMODH–PMODL)

20.8.1 PIT Status and Control Register

The PIT status and control register:

• Enables PIT interrupt • Flags PIT overflows • Stops the PIT counter • Resets the PIT counter • Prescales the PIT counter clock

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Programmable Interrupt Timer (PIT) 293 ehia aaMC68HC Semiconductor Freescale (PIT) Timer Interrupt Programmable 294 Technical Data Programmable InterruptTimer(PIT) drs:$004B Address: POF —PITOverflowFlagBit PSTOP — PIT StopBit PSTOP —PIT POIE —PITOverflow Reset:00100000 ed POF Read: rt:0PRST 0 Write: clearing sequenceiscomp writing alogic0toPO reading thePITstatus value programmedinthePITcounter This read/writeflagis This read/writebitstop 1 toPOFhas inadvertent clearingofPOF.Reset effect. Therefore,aPOFinterrup counter untilsoftware PSTOP iscleared.Resetsets POIEbit. the clears Reset becomes set. This read/writebit 0 =PIToverflow 1 =PIToverflow 0 =PITcounterhasnotreachedmodulovalue 1 =PITcounterhas 0 =PITcounteractive 1 =PITcounterstopped Figure 20-3.PITStatusand Bit 7654321Bit 0 = Unimplemented OEPSTOP POIE no effect. enables PIToverflowinte interrupts disabled interrupts enabled Interrupt EnableBit andcontrolregisterwhenPOFissetthen F. IfanotherPIToverfl set whenthePITcounter clears thePSTOPbit. s thePITcounter.Countingresumeswhen reached modulovalue lete, thenwritingl the PSTOPbit, 00 t requestcannot Control Register(PSC) clears thePOFbit.Writingalogic moduloregisters.ClearPOFby rrupts whenthePOFbit ogic 0toPOFhasno ow occursbeforethe P2PS PPS0 PPS1 PPS2 stopping thePIT reachesthemodulo be lostdueto 08AZ60 — Rev 1.1 Rev — 08AZ60 Programmable Interrupt Timer (PIT) I/O Registers

NOTE: Do not set the PSTOP bit before entering wait mode if the PIT is required to exit wait mode.

PRST — PIT Reset Bit Setting this write-only bit resets the PIT counter and the PIT prescaler. Setting PRST has no effect on any other registers. Counting resumes from $0000. PRST is cleared automatically after the PIT counter is reset and always reads as logic zero. Reset clears the PRST bit. 1 = Prescaler and PIT counter cleared 0 = No effect

NOTE: Setting the PSTOP and PRST bits simultaneously stops the PIT counter at a value of $0000.

PPS[2:0] — Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the PIT counter as Table 20-2 shows. Reset clears the PPS[2:0] bits.

Table 20-2. Prescaler Selection

PPS[2:0] PIT Clock Source 000 Internal Bus Clock ÷1 001 Internal Bus Clock ÷ 2 010 Internal Bus Clock ÷ 4 011 Internal Bus Clock ÷ 8 100 Internal Bus Clock ÷ 16 101 Internal Bus Clock ÷ 32 110 Internal Bus Clock ÷ 64 111 Internal Bus Clock ÷ 64

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Programmable Interrupt Timer (PIT) 295 ehia aaMC68HC Semiconductor Freescale (PIT) Timer Interrupt Programmable 296 Technical Data 20.8.2 PITCount Programmable InterruptTimer(PIT) NOTE: er Registers drs:$004D Address: drs:$004C Address: also clearsthePI Reset clearsthePITcounterregister PCNTH donotaffectth the contentsoflowbyte(PCNTL) of thevalueinPITcounter.Readi The tworead-onlyPITcounterregist retains the value latc thevalue retains by readingPCNTLbeforeexitingthe If youreadPCNTHduringabreakin Reset:00000000Reset:00000000 Read: Bit 15 14 13 12 11 10 9 Bit 8 Bit 9 10 11 12 13 14 Bit15 Read: Read: Bit 15 14 13 12 11 10 9 Bit 8 Bit 9 10 11 12 13 14 Bit15 Read: Write: Write: Figure 20-4.PITCounter Bit 7654321Bit 0 Bit 7654321Bit 0 = Unimplemented T counterregisters. hed duringthebreak. e latchedPCNTLvalue Registers (PCNTH–PCNTL) break interrupt.Otherwise,PCNTL ers containthehighandlowbytes intoabuffer.Subsequentreadsof terrupt, besureto s. SettingthePIT ng thehighbyte until PCNTLisread. (PCNTH)latches unlatchPCNTL reset bit (PRST) (PRST) bit reset 08AZ60 — Rev 1.1 Rev — 08AZ60 Programmable Interrupt Timer (PIT) I/O Registers

20.8.3 PIT Counter Modulo Registers

The read/write PIT modulo registers contain the modulo value for the PIT counter. When the PIT counter reaches the modulo value the overflow flag (POF) becomes set and the PIT counter resumes counting from $0000 at the next timer clock. Writing to the high byte (PMODH) inhibits the POF bit and overflow interrupts until the low byte (PMODL) is written. Reset sets the PIT counter modulo registers.

Address: $004E:$004F

Bit 7654321Bit 0

Read: Bit 15 14 13 12 11 10 9 Bit 8 Write:

Reset:11111111

Address: $004E:$004F

Bit 7654321Bit 0

Read:

Bit 7654321Bit 0 Write:

Reset:11111111 Figure 20-5. PIT Counter Modulo Registers (PMODH–PMODL)

NOTE: Reset the PIT counter before writing to the PIT counter modulo registers.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Programmable Interrupt Timer (PIT) 297 ehia aaMC68HC Semiconductor Freescale (PIT) Timer Interrupt Programmable 298 Technical Data Programmable InterruptTimer(PIT) 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 21. Input/Output Ports

21.1 Contents

21.2 Introduction...... 300 21.3 Port A...... 301 21.3.1 Port A Data Register ...... 301 21.3.2 Data Direction Register A ...... 301 21.4 Port B...... 303 21.4.1 Port B Data Register ...... 303 21.4.2 Data Direction Register B ...... 304 21.5 Port C...... 306 21.5.1 Port C Data Register ...... 306 21.5.2 Data Direction Register C ...... 307 21.6 Port D...... 309 21.6.1 Port D Data Register ...... 309 21.6.2 Data Direction Register D ...... 310 21.7 Port E ...... 312 21.7.1 Port E Data Register...... 312 21.7.2 Data Direction Register E ...... 314

21.8 Port F ...... 316 21.8.1 Port F Data Register...... 316 21.8.2 Data Direction Register F ...... 317 21.9 Port G...... 319 21.9.1 Port G Data Register ...... 319 21.9.2 Data Direction Register G ...... 320

21.10 Port H...... 321 21.10.1 Port H Data Register ...... 321 21.10.2 Data Direction Register H ...... 322

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Input/Output Ports 299

300 Input/Output Ports Freescale Semiconductor Freescale MC68HC Ports Input/Output 300 Technical Data 21.2 Introduction Input/Output Ports 00 DataDirection Register DataDirection Register $000F $000E 00 otHDt eitr(T)000000PH PTH0 PTH1 PTG0 0 PTG1 PTG2 0 0 0 PTF0 0 PTF1 0 PTF2 PTE0 0 PTF3 PTE1 0 PTF4 PTE2 0 PTF5 PTE3 0 DataDirectionRegisterF(DDRF) PTF6 PTE4 DD PortHDataRegister(PTH) 0 DataDirection RegisterE(DDRE) PTE5 0 Port GDataRegister(PTG) PTE6 $000D PortFData Register (PTF) PTE7 $000C PortEDataRegister(PTE) $000B $000A $0009 $0008 00 aaDrcinRgse DR)DDR DataDirection RegisterD(DDRD) DataDirection RegisterC(DDRC) DD DataDirection RegisterB(DDRB) $0007 $0006 $0005 00 otBDt eitr(T)PB T6PB T4PB T2PB PTB0 PTB1 PTA0 PTB2 PTA1 PTB3 PTA2 PTB4 PTA3 P PTB5 PTA4 DD PortDDataRegister(PTD) DataDirection RegisterA(DDRA) PTB6 PTA5 PortCDataRegister(PTC PTB7 PTA6 PortBDataRegister(PTB) PTA7 $0004 PortADataRegister(PTA) $0003 $0002 $0001 $0000 dr eitrNm i Bit 0 1 2 3 4 5 6 7 Bit Register Name Addr. NOTE: Figure 1.CANProtocolI/ V possibility ofel operation, terminationreducese Connect anyunusedI/Opinstoanappr are programmableas Fifty bidirectionalinput/ SS . AlthoughtheI/O H(DH DH‘DDRH0 DDRH1‘ 0 0 0 0 0 0 H(DDRH) DR)00000DR2DR1DDRG0 DDRG1 DDRG2 0 0 0 0 0 G (DDRG) T5PC T3PC T1PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 0 0 ) ectrostatic damage. CKN0DR5DDRC4 DDRC5 0 MCLKEN D T6PD T4PD T2PD PTD0 PTD1 PTD2 PTD3 PTD4 PTD5 PTD6 TD7 DF DF DF DD DDRF4 DDRF5 DDRF6 0 E DE DE DE DD DDRE4 DDRE5 DDRE6 RE7 B DB DB DB DD DDRB4 DDRB5 DDRB6 RB7 A DA DA DA DD DDRA4 DDRA5 DDRA6 RA7 7DR6DR5DDRD4 DDRD5 DDRD6 D7 inputs oroutputs. ports donotrequirete output (I/O)formsevenpar O PortRegisterSummary xcess currentconsumptionandthe opriate logiclevel,eitherV DD DD D DDRD2 DDRD3 DC DC D DDRC2 DDRC3 rmination forproper E DE DE DDRE0 DDRE1 DDRE2 RE3 B DB DB DDRB0 DDRB1 DDRB2 RB3 A DA DA DDRA0 DDRA1 DDRA2 RA3 F DF DF DDRF0 DDRF1 DDRF2 RF3 allel ports.AllI/Opins 08AZ60 — Rev 1.1 Rev — 08AZ60 R1DDRD0 DRD1 R1DDRC0 DRC1 DD or Input/Output Ports Port A

21.3 Port A

Port A is an 8-bit general-purpose bidirectional I/O port.

21.3.1 Port A Data Register

The port A data register contains a data latch for each of the eight port A pins.

Address: $0000

Bit 7654321Bit 0

Read: PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 Write:

Reset: Unaffected by Reset Figure 21-1. Port A Data Register (PTA)

PTA[7:0] — Port A Data Bits

These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data.

21.3.2 Data Direction Register A

Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer.

Address: $0004

Bit 7654321Bit 0

Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Write:

Reset:00000000 Figure 21-2. Data Direction Register A (DDRA)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Input/Output Ports 301

302 Input/Output Ports Freescale Semiconductor Freescale MC68HC Ports Input/Output 302 Technical Data Input/Output Ports NOTE: the operationof regardless ofthestate the voltagelevelonpin.The data latch.WhenbitDDRAxisa When bitDDRAxisal Figure 21-3 changing datadirectionregist Avoid glitchesonportApi —DataDire DDRA[7:0] INTERNAL DATA BUS DDRA[7:0], configuringall These read/writebitscontrolport 0 =CorrespondingportA 1 =CorrespondingportA READ PTA ($0000)READ PTA WRITE PTA($0000) WRITE DDRA($0004) ($0004)READ DDRA showstheportAI/Ologic. the portApins. Figure 21-3.PortAI/OCircuit RESET ogic 1,readingaddress ction Register ABits Register ction itsdatadirectionbit. ns bywritingtotheport port Apinsasinputs. er Abitsfr pin configuredasinput pin configuredasoutput data latchcanalwaysbewritten, logic 0,reading DDRAx PTAx A datadirection.Resetclears om 0to1. Table 21-1 $0000 readsthePTAx Adataregisterbefore address $0000reads 08AZ60 — Rev 1.1 Rev — 08AZ60 summarizes PTAx Input/Output Ports Port B

Table 21-1. Port A Pin Functions

Accesses Accesses to PTA DDRA PTA I/O Pin to DDRA Bit Bit Mode Read/Write Read Write

0 X Input, Hi-Z DDRA[7:0] Pin PTA[7:0](1)

1 X Output DDRA[7:0] PTA[7:0] PTA[7:0]

X = don’t care Hi-Z = high impedance 1. Writing affects data register, but does not affect input.

21.4 Port B

Port B is an 8-bit special function port that shares all of its pins with the analog-to-digital converter.

21.4.1 Port B Data Register

The port B data register contains a data latch for each of the eight port B pins.

Address: $0001

Bit 7654321Bit 0

Read: PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 Write:

Reset: Unaffected by Reset

Alternate ATD7 ATD6 ATD5 ATD4 ATD3 ATD2 ATD1 ATD0 Functions: Figure 21-4. Port B Data Register (PTB)

PTB[7:0] — Port B Data Bits These read/write bits are software programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Input/Output Ports 303

304 Input/Output Ports Freescale Semiconductor Freescale MC68HC Ports Input/Output 304 Technical Data 21.4.2 DataDir Input/Output Ports NOTE: ection RegisterB drs:$0005 Address: Figure 21-6 changing datadirectionregist Avoid glitchesonportBpi —DataDire DDRB[7:0] the correspondingportBpin;alogi or anoutput.Writingalogic1to Data directionregisterBdetermine ATD[7:0] —ADCChannels Reset:00000000 Read: Write: port Breturnstothestates DDRBbitsa ADC.However,the the does notaffectthedatadirectionof Converter (ADC-15) the datawillreflectva if thedatadirectionfo corresponding bitintheportBdata purpose I/Opins.Ifan the PTB7/ATD7–PTB0/ATD0pins channels. TheADCchannelselectbits PTB7/ATD7–PTB0/ATD0 areeightof DDRB[7:0], configuringall These read/writebitscontrolport 0 =CorrespondingportB 1 =CorrespondingportB DB DB DB DB DB DB DB DDRB0 DDRB1 DDRB2 DDRB3 DDRB4 DDRB5 DDRB6 DDRB7 Bit 7654321Bit 0 Figure 21-5.DataDirect showstheportBI/Ologic. ction Register BBits Register ction r thisbitisprogramm on page417).Datadirecti ADC channelisselected ns bywritingtotheport lue inthedatalatch.(See port Bpinsasinputs. er Bbitsfr of thelatchesorlogic0. pin configuredasinput pin configuredasoutput DDRB bitenablest s whethereachport c 0disablestheoutputbuffer. ion RegisterB(DDRB) B datadirection.Resetclears areADCchann port Bpinsthatarebeingusedby lways determinewhetherreading register occurs,thedatawillbe0 om 0to1. theanalog-to-digitalconverter , CH[4:0],determinewhether ed asaninput.Otherwise, Bdataregisterbefore on registerB(DDRB) andareadofthis he outputbufferfor Analog-to-Digital els orgeneral- B pinisaninput 08AZ60 — Rev 1.1 Rev — 08AZ60 Input/Output Ports Port B

READ DDRB ($0005)

WRITE DDRB ($0005) DDRBx RESET

WRITE PTB ($0001) PTBx PTBx INTERNAL DATA BUS INTERNAL READ PTB ($0001)

Figure 21-6. Port B I/O Circuit

When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 21-2 summarizes the operation of the port B pins.

Table 21-2. Port B Pin Functions

Accesses Accesses to PTB DDRB PTB I/O Pin to DDRB Bit Bit Mode Read/Write Read Write

0 X Input, Hi-Z DDRB[7:0] Pin PTB[7:0](1)

1 X Output DDRB[7:0] PTB[7:0] PTB[7:0]

X = don’t care Hi-Z = high impedance 1. Writing affects data register, but does not affect input.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Input/Output Ports 305

306 Input/Output Ports Freescale Semiconductor Freescale MC68HC Ports Input/Output 306 Technical Data 21.5.1 PortCDataRegister 21.5 PortC Input/Output Ports Functions: Alternate drs:$0002 Address: The portCdataregist Port Cisan6-bitgeneral-pur MCLK —T12SystemClockBit PTC[5:0] —PortCDataBits pins. ee:UnaffectedbyReset Reset: ed 0 0 Read: rt:RR R Write: in PTCDDR7. The systemclockisdriv direction registerC.Resethas each portCpinisunderthecontrol These read/writebitsaresoftware-p Bit 7654321Bit 0 R= Reserved Figure 21-7.PortCDa er containsadatalatchfo T5PC T3PC T1PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 en outofPTC2whenenabledbyMCLKENbit pose bidirectionalI/Oport. noeffectonportCdata(5:0). ta Register(PTC) of thecorrespondingbitindata rogrammable. Datadirectionof r eachoft MCLK 08AZ60 — Rev 1.1 Rev — 08AZ60 he sixportC Input/Output Ports Port C

21.5.2 Data Direction Register C

Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer.

Address: $0006

Bit 7654321Bit 0

Read: 0 MCLKEN DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 Write: R

Reset:00000000

R= Reserved Figure 21-8. Data Direction Register C (DDRC)

MCLKEN — MCLK Enable Bit This read/write bit enables MCLK to be an output signal on PTC2. If MCLK is enabled, DDRC2 has no effect. Reset clears this bit.

1 = MCLK output enabled 0 = MCLK output disabled

DDRC[5:0] — Data Direction Register C Bits These read/write bits control port C data direction. Reset clears DDRC[7:0], configuring all port C pins as inputs. 1 = Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input

NOTE: Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1.

Figure 21-9 shows the port C I/O logic.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Input/Output Ports 307

308 Input/Output Ports Freescale Semiconductor Freescale MC68HC Ports Input/Output 308 Technical Data Input/Output Ports the operationof regardless ofthestate the voltagelevelonpin.The data latch.WhenbitDDRCxisa When bitDDRCxisal 1. Writing Writing affects data register, but does not affect input. 1. = highHi-Z impedance X =don’t care INTERNAL DATA BUS Value Bit uptDR[:]PC50 PTC[5:0] PTC[5:0] DDRC[5:0] Output X 1 uptDR[]0— PTC2 0 Pin Pin DDRC[2] DDRC[5:0] Input,Hi-Z Output DDRC[2] X Input,Hi-Z 2 2 0 1 0 READ PTC($0002) WRITE PTC($0002) WRITE DDRC($0006) READ DDRC($0006) PTC Bit the portCpins. Table 21-3.Port CPinFunctions Figure 21-9.PortCI/OCircuit RESET ogic 1,readingaddress itsdatadirectionbit. I/O Pin Mode data latchcanalwaysbewritten, logic 0,reading DDRCx PTCx edWieRa Write Read Read/Write Accesses to DDRC Table 21-3 $0002 readsthePTCx address $0002reads Accesses toPTC 08AZ60 — Rev 1.1 Rev — 08AZ60 summarizes PTC[5:0] PTCx (1) Input/Output Ports Port D

21.6 Port D

Port D is an 8-bit general-purpose I/O port.

21.6.1 Port D Data Register

Port D is a 8-bit special function port that shares seven of its pins with the analog to digital converter and two with the timer interface modules.

Address: $0003

Bit 7654321Bit 0

Read: PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 Write:

Reset: Unaffected by Reset

Alternate ATD14/ ATD12/ R ATD13 ATD11 ATD10 ATD9 ATD8 Functions: TACLK TBCLK

Figure 21-10. Port D Data Register (PTD)

PTD[7:0] — Port D Data Bits PTD[7:0] are read/write, software programmable bits. Data direction of PTD[7:0] pins are under the control of the corresponding bit in data direction register D.

ATD[14:8] — ADC Channel Status Bits

PTD6/ATD14/TACLK–PTD0/ATD8 are seven of the 15 analog-to- digital converter channels. The ADC channel select bits, CH[4:0], determine whether the PTD6/ATD14/TACLK–PTD0/ATD8 pins are ADC channels or general-purpose I/O pins. If an ADC channel is selected and a read of this corresponding bit in the port B data register occurs, the data will be 0 if the data direction for this bit is programmed as an input. Otherwise, the data will reflect the value in the data latch. (See Analog-to-Digital Converter (ADC-15) on page 417).

Data direction register D (DDRD) does not affect the data direction of port D pins that are being used by the TIMA or TIMB. However, the

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Input/Output Ports 309

310 Input/Output Ports Freescale Semiconductor Freescale MC68HC Ports Input/Output 310 Technical Data 21.6.2 DataDir Input/Output Ports NOTE: ection RegisterD drs:$0007 Address: Figure 21-12 changing datadirection regist Avoid glitchesonportDpinsbywrit —DataDire DDRD[7:0] the correspondingportDpin;alogi or anoutput.Writingalogic1to Data directionregister TACLK/TBCLK —TimerClockInputBit of thelatchesorlogic0. DDRD bitsalwaysdetermine Reset:00000000 Read: Write: DDRD[7:0], configuringall These read/writebitscontrolport Status andControlRegisters PTD4/ATD12/TBLCK The prescalerselectbits,PS[2:0 The PTD4/ATD12/TBLCKpinistheexte The PTD6/ATD14/TACLKpinistheexte corresponding DDRDbitshavenoeffect. available forgeneral-purposeI/O. Status andControlRegisters the TIMclock,PTD6/ATD14/TACLK 0 =CorrespondingportD 1 =CorrespondingportD DD DD DD DD DD DD DD DDRD0 DDRD1 DDRD2 DDRD3 DDRD4 DDRD5 DDRD6 DDRD7 Bit 7654321Bit 0 Figure 21-11.DataDir showstheportDI/O logic. Ddetermineswhethereac ction Register DBits Register ction

as theTIMclockinput.(See whetherreadingport port Dpinsasinputs. er Dbitsfr pin configuredasinput pin configuredasoutput ection RegisterD(DDRD) DDRD bitenablestheoutputbufferfor on page281).When on page406and ing totheportDdat c 0disablestheoutputbuffer. ], selectPTD6/ATD14/TACLKor D datadirection.Resetclears While TACLK/TBCLKareselected and om 0to1. rnal clockinputfortheTIMB. rnal clockinputfortheTIMA. PTD4/ATD12/TBLCK h portDpinisaninput D returns the states thestates D returns TIMB Channel TIMA Channel a registerbefore 08AZ60 — Rev 1.1 Rev — 08AZ60 not selectedas

are Input/Output Ports Port D

READ DDRD ($0007)

WRITE DDRD ($0007) DDRDx RESET

WRITE PTD ($0003) PTDx PTDx INTERNAL DATA BUS INTERNAL READ PTD ($0003)

Figure 21-12. Port D I/O Circuit

When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 21-4 summarizes the operation of the port D pins.

Table 21-4. Port D Pin Functions

Accesses to Accesses to PTD DDRD PTD I/O Pin DDRD Bit Bit Mode Read/Write Read Write 0 X Input, Hi-Z DDRD[7:0] Pin PTD[7:0](1) 1 X Output DDRD[7:0] PTD[7:0] PTD[7:0] X = don’t care Hi-Z = high impedance 1. Writing affects data register, but does not affect input.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Input/Output Ports 311

312 Input/Output Ports Freescale Semiconductor Freescale MC68HC Ports Input/Output 312 Technical Data 21.7.1 PortEDataRegister 21.7 PortE Input/Output Ports Function: Alternate drs:$0008 Address: serial peripheralinterfacemodule(SPI). MOSI — Master Out/Slave InBit Out/Slave MOSI —Master SPSCK —SPISeri PTE[7:0] —PortEDataBits E pins. The portEdataregist communications interfacem tw (TIMA), interfacemodule timer Port Eisan8-bitspecialfunctionportt ee:UnaffectedbyReset Reset: Read: Write: general-purpose I/O. module. Whenthe The PTE6/MOSIpinisthemasterout SPI ControlRegi clear, thePTE7/SPSCKpinisavaila and serialclockoutput The PTE7/SPSCK direction registerE. of eachportEpinis PTE[7:0] areread/write,software PC OIMS SS MISO MOSI SPSCK T7PE T5PTE4 PTE5 PTE6 PTE7 Bit 7654321Bit 0 Figure 21-13.PortE al ClockBit ster (SPCR)

SPE bitisclear,thePTE6/M pin istheserialclocki er containsadatalatchfo under thecontrolofco of anSPImastermodule. odule (SCI), an (SCI), odule o ofitspinswi on page256). Data Register(PTE) programmable bits.Datadirection hat sharestwoofitspinswiththe ble forgeneral-purposeI/O.(See AH AH x TxD RxD TACH0 TACH1 /slave interminaloftheSPI T3PE T1PTE0 PTE1 PTE2 PTE3 nput ofanSPIslavemodule d fourofits th theserial r eachoftheeightport rresponding bitindata OSI pinisavailablefor WhentheSPEbitis pins withthe 08AZ60 — Rev 1.1 Rev — 08AZ60 Input/Output Ports Port E

MISO — Master In/Slave Out Bit The PTE5/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit, SPE, is clear, the SPI module is disabled, and the PTE5/MISO pin is available for general-purpose I/O. (See SPI Control Register (SPCR) on page 256).

SS — Slave Select Bit The PTE4/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the SPI master bit, SPMSTR, is set and MODFEN bit is low, the PTE4/SS pin is available for general-purpose I/O. (See SS (Slave Select) on page 254). When the SPI is enabled as a slave, the DDRF0 bit in data direction register E (DDRE) has no effect on the PTE4/SS pin.

NOTE: Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the SPI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. (See Table 21-5).

TACH[1:0] — Timer Channel I/O Bits The PTE3/TACH1–PTE2/TACH0 pins are the TIM input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTE3/TACH1–PTE2/TACH0 pins are timer channel I/O pins or general-purpose I/O pins. (See TIMA Channel Status and Control Registers on page 406).

NOTE: Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the TIM. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. (See Table 21-5).

RxD — SCI Receive Data Input Bit The PTE1/RxD pin is the receive data input for the SCI module. When the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. (See SCI Control Register 1 on page 213).

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Input/Output Ports 313

314 Input/Output Ports Freescale Semiconductor Freescale MC68HC Ports Input/Output 314 Technical Data 21.7.2 DataDir Input/Output Ports NOTE: NOTE: ection RegisterE drs:$000C Address: Figure 21-15 changing datadirectionregist Avoid glitchesonportEpi —DataDire DDRE[7:0] the correspondingportEpin;alogi or anoutput.Writingalogic1to Data directionregisterEdetermine latches orthestates bits alwaysdeterminew port Epinsthatarebei Data directionregisterE(DDRE)does TxD —SCITransmitDataOutput Reset:00000000 Read: Write: Control Register1 and thePTE0/TxDpinisavailabl When theenableSCIbit, The PTE0/TxDpinisthetransmit DDRE[7:0], configuringall These read/writebitscontrolport 0 =CorrespondingportE 1 =CorrespondingportE DE DE DE DE DE DE DE DDRE0 DDRE1 DDRE2 DDRE3 DDRE4 DDRE5 DDRE6 DDRE7 Bit 7654321Bit 0 Figure 21-14.DataDir showstheportEI/Ologic. ofthepins.(See ng usedbytheSCImodu on page213). ction Register EBits Register ction hether readingportEretu ns bywritingtotheport ENSCI, isclear,theSC port Epinsasinputs. er Ebitsfr pin configuredasinput pin configuredasoutput ection RegisterE(DDRE) DDRE bitenablest s whethereachport c 0disablestheoutputbuffer. e forgeneral-pur E datadirection.Resetclears data outputfor Table 21-5 notaffectthedatadirectionof om 0to1. le. However,theDDRE Edataregisterbefore ). rns thestatesof I moduleisdisabled, the SCImodule. pose I/O.(See he outputbufferfor E pinisaninput 08AZ60 — Rev 1.1 Rev — 08AZ60 SCI Input/Output Ports Port E

READ DDRE ($000C)

WRITE DDRE ($000C) DDREx RESET

WRITE PTE ($0008) PTEx PTEx INTERNAL DATA BUS INTERNAL READ PTE ($0008)

Figure 21-15. Port E I/O Circuit

When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 21-5 summarizes the operation of the port E pins.

Table 21-5. Port E Pin Functions

Accesses Accesses to PTE DDRE PTE I/O Pin to DDRE Bit Bit Mode Read/Write Read Write

0 X Input, Hi-Z DDRE[7:0] Pin PTE[7:0](1)

1 X Output DDRE[7:0] PTE[7:0] PTE[7:0]

X = don’t care Hi-Z = high impedance 1. Writing affects data register, but does not affect input.

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Freescale Semiconductor Input/Output Ports 315

316 Input/Output Ports Freescale Semiconductor Freescale MC68HC Ports Input/Output 316 Technical Data 21.8.1 PortFDataRegister 21.8 PortF Input/Output Ports Function: Alternate drs:$0009 Address: TACH[5:2] —TimerAChannelI/OBits PTF[6:0] —PortFDataBits F pins. The portFdataregistercontainsa interface module(TIMB). timer interfacemodule(TIMA-6)and Port Fisa7-bitspecial ee:UnaffectedbyReset Reset: ed 0 Read: rt:R Write: whether thePTF3–PTF0/T compare pins.Theedge/leve The PTF3–PTF0/TACH2pinsare direction registerF.Rese each portFpinisunderthecontrol These read/writebitsaresoftware on page401). general-purpose I/Opins.(See Bit 7654321Bit 0 R= Reserved Figure 21-16.PortF T6PF T4PT PTF4 PTF5 PTF6 function portthatsharesf BH BH AH AH AH TACH2 TACH3 TACH4 TACH5 TBCH0 TBCH1 t hasnoeffectonPTF[6:0]. ACH2 pinsaretimer l selectbits,ELSx TIMA StatusandControlRegister data latchforeachofthesevenport Data Register(PTF) the TIMinputcapture/output two ofitspins programmable. Datadirectionof of thecorrespondi 3PF T1PTF0 PTF1 PTF2 F3 our ofitspinswiththe B:ELSxA, determine channel I/Opinsor with thetimer 08AZ60 — Rev 1.1 Rev — 08AZ60 ng bitindata Input/Output Ports Port F

TBCH[1:0] — Timer B Channel I/O Bits The PTF5/TBCH1–PTF4/TBCH0 pins are the TIMB input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTF5/TBCH1–PTF4/TBCH0 pins are timer channel I/O pins or general-purpose I/O pins. (See PIT Status and Control Register on page 293).

NOTE: Data direction register F (DDRF) does not affect the data direction of port F pins that are being used by the TIM. However, the DDRF bits always determine whether reading port F returns the states of the latches or the states of the pins. (See Table 21-6).

21.8.2 Data Direction Register F

Data direction register F determines whether each port F pin is an input or an output. Writing a logic 1 to a DDRF bit enables the output buffer for the corresponding port F pin; a logic 0 disables the output buffer.

Address: $000D

Bit 7654321Bit 0

Read: 0 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 Write: R

Reset:00000000

R= Reserved Figure 21-17. Data Direction Register F (DDRF)

DDRF[6:0] — Data Direction Register F Bits These read/write bits control port F data direction. Reset clears DDRF[6:0], configuring all port F pins as inputs. 1 = Corresponding port F pin configured as output 0 = Corresponding port F pin configured as input

NOTE: Avoid glitches on port F pins by writing to the port F data register before changing data direction register F bits from 0 to 1.

Figure 21-18 shows the port F I/O logic.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Input/Output Ports 317

318 Input/Output Ports Freescale Semiconductor Freescale MC68HC Ports Input/Output 318 Technical Data Input/Output Ports the operationof regardless ofthestate the voltagelevelonpin.The data latch.WhenbitDD When bitDDRFxisal 1. Writing Writing affects data register, but does not affect input. 1. = highHi-Z impedance X =don’t care INTERNAL DATA BUS DDRF Bit nu,H- DF60 Pin DDRF[6:0] Input, Hi-Z X 0 uptDR[:]PF60 PTF[6:0] PTF[6:0] DDRF[6:0] Output X 1 READ PTF($0009) ($0009) PTFWRITE ($000D) DDRFWRITE READ DDRF($000D) PTF Bit the portFpins. Table 21-6.Port FPinFunctions Figure 21-18.PortFI/OCircuit RESET ogic 1,readingaddress RFx isalogic0,r itsdatadirectionbit. I/O Pin Mode data latchcanalwaysbewritten, DDRFx PTFx edWieRa Write Read Read/Write Accesses to DDRF eading address$0009reads Table 21-6 $0009 readsthePTFx Accesses toPTF 08AZ60 — Rev 1.1 Rev — 08AZ60 summarizes PTF[6:0] PTFx (1) Input/Output Ports Port G

21.9 Port G

Port G is a 3-bit special function port that shares all of its pins with the keyboard interrupt module (KBD).

21.9.1 Port G Data Register

The port G data register contains a data latch for each of the three port G pins.

Address: $000A

Bit 7654321Bit 0

Read: 00000 PTG2 PTG1 PTG0 Write:RRRRR

Reset: Unaffected by Reset

Alternate KBD2 KBD1 KBD0 Function:

R= Reserved Figure 21-19. Port G Data Register (PTG)

PTG[2:0] — Port G Data Bits These read/write bits are software programmable. Data direction of each port G pin is under the control of the corresponding bit in data direction register G. Reset has no effect on PTG[2:0].

KBD[2:0] — Keyboard Wakeup pins The keyboard interrupt enable bits, KBIE[2:0], in the keyboard interrupt control register, enable the port G pins as external interrupt pins (See Keyboard Module (KBD) on page 375). Enabling an external interrupt pin will override the corresponding DDRGx.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Input/Output Ports 319

320 Input/Output Ports Freescale Semiconductor Freescale MC68HC Ports Input/Output 320 Technical Data 21.9.2 DataDir Input/Output Ports NOTE: ection RegisterG drs:$000E Address: Avoid glitchesonportGpi RegisterGBits Direction DDRG[2:0] —Data for thecorrespondingport or anoutput.Writingalo Data directionregi changing datadirectionregist Figure 21-21 Reset:00000000 Read: INTERNAL DATA BUS Write:RRRRR DDRG[2:0], configuringal These read/writebitscontrolportG 0 =CorrespondingportG 1 =CorrespondingportGpi READ PTG ($000A) READ PTG PTG($000A)WRITE DDRG($000E) WRITE ($000E) READ DDRG Bit 7654321Bit 0 Figure 21-20.DataDir R= Reserved 00000 showstheportGI/Ologic. ster Gdetermineswhether Figure 21-21.PortG I/O Circuit RESET gic 1toaDDRGbitenab ns by writing to the por the to bywriting ns Gpin;alogic0dis l portGpinsasinputs. er Gbitsfrom0to1. pin configuredasinput ection RegisterG(DDRG) n configuredasoutput DDRGx PTGx data direction.Resetclears each portGpinisaninput ables theoutputbuffer. t Gdataregisterbefore DG DG DDRG0 DDRG1 DDRG2 les theoutputbuffer 08AZ60 — Rev 1.1 Rev — 08AZ60 PTGx Input/Output Ports Port H

When bit DDRGx is a logic 1, reading address $000A reads the PTGx data latch. When bit DDRGx is a logic 0, reading address $000A reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 21-7 summarizes the operation of the port G pins.

Table 21-7. Port G Pin Functions

Accesses Accesses to PTG DDRG PTG I/O Pin to DDRG Bit Bit Mode Read/Write Read Write

0 X Input, Hi-Z DDRG[2:0] Pin PTG[2:0](1)

1 X Output DDRG[2:0] PTG[2:0] PTG[2:0]

X = don’t care Hi-Z = high impedance 1. Writing affects data register, but does not affect input.

21.10 Port H

Port H is a 2-bit special function port that shares all of its pins with the keyboard interrupt module (KBD).

21.10.1 Port H Data Register

The port H data register contains a data latch for each of the two port H pins.

Address: $000B

Bit 7654321Bit 0

Read: 000000 PTH1 PTH0 Write:RRRRRR

Reset: Unaffected by Reset

Alternate KBD4 KBD3 Function: Figure 21-22. Port H Data Register (PTH)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Input/Output Ports 321

322 Input/Output Ports Freescale Semiconductor Freescale MC68HC Ports Input/Output 322 Technical Data 21.10.2 DataDirectionRegisterH Input/Output Ports NOTE: drs:$000F Address: changing datadirection regist Avoid glitchesonportHpinsbywrit —DataDire DDRH[1:0] the correspondingportHpin;alogi or anoutput.Writingalogic1to Data directionregister KBD[4:3] —KeyboardWake-uppins PTH[1:0] —PortHDataBits Reset:00000000 Read: Write:RRRRRR DDRG[1:0], configuringal These read/writebitscontrolport pins (See interrupt controlregist The keyboardinterruptenablebits direction registerH.Reset each portHpinisunderthecontrol These read/writebitsaresoftware 0 =CorrespondingportH 1 =CorrespondingportH Bit 7654321Bit 0 Figure 21-23.DataDir R= Reserved R= Reserved 000000 Keyboard Module(KBD) Figure 21-22.PortH Hdetermineswhethereac ction Register HBits Register ction er, enabletheportHpins l portHpinsasinputs. has noeffectonPTH[1:0]. er Hbitsfr pin configuredasinput pin configuredasoutput ection RegisterH(DDRH) DDRH bitenablestheoutputbufferfor Data Register(PTH) ing totheportHdat c 0disablestheoutputbuffer. H datadirection.Resetclears , KBIE[4:3],in programmable. Datadirectionof of thecorrespondingbitindata on page375). om 0to1. h portHpinisaninput as externalinterrupt thekeyboard a registerbefore 08AZ60 — Rev 1.1 Rev — 08AZ60 DH DDRH0 DDRH1 Input/Output Ports Port H

Figure 21-24 shows the port H I/O logic.

READ DDRH ($000F)

WRITE DDRH ($000F) DDRHx RESET

WRITE PTH ($000B) PTHx PTHx INTERNAL DATA BUS INTERNAL

READ PTH ($000B)

Figure 21-24. Port H I/O Circuit

When bit DDRHx is a logic 1, reading address $000B reads the PTHx data latch. When bit DDRHx is a logic 0, reading address $000B reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 21-8 summarizes

the operation of the port H pins.

Table 21-8. Port H Pin Functions

Accesses Accesses to PTH DDRH PTH I/O Pin to DDRH Bit Bit Mode Read/Write Read Write

0 X Input, Hi-Z DDRH[1:0] Pin PTH[1:0](1)

1 X Output DDRH[1:0] PTH[1:0] PTH[1:0]

X = don’t care Hi-Z = high impedance 1. Writing affects data register, but does not affect input.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Input/Output Ports 323

324 Input/Output Ports Freescale Semiconductor Freescale MC68HC Ports Input/Output 324 Technical Data Input/Output Ports 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 22. MSCAN Controller (MSCAN08)

22.1 Contents

22.2 Introduction...... 326 22.3 Features...... 327 22.4 External Pins...... 328 22.5 Message Storage ...... 329 22.5.1 Background ...... 329 22.5.2 Receive Structures...... 330 22.5.3 Transmit Structures ...... 333 22.6 Identifier Acceptance Filter ...... 334

22.7 Interrupts...... 339 22.7.1 Interrupt Acknowledge ...... 340 22.7.2 Interrupt Vectors ...... 341 22.8 Protocol Violation Protection ...... 341 22.9 Low Power Modes ...... 342 22.9.1 MSCAN08 Sleep Mode ...... 343 22.9.2 MSCAN08 Soft Reset Mode ...... 344 22.9.3 MSCAN08 Power Down Mode ...... 345 22.9.4 CPU Wait Mode...... 345 22.9.5 Programmable Wakeup Function ...... 346 22.10 Timer Link ...... 346 22.11 Clock System ...... 346 22.12 Memory Map ...... 350 22.13 Programmer’s Model of Message Storage ...... 350 22.13.1 Message Buffer Outline ...... 351 22.13.2 Identifier Registers...... 351

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Freescale Semiconductor MSCAN Controller (MSCAN08) 325

ehia aaMC68HC Controller(MSCAN08 MSCAN 326 Technical Data 22.2 Introduction MSCAN Controller (MSCAN08) predictable real-timebehavior,andsi MSCAN08 utilizesanadvanc required bandwidth. interference (EMI)environmentofa this field:real-timepr used asavehicleserialdatabus,me The CANprotocolwasprim 1991. A/B protocolasdefined The moduleisacommunica Microcontroller Family. area network(MSCAN)concepttarg The MSCAN08isthespecific MSCAN08 Module 22.14.1 Programmer’sModel 22.14 Transmit Buffer 22.13.5 Data Segment 22.13.4 Data LengthR 22.13.3 21. MSCAN08 BusTimingRegister0 22.14.3 MSCAN08 Module 22.14.2 21. MSCAN08 Iden 22.14.9 MSCAN08 Transmit 22.14.8 MSCAN08 Transm 22.14.7 MSCAN08 ReceiverInterruptEnableRegister 22.14.6 MSCAN08 ReceiverFl 22.14.5 MSCAN08 BusTimingRegister1 22.14.4 21.0MSCAN08Recei 22.14.10 21.2MSCAN08Identifi 22.14.12 MSCAN08Transm 22.14.11 21.3MSCAN08Iden 22.14.13 ocessing, reliableoperati intheBOSCHspecific egister (DLR) Registers (DSRn) tifier AcceptanceCo tifier MaskRegisters(CIDMR0-3) Priority ve ErrorCounter arily, butnotexclus tion controllerimpl er AcceptanceRegisters itter FlagRegister it ErrorCounter ed bufferarrangemen implementationoft Control Register1 Control Register0 of ControlRegisters ter ControlRegister ag Register(CRFLG) Registers vehicle, cost-effectivenessand Freescale Semiconductor ) eted fortheFreescaleM68HC08 mplifies theapplicationsoftware. eting thespecificrequirementsof . . . . . on intheelectromagnetic . ation datedSeptember . ementing theCAN2.0 ively, designedtobe ntrol Register . he scalablecontroller . . t, resulting in a ina t, resulting . . . 08AZ60 — Rev 1.1 Rev — 08AZ60 ...... 356 356 355 355 361 359 362 370 367 365 369 363 371 373 373 375 374 MSCAN Controller (MSCAN08) Features

22.3 Features

Basic features of the MSCAN08 are:

• Modular Architecture • Implementation of the CAN Protocol — Version 2.0A/B – Standard and Extended Data Frames. – 0–8 Bytes Data Length. – Programmable Bit Rate up to 1 Mbps Depending on the Actual Bit Timing and the Clock Jitter of the PLL • Support for Remote Frames • Double-Buffered Receive Storage Scheme • Triple-Buffered Transmit Storage Scheme with Internal Prioritisation Using a “Local Priority” Concept • Flexible Maskable Identifier Filter Supports Alternatively One Full Size Extended Identifier Filter or Two 16-Bit Filters or Four 8-Bit

Filters • Programmable Wakeup Functionality with Integrated Low-Pass Filter • Programmable Loop-Back Mode Supports Self-Test Operation • Separate Signalling and Interrupt Capabilities for All CAN Receiver and Transmitter Error States (Warning, Error Passive, Bus Off) • Programmable MSCAN08 Clock Source Either CPU Bus Clock or Crystal Oscillator Output • Programmable Link to On-Chip Timer Interface Module (TIMB) for Time-Stamping and Network Synchronization • Low-Power Sleep Mode

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 327

ehia aaMC68HC Controller(MSCAN08 MSCAN 328 Technical Data 22.4 ExternalPins MSCAN Controller (MSCAN08) output (TxCAN).TheTxCANpi The MSCAN08usestwoexternalpi A typicalCANsystemwith CAN: 0isforadominantstate, defective stations. needed fortheCANandhas a transceiverchip.Theis Each CANstationisconnectedphysi CAN_H XA RXCAN TXCAN CAN NODE 1 NODE CAN TRANSCEIVER CAN CONTROLLER MCU Figure 22-1. TheCANSystem Figure 22-1. (MSCAN08) MSCAN08isshownin CAN_L current protectionagain and 1isforarecessivestate. C A N BUS CAN STATION 1 ns, oneinput(RxCAN)and Freescale Semiconductor ) capable ofdriving cally totheCANbuslinesthrough n representsthel CAN NODE 2 CAN NODE N NODE CAN 2 NODE CAN Figure 22-1 st defectiveCANor the largecurrent ogic levelonthe 08AZ60 — Rev 1.1 Rev — 08AZ60 . MSCAN Controller (MSCAN08) Message Storage

22.5 Message Storage

MSCAN08 facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications.

22.5.1 Background

Modern application layer software is built under two fundamental assumptions:

1. Any CAN node is able to send out a stream of scheduled messages without releasing the bus between two messages. Such nodes will arbitrate for the bus right after sending the previous message and will only release the bus in case of lost arbitration. 2. The internal message queue within any CAN node is organized as such that the highest priority message will be sent out first if more than one message is ready to be sent.

Above behaviour cannot be achieved with a single transmit buffer. That buffer must be reloaded right after the previous message has been sent. This loading process lasts a definite amount of time and has to be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt.

A double buffer scheme would de-couple the re-loading of the transmit buffers from the actual message being sent and as such reduces the reactiveness requirements on the CPU. Problems may arise if the sending of a message would be finished just while the CPU re-loads the second buffer. In that case, no buffer would then be ready for transmission and the bus would be released.

At least three transmit buffers are required to meet the first of the above requirements under all circumstances. The MSCAN08 has three transmit buffers.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 329

ehia aaMC68HC Controller(MSCAN08 MSCAN 330 Technical Data 22.5.2 ReceiveStructures MSCAN Controller (MSCAN08) 2. The receive interrupt will occur only if no if only occur will interrupt receive 2. The isnot flag set. 1. ifthe RXF Only filter function. The overwritingoftheba immediately aftertheIFS to releasetheforegroundbuffer. from RxFGandtoresettheRXFfl CPU arrangement intoasi (FIFO). Thetwomessagebuffers The receivedmessagesare described in which theMSCAN08implementswith The secondrequirementcallsforsome address areaisapplicablefo CPU08. Thisschemesimplifiest MSCAN08, theforegroundre background receivebuffer RxFG MSCAN08c intoRxBG.The written details see On reception,eachmessageischeckedto is set. contains acorrectlyreceivedmessage 365), signalsthestatusofforegr (CRFLG) (see The receiverfullflag Programmer’s ModelofMessageStorage identifier (standardor Both buffershaveasizeof13byte also. (2) (1) . Theuser’sreceivehandlerha , setstheRXFflag,andgenerates Identifier AcceptanceFilter Receive Structures MSCAN08 ReceiverFlag (RXF) intheMSCAN08re ngle memoryarea(see extended),andthedatac ckground bufferisinde field oftheCANframe,isreceivedintoRxBG. (RxBG) isexclusivel stored ina2-stageinpu r thereceiveprocess. ceive buffer(RxFG)isaddressablebythe t masked. A polling scheme can be applied onRXF schemecanbe applied t masked.A polling he handlersoftware,becauseonlyone A newmessagewhichcanfollow are mappedusingaPingPong on page330. ag toacknowledget s tostoretheCANcontrolbits, ound receive opies thecontentofRxBGinto Freescale Semiconductor ) s toreadthereceivedmessage the “localpriority”concept with matchingident sort ofinternal on page334)andinparallelis Register (CRFLG) areceiveinterrupttothe seeifitpassesthefilter(for Figure 22-2 on page350). y associatedtothe ceiver flagregister pendent oftheidentifier ontent (fordetails,see buffer. Whenthebuffer t firstinout prioritisation he interruptand 08AZ60 — Rev 1.1 Rev — 08AZ60 ). While the the ). While ifier, thisflag on page MSCAN Controller (MSCAN08) Message Storage

When the MSCAN08 module is transmitting, the MSCAN08 receives its own messages into the background receive buffer, RxBG. It does NOT overwrite RxFG, generate a receive interrupt or acknowledge its own messages on the CAN bus. The exception to this rule is in loop-back mode (see MSCAN08 Module Control Register 1 on page 361), where the MSCAN08 treats its own messages exactly like all other incoming messages. The MSCAN08 receives its own transmitted messages in the event that it loses arbitration. If arbitration is lost, the MSCAN08 must be prepared to become receiver.

An overrun condition occurs when both the foreground and the background receive message buffers are filled with correctly received messages with accepted identifiers and another message is correctly received from the bus with an accepted identifier. The latter message will be discarded and an error interrupt with overrun indication will be generated if enabled. The MSCAN08 is still able to transmit messages with both receive message buffers filled, but all incoming messages are discarded.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 331

ehia aaMC68HC Controller(MSCAN08 MSCAN 332 Technical Data MSCAN Controller (MSCAN08) MSCAN08 Figure 22-2.UserModelfo RxBG Tx0 RxFG Tx2 Tx1 r MessageBufferOrganization Freescale Semiconductor ) PRIO PRIO PRIO RXF TXE TXE TXE 08AZ60 — Rev 1.1 Rev — 08AZ60 CPU08 Ibus MSCAN Controller (MSCAN08) Message Storage

22.5.3 Transmit Structures

The MSCAN08 has a triple transmit buffer scheme to allow multiple messages to be set up in advance and to achieve an optimized real-time performance. The three buffers are arranged as shown in Figure 22-2.

All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see Programmer’s Model of Message Storage on page 350). An additional transmit buffer priority register (TBPR) contains an 8-bit “local priority” field (PRIO) (see Transmit Buffer Priority Registers on page 356).

To transmit a message, the CPU08 has to identify an available transmit buffer which is indicated by a set transmit buffer empty (TXE) flag in the MSCAN08 transmitter flag register (CTFLG) (see MSCAN08 Transmitter Flag Register on page 369).

The CPU08 then stores the identifier, the control bits and the data content into one of the transmit buffers. Finally, the buffer has to be flagged ready for transmission by clearing the TXE flag.

The MSCAN08 then will schedule the message for transmission and will signal the successful transmission of the buffer by setting the TXE flag. A transmit interrupt is generated(1) when TXE is set and can be used to drive the application software to re-load the buffer.

In case more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration, the MSCAN08 uses the local priority setting of the three buffers for prioritisation. For this purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software sets this field when the message is set up. The local priority reflects the priority of this particular message relative to the set of messages being emitted from this node. The lowest binary value of the PRIO field is defined as the highest priority.

1. The transmit interrupt will occur only if not masked. A polling scheme can be applied on TXE also.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 333

ehia aaMC68HC Controller(MSCAN08 MSCAN 334 Technical Data Filter Acceptance 22.6 Identifier MSCAN Controller (MSCAN08) programmable tooperatein been introducedtor A veryflexibleprogrammablegeneric priority. ormo occurs(two hit one than more software’s tasktoidentify section thatcausedtheacceptanc page 371).TheseIdentifierHit Register (see (CRFLG) (Receive Buffer A filterhitisindicatedtothe Registers (CIDMR0-3). Any ofthesebitscanbemarked‘d patterns ofthestandardorextendedid The IdentifierAcceptanceRegisters(C The internalschedulingprocessta transmission cannotbeabor in oneofthethreetransmitbuffers. it maybecomenecessarytoaborta When ahighprioritymessageisschedul transmission error. arbitrates forthebus.Thisisalso message wasactuallyaborted(ABTAK fromthesett cantell software and bygeneratingatransmitinterrup acknowledge (ABTAK)andtheTXEflag request, ifpossible, transmission controlregister(CTCR) setting thecorrespon on page365)andtwobitsinthe MSCAN08 IdentifierA FullFlag,see educe theCPUinterruptl by settingthecorres ding abortrequestflag(ABTRQ)inthe the causeofreceiver fourdifferentmodes: application onsoftwarebyasetRXF ted, theuserhasto ing oftheABTAK Flags(IDHIT1-0)clear MSCAN08 ReceiverFlagRegister thecaseafteroccurrenceofa e. Theysimplify kes placewhenever on’t care’inthe As messagesthatarealreadyunder lower priorityme re filters match) match) re filters Freescale Semiconductor ) . TheMSCAN08willthengrantthe t. Thetransmitin identifieracceptancefilterhas cceptance ControlRegister IDAR0-3) define entifier (ID10-ID0orID28-ID0). =1)orsent(ABTAK0). ed bytheapplicationsoftware, ponding abortrequest in ordertoreleasethebuffer Identifier AcceptanceControl oading. Thefilteris flag whetherthe request theabortby interrupt. Incasethat the application Identifier Mask Identifier ssage beingsetup the lowerhithas ly identifythefilter terrupt handler theMSCAN08 08AZ60 — Rev 1.1 Rev — 08AZ60 the acceptance on MSCAN Controller (MSCAN08) Identifier Acceptance Filter

• Single identifier acceptance filter, each to be applied to a) the full 29 bits of the extended identifier and to the following bits of the CAN frame: RTR, IDE, SRR or b) the 11 bits of the standard identifier plus the RTR and IDE bits of CAN 2.0A/B messages. This mode implements a single filter for a full length CAN 2.0B compliant extended identifier. Figure 22-3 shows how the 32-bit filter bank (CIDAR0-3, CIDMR0-3) produces a filter 0 hit. • Two identifier acceptance filters, each to be applied to a) the 14 most significant bits of the extended identifier plus the SRR and the IDE bits of CAN2.0B messages, or b) the 11 bits of the identifier plus the RTR and IDE bits of CAN 2.0A/B messages. Figure 22-4 shows how the 32-bit filter bank (CIDAR0-3, CIDMR0-3) produces filter 0 and 1 hits. • Four identifier acceptance filters, each to be applied to the first eight bits of the identifier. This mode implements four independent filters for the first eight bits of a CAN 2.0A/B compliant standard identifier. Figure 22-5 shows how the 32-bit filter bank (CIDAR0- 3, CIDMR0-3) produces filter 0 to 3 hits.

• Closed filter. No CAN message will be copied into the foreground buffer RxFG, and the RXF flag will never be set.

ID28IDR0 ID21 ID20IDR1 ID15 ID14IDR2 ID7 ID6IDR3 RTR ID10IDR0 ID3 ID2IDR1 IDE ID10IDR2 ID3 ID10IDR3 ID3

AM7CIDMR0 AM0 AM7CIDMR1 AM0 AM7CIDMR2 AM0 AM7CIDMR3 AM0

AC7CIDAR0 AC0 AC7CIDAR1 AC0 AC7CIDAR2 AC0 AC7CIDAR3 AC0

ID Accepted (Filter 0 Hit)

Figure 22-3. Single 32-Bit Maskable Identifier Acceptance Filter

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 335

ehia aaMC68HC Controller(MSCAN08 MSCAN 336 Technical Data MSCAN Controller (MSCAN08) C AC0 AM0 AC7 AM7 AC0 AM0 AC7 AM7 D0ID3 ID21 ID10 ID28 Figure 22-4.Dual16-Bit CIDMR2 CIDMR0 CIDAR2 CIDAR0 IDR0 IDR0 ID ACCEPTEDHIT) 1 (FILTER ID ACCEPTEDHIT) 0 (FILTER C AC0 AM0 AC7 AM7 AC0 AM0 AC7 AM7 D IDE ID15 ID2 ID20 CIDMR3 CIDMR1 CIDAR3 CIDAR1 IDR1 IDR1 Maskable AcceptanceFilters Freescale Semiconductor ) D0ID3 ID7 ID10 ID14 IDR2 IDR2 D0ID3 RTR ID10 ID6 08AZ60 — Rev 1.1 Rev — 08AZ60 IDR3 IDR3 MSCAN Controller (MSCAN08) Identifier Acceptance Filter

.

ID28IDR0 ID21 ID20IDR1 ID15 ID14IDR2 ID7 ID6IDR3 RTR ID10IDR0 ID3 ID2IDR1 IDE ID10IDR2 ID3 ID10IDR3 ID3

AM7CIDMR0 AM0

AC7CIDAR0 AC0

ID ACCEPTED (FILTER 0 HIT)

AM7CIDMR1 AM0

AC7CIDAR1 AC0

ID ACCEPTED (FILTER 1 HIT)

AM7CIDMR2 AM0

AC7CIDAR2 AC0

ID ACCEPTED (FILTER 2 HIT)

AM7CIDMR3 AM0

AC7CIDAR3 AC0

ID ACCEPTED (FILTER 3 HIT)

Figure 22-5. Quadruple 8-Bit Maskable Acceptance Filters

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 337

ehia aaMC68HC Controller(MSCAN08 MSCAN 338 Technical Data 22.6.1 MSCANExtended MSCAN Controller (MSCAN08) 22.6.1.1 Work-around 2nd byteofthefilter When anaffectedIDisreceived, g) f) e) d) c) b) 11111000001 For 32-bitand16-biti mode). certain bitswithIDMR If theproblematicID is shiftedin(i.e. bit mode).Thisincorrectvalueisth a) ID15: Extended IDs(ID28-ID0)whichgener rejected, dependingonI frame withastuffbitbetween DR DR DR IDAR3 IDAR2 xxxxxxxx xxxxxxxx IDAR1 ***1111x ******** IDAR0 Affected extendedIDs(I =0or x where ID RejectedifStuff 10000011111 11111111111 10000000000 x0111110000 xxxx0111111 xxxxx100000 xxxxxxxxx01 * =patternforID28to right shiftedby1). 1 (don'tcare) s cannotbeavoided,th (IDAR1 andIDAR5,plus dentifier acceptancem 1 (andIDMR5,plusID exception: exception: exceptions: Bit BetweenID DAR0, IDAR1,andIDMR1. D28 -ID18)patterns: ID16 andID15canbeerroneously ID18(seefollowing). e shiftregistercontentsbeforeID15 00000111111 01111100000 xxxx1000001 01111100001 00000000001 Freescale Semiconductor ) incorrect valueis ate astuffbitbetweenID16and 16 andID15 e workaroundistomask odes, anextendedIDCAN MR3 andIDMR7in16-bit IDAR3 andIDAR7in16- except comparedtothe 08AZ60 — Rev 1.1 Rev — 08AZ60 MSCAN Controller (MSCAN08) Interrupts

Example 1: to receive the message IDs xxxx xxxx x011 111x xxxx xxxx xxxx xxxx IDMR1 etc. must be 111x xxx1, i.e. ID20,19,18,15 must be masked. Example 2: to receive the message IDs xxxx 0111 1111 111x xxxx xxxx xxxx xxxx IDMR1 etc. must be 1xxx xxx1, i.e. ID20 and ID15 must be masked. In general, using IDMR1 etc. 1111 xxx1, i.e. masking ID20,19,18,SRR,15, hides the problem.

22.7 Interrupts

The MSCAN08 supports four interrupt vectors mapped onto eleven different interrupt sources, any of which can be individually masked (for details see MSCAN08 Receiver Flag Register (CRFLG) on page 365, to MSCAN08 Transmitter Control Register on page 370).

• Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message

for transmission. The TXE flags of the empty message buffers are set. • Receive Interrupt: A message has been received successfully and loaded into the foreground receive buffer. This interrupt will be emitted immediately after receiving the EOF symbol. The RXF flag is set. • Wakeup Interrupt: An activity on the CAN bus occurred during MSCAN08 internal sleep mode or power-down mode (provided SLPAK = WUPIE = 1). • Error Interrupt: An overrun, error, or warning condition occurred. The receiver flag register (CRFLG) will indicate one of the following conditions: – Overrun: An overrun condition as described in Receive Structures on page 330, has occurred. – Receiver Warning: The receive error counter has reached the CPU Warning limit of 96.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 339

ehia aaMC68HC Controller(MSCAN08 MSCAN 340 Technical Data 22.7.1 InterruptAcknowledge MSCAN Controller (MSCAN08) NOTE: flags. Bit manipulationinstructions( A flagcannotbeclearediftheres The flagsareresetthroughwritinga‘1’ be resetwithintheinterrupthandler of thecorrespondingflags transmitter flagregister the MSCAN08receiver Interrupts aredirectlyassociatedwith – – – – MSCAN08 hasgoneto Bus Off gone toerrorpassivestate. exceeded theerrorpassive Transmitter ErrorPassive gone toerrorpassivestate. exceeded theerrorpassive Receiver ErrorPassive 96. CPUWarninglimitof the Transmitter Warning : Thetransmiterrorcounterhasexceeded255and (CTFLG). Interruptsare flag register(CRF is set.Theflagsint BSET : Thetransmiterrorco busoffstate. : Thereceiveerrorcounterhas pective conditionstillprevails. ) shallnotbeused : Thetransmiterrorcounterhas inordertohandshaketheinterrupt. Freescale Semiconductor ) limit of127and limit of127and one ormorestatus to thecorrespondingbitposition. LG) ortheMSCAN08 he aboveregistersmust pending aslongone unter hasreached MSCAN08 has MSCAN08 has to clearinterrupt 08AZ60 — Rev 1.1 Rev — 08AZ60 flagsineither MSCAN Controller (MSCAN08) Protocol Violation Protection

22.7.2 Interrupt Vectors

The MSCAN08 supports four interrupt vectors as shown in Table 22-1. The vector addresses and the relative interrupt priority are defined in Table 2-1. Table 22-1. MSCAN08 Interrupt Vector Addresses Local Global Function Source Mask Mask Wakeup WUPIF WUPIE RWRNIF RWRNIE TWRNIF TWRNIE Error RERRIF RERRIE Interrupts TERRIF TERRIE BOFFIF BOFFIE I Bit OVRIF OVRIE Receive RXF RXFIE TXE0 TXEIE0 Transmit TXE1 TXEIE1 TXE2 TXEIE2

22.8 Protocol Violation Protection

The MSCAN08 will protect the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features:

• The receive and transmit error counters cannot be written or otherwise manipulated. • All registers which control the configuration of the MSCAN08 can not be modified while the MSCAN08 is on-line. The SFTRES bit in the MSCAN08 module control register (see MSCAN08 Module Control Register 0 on page 359) serves as a lock to protect the following registers: – MSCAN08 module control register 1 (CMCR1) – MSCAN08 bus timing register 0 and 1 (CBTR0 and CBTR1) – MSCAN08 identifier acceptance control register (CIDAC) – MSCAN08 identifier acceptance registers (CIDAR0–3)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 341

ehia aaMC68HC Controller(MSCAN08 MSCAN 342 Technical Data 22.9 LowPower Modes MSCAN Controller (MSCAN08) consumption stand-bymo The WAITandSTOPin Down mode,allclocksare by stoppingallclocksexceptthoseto modes. InSleepandSoftRe reduced powerconsumption:Sleep, In additionto MSCAN08 andCPUmodes.A . SLPAK=WUPIE=1. inte wake-up anMSCAN modes, entered forthegivensettingsof 1. ‘X’ means don’t care. don’t means 1. ‘X’ TheTxCANpinisforcedtorece • MSCAN Mode MSCAN any oftheLowPowerModes. MSCAN08 identifiermaskregisters (CIDMR0–3) – Power Down Power Soft Reset Normal Sleep al 22MSCAN08 vs Table 22-2 normal mode,theMSCAN08 structions putthe des. summarizest stopped andnopowerisconsumed. set mode,powerconsumptionisreduced SLPAK = X SLPAK = SFTRES =X particular combinat the bitsSLPAKandSFTRES.Forall STOP WAIT orRUN WAIT STOP rrupt canoccuronlyif SoftResetandPowerDown Freescale Semiconductor ) accesstheregisters.InPower CPU OperatingModes ssive whenthe (1) MCU inlowpower CPU Mode CPU has threemodeswith he combinationsof ion ofmodesis MSCAN08 isin SFTRES =0 SFTRES =1 SFTRES =0 SLPAK =0 SLPAK =0 SLPAK =1 08AZ60 — Rev 1.1 Rev — 08AZ60 MSCAN Controller (MSCAN08) Low Power Modes

22.9.1 MSCAN08 Sleep Mode

The CPU can request the MSCAN08 to enter the low-power mode by asserting the SLPRQ bit in the module configuration register (see Figure 22-6). The time when the MSCAN08 enters Sleep mode depends on its activity:

• if it is transmitting, it continues to transmit until there is no more message to be transmitted, and then goes into Sleep mode • if it is receiving, it waits for the end of this message and then goes into Sleep mode • if it is neither transmitting or receiving, it will immediately go into Sleep mode

NOTE: The application software must avoid setting up a transmission (by clearing or more TXE flags) and immediately request Sleep mode (by setting SLPRQ). It then depends on the exact sequence of operations whether MSCAN08 starts transmitting or goes into Sleep mode directly.

During Sleep mode, the SLPAK flag is set. The application software

should use SLPAK as a handshake indication for the request (SLPRQ) to go into Sleep mode. When in Sleep mode, the MSCAN08 stops its internal clocks. However, clocks to allow register accesses still run. If the MSCAN08 is in buss-off state, it stops counting the 128*11 consecutive recessive bits due to the stopped clocks. The TxCAN pin stays in recessive state. If RXF=1, the message can be read and RXF can be cleared. Copying of RxGB into RxFG doesn’t take place while in Sleep mode. It is possible to access the transmit buffers and to clear the TXE flags. No message abort takes place while in Sleep mode.

The MSCAN08 leaves Sleep mode (wake-up) when:

• bus activity occurs or • the MCU clears the SLPRQ bit or • the MCU sets the SFTRES bit

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 343

ehia aaMC68HC Controller(MSCAN08 MSCAN 344 Technical Data 22.9.2 MSCAN08 MSCAN Controller (MSCAN08) NOTE: Soft ResetMode timing andtheCANme accessed. Thismodeisusedtoinit In SoftResetmode,t was left,itcontinuescountingt issti IftheMSCAN08 transmissions. wake-up: copyingofRxBGinto before Sleepmodewasent buffers (RxFGandRxBG)containme up byaCANframe,thisframeis thebus.Asac synchronize to After wake-up,theMSCAN mode (SLPAK=1). The MCUcannotcleart Register 0 mode. or MSCAN08 Figure 22-6.Sleep MCU on page359foracompletedescr MSCAN08 Sleeping SLPRQ = 1 = SLPRQ SLPAK = 1 he MSCAN08isstopped.R ssage filter.See he SLPRQbitbeforetheMSCAN08isinSleep 08 waits for11consecut ered. Allpendingaction MSCAN08 Running onsequence, if the MSCAN08 iswoken- if theMSCAN08 onsequence, Request/Acknowledge Cycle he 128*11consecutiverecessivebits. RxFG, messageabortsand SLPRQ = 0 = SLPRQ SLPAK = 0 MSCAN08 notreceived.The ialize themodulec Freescale Semiconductor ) ll in bus-off state after Sleep mode ll inbus-offstateafterSleep ssages iftheywerereceived MSCAN08 Module Control Control MSCAN08 Module iption oft Sleep Request SLPRQ = 1 = SLPRQ SLPAK = 0 egisters canstillbe s areexecutedupon ive recessivebitsto receive message MCU onfiguration, bit he SoftReset 08AZ60 — Rev 1.1 Rev — 08AZ60 MSCAN Controller (MSCAN08) Low Power Modes

When setting the SFTRES bit, the MSCAN08 immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations.

NOTE: The user is responsible to take care that the MSCAN08 is not active when Soft Reset mode is entered. The recommended procedure is to bring the MSCAN08 into Sleep mode before the SFTRES bit is set.

22.9.3 MSCAN08 Power Down Mode

The MSCAN08 is in Power Down mode when the CPU is in Stop mode.

When entering the Power Down mode, the MSCAN08 immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations.

NOTE: The user is responsible to take care that the MSCAN08 is not active when Power Down mode is entered. The recommended procedure is to bring the MSCAN08 into Sleep mode before the STOP instruction is

executed.

To protect the CAN bus system from fatal consequences of violations to the above rule, the MSCAN08 drives the TxCAN pin into recessive state.

In Power Down mode, no registers can be accessed.

MSCAN08 bus activity can wake the MCU from CPU Stop/MSCAN08 power-down mode. However, until the oscillator starts up and synchronisation is achieved the MSCAN08 will not respond to incoming data.

22.9.4 CPU Wait Mode

The MSCAN08 module remains active during CPU wait mode. The MSCAN08 will stay synchronized to the CAN bus and generates transmit, receive, and error interrupts to the CPU, if enabled. Any such interrupt will bring the MCU out of wait mode.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 345

ehia aaMC68HC Controller(MSCAN08 MSCAN 346 Technical Data 22.11 ClockSystem Link 22.10 Timer 22.9.5 ProgrammableWakeupFunction MSCAN Controller (MSCAN08) electromagnetic inferenc bus ratesrangingfrom With thisflexibleclockingscheme circuitry anditsinteractionwith Figure 22-7 stamps whichcanbestored events, itcanbeused After theTIMBmodule in theCMCR0. Channel 0inputunderthecontrolof Timer InterfaceModuleB(TIMB). The previouslydescribedtimersig generated afterasuccessfultransmission. receives theframesbeingsentby pulse ofonebitti successfully, thetimersi valid ifnoerrorsoccurredbefore been received.BecausetheCANspec The MSCAN08willgenerat due toshortglitchesonth 361). Thisfeaturecanbeusedtopr control bitWUPMin the RxCANinputlinewhil The MSCAN08canbeprogramm showsthestructureof me isgenerated.AstheMS MSCAN08 ModuleCont under softwarecontrol 10 kbpsupto1Mbps. has beenprogram gnal willbegeneratedri e withinnoisyenvironments. e CANbuslines.Suchgl e ininternalsleepm e atimersignalwhenev with thereceivedmessage. the clockgenerat theEOFfieldhasbeentransmitted ed toapplyalow-passfilterfunction This signalisconnectedtothe itself,atimersignalalsowillbe the MSCAN08isable nal canberoutedintotheon-chip the MSCAN08clockgeneration otect theMSCAN08fromwake-up thetimerlinke Freescale Semiconductor ) ification definesaframetobe med tocapturerisingedge CAN08 receiver to generate16-bittime rol Register1 ode (seeinformationon ght aftertheEOF.A ion module(CGM). itches canresultfrom er avalidframehas nable (TLNKEN)bit 08AZ60 — Rev 1.1 Rev — 08AZ60 tohandleCAN enginealso on page MSCAN Controller (MSCAN08) Clock System

CGMXCLK OSC ÷ 2 CGMOUT (TO SIM)

BCS

PLL ÷ 2

CGM

MSCAN08

(2 * BUS FREQ.)

÷ 2

MSCANCLK PRESCALER (1 .. 64) CLKSRC

Figure 22-7. Clocking Scheme

The clock source bit (CLKSRC) in the MSCAN08 module control register (CMCR1) (see MSCAN08 Module Control Register 0 on page 359) defines whether the MSCAN08 is connected to the output of the crystal oscillator or to the PLL output.

The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the CAN protocol are met.

NOTE: If the system clock is generated from a PLL, it is recommended to select the crystal clock source rather than the system clock source due to jitter considerations, especially at faster CAN bus rates.

A programmable prescaler is used to generate out of the MSCAN08 clock the time quanta (Tq) clock. A time quantum is the atomic unit of time handled by the MSCAN08.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 347

ehia aaMC68HC Controller(MSCAN08 MSCAN 348 Technical Data MSCAN Controller (MSCAN08) NOTE: 10.3. oft furtherexplanation 1. For and therelatedpar Table 22-8 in compliancewith It istheuser’sresponsibilitytomake page 362and registers, CBTR0–CBTR1,see The aboveparameterscanbeset of 1to4time The synchronizationjumpwidth(S A bittimeissubdivi Time segment2:This • Time segment1:Thissegmen • SYNC_SEG: Thissegmenthas • parameter tobe2 CAN standard.Itcanbeprogra setting theparameter PHASE_SEG1 oftheC quantum. Signaledgesareexpected givesanoverview quanta bysetting MSCAN08 BusTimi theCANstandard, ameter values. ded intothreesegments Bit rate= he underlying concepts please refe please concepts he underlying f Tq 8timequantalong. = TSEG1 toconsistof416timequanta. AN standard.Itcan on theCANconformi No. oftimequanta Presc value MSCAN08 BusTimi the SJWparameter. f MSCANCLK by programmingthebustiming JW) canbeprogrammedinarange ng Register1 surethatthebittimingsettingsare Freescale Semiconductor ) t includesthePROP_SEGand mmed bysettingtheTSEG2 represents PHASE_ f a fixedlength Tq to happenwithinthissection. (1) (see r to ISO/DIS 11 519-1, Section r Section to ISO/DIS11 519-1, be programmedby on page363). ng segmentsettings Figure 22-8 of onetime ng Register0 08AZ60 — Rev 1.1 Rev — 08AZ60 SEG2 ofthe ). on MSCAN Controller (MSCAN08) Clock System

NRZ SIGNAL

SYNC TIME SEGMENT 1 TIME SEG. 2 _SEG (PROP_SEG + PHASE_SEG1) (PHASE_SEG2)

1 4 ... 16 2 ... 8

8... 25 TIME QUANTA = 1 BIT TIME

SAMPLE POINT (SINGLE OR TRIPLE SAMPLING)

Figure 22-8. Segments Within the Bit Time

Table 22-3. Time segment syntax

System expects transitions to occur on the bus SYNC_SEG during this period. A node in transmit mode will transfer a new Transmit point value to the CAN bus at this point. A node in receive mode will sample the bus at this point. If the three samples per bit option is Sample point selected then this point marks the position of the third sample.

Time Time Synchron. TSEG1 TSEG2 SJW Segment 1 Segment 2 Jump Width 5 .. 10 4 .. 9 2 1 1 .. 2 0 .. 1 4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2 5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3 6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3 7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3 8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3 9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3 Table 22-4. CAN Standard Compliant Bit Time Segment Settings

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 349

ehia aaMC68HC Controller(MSCAN08 MSCAN 350 Technical Data 22.13 Programmer’s ModelofMessageStorage Map 22.12 Memory MSCAN Controller (MSCAN08) transmit buffer priority register (TBPR register priority transmit buffer in thememorymapcontaininga13-by buffers havethesame programmer interfacesimplification, message buffersandthe This sectiondetailst shown in The MSCAN08occupies128bytesin Figure 22-9 Figure 22-9.MSCAN08MemoryMap $050D $050E $057F $056F $055F $054F $053F $050F he organizationoft $0570 $0560 $0550 $0540 $0518 $0517 $0510 $0509 $0508 $0500 . outline. Eachmessagebuf associated controlregisters.Forreasonsof CONTROL REGISTERS TRANSMIT BUFFER 2 BUFFER TRANSMIT TRANSMIT BUFFER 1 BUFFER TRANSMIT TRANSMIT BUFFER 0 BUFFER TRANSMIT ERROR COUNTERS IDENTIFIER FILTER RECEIVE BUFFER RECEIVE RESERVED RESERVED 40 BYTES thereceiveand 8 BYTES 9 BYTES 2 BYTES 5 BYTES Freescale Semiconductor ) ) isdefinedfort the CPU08memoryspace,as te datastructure. he receiveandtransmit fer allocates16bytes he transmitbuffers. transmit message 08AZ60 — Rev 1.1 Rev — 08AZ60 Anadditional MSCAN Controller (MSCAN08) Programmer’s Model of Message Storage

Addr(1) Register Name $05b0 IDENTIFIER REGISTER 0 $05b1 IDENTIFIER REGISTER 1 $05b2 IDENTIFIER REGISTER 2 $05b3 IDENTIFIER REGISTER 3 $05b4 DATA SEGMENT REGISTER 0 $05b5 DATA SEGMENT REGISTER 1 $05b6 DATA SEGMENT REGISTER 2 $05b7 DATA SEGMENT REGISTER 3 $05b8 DATA SEGMENT REGISTER 4 $05b9 DATA SEGMENT REGISTER 5 $05bA DATA SEGMENT REGISTER 6 $05bB DATA SEGMENT REGISTER 7 $05bC DATA LENGTH REGISTER TRANSMIT BUFFER PRIORITY $05bD REGISTER(2) $05bE UNUSED $05bF UNUSED 1. Where b equals the following: b=4 for Receive Buffer b=5 for Transmit Buffer 0 b=6 for Transmit Buffer 1 b=7 for Transmit Buffer 2 2. Not applicable for receive buffers Figure 22-10. Message Buffer Organization

22.13.1 Message Buffer Outline

Figure 22-11 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 22-12. All bits of the 13-byte data structure are undefined out of reset.

NOTE: The foreground receive buffer can be read anytime but cannot be written. The transmit buffers can be read or written anytime.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 351

ehia aaMC68HC Controller(MSCAN08 MSCAN 352 Technical Data 22.13.2 IdentifierRegisters MSCAN Controller (MSCAN08) Figure 22-11.Receive/TransmitM $05b $05b $05b $05b $05b $05b Addr Register Bit 7 6 5 4 3 2 1 Bit 0 Bit 1 2 3 4 5 6 Bit7 Register Addr 5DSR14DSR03IDR32IDR21IDR10IDR0 Read: Read: Read: Read: Read: Read: Write: Write: Write: Write: Write: Write: SRR —Substitute RemoteRequest number. The priorityofanidentifierisdefined bit andistransmittedfirs bits (ID28–ID0)fortheextendedformat. The identifiersconsistofeither11 to 1bytheuser This fixedrecessivebitisusedonly on theCANbusforreceivebuffers. D4I1 D2I1 D0I9I8ID7 ID8 ID9 ID15 ID21 ID10 ID16 ID22 ID11 ID17 ID23 ID12 (=1) IDE ID24 (=1) SRR ID13 ID18 ID25 ID14 ID19 ID26 ID20 ID27 ID28 B B B B B B B DB0 DB1 DB0 DB2 DB1 DB3 DB2 DB4 DB3 DB5 DB4 DB6 DB5 DB7 DB6 DB7 D D D D D D D RTR ID0 ID1 ID2 ID3 ID4 ID5 ID6 essage BufferExtend for transmissionbu t onthebusduring bits (ID10–ID0)forthestandard,or29 ed Identifier(IDRn) to behighestforthesmallestbinary Freescale Semiconductor ) ffers andwillbest in extendedformat.Itmustbeset ID10/28 isthemostsignificant arbitration procedure. ored asreceived 08AZ60 — Rev 1.1 Rev — 08AZ60 (Sheet1of2) MSCAN Controller (MSCAN08) Programmer’s Model of Message Storage

Addr Register Bit 7 6 5 4 3 2 1 Bit 0 Read: $05b6DSR2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write: Read: $05b7DSR3 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write: Read: $05b8DSR4 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write: Read: $05b9DSR5 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write: Read: $05bADSR6 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write: Read: $05bBDSR7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write: Read: $05bCDLR DLC3 DLC2 DLC1 DLC0 Write:

= Unimplemented

Figure 22-11. Receive/Transmit Message Buffer Extended Identifier (IDRn) (Sheet 2 of 2)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 353

ehia aaMC68HC Controller(MSCAN08 MSCAN 354 Technical Data MSCAN Controller (MSCAN08) $05b $05b $05b $05b AddrRegister Bit 7654321Bit 0 3IDR32IDR21IDR10IDR0 Read: Read: Read: Read: Write: Write: Write: Write: IDE —IDExtended RTR —RemoteTransmissionRequest Figure 22-12.Standard This flagindicateswhet being receivedandindica is appliedinthisbuffer.Incaseof setting oftheRTRbittobesent. tran ofa Incase software. frame in the receivedframeandsupports the CANframe.Incase This flagreflectsthest MSCAN08 whattypeof identifier registers.Incaseofatr D0I9I8I7I6I5I4ID3 ID4 ID5 ID6 ID7 ID8 ID9 ID10 D D D T IDE(=0) RTR ID0 ID1 ID2 0 =Dataframe 1 = Remoteframe 0 =Standardformat,11bits 1 =Extendedformat,29bits = Unimplemented = atus oftheremotetr her theextendedorstanda Identifier Mapping of areceivebuffer,iti identifier tosend. tes totheCPUhow ansmit buffer,thefl the transmissionofananswering Freescale Semiconductor ) a receivebuffer,t smit buffer,this ansmission requestbitin ndicates thestatusof processthebuffer rd identifierformat ag indicatestothe flag definesthe he flagissetas 08AZ60 — Rev 1.1 Rev — 08AZ60 MSCAN Controller (MSCAN08) Programmer’s Model of Message Storage

22.13.3 Data Length Register (DLR)

This register keeps the data length field of the CAN frame.

DLC3–DLC0 — Data Length Code Bits The data length code contains the number of bytes (data byte count) of the respective message. At transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 22-5 shows the effect of setting the DLC bits.

Table 22-5. Data Length Codes

Data Length Code Data Byte DLC3 DLC2 DLC1 DLC0 Count

00000

00011

00102

00113

01004

01015

01106

01117

10008

22.13.4 Data Segment Registers (DSRn)

The eight data segment registers contain the data to be transmitted or received. The number of bytes to be transmitted or being received is determined by the data length code in the corresponding DLR.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 355

ehia aaMC68HC Controller(MSCAN08 MSCAN 356 Technical Data Mode 22.14 Programmer’s 22.13.5 TransmitBuffer MSCAN Controller (MSCAN08) drs:$05bD Address: of theMSCAN08. efficiency. The programmer’smodelha PRIO7–PRIO0 — Reset:uuuuuuuu Read: Write: PriorityRegisters This fielddefinesthelo • In case more than one one than casemore In • Thetransmissionbufferwiththelowe • All transmission bufferswithacl • prioritisation mechanism: number. TheMSCAN08implements MSCAN08 andisdefinedto The localpriorityisusedfortheinte Figure 22-13.TransmitBuffer message buffer with the with buffer message prioritisation. prioritisation rightbefo RO RO RO RO RO RO RO PRIO0 PRIO1 PRIO2 PRIO3 PRIO4 PRIO5 PRIO6 PRIO7 Bit 7654321Bit 0 l ofControlRegisters Figure 22-14 Local Priority givesanoverviewonthe cal priorityoftheassociatedmessagebuffer. s beenlaidoutfor re theSOFissent. buffer hasthesamelowestpriority, behighestforthe lower indexnumberwins. Freescale Semiconductor ) Priority Register (TBPR) eared TXEflagpar rnal prioritisationprocessofthe the followinginternal st localpriorityfieldwinsthe maximum simplicityand smallest binary control registerblock 08AZ60 — Rev 1.1 Rev — 08AZ60 ticipate inthe MSCAN Controller (MSCAN08) Programmer’s Model of Control Registers

Addr Register Bit 7 6 5 4 3 2 1 Bit 0

Read: 0 0 0 SYNCH SLPAK $0500 CMCR0 TLNKEN SLPRQ SFTRES Write:

Read: 0 0 0 0 0 $0501 CMCR1 LOOPB WUPM CLKSRC Write:

Read: $0502 CBTR0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Write:

Read: $0503 CBTR1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Write:

Read: $0504 CRFLG WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF Write:

Read: $0505 CRIER WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE Write:

Read: 0 ABTAK2 ABTAK1 ABTAK0 0 $0506 CTFLG TXE2 TXE1 TXE0 Write:

Read: 0 0 $0507 CTCR ABTRQ2 ABTRQ1 ABTRQ0 TXEIE2 TXEIE1 TXEIE0 Write:

Read: 0 0 0 0 IDHIT1 IDHIT0 $0508 CIDAC IDAM1 IDAM0 Write:

Read: $0509 Reserved RRRRRRRR Write:

= Unimplemented R = Reserved

Figure 22-14. MSCAN08 Control Register Structure

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 357

ehia aaMC68HC Controller(MSCAN08 MSCAN 358 Technical Data MSCAN Controller (MSCAN08) 00 CRXERR $050E drRgse i Bit 0 1 2 3 4 5 6 Bit 7 Register Addr 00 CTXERR $050F 01 CIDMR3 $0517 01 CIDMR2 $0516 01 CIDMR1 $0515 01 CIDMR0 $0514 CIDAR3 $0513 CIDAR2 $0512 CIDAR1 $0511 CIDAR0 $0510 Figure 22-14.MSCAN08Control Read: Read: Read: Read: Read: Read: Read: Read: Read: Read: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: XR7RER XR5RXERR4 RXERR5 RXERR6 RXERR7 XR7TER XR5TXERR4 TXERR5 TXERR6 TXERR7 AM7AM6AM5AM4AM3AM2AM1AM0 AM7AM6AM5AM4AM3AM2AM1AM0 AM7AM6AM5AM4AM3AM2AM1AM0 AM7AM6AM5AM4AM3AM2AM1AM0 C C C C C C C AC0 AC1 AC0 AC2 AC1 AC0 AC3 AC2 AC1 AC0 AC4 AC3 AC2 AC1 AC5 AC4 AC3 AC2 AC6 AC5 AC4 AC3 AC7 AC6 AC5 AC4 AC7 AC6 AC5 AC7 AC6 AC7 Register Struct Freescale Semiconductor ) XR3RER XR1RXERR0 RXERR1 RXERR2 RXERR3 XR3TER XR1TXERR0 TXERR1 TXERR2 TXERR3 ure (Continued) 08AZ60 — Rev 1.1 Rev — 08AZ60 MSCAN Controller (MSCAN08) Programmer’s Model of Control Registers

22.14.1 MSCAN08 Module Control Register 0

Address: $0500

Bit 7654321Bit 0

Read: 0 0 0 SYNCH SLPAK TLNKEN SLPRQ SFTRES Write:

Reset:00000001

= Unimplemented Figure 22-15. Module Control Register 0 (CMCR0)

SYNCH — Synchronized Status This bit indicates whether the MSCAN08 is synchronized to the CAN bus and as such can participate in the communication process. 1 = MSCAN08 synchronized to the CAN bus 0 = MSCAN08 not synchronized to the CAN bus

TLNKEN — Timer Enable This flag is used to establish a link between the MSCAN08 and the on-chip timer (see Timer Link on page 346). 1 = The MSCAN08 timer signal output is connected to the Timer Interface Module B Channel 0. 0 = The port is connected to the timer input.

SLPAK — Sleep Mode Acknowledge This flag indicates whether the MSCAN08 is in module internal sleep mode. It shall be used as a handshake for the sleep mode request (see MSCAN08 Sleep Mode on page 343). If the MSCAN08 detects bus activity while in Sleep mode, it clears the flag. 1 = Sleep – MSCAN08 in internal sleep mode 0 = Wakeup – MSCAN08 is not in Sleep mode

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 359

ehia aaMC68HC Controller(MSCAN08 MSCAN 360 Technical Data MSCAN Controller (MSCAN08) SFTRES —SoftReset SLPRQ —SleepRequest,Go separate instructions. Clearing SFTRESandwriti of 11recessivebits. MSCAN08 isinbus-offst it willbesynchroniz synchronize totheCAN When thisbitisclearedbyt soft reset. soft resetstate.Theva CIDMR0–3 canonlybewrittenby The registersCMCR1,CBTR0,CB CMCR0, CRFLG,CRIER, The followingregistersent synchronization tothebusislost. soft resetstate.Anyongoingtr When thisbitissetby This flagrequeststhe mode (see 0 =Normaloperation 1 =MSCAN08insoftresetstate 0 =Wakeup—TheMSCAN08 1 =Sleep—TheMSCA MSCAN08 SleepMode ed after11recessivebits theCPU,MSCAN08 MSCAN08 togointoan lues oftheerrorcount bus. IftheMSCAN08isno ate, itcontinuestowaitfor128occurrences CTFLG,andCTCR. er andstayinthei N08 willgointointernalsleepmode. ng tootherbitsin he CPU,theMSCAN08triesto to InternalSleepMode ansmission orrecept Freescale Semiconductor ) the CPUwhenMSCAN08isin will functionnormally. TR1, CIDAC,CIDAR0–3,and on page343). r hardresetstate: CMCR0mustbein onthebus;if ers arenotaffectedby immediately entersthe internal power-saving ion isabortedand t inbus-offstate, 08AZ60 — Rev 1.1 Rev — 08AZ60 MSCAN Controller (MSCAN08) Programmer’s Model of Control Registers

22.14.2 MSCAN08 Module Control Register 1

Address: $0501 Bit 7654321Bit 0 Read: 00000 LOOPB WUPM CLKSRC Write: Reset:00000000 = Unimplemented Figure 22-16. Module Control Register (CMCR1)

LOOPB — Loop Back Self-Test Mode When this bit is set, the MSCAN08 performs an internal loop back which can be used for self-test operation: the bit stream output of the transmitter is fed back to the receiver internally. The RxCAN input pin is ignored and the TxCAN output goes to the recessive state (logic ‘1’). The MSCAN08 behaves as it does normally when transmitting and treats its own transmitted message as a message received from

a remote node. In this state the MSCAN08 ignores the bit sent during the ACK slot of the CAN frame Acknowledge field to insure proper reception of its own message. Both transmit and receive interrupt are generated. 1 = Activate loop back self-test mode 0 = Normal operation

WUPM — Wakeup Mode This flag defines whether the integrated low-pass filter is applied to protect the MSCAN08 from spurious wakeups (see Programmable Wakeup Function on page 346). 1 = MSCAN08 will wake up the CPU only in cases of a dominant pulse on the bus which has a length of at least twup. 0 = MSCAN08 will wake up the CPU after any recessive to dominant edge on the CAN bus.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 361

ehia aaMC68HC Controller(MSCAN08 MSCAN 362 Technical Data 22.14.3 MSCAN08Bus MSCAN Controller (MSCAN08) NOTE: drs:$0502 Address: SJW1 andSJW0—Synchr MSCAN08 modulecontro The CMCR1registercan Source CLKSRC —Clock Reset:00000000 Timing Register0 Read: Write: bus (see lengthened, toachieveresynchron of timequanta(T The synchronizationjumpwidth(SJW from (see defineswhichclock sour This flag 0 =TheMSCAN08clocksour 1 =TheMSCAN08clocksour J1SW R5BP R3BP R1BRP0 BRP1 BRP2 BRP3 BRP4 BRP5 SJW0 SJW1 Bit 7654321Bit 0 Figure 22-17.BusTimi Table 22-6 J1SW Synchronization Jump Width SJW0 SJW1 Clock System Table 22-6.Synchronization Jump Width 00 11 10 01 q ) clockcyclesbywhicha ). l registerisset be writtenonlyifthe onization JumpWidth on page346). ce is CGMXCLK/2 (see ce isCGMXCLK/2(see ng Register0(CBTR0) ce isCGMOUT(see Freescale Semiconductor ) ce the MSCAN08 module isdriven module MSCAN08 ce the ization ondatatransitionsthe ) definesthemaximumnumber 1 T 4 T 3 T 2 T bit maybeshortened,or SFTRES bi q q q q cycle cycle cycle cycle 08AZ60 — Rev 1.1 Rev — 08AZ60 Figure 22-7 t inthe Figure 22-7 ). ). MSCAN Controller (MSCAN08) Programmer’s Model of Control Registers

BRP5–BRP0 — Baud Rate Prescaler

These bits determine the time quanta (Tq) clock, which is used to build up the individual bit timing, according toTable 22-7. Table 22-7. Baud Rate Prescaler

BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler Value (P) 000000 1 000001 2 000010 3 000011 4 :::::: : :::::: : 111111 64

NOTE: The CBTR0 register can be written only if the SFTRES bit in the MSCAN08 module control register is set.

22.14.4 MSCAN08 Bus Timing Register 1

Address: $0503

Bit 7654321Bit 0

Read: SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 Write:

Reset:00000000 Figure 22-18. Bus Timing Register 1 (CBTR1)

SAMP — Sampling This bit determines the number of serial bus samples to be taken per bit time. If set, three samples per bit are taken, the regular one (sample point) and two preceding samples, using a majority rule. For higher bit rates, SAMP should be cleared, which means that only one sample will be taken per bit. 1 = Three samples per bit(1) 0 = One sample per bit

1. In this case PHASE_SEG1 must be at least 2 time quanta.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 363

ehia aaMC68HC Controller(MSCAN08 MSCAN 364 Technical Data MSCAN Controller (MSCAN08) SG3TE1 SG1TSEG10 TSEG11 TSEG12 TSEG13 1. This setting is not valid. Please refer to refer Please isnotvalid. 1. This setting 0000 0010 1111 0011 0001 ...... NOTE: MSCAN08 modulecontro The CBTR1registercanonlybewrit TSEG22–TSEG10 —TimeSegment prescaler, andthenum The bittimeisdeterminedbythe programmable asshownin Time segment1(TSEG1)andtime2(TSEG2)are bit timeandthelocation Time segmentswithinthebittime shown in Table 22-8.TimeSegmentValues Table 22-4 Bit time= Table 22-9 2 T 3T 16 T 16 1 T 4 T Segment 1 for valid settings. q q q Cycles Cycles Time q Cycle q Cycles Cycles f Pres value MSCANCLK ). (1) (1) (1) l registerisset. ber oftimequanta(T of thesamplepoint. Table 22-9 SG2TE2 TSEG20 TSEG22 TSEG21 • numberofTimeQuanta 111 001 000 ...... oscillator frequen Freescale Semiconductor ) ten iftheSFTRESbitin fix thenumberofclockcyclesper . q ) clockcyclesperbitas cy, thebaudrate 08AZ60 — Rev 1.1 Rev — 08AZ60 1 T 2 T Segment 2 8T q q Time q Cycle Cycles Cycles (1) MSCAN Controller (MSCAN08) Programmer’s Model of Control Registers

22.14.5 MSCAN08 Receiver Flag Register (CRFLG)

All bits of this register are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position. A flag can be cleared only when the condition which caused the setting is valid no more. Writing a 0 has no effect on the flag setting. Every flag has an associated interrupt enable flag in the CRIER register. A hard or soft reset will clear the register.

Address: $0504

Bit 7654321Bit 0

Read: WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF Write:

Reset:00000000 Figure 22-19. Receiver Flag Register (CRFLG)

WUPIF — Wakeup Interrupt Flag

If the MSCAN08 detects bus activity while in Sleep mode, it sets the WUPIF flag. If not masked, a wake-up interrupt is pending while this flag is set. 1 = MSCAN08 has detected activity on the bus and requested wake-up. 0 = No wake-up interrupt has occurred.

RWRNIF — Receiver Warning Interrupt Flag This flag is set when the MSCAN08 goes into warning status due to the receive error counter (REC) exceeding 96 and neither one of the Error Interrupt flags or the Bus-off Interrupt flag is set(1). If not masked, an error interrupt is pending while this flag is set. 1 = MSCAN08 has gone into receiver warning status. 0 = No receiver warning status has been reached.

1. Condition to set the flag: RWRNIF = (96 ð REC) & RERRIF & TERRIF & BOFFIF

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 365

ehia aaMC68HC Controller(MSCAN08 MSCAN 366 Technical Data MSCAN Controller (MSCAN08) TERRIF — Transmitter Error Passive Interrupt Flag Interrupt Passive Error —Transmitter TERRIF RERRIF —ReceiverError 3. Condition to set the flag: ð &BOFFIF TERRIF = theflag: (128 TEC ð255) to set 3. Condition RE theflag: set to 2. Condition theflag: set to 1. Condition BOFFIF —Bus-OffInterruptFlag TWRNIF —TransmitterWa flag isnotset to theTransmitErrorcounterexce This flagissetwhent flag isset. flag flag isset. flag bits onthebus.Ifnotmasked,anEr the MSCAN08hasmonitored128ti the transmiterrorcounterexceeding This flagissetwhent isset. flag flag isnotset to thereceiveerrorcounterexce This flagissetwhent an errorinterruptispending error interruptflagsorthe the transmiterrorcounter(TEC) This flagissetwhen 0 =Noreceivererrorpa 1 =MSCAN08hasgoneintorece 0 =Nobus-offstat 1 =MSCAN08hasgoneinto 0 =Notransmiterrorpassi 1 =MSCAN08wentin 0 =Notransmitterwarningstatushasbeenreached. 1 =MSCAN08hasgoneintotr (2) (3) . Ifnotmasked,anErrorin . Ifnotmasked,anErrorin TWRNIF =(96ðTEC)& TWRNIF RERRIF RRIF = (127 RRIF =(127 ð REC255) & BOFFIF he MSCAN08goesintoerro he MSCAN08goesintoerro the MSCAN08goes us hasbeereached. he MSCAN08goesin Passive InterruptFlag to transmiterro rning InterruptFlag bus-off interruptflagisset ssive statushasbeenreached. while thisflagisset. ve statushasbeenreached. bus-offstatus. exceeding 96andnei eding 127andthebus-offinterrupt ansmitter warn Freescale Semiconductor ) eding 127andtheBus-offinterrupt mes 11consecutive‘recessive’ ror interruptispendingwhilethis iver errorpa 255. Itcannotbeclearedbefore r passivestatus. terrupt ispendingwhilethis terrupt ispendingwhilethis into warningstatusdueto &TERRIF to bus-offstatus,due ing status. r passivestatusdue r passivestatusdue ssive status. (1) & BOFFIF 08AZ60 — Rev 1.1 Rev — 08AZ60 . Ifnotmasked, ther oneofthe MSCAN Controller (MSCAN08) Programmer’s Model of Control Registers

OVRIF — Overrun Interrupt Flag This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this flag is set. 1 = A data overrun has been detected since last clearing the flag. 0 = No data overrun has occurred.

RXF — Receive Buffer Full The RXF flag is set by the MSCAN08 when a new message is available in the foreground receive buffer. This flag indicates whether the buffer is loaded with a correctly received message. After the CPU has read that message from the receive buffer the RXF flag must be cleared to release the buffer. A set RXF flag prohibits the exchange of the background receive buffer into the foreground buffer. If not masked, a receive interrupt is pending while this flag is set. 1 = The receive buffer is full. A new message is available. 0 = The receive buffer is released (not full).

NOTE: To ensure data integrity, no registers of the receive buffer shall be read while the RXF flag is cleared.

NOTE: The CRFLG register is held in the reset state when the SFTRES bit in CMCR0 is set.

22.14.6 MSCAN08 Receiver Interrupt Enable Register

Address: $0505

Bit 7654321Bit 0

Read: WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE Write:

Reset:00000000 Figure 22-20. Receiver Interrupt Enable Register (CRIER)

WUPIE — Wakeup Interrupt Enable 1 = A wakeup event will result in a wakeup interrupt. 0 = No interrupt will be generated from this event.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 367

ehia aaMC68HC Controller(MSCAN08 MSCAN 368 Technical Data MSCAN Controller (MSCAN08) NOTE: BOFFIE —Bus-Off RXFIE —ReceiverFullInterruptEnable OVRIE —OverrunInterruptEnable TERRIE —TransmitterErro RERRIE —ReceiverError CMCR0 isset. CMCR0 The CRIERregisterishe RWRNIE —ReceiverWa TWRNIE —TransmitterWa 0 =Nointerruptisgeneratedfromthisevent. 0 =Nointerruptwillbe 1 =Areceivebufferfull(successf 0 =Nointerruptisgeneratedfromthisevent. 1 =Anoverruneventwillre 0 =Nointerruptisgeneratedfromthisevent. 1 =Abus-offeventwillresu 1 =Atransmittererrorpassivestat 0 =Nointerruptisgeneratedfromthisevent. 1 =Areceivererrorpa 0 =Nointerruptisgeneratedfromthisevent. 1 =Atransmitterwarningstatus 0 =Nointerruptisgeneratedfromthisevent. warn 1 =Areceiver interrupt. result inareceiveinterrupt. result interrupt. interrupt. Interrupt Enable ing statuseventwillresu ld intheresetstate rning InterruptEnable Passive InterruptEnable rning InterruptEnable ssive statuseventwill r PassiveInterruptEnable generated fromthisevent. sult inanerrorinterrupt. lt inanerrorinterrupt. Freescale Semiconductor ) event willresultinanerror ul messagereception)eventwill us eventwillresu when theSFTRESbitin lt inanerrorinterrupt. resultinanerror 08AZ60 — Rev 1.1 Rev — 08AZ60 lt inanerror MSCAN Controller (MSCAN08) Programmer’s Model of Control Registers

22.14.7 MSCAN08 Transmitter Flag Register

The Abort Acknowledge flags are read only. The Transmitter Buffer Empty flags are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect on the flag setting. The Transmitter Buffer Empty flags each have an associated interrupt enable bit in the CTCR register. A hard or soft reset will resets the register.

Address: $0506 5

Bit 7654321Bit 0

Read: 0 ABTAK2 ABTAK1 ABTAK0 0 TXE2 TXE1 TXE0 Write:

Reset:00000111

= Unimplemented Figure 22-21. Transmitter Flag Register (CTFLG)

ABTAK2–ABTAK0 — Abort Acknowledge This flag acknowledges that a message has been aborted due to a pending abort request from the CPU. After a particular message buffer has been flagged empty, this flag can be used by the application software to identify whether the message has been aborted successfully or has been sent. The ABTAKx flag is cleared implicitly whenever the corresponding TXE flag is cleared. 1 = The message has been aborted. 0 = The message has not been aborted, thus has been sent out.

TXE2–TXE0 — Transmitter Empty This flag indicates that the associated transmit message buffer is empty, thus not scheduled for transmission. The CPU must handshake (clear) the flag after a message has been set up in the transmit buffer and is due for transmission. The MSCAN08 sets the flag after the message has been sent successfully. The flag is also set by the MSCAN08 when the transmission request was successfully

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 369

ehia aaMC68HC Controller(MSCAN08 MSCAN 370 Technical Data 22.14.8 MSCAN08 MSCAN Controller (MSCAN08) NOTE: NOTE: Transmitter ControlRegister drs:$0507 Address: ABTRQ2–ABTRQ0 —AbortRequest ABTRQ2–ABTRQ0 isset. CMCR0 The CTFLGregisterisheldinthere towhiletheasso written To ensuredataintegrity, Reset:00000000 ed 0 Read: Write: flag (ABTAK) (see (see (ABTAK) flag message isabor transmission isnotsuccessful(los request ifthemessagehas message buffer(TXE The CPUsetsanABTRQxbitto is cleared. ABTRQx bit(ABTRQ,see (ABTAK, seeabove).WhenaTXEx Clearing aTXExflagalsoclear pending whilethisflagisset. Priority Registers aborted duetoapendi 0 =Theassociatedmessagebufferis 1 =Theassociatedmessagebuffer Figure 22-22.TransmitterCo Bit 7654321Bit 0 due fortransmission). BR2ATQ ABTRQ0 ABTRQ1 ABTRQ2 = Unimplemented ted theassociatedTXE MSCAN08 Transmitter FlagRegister on page356).Ifnotmasked, ciated TXEflagiscleared. noregistersofthetr = 0)beaborted.TheMSC ng abortrequest(see MSCAN08 TransmitterControlRegister notalreadystartedtr s thecorrespondingABTAKxflag request thatanalreadyscheduled set statewhenthe Freescale Semiconductor ) t arbitrationor ntrol Register(CTCR) flag isset,t is empty(notscheduled). 0 full(loadedwi and theabortacknowledge ansmit buffersshouldbe Transmit Buffer XI2TEE TXEIE0 TXEIE1 TXEIE2 areceiveinterruptis he corresponding ansmission, orifthe error). When a a When error). AN08 willgrantthe SFTRES bitin 08AZ60 — Rev 1.1 Rev — 08AZ60 th amessage on page ) MSCAN Controller (MSCAN08) Programmer’s Model of Control Registers

369) will be set and an TXE interrupt is generated if enabled. The CPU cannot reset ABTRQx. ABTRQx is cleared implicitly whenever the associated TXE flag is set. 1 = Abort request pending 0 = No abort request

NOTE: The software must not clear one or more of the TXE flags in CTFLG and simultaneously set the respective ABTRQ bit(s).

TXEIE2–TXEIE0 — Transmitter Empty Interrupt Enable 1 = A transmitter empty (transmit buffer available for transmission) event results in a transmitter empty interrupt. 0 = No interrupt is generated from this event.

NOTE: The CTCR register is held in the reset state when the SFTRES bit in CMCR0 is set.

22.14.9 MSCAN08 Identifier Acceptance Control Register

Address: $0508

Bit 7654321Bit 0

Read: 0 0 0 0 IDHIT1 IDHIT0 IDAM1 IDAM0 Write:

Reset:00000000

= Unimplemented Figure 22-23. Identifier Acceptance Control Register (CIDAC)

IDAM1–IDAM0— Identifier Acceptance Mode The CPU sets these flags to define the identifier acceptance filter organization (see Identifier Acceptance Filter on page 334). Table 22-9 summarizes the different settings. In “filter closed” mode no messages will be accepted so that the foreground buffer will never be reloaded.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 371

ehia aaMC68HC Controller(MSCAN08 MSCAN 372 Technical Data MSCAN Controller (MSCAN08) NOTE: the foregroundbuffer,i foreground buffer.W The IDHITindicatorsar is set. The CIDACregistercanbewrittenonl IDHIT1–IDHIT0— Iden summarizes thedifferentsettings. (see (see The MSCAN08setstheseflagstoindi Identifier AcceptanceFilter DI1IHT Identifi IDHIT1 IDHIT0 DM DM Identifier Acceptance IDAM1 IDAM0 Mode Table 22-10.IdentifierAc Table 22-9.Identifier Filter3Hit Filter2Hit Filter1Hit Filter0Hit 1 0 1 0 1 1 0 0 FilterClosed Four 8-Bit AcceptanceFilters Two 16-BitAcceptance Filter 1 Acceptance Filter Single32-Bit 0 1 0 1 1 0 0 hen amessagegetscopiedfromthebackgroundto tifier AcceptanceHitIndicator e alwaysrelatedto ndicators areupdatedaswell. AcceptanceModeSettings Freescale Semiconductor ) ceptance HitIndication on page334). y iftheSFTRESbitinCMCR0 cate anidentifieracceptancehit the messagein er Acceptance Hit Table 22-9 08AZ60 — Rev 1.1 Rev — 08AZ60

MSCAN Controller (MSCAN08) Programmer’s Model of Control Registers

22.14.10 MSCAN08 Receive Error Counter

Address: $050E

Bit 7654321Bit 0

Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0

Write:

Reset:00000000

= Unimplemented Figure 22-24. Receiver Error Counter (CRXERR)

This register reflects the status of the MSCAN08 receive error counter. The register is read only.

22.14.11 MSCAN08 Transmit Error Counter

Address: $050F

Bit 7654321Bit 0

Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0

Write:

Reset:00000000

= Unimplemented Figure 22-25. Transmit Error Counter (CTXERR)

This register reflects the status of the MSCAN08 transmit error counter. The register is read only.

NOTE: Both error counters may only be read when in Sleep or Soft Reset mode.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 373

ehia aaMC68HC Controller(MSCAN08 MSCAN 374 Technical Data 22.14.12 MSCAN08 MSCAN Controller (MSCAN08) Identifier A CIDAR3 CIDAR2 CIDAR1 CIDAR0 CIDAR0/1) areapplied. For extendedidentifiers IDR3 registersofin The acceptanceregistersoftheMS next message(dropped). registers (accepted);ot passes thecriteriainidenti buffer. TheCPUisonly On receptioneachmessageiswrit applied. Forstandardi Figure 22-26.Identi ee:UnaffectedbyReset UnaffectedbyReset Reset: UnaffectedbyReset Reset: UnaffectedbyReset Reset: Reset: Read: Read: Read: Read: Write: Write: Write: Write: BitBit 7654321BitBit 7654321Bit 0 Bit 7654321Bit 0 7654321Bit 0 0 C C C C C C C AC0 AC1 AC2 AC3 AC0 AC4 AC1 AC5 AC2 AC6 AC3 AC0 AC7 AC4 AC1 AC5 AC2 AC6 AC3 AC0 AC7 AC4 AC1 AC5 AC2 AC6 AC3 AC7 AC4 AC5 AC6 AC7 Address: $0513 Address: $0512 Address: $0511 Address: $0510 cceptance Registers coming messagesina fier AcceptanceRegist dentifiers onlythefi herwise, themessagewill , allfouracceptance signalled toreadtheme fier acceptanceandidentifiermask ten intotheba CAN08 areapplied Freescale Semiconductor ) rst two(CIDMR0/1and bit bymanner. and maskregistersare ers (CIDAR0–CIDAR3) ssage, however,ifit ckground receive be overwrittenbythe 08AZ60 — Rev 1.1 Rev — 08AZ60 on theIDR0to MSCAN Controller (MSCAN08) Programmer’s Model of Control Registers

AC7–AC0 — Acceptance Code Bits AC7–AC0 comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register.

NOTE: The CIDAR0–3 registers can be written only if the SFTRES bit in CMCR0 is set

22.14.13 MSCAN08 Identifier Mask Registers (CIDMR0-3)

The identifier mask registers specify which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. For standard identifiers it is required to program the last three bits (AM2- AM0) in the mask register CIDMR1 to ‘don’t care’.

CIDMRO Address: $0514 Bit 7654321Bit 0

Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write: Reset: Unaffected by Reset CIDMR1 Address: $0515 Bit 7654321Bit 0 Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write: Reset: Unaffected by Reset CIDMR2 Address: $0516 Bit 7654321Bit 0 Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write: Reset: Unaffected by Reset CIDMR3 Address: $0517 Bit 7654321Bit 0 Read: AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 Write: Reset: Unaffected by Reset Figure 22-27. Identifier Mask Registers (CIDMR0–CIDMR3)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor MSCAN Controller (MSCAN08) 375

ehia aaMC68HC Controller(MSCAN08 MSCAN 376 Technical Data MSCAN Controller (MSCAN08) NOTE: CMCR0 isset CMCR0 The CIDMR0-3registersca AM7–AM0 —AcceptanceMaskBits accepted. acceptance registerwillnotaffect indicates thatthestateof message willbeaccepted same asitsidentif corresponding bitintheidentifier If aparticularbitinth 0 =Matchcorrespondingacceptanc 1 =Ignorecorrespondingaccept bits. ier bitbeforeamatc is register is cleared, this indicates that the the that indicates this cleared, registeris is n bewrittenonlyift if allsuchbitsmatch. corresponding bitintheidentifier acceptance registermustbethe whetherornotthemessageis Freescale Semiconductor ) ance coder h willbedetected.The e coderegisterandidentifier he SFTRESbitinthe egister bit. Ifabitisset,it 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 23. Keyboard Module (KBD)

23.1 Contents

23.2 Introduction...... 375 23.3 Features...... 376 23.4 Functional Description...... 376 23.5 Keyboard Initialization ...... 379 23.6 Low-Power Modes ...... 380 23.6.1 Wait Mode ...... 380 23.6.2 Stop Mode ...... 380 23.7 Keyboard Module During Break Interrupts ...... 380

23.8 I/O Registers ...... 381 23.8.1 Keyboard Status and Control Register ...... 381 23.8.2 Keyboard Interrupt Enable Register...... 382

23.2 Introduction

The keyboard interrupt module (KBD) provides five independently maskable external interrupt pins.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Keyboard Module (KBD) 375 ehia aaMC68HC Freescale Semiconductor KeyboardModule (KBD) 376 Technical Data 23.4 FunctionalDescription 23.3 Features Keyboard Module(KBD) control registercontrols low afterallwerehigh.TheMODEK A keyboardinterruptislatchedw pin latchesakeyboardinterruptrequest. internal pullupdevice. keyboard interruptpin.En independently enablesordisables Writing totheKBIE4–KBIE0 KBD featuresinclude: If thekeyboardinterruptisfalli • If thekeyboardinterrupt ise • Exit fromLow • Automatic InterruptAcknowledge • Programmable Edge-OnlyorEdge- • Hysteresis Buffers • Five KeyboardInterruptPins • interrupt requestispresentas the latterpinwh on onepinbecauseanother keyboard pinisalreadylow.Topr keyboard pindoesnotlatchanin Enable BitsandOneKeyboardInterruptMask -Power Modes ile itislow. A logic0appliedtoan thetriggeringmodeof abling akeyboardinterrupt bitsinthekeyboard hen oneormorekeyboardpinsgoes dge-sensitive only,afallingedgeon pinisstilllow,softwarecandisable each portGorHpinasa with SeparateKeyboardInterrupt ng edge-andlowlevel-sensitive,an bit inthekeyboardstatusand long asanykeyboardpinislow. event losinganinterruptrequest terrupt reques and Level-Interr enabled keyboardinterrupt the keyboardinterrupt. interrupt enableregister pinalsoenablesits t ifanother 08AZ60 — Rev 1.1 Rev — 08AZ60 upt Sensitivity Keyboard Module (KBD) Functional Description KEYBOARD INTERRUPT REQUEST KEYF IMASKK MODEK SYNCHRONIZER IMASKK DECODER ACKK INTERNAL BUS INTERNAL VECTOR FETCH VECTOR KEYF 0 ACKK RESET KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 KEYBOARD INTERRUPT FF INTERRUPT egister Summary er Address Summary CLR

CK DQ DD $001A $001B V KBSCR KBIER = Unimplemented MODEK 0000 Figure 23-2. I/O R Register Address Write: Write: Read: 0 0 0 Read: Reset:00000000 Reset:00000000 Table 23-1. I/O Regist Table Figure 23-1. Keyboard Module Block Diagram . . . ter (KBIER)ter ister (KBSCR) KB0IE KB4IE Register NameBit 7654321Bit 0 7654321Bit NameBit Register KBD0 KBD4 Keyboard Interrupt Enable Regis- Keyboard Status and Control Reg- Status Keyboard TO PULLUP ENABLE PULLUP TO ENABLE PULLUP TO

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Keyboard Module (KBD) 377 ehia aaMC68HC Freescale Semiconductor KeyboardModule (KBD) 378 Technical Data Keyboard Module(KBD) register. direction registerto To determinethelogi useful inapplicationswh affected bythekeyboardinterrupt the interruptrequesteven Reset clearsthekeyboardinterrupt immediately clearstheke can beusedtoseeifapendinginte The keyboardflagbit(KEYF)intheke sensitive only.WithMO If theMODEKbitisclear,key interrupt pinstologic The vectorfetchorsoftwareclear clear akeyboardinterruptrequest: and lowlevel-sensitive,bothoft If theMODEKbitisset,keyboard Return ofallenabledke • Vector fetchorsoftwareclear • interrupt remainsset. any enabledkeyboardinte $FFDF. program counterwiththevector maskbit,IMASK keyboard interrupt writing totheACKKbi on thekeyboardinterruptpins.A due tonoise.Setting an interruptserviceroutinealso keyboard interruptrequest.Writingto the keyboardinterrupt writing alogic1tot Software maygeneratetheinte interrupt acknowledgesignalto register (KBSCR).TheA configure thepinasan c levelonakeyboardinte 1 mayoccurinanyorder. DEK clear,avectorfetc ere pollingispreferred. he ACKKbitinthekeyboa yboard interruptrequest. ifakeyboardinterrupt ACKK doesnotaffect t latchesanotherinte pins andrequiresoftwaretoclearthe yboard interruptpinsto CKK bitisusefulinapplicationsthatpoll rrupt pinisatl board interruptpin and thereturnof mask bit(IMASKK) request andtheMODEKbit,clearing rrupt exists.The interruptpinsar — Avectorfetc he followingactionsmustoccurto rrupt acknowle yboard statusand addressatlocations$FFDEand clear theinterruptrequest. can preventspuriousinterrupts falling edgethatoccursafter K, isclear,theCPUloads theACKKbitpriortoleaving inputandreadthedata ogic 0,thekeyboard rrupt pin,usethedata h orsoftwareclear pinstaysatlogic0. subsequent transitions rrupt request.Ifthe allenabledkeyboard rd statusandcontrol h generatesan e bothfallingedge- dge signalby is fallingedge- KEYF bitisnot logic 1.Aslongas which makesit 08AZ60 — Rev 1.1 Rev — 08AZ60 control register Keyboard Module (KBD) Keyboard Initialization

NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin.

23.5 Keyboard Initialization

When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. Therefore, a false interrupt can occur as soon as the pin is enabled.

To prevent a false interrupt on keyboard initialization:

1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register 3. Write to the ACKK bit in the keyboard status and control register

to clear any false interrupts 4. Clear the IMASKK bit.

An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load.

Another way to avoid a false interrupt:

1. Configure the keyboard pins as outputs by setting the appropriate DDRG bits in data direction register G. 2. Configure the keyboard pins as outputs by setting the appropriate DDRH bits in data direction register H. 3. Write logic 1s to the appropriate port G and port H data register bits. 4. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Keyboard Module (KBD) 379 ehia aaMC68HC Freescale Semiconductor KeyboardModule (KBD) 380 Technical Data 23.7 KeyboardModule 23.6.2 StopMode 23.6.1 WaitMode 23.6 Low-Power Modes Keyboard Module(KBD) interrupt requests brin to requests interrupt 381. has noeffect.See (ACKK) inthekeyboardstatusandcont BCFE bit.Withat To protecttheKEYFbitdur remains clearedwhentheM logic 1totheBCFEbit. To allowsoftwaretocleartheKEYF 149. bitsdu status clear to The BCFEbitinthebreak IMASKK bitinthekeyboar The keyboardmoduleremainsactive IMASKK bitinthekeyboar The keyboardmoduleremainsactive consumption standbymodes. The WAITandSTOPin During BreakInterrupts to bringtheMCU Keyboard StatusandControlRegister ring thebreakstate.See If KEYF is cleared durin cleared is IfKEYF logic0,writingtot structions putthe g theMCUoutofwaitmode. d statusandcontrolr d statusandcontrolr flag controlregister ing thebreakstate,wr CU exitsthebreakstate. out ofstopmode. bit duringabreakin instopmode.Clearingthe inwaitmode.Clearingthe rol registerduringthebreakstate MCU inlow-power- he keyboardacknowledgebit (BFCR) enablessoftware egister enableskeyboard egister enableskeyboard Break Module g thebreakstate,it ite alogic0tothe 08AZ60 — Rev 1.1 Rev — 08AZ60 terrupt, writea terrupt, on page on page Keyboard Module (KBD) I/O Registers

23.8 I/O Registers

The following registers control and monitor operation of the keyboard module:

• Keyboard status and control register (KBSCR) • Keyboard interrupt enable register (KBIER)

23.8.1 Keyboard Status and Control Register

The keyboard status and control register:

• Flags keyboard interrupt requests • Acknowledges keyboard interrupt requests • Masks keyboard interrupt requests • Controls keyboard interrupt triggering sensitivity

Address: $001A

Bit 7654321Bit 0

Read: 0000KEYF 0 IMASKK MODEK Write: ACKK

Reset:00000000

= Unimplemented Figure 23-3. Keyboard Status and Control Register (KBSCR)

Bits 7–4 — Not used These read-only bits always read as logic 0s.

KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Keyboard Module (KBD) 381 ehia aaMC68HC Freescale Semiconductor KeyboardModule (KBD) 382 Technical Data 23.8.2 KeyboardInte Keyboard Module(KBD) rrupt EnableRegister drs:$001B Address: KBIE4–KBIE0 —KeyboardInterruptEnable Bits and eachportHpintooperateas The keyboardinterruptenabl Tri MODEK —Keyboard IMASKK —KeyboardInterruptMaskBit ACKK —KeyboardAcknowledgeBit Reset:00000000 ed 0 0 0 Read: Write: interrupt enableregister. interrupt pintolatch Each oftheseread/writebits interrupt pins.ResetclearsMODEK. This read/writebit Writing alogic1toth request. ACKKalwaysreadsas Writing alogic1toth clears theIMASKKbit. keyboard interruptmaskfromgene Figure 23-4.KeyboardInterr 0 =Portpinnotenabled as 1 =Portpinenabledas 0 =Keyboardinterruptrequestsonfallingedgesonly 1 =Keyboardinterruptreques 0 =Keyboardinterruptrequestsnotmasked 1 =Keyboardinterruptrequestsmasked Bit 7654321Bit 0 = Unimplemented controls thetri is read/writebitprev is write-onlybitclears ggering SensitivityBit e registerenablesor keyboard interruptpin enables thecorres requests. Resetclearsthekeyboard BE BE BE BE KBIE0 KBIE1 KBIE2 KBIE3 KBIE4 keyboard interruptpin akeyboardinterruptpin. upt EnableRegister(KBIER) logic 0.Rese ggering sensitivity ts onfallingedgesandlowlevels rating interruptrequests.Reset ents theoutputof the keyboardinterrupt t clearsACKK. disableseachportG ponding keyboard of thekeyboard 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 24. Timer Interface Module A (TIMA)

24.1 Contents

24.2 Introduction...... 386 24.3 Features...... 386 24.4 Functional Description...... 389 24.4.1 TIMA Counter Prescaler...... 389 24.4.2 Input Capture ...... 389 24.4.3 Output Compare ...... 390 24.4.3.1 Unbuffered Output Compare...... 391 24.4.3.2 Buffered Output Compare...... 392 24.4.4 Pulse Width Modulation (PWM) ...... 393 24.4.4.1 Unbuffered PWM Signal Generation ...... 394

24.4.4.2 Buffered PWM Signal Generation...... 395 24.4.4.3 PWM Initialization ...... 397 24.5 Interrupts...... 398 24.6 Low-Power Modes ...... 399 24.6.1 Wait Mode ...... 399 24.6.2 Stop Mode ...... 399 24.7 TIMA During Break Interrupts ...... 399

24.8 I/O Signals ...... 400 24.8.1 TIMA Clock Pin (PTD6/ATD14/ TCLK)...... 400 24.8.2 TIMA Channel I/O Pins (PTF3–PTF0/TACH2 and PTE3/TACH1–PTE2/TACH0)400 24.9 I/O Registers ...... 401 24.9.1 TIMA Status and Control Register ...... 401 24.9.2 TIMA Counter Registers ...... 403 24.9.3 TIMA Counter Modulo Registers...... 404 24.9.4 TIMA Channel Status and Control Registers...... 405 24.9.5 TIMA Channel Registers ...... 411

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module A (TIMA) 385 ehia aaMC68HC Semiconductor Freescale (TIMA) A Module Interface Timer 386 Technical Data 24.3 Features 24.2 Introduction Timer InterfaceModuleA(TIMA) Features oft please consulttheHC08Time For furtherinformationregardingti block diagram output compare,andpulse-wid 6-channel timerthatprov This sectiondescribesthetimerinte • TIMA Counter Stop and ResetBits Stopand TIMA Counter • Toggle Any ChannelPinonOverflow • Free-Running orModuloUp-CountOperation • Programmable TIMAClockInput • Buffered andUnbufferedPulse • Six InputCapture/Ou • External TIMAClockInput – 7-Frequency InternalBusClockPrescalerSelection – Generation Set, Clear,orToggle – Rising-Edge, Falling- – he TIMAinclude: of theTIMA. ides atimingreferenc tput CompareChannels r ReferenceManual,TIM08RM/AD. Edge, orAny-EdgeI th-modulation functions. Output CompareAction mers onM68HC08familydevices, rface module(TIMA).TheTIMAisa (4-MHzMaximumFrequency) Width Modulation(PWM)Signal e withinputcapture, nput CaptureTrigger Figure 24-1 08AZ60 — Rev 1.1 Rev — 08AZ60 is a isa Timer Interface Module A (TIMA) Features

TCLK PTD6/ATD14/TACLK INTERNAL PRESCALER SELECT BUS CLOCK PRESCALER

TSTOP PS2 PS1 PS0 TRST

16-BIT COUNTER TOF INTER- RUPT TOIE LOGIC 16-BIT COMPARATOR TMODH:TMODL

CHANNEL 0 ELS0B ELS0A TOV0 16-BIT COMPARATOR CH0MAX PTE2 PTE2/TACH0 LOGIC TCH0H:TCH0L CH0F INTER- 16-BIT LATCH RUPT CH0IE LOGIC MS0A MS0B CHANNEL 1 ELS1B ELS1A TOV1 16-BIT COMPARATOR CH1MAX PTE3 PTE3/TACH1 LOGIC TCH1H:TCH1L CH1F INTER- 16-BIT LATCH RUPT LOGIC MS1A CH1IE

CHANNEL 2 ELS2B ELS2A TOV2 16-BIT COMPARATOR CH2MAX PTF0 PTF0/TACH2 LOGIC TCH2H:TCH2L CH2F INTER- 16-BIT LATCH RUPT CH2IE LOGIC MS2A MS2B CHANNEL 3 ELS3B ELS3A TOV3 16-BIT COMPARATOR CH3MAX PTF1 PTF1/TACH3 LOGIC TCH3H:TCH3L CH3F INTER- 16-BIT LATCH RUPT LOGIC MS3A CH3IE

CHANNEL 4 ELS4B ELS4A TOV4 16-BIT COMPARATOR CH5MAX PTF2 PTF2 LOGIC TCH4H:TCH4L CH4F INTER- 16-BIT LATCH RUPT CH4IE LOGIC MS4A MS4B CHANNEL 5 ELS5B ELS5A TOV5 16-BIT COMPARATOR CH5MAX PTF3 PTF3 LOGIC TCH5H:TCH5L CH5F INTER- 16-BIT LATCH RUPT LOGIC MS5A CH5IE

Figure 24-1. TIMA Block Diagram

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module A (TIMA) 387 ehia aaMC68HC Semiconductor Freescale (TIMA) A Module Interface Timer 388 Technical Data Timer InterfaceModuleA(TIMA) 03 IAC.5Rgse ih(AHH i 51 31 11 Bit 8 9 10 Bit 8 11 9 12 10 Bit 8 13 11 9 Bit7 14 12 10 Bit 8 TIMACh.5RegisterLow(TACH5L) Bit15 13 TIMACh. 5 RegisterHigh(TACH5H) 11 9 $0037 Bit7 14 12 10 Bit 8 TIMACh.4RegisterLow(TACH4L) $0036 TIMACh.5Status/Control Register Bit15 13 TIMACh. 4 RegisterHigh(TACH4H) $0035 11 9 $0034 Bit7 14 12 10 Bit 8 TIMACh.3RegisterLow(TACH3L) $0033 TIMACh.4Status/Control Register(T Bit15 13 TIMACh.3RegisterHigh(TACH3H) $0032 9 11 $0031 Bit7 14 12 10 TIMACh. 2RegisterLow(TACH2L) $0030 TIMACh.3Status/Control Register Bit15 13 $002F 11 TIMACh. 2RegisterHigh(TACH2H) Bit 8 $002E Bit7 14 12 9 TIMACh. 1RegisterLow(TACH1L) $002D TIMACh.2Status/Control Register(T Bit15 13 $002C TIMACh.1RegisterHigh(TACH1H) 10 $002B Bit7 14 11 R TIMACh.0RegisterLow(TACH0L) $002A PS0 TIMACh.1Status/Control Register Bit15 12 TIMACh.0RegisterHigh(TACH0H) $0029 R PS1 $0028 Reserved 13 PS2 $0027 TIMACh.0Status/Control Register(T Bit7 14 0 $0026 TIMACounter ModuloReg.Low(TAMODL) Bit7 Bit15 $0025 TRST TIMACounter RegisterLow(TACNTL) TIMACounter ModuloReg.High(TAMODH) TSTOP $0024 TOIE TIMACounterRegisterHigh(T $0023 TOF $0022 TIMAStatus/Control Register(TASC) $0021 $0020 Addr. Register Name Bit 7654321Bit 0 Figure 24-2.TIMAI/ TS5 HFC5E0M5 L5 L5 O5CH5MAX TOV5 ELS5A ELS5B MS5A 0 CH5IE CH5F CH3MAX (TASC5) TOV3 ELS3A ELS3B MS3A 0 CH3IE CH3F CH1MAX (TASC3) TOV1 ELS1A ELS1B MS1A 0 CH1IE CH1F (TASC1) CT)Bt1 41 21 09Bit 8 9 10 11 12 13 14 Bit15 ACNTH) S4 HFC4EM4 SAESBESATV CH4MAX TOV4 ELS4A ELS4B MS4A MS4B CH4IE CH4F ASC4) CH2MAX TOV2 ELS2A ELS2B MS2A MS2B CH2IE CH2F ASC2) CH0MAX TOV0 ELS0A ELS0B MS0A MS0B CH0IE CH0F ASC0) R= Reserved O RegisterSummary 654321Bit654321Bit 0 654321Bit 0 654321Bit 0 654321Bit 0 654321Bit 0 654321Bit654321Bit 0 0 0 RRRRRR 08AZ60 — Rev 1.1 Rev — 08AZ60 Timer Interface Module A (TIMA) Functional Description

24.4 Functional Description

Figure 24-1 shows the TIMA structure. The central component of the TIMA is the 16-bit TIMA counter that can operate as a free-running counter or a modulo up-counter. The TIMA counter provides the timing reference for the input capture and output compare functions. The TIMA counter modulo registers, TAMODH–TAMODL, control the modulo value of the TIMA counter. Software can read the TIMA counter value at any time without affecting the counting sequence.

The six TIMA channels are programmable independently as input capture or output compare channels.

24.4.1 TIMA Counter Prescaler

The TIMA clock source can be one of the seven prescaler outputs or the TIMA clock pin, PTD6/ATD14/TACLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIMA status and control register select the TIMA clock source.

24.4.2 Input Capture

An input capture function has three basic parts: edge select logic, an input capture latch, and a 16-bit counter. Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined transition. The polarity of the active edge is programmable. The level transition which triggers the counter transfer is defined by the corresponding input edge bits (ELSxB and ELSxA in TASC0 through TASC5 control registers with x referring to the active channel number). When an active edge occurs on the pin of an input capture channel, the TIMA latches the contents of the TIMA counter into the TIMA channel registers, TACHxH–TACHxL. Input captures can generate TIMA CPU interrupt requests. Software can determine that an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module A (TIMA) 389 ehia aaMC68HC Semiconductor Freescale (TIMA) A Module Interface Timer 390 Technical Data Timer InterfaceModuleA(TIMA) 24.4.3 OutputCompare reference. Inthiscase captured. Tomeasureapulsewidth, measure aperiod,two software candeterminetheperiodand/or By recordingthetime same pin;otherwise, event. However,thismustbedonepr respond tothiseventat register 2buscyclesafte time oftheevent.Becausethisvalu generated ifenabled.T registers) issetorclea whether theTIMAchannelfl Registers status andcontrolregist The free-runningc Channel Registers edge occurred.Anumberco (edge), usetheinputcapturefunction signal aspecifiednumber with anoutputcomparefunction.Fo Another usefortheinput counter toextenditsrange. captured. Softwareshouldtrackt counter reachesthevalue inther pulse withaprogr With theoutputcomparefunction, (TACHxH–TACHxL). Reset doesnotaffectthecontentsof latencies. software delay canbecontrolledtothereso output comparesarerefe this capturedvalueandstoredto on page411),eachpropersi ammable polarity,duration, ounter contentsaretransfe on page411).Becausebothinputcapturesand s forsuccessiveedgesonanincomingsignal, the previoustimeva , aninputcapturefunction r. Whenthestatusflagis successive edgesoft he valueofthecountlatc a latertimeanddetermine er (TACHxH– capturefunctionis r theactualev renced tothesame16-bitmodulocounter, of clockcyclesafterdet rresponding tothedesir ag (CH0F–CH5FinTASC0–TASC5 egisters ofanoutput an outputcompareregister(see he overflowsatthe16-bitmodule theTIMAcan lution ofthecounterindependent e isstoredintheinputcapture r example,toactivateanoutput twoalternatepol ior toanotherinput the inputcapture TACHxL, see to recordthetimeatwhich ent occurs,usersoftwarecan pulsewidthof lue willbelost. gnal transitionregardlessof to establishatime he samepolarityare andfrequency.When the rred totheTIMAchannel hed or“captured”isthe set, aCPUinterruptis isusedinconjunction generate aperiodic ecting aninputevent the actualtimeof ed delayisaddedto TIMA Channel comparechannel, arity edgesare channel register 08AZ60 — Rev 1.1 Rev — 08AZ60 captureonthe the signal.To TIMA Timer Interface Module A (TIMA) Functional Description

the TIMA can set, clear, or toggle the channel pin. Output compares can generate TIMA CPU interrupt requests.

24.4.3.1 Unbuffered Output Compare

Any output compare channel can generate unbuffered output compare pulses as described in Output Compare on page 390. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIMA channel registers.

An unsynchronized write to the TIMA channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIMA overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIMA may pass the new value before it is written.

Use the following methods to synchronize unbuffered changes in the

output compare value on channel x:

• When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. • When changing to a larger output compare value, enable TIMA overflow interrupts and write the new value in the TIMA overflow interrupt routine. The TIMA overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module A (TIMA) 391 ehia aaMC68HC Semiconductor Freescale (TIMA) A Module Interface Timer 392 Technical Data 24.4.3.2 BufferedOutputCompare Timer InterfaceModuleA(TIMA) channel whoseoutputappearsonthe Channels 4and5canbelinkedto general-purpose I/Opin. MS2B bitisset,thechannel3pin, TIMA channel3statusandcontrolregi TASC2 controlsandmonitorsthebuf registers (2or3)that TIMA overflows.Ateachsubseque TIMA channel3registerstosynchr PTF0/TACH2 pin.Writin TIMA channel2regist (TASC2) linkschannel2 Setting theMS2BbitinTIMAchanne channel registersofth channel whoseoutputappe Channels 2and3canbelinkedto general-purpose I/Opin. MS0B bitisset,thechannel1pin, TIMA channel1statusandcontrolregi TASC0 controlsandmonitorsthebuf registers (0or1)that TIMA overflows.Ateachsubseque TIMA channel1registerstosynchr PTE2/TACH0 pin.WritingtotheTI TIMA channel0regist (TASC0) linkschannel0 Setting theMS0BbitinTIMAchanne channel registersofth channel whoseoutputappe Channels 0and1canbelinkedto (TSC4) linkschannel4 and Setting theMS4Bbitin TIMAchanne registers ofthelin ked pairalternatel controltheoutputaret controltheoutputaret ers initiallycontrolstheoutputon ers initiallycontrolstheoutputon e linkedpairalternatel e linkedpairalternatel g totheTIMAchannel and channel3.Theoutput and channel1.Theoutput channel 5.Theoutput ars onthePTF0/TACH ars onthePTE2/TACH PTF1/TACH3,isavailableasa PTE3/TACH1,isavailableasa MA channel1registersenablesthe form abuffered form abuffered form abuffered onously controltheoutputafter onously controltheoutputafter nt overflow,theTIMAchannel nt overflow,theTIMAchannel y controltheoutput. fered outputcompar fered outputcompar l 2statusandcontrolregister l 0statusandcontrolregister l 4statusandcontrolregister ster (TASC3)isunused.Whilethe ster (TASC1)isunused.Whilethe PTF2 pin.The he oneswrittentolast. he oneswrittentolast. y controltheoutput. y controltheoutput. 3 registersenablesthe compare valueinthe compare valueinthe compare valueinthe 2 pin.TheTIMA output compare output compare 0 pin.TheTIMA output compare TIMA channel 08AZ60 — Rev 1.1 Rev — 08AZ60 e function,and e function,and Timer Interface Module A (TIMA) Functional Description

TIMA channel 4 registers initially controls the output on the PTF2 pin. Writing to the TIMA channel 5 registers enables the TIMA channel 5 registers to synchronously control the output after the TIMA overflows. At each subsequent overflow, the TIMA channel registers (4 or 5) that control the output are the ones written to last. TASC4 controls and monitors the buffered output compare function, and TIMA channel 5 status and control register (TASC5) is unused. While the MS4B bit is set, the channel 5 pin, PTF3, is available as a general-purpose I/O pin.

NOTE: In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares.

24.4.4 Pulse Width Modulation (PWM)

By using the toggle-on-overflow feature with an output compare channel, the TIMA can generate a PWM signal. The value in the TIMA counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIMA counter modulo registers. The time between overflows is the period of the PWM signal.

As Figure 24-3 shows, the output compare value in the TIMA channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIMA to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIMA to set the pin if the state of the PWM pulse is logic 0.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module A (TIMA) 393 ehia aaMC68HC Semiconductor Freescale (TIMA) A Module Interface Timer 394 Technical Data 24.4.4.1 Unbuffered Timer InterfaceModuleA(TIMA) PWM SignalGeneration 256 increments.Writing routine towriteanew, compare duringthatPWM the oldvaluebut periods. Forexample,writingane pulse widthvaluecoul An unsynchronizedwritetothe registers. new pulsewidthvalueov are unbufferedbecausechangingthepul described in Any outputcomparechannelcan produces adutycycl the PWMoutput.Thepuls The valueintheTIMAchannelregist value is$000(see period of256timesthein $00FF (255)totheTIMA frequency ofan8-bitPWMsignalisva prescaler outputdeterminesthe The valueintheTIMAcounterm PTEx/TCHx VRLWOEFO OVERFLOW OVERFLOW OVERFLOW Pulse WidthModulation(PWM) Figure 24-3.PWMPeri after thecounterreaches WIDTH PULSE TIMA Statusand PERIOD e of128/256or50%. smaller pulsewidthval d causeincorrectoperat COMPARE OUTPUT $0080 (128)totheTIMA countermoduloregi er thevaluecurrently ternal busclockperiodif e widthofan8-bitPWM period. Also,usingaTI TIMA channelregisterstochangea frequency ofthePWMoutput.The odulo registersand generate unbufferedPWMpulsesas w valuebeforethe ers determinesthepulsewidthof od andPulseWidth Control Register riable in256 se widthrequire the newvaluepreventsany COMPARE ue maycausethecompare OUTPUT sters producesaPWM on page393.Thepulses intheTIMAchannel ion foruptotwoPWM channelregisters MA overflowinterrupt theprescalerselect signal isvariablein theselected crements. Writing counter reaches 08AZ60 — Rev 1.1 Rev — 08AZ60 on page401). s writingthe COMPARE OUTPUT Timer Interface Module A (TIMA) Functional Description

to be missed. The TIMA may pass the new value before it is written to the TIMA channel registers.

Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x:

• When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. • When changing to a longer pulse width, enable TIMA overflow interrupts and write the new value in the TIMA overflow interrupt routine. The TIMA overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period.

NOTE: In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0%

duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.

24.4.4.2 Buffered PWM Signal Generation

Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the PTE2/TACH0 pin. The TIMA channel registers of the linked pair alternately control the pulse width of the output.

Setting the MS0B bit in TIMA channel 0 status and control register (TASC0) links channel 0 and channel 1. The TIMA channel 0 registers initially control the pulse width on the PTE2/TACH0 pin. Writing to the TIMA channel 1 registers enables the TIMA channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIMA channel registers (0 or 1) that control the pulse width are the ones written to last. TASC0 controls and monitors the buffered PWM function, and TIMA channel 1

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module A (TIMA) 395 ehia aaMC68HC Semiconductor Freescale (TIMA) A Module Interface Timer 396 Technical Data Timer InterfaceModuleA(TIMA) NOTE: the channel5pin,P status andcontrolregister(TASC5)is to thecurrentlyactive In bufferedPWMsignalgener controls andmonitorsthebuffer 5) thatcontrolthepul period. Ateachsubsequentoverflow, synchronously controlthepulsewidth channel 5registersena TIMA channel3regist initially controlthepulsewidthon (TASC2) linkschannel Setting theMS2BbitinTIMAchanne the linkedpairalternatelycontro output appearsonthe Channels 2and3canbe pin. the channel1pin,PTE3/TACH1,is status andcontrolregister(TASC1)is generating unbuffer channel. Writingtothe activec currently activechanneltoprevent (TASC4) linkschannel Setting theMS4BbitinTIMAchanne linked pairalternatel output appearsonth Channels 4and5canbe pin. the channel3pin,PTF1/ status andcontrolregister(TASC3)is 3) thatcontrolthepul period. Ateachsubsequentoverflow, synchronously controlthepulsewidth initially controlthepul controls andmonitorsthebuffer ed PWMsignals. TF3, isavailableas y controlthepulse e PTF2pin.TheTIMAch se widtharetheones se widtharetheones se widthonthePTF2 channel registers.Userso ers enablestheTIMA PTF0/TACH2 pin.TheTIMA 2 andchannel3. 4 andchannel5. bles theTIMAcha TACH3, isavailable linked toformabufferedPWMchannelwhose linked toformabufferedPWMchannelwhose ation, donotwritenewpulsewidthvalues hannel registersis ed PWMfunction,and ed PWMfunction,and l thepulsewidthofoutput. the PTF0/TACH2pin. writing anewvaluetotheactive available asageneral-purposeI/O unused.WhiletheMS4Bbitisset, unused.WhiletheMS0Bbitisset, unused.WhiletheMS2Bbitisset, l 2statusandcontrolregister l 4statusandcontrolregister at thebeginningofnextPWM at thebeginningofnextPWM the TIMAchannelregisters(4or the TIMAchannelregisters(2or width oftheoutput. a general-purposeI/Opin. The TIMAchannel2registers The TIMAchannel4registers nnel 5registersto

written tolast.TASC4 written tolast.TASC2 pin. WritingtotheTIMA channel 3regi as ageneral-purposeI/O annel registersofthe ftware shouldtrackthe thesameas channelregistersof TIMA channel5 TIMA channel3 08AZ60 — Rev 1.1 Rev — 08AZ60 Writing tothe Writing sters to Timer Interface Module A (TIMA) Functional Description

24.4.4.3 PWM Initialization

To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure:

1. In the TIMA status and control register (TASC): a. Stop the TIMA counter by setting the TIMA stop bit, TSTOP. b. Reset the TIMA counter and prescaler by setting the TIMA reset bit, TRST. 2. In the TIMA counter modulo registers (TAMODH–TAMODL), write the value for the required PWM period. 3. In the TIMA channel x registers (TACHxH–TACHxL), write the value for the required pulse width. 4. In TIMA channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB–MSxA. (See Table 24-2).

b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB–ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 24-2.)

NOTE: In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.

5. In the TIMA status control register (TASC), clear the TIMA stop bit, TSTOP.

Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIMA channel 0 registers (TACH0H–TACH0L) initially control the buffered PWM output. TIMA status control register 0

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module A (TIMA) 397 ehia aaMC68HC Semiconductor Freescale (TIMA) A Module Interface Timer 398 Technical Data 24.5 Interrupts Timer InterfaceModuleA(TIMA) The followingTIMAsourcescan Status andCont TOVx bitgeneratesa100% Setting thechannelxmaximumduty output. a stateitisalreadyin Clearing thetoggle-on-overflowbit, channels. MS4Btakespr (TASC4) controlsandmonitors buff initially controlthe PWM operation.TheTIMAchannel Setting MS4Blinkschann channels. MS2Btakespr (TASC2) controlsandmonitors buff initially controlthe PWM operation.TheTIMAchannel Setting MS2Blinkschann channels. MS0Btakespr (TASC0) controlsandmonitors TIMA overflows.Subsequen TIMA channelflags(CH5F–CH0F) • TIMA overflowflag(TOF)—TheTO • interrupt enablebit,CHxIE. CPUinterruptr TIMA input captureoroutputcompar TOIE areintheTIMAst TOIE, enablesTIMAoverflowCP counter moduloregisters.TheTIMA counter valuereachesthemodulo rol Registers andhavenoeffect.Theresu ered PWM output. TIMA st ered PWM output. TIMA st iority overMS4A. iority overMS2A. iority overMS0A. els 4and5configur els 2and3configur equests arecontrolled dutycycleoutput.(See t outputcomparestryto atus andcontrolregister. the PWMsignalfr the PWMsignalfr the PWMsignalfr on page405). generate interruptrequests: TOVx,inhibits 4 registers(TACH4H–TACH4L) 2 registers(TACH2H–TACH2L) cycle bit(CHxMAX)andsettingthe e occursonchannelx.Channelx U interruptr —TheCHxFbitissetwhenan value programmedintheTIMA overflow interruptenablebit, F bitissetwhentheTIMA atus controlregister4 atus controlregister2 om thelinked om thelinked om thelinked es themforbuffered es themforbuffered by thechannelx output toggleson lt isa0%dutycycle equests. TOFand forcetheoutputto TIMA Channel 08AZ60 — Rev 1.1 Rev — 08AZ60 Timer Interface Module A (TIMA) Low-Power Modes

24.6 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power- consumption standby modes.

24.6.1 Wait Mode

The TIMA remains active after the execution of a WAIT instruction. In wait mode, the TIMA registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIMA can bring the MCU out of wait mode.

If TIMA functions are not required during wait mode, reduce power consumption by stopping the TIMA before executing the WAIT instruction.

24.6.2 Stop Mode

The TIMA is inactive after the execution of a STOP instruction. The

STOP instruction does not affect register conditions or the state of the TIMA counter. TIMA operation resumes when the MCU exits stop mode.

24.7 TIMA During Break Interrupts

A break interrupt stops the TIMA counter and inhibits input captures.

The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See SIM Break Flag Control Register on page 119).

To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state.

To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module A (TIMA) 399

24.8.2 TIMAChannelI/ ehia aaMC68HC Semiconductor Freescale (TIMA) A Module Interface Timer 400 Technical Data TCLK) 24.8.1 TIMAClock 24.8 I/OSignals Timer InterfaceModuleA(TIMA) Pin (PTD6/ATD14/ capture pinoranout Each channelI/Opinisprogr of thestate PTD6/ATD14/TACLK pinist channel whennotused PTD6/ATD14/TACLK isavailableas The maximumTCLKfrequencyisthe Register prescaler selectbits,PS[2:0].(See Select thePTD6/ATD14/TACLK source fortheTIMAcount PTD6/ATD14/TACLK isan PTF0/TACH2, PTF1/TACH PTD6/ATD14/TACLK isanex with theTIMAandportFshares Port Dsharesoneofitspinswiththe status bitshavea2-st I/O registersduringthebreakstatewi The sixTIMAchannelI/Opins the firststeponsuchabitbefore second stepclears the breakstateas O Pins(PTF3–PTF0/TACH2and .) TheminimumTCLK DDRD6 bitindatadi long asBCFEisatlogic0. the statusbit. put comparepin.PTE2/T ep read/writeclearingproced astheTIMAcl bus frequency ------er insteadofthepresca 3, PTF2,andPTF3. external clockinput he TIMAclockinput,it ammable independently ternal clockinputto are PTE2/TACH0,PTE3/TACH1, pulsewidth,TCLK

1 the break,bitcannotchangeduring input bywritinglogi four ofitspins ------t ------PTE3/TACH1–PTE2/TACH0) TIMA Status ageneral-purpose TIMA. PortEsharestwoofitspins least: 4MHzor thout affecting status bits. Some Some statusbits. affecting thout ock input.Whenthe rection registerD. + SU Afterthebreak,doing ACH0, PTE6/TACH2, and ACH0, PTE6/TACH2, and withtheTIMA. that canbetheclock and Control led internalbusclock. theTIMAprescaler. is aninputregardless LMIN ure. Ifsoftwaredoes c 1stothethree busfrequency asaninput orTCLK 08AZ60 — Rev 1.1 Rev — 08AZ60 I/O pinorADC HMIN , is: ÷ 2. Timer Interface Module A (TIMA) I/O Registers

PTF2 can be configured as buffered output compare or buffered PWM pins.

24.9 I/O Registers

These I/O registers control and monitor TIMA operation:

• TIMA status and control register (TASC) • TIMA control registers (TACNTH–TACNTL) • TIMA counter modulo registers (TAMODH–TAMODL) • TIMA channel status and control registers (TASC0, TASC1, TASC2, TASC3, TASC4, and TSAC5) • TIMA channel registers (TACH0H–TACH0L, TACH1H–TACH1L, TACH2H–TACH2L, TACH3H–TACH3L, TACH4H–TACH4L, and TACH5H–TACH5L)

24.9.1 TIMA Status and Control Register

The TIMA status and control register:

• Enables TIMA overflow interrupts • Flags TIMA overflows • Stops the TIMA counter • Resets the TIMA counter • Prescales the TIMA counter clock

Address: $0020 Bit 7654321Bit 0 Read: TOF 00 TOIE TSTOP PS2 PS1 PS0 Write: 0 TRST R Reset:00100000 R= Reserved Figure 24-4. TIMA Status and Control Register (TASC)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module A (TIMA) 401 ehia aaMC68HC Semiconductor Freescale (TIMA) A Module Interface Timer 402 Technical Data Timer InterfaceModuleA(TIMA) NOTE: TOIE — TIMA Overflow TOIE —TIMA required toexitwaitmode.Also, Do notsettheTSTOPbitbeforeenter TSTOP —TIMAStopBit TOF —TIMAOverflowFlagBit capture modeisenabled,inputcaptur TRST — TIMA Reset Bit —TIMAReset TRST cleared. 1 toTOFhasnoeffect. inadvertent clearingofTOF.Reset effect. Therefore,aTOFinterrupt counter untilsoftware TSTOP iscleared.Resetsetst This read/writebitstop becomes set.Resetcl This read/writebitenables the clearingsequenceisco then writingalogic0to by readingtheTIMAstatusandcontrolregisterwhenTOFisset value programmedint This read/writeflagisse the TIMAcounterisre Counting resumesfrom$0000 prescaler. SettingTRSThasnoef Setting thiswrite-onlybitresets the TRSTbit. 1 =TIMAcounterha 0 =TIMAcounterhasnot 0 =TIMAcounteractive 1 =TIMAcounterstopped 0 =TIMAoverflowinterruptsdisabled 1 =TIMAoverflowinterruptsenabled 0 =Noeffect 1 =PrescalerandTIMA countercleared InterruptEnableBit clears theTSTOPbit. ears the TOIE bit. TOIE the ears set andalwaysreadsas he TIMAcountermodulo s theTIMAcounter. TOF.IfanotherTIMA s reachedmodulovalue. t whentheTIMAcounte TIMA overflowinterr mplete, thenwritingl reachedmodulovalue. when theTSTOPbit . TRSTiscleared he TSTOPbit,stoppingtheTIMA the TIMA counte TIMA the requestcannotbelostdueto fect onanyotherregisters. clears theTOFbit. es areinhibited ing wait mode if the TIMA is is TIMA the if mode ing wait Counting resumeswhen overflow occursbefore upts whentheTOFbit logic 0.Resetclears r reachesthemodulo ogic 0toTOFhasno registers. ClearTOF r andtheTIMA automatically after is setandinput until TSTOPis 08AZ60 — Rev 1.1 Rev — 08AZ60 Writing alogic Writing Timer Interface Module A (TIMA) I/O Registers

NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIMA counter at a value of $0000.

PS[2:0] — Prescaler Select Bits These read/write bits select either the PTD6/ATD14/TACLK pin or one of the seven prescaler outputs as the input to the TIMA counter as Table 24-1 shows. Reset clears the PS[2:0] bits.

Table 24-1. Prescaler Selection

PS[2:0] TIMA Clock Source 000 Internal Bus Clock ÷1 001 Internal Bus Clock ÷ 2 010 Internal Bus Clock ÷ 4 011 Internal Bus Clock ÷ 8 100 Internal Bus Clock ÷ 16 101 Internal Bus Clock ÷ 32 110 Internal Bus Clock ÷ 64

111 PTD6/ATD14/TACLK

24.9.2 TIMA Counter Registers

The two read-only TIMA counter registers contain the high and low bytes of the value in the TIMA counter. Reading the high byte (TACNTH) latches the contents of the low byte (TACNTL) into a buffer. Subsequent reads of TACNTH do not affect the latched TACNTL value until TACNTL is read. Reset clears the TIMA counter registers. Setting the TIMA reset bit (TRST) also clears the TIMA counter registers.

NOTE: If TACNTH is read during a break interrupt, be sure to unlatch TACNTL by reading TACNTL before exiting the break interrupt. Otherwise, TACNTL retains the value latched during the break.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module A (TIMA) 403 ehia aaMC68HC Semiconductor Freescale (TIMA) A Module Interface Timer 404 Technical Data 24.9.3 TIMACounterModuloRegisters Timer InterfaceModuleA(TIMA) (TAMODH) inhibitstheTO counting from$0000att overflow flag(TOF)bec TIMA counter.Whenthecounter The read/writeTIMAmodulo (TAMODL) iswritten.Resetsets Reset:00000000Reset:00000000 Read: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 8 BIT BIT7 BIT9 Read: BIT10 BIT11 BIT12 BIT13 BIT14 BIT15 Read: Write:RRRRRRRRWrite:RRRRRRRR eitrNm n drs TCNTL —$0023 Register NameandAddress TCNTH —$0022 Register NameandAddress Figure 24-5.TIMACounter Bit 7654321BitBit 7654321Bit 0 0 R = Reserved omes set,an he nexttimerclock.Wr F bitandoverflowinterr registers containthe Registers (TCNTHandTCNTL) the TIMAcounter d theTIMAcounterresumes reachesthem iting tothehighbyte upts untilthelowbyte modulo valueforthe modulo registers. odulo value,the 08AZ60 — Rev 1.1 Rev — 08AZ60 Timer Interface Module A (TIMA) I/O Registers

Register Name and Address TAMODH — $0024

Bit 7654321Bit 0

Read: BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 Write:

Reset:11111111

Register Name and Address TAMODL — $0025

Bit 7654321Bit 0

Read: BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Write:

Reset:11111111 Figure 24-6. TIMA Counter Modulo Registers (TAMODH and TAMODL)

NOTE: Reset the TIMA counter before writing to the TIMA counter modulo registers.

24.9.4 TIMA Channel Status and Control Registers

Each of the TIMA channel status and control registers:

• Flags input captures and output compares • Enables input capture and output compare interrupts • Selects input capture, output compare, or PWM operation • Selects high, low, or toggling output on output compare • Selects rising edge, falling edge, or any edge as the active input capture trigger • Selects output toggling on TIMA overflow • Selects 0% and 100% PWM duty cycle • Selects buffered or unbuffered output compare/PWM operation

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module A (TIMA) 405 ehia aaMC68HC Semiconductor Freescale (TIMA) A Module Interface Timer 406 Technical Data Timer InterfaceModuleA(TIMA) Reset:00000000Reset:00000000 ed CH1F Read: CH0F Read: rt:0R 0 Write: 0 Write: Register Name and Address TASC1 —$0029 TASC1 Register NameandAddress —$0026 TASC0 Register NameandAddress Bit 7654321BitBit 7654321Bit 0 0 R= Reserved and ControlRegi CH1IE CH0MAX TOV0 ELS0A ELS0B MS0A MS0B CH0IE Figure 24-7.TI 0 sters (TACC0–TASC5) MA ChannelStatus SAESBESATV CH1MAX TOV1 ELS1A ELS1B MS1A 08AZ60 — Rev 1.1 Rev — 08AZ60 Timer Interface Module A (TIMA) I/O Registers

Register Name and Address TASC2 — $002C

Bit 7654321Bit 0

Read: CH2F CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX Write: 0

Reset:00000000

Register Name and Address TASC3 — $002F

Bit 7654321Bit 0

Read: CH3F 0 CH3IE MS3A ELS3B ELS3A TOV3 CH3MAX Write: 0 R

Reset:00000000

Register Name and Address TASC4 — $0032

Bit 7654321Bit 0

Read: CH4F

CH4IE MS4B MS4A ELS4B ELS4A TOV4 CH4MAX Write: 0

Reset:00000000

Register Name and Address TASC5 — $0035

Bit 7654321Bit 0

Read: CH5F 0 CH5IE MS5A ELS5B ELS5A TOV5 CH5MAX Write: 0 R

Reset:00000000

R = Reserved Figure 24-7. TIMA Channel Status and Control Registers (TACC0–TASC5) (Continued)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module A (TIMA) 407 ehia aaMC68HC Semiconductor Freescale (TIMA) A Module Interface Timer 408 Technical Data Timer InterfaceModuleA(TIMA) MSxB —ModeSelectBitB CHxIE —ChannelxIn CHxF —Chann Reset clearstheMSxBbit. reverts TACH5pinto Setting MS4Bdisablesthechannel reverts TACH3pinto Setting MS2Bdisablesthechannel reverts TACH1pinto Setting MS0Bdisablesthechannel channel 4statusand MSxB existsonlyintheTIMAc This read/writebitsele Reset clearstheCHxIEbit. This read/writebitenabl Reset clearstheCHxFbit. interrupt requestcannotbelostdue complete, thenwritingl another interruptrequestoccurs control registerwithCHxFset,a When CHxIE=1,clearCHxFbyre counter registersmatche an outputcomparechannel,CHxFis when anactiveedgeoccursonthe When channelxisaninpu 0 =Bufferedoutputcompar 1 =Bufferedoutputcom 0 =ChannelxCPUinterr 1 =ChannelxCPUinte 0 =Noinputcaptureor 1 =Inputcaptureorout el xFlagBit terrupt EnableBit general-purposeI/O. general-purposeI/O. general-purposeI/O. control registers. cts bufferedoutputco ogic 0toCHxFhasno es TIMACPUinterruptsonchannelx. s thevalueinTI put compareonchannelx Writingalogic1to rrupt requestsenabled output compareonchannelx t capturechannel,this pare/PWM operationenabled upt requestsdisabled e/PWM operationdisabled hannel 0,TIMAchannel2,and nd thenwritingalogi before theclearingsequenceis ading TIMAchannelxstatusand channel xpin.Whenis 5 statusandcontrolregister 3 statusandcontrolregister 1 statusandcontrolregister to inadvertent set whenthevalueinTIMA mpare/PWM operation. MA channelxregisters. CHxFhasnoeffect. effect. Therefore,an read/write bitisset clearing ofCHxF. 08AZ60 — Rev 1.1 Rev — 08AZ60 c 0toCHxF.If Timer Interface Module A (TIMA) I/O Registers

MSxA — Mode Select Bit A When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 24-2. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin once PWM, output compare mode, or input capture mode is enabled. See Table 24-2. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high

NOTE: Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIMA status and control register (TSC).

ELSxB and ELSxA — Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x.

When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to port E or port F, and pin PTEx/TACHx or pin PTFx/TACHx is available as a general-purpose I/O pin. However, channel x is at a state determined by these bits and becomes transparent to the respective pin when PWM, input capture mode, or output compare operation mode is enabled. Table 24-2 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module A (TIMA) 409 ehia aaMC68HC Semiconductor Freescale (TIMA) A Module Interface Timer 410 Technical Data Timer InterfaceModuleA(TIMA) NOTE: NOTE: channel xoutputcompareifbot When TOVxisset,aTIMAcounter TOVx —Toggle-On-OverflowBit least twobusclocks. make surethatthePTEx Before enablingaTIMA SBMx Lx:Lx oeConfiguration Mode ELSxB:ELSxA MSxB:MSxA effect. Reset clear effect. Reset overflows. Whenchannelxisani controls thebehaviorofchannel When channelxisanoutputcompar 0 =Channelxpindoesnottoggl 1 =ChannelxpintogglesonTIMAcounteroverflow. 100 X1 000 X0 X0 Buffered 01 1X 1X 11 Set Output on Compare on Output Set Compare on Output Clear 11 10 1X 1X 00 11 Capture on Rising or Falling CaptureonRising Edge CaptureonFalling EdgeOnly 01 11 10 01 01 00 00 00 01 11 Set Output on Compare on Output Set Compare on Output Clear 11 10 01 01 Table Edge, 24-2.Mode, s theTOVxbit. channel registerforinputcaptureoperation, /TACHx pinorPTFx/TACH or Bufferedor Compare Compare Compare or PWM or Capture h occuratthesametime. Output Output Output Preset Output Output PWM Input overflowtakesprecedenceovera nput capturechannel,TOVxhasno andLevel Selection e onTIMAcounteroverflow. xoutputwhentheTIMAcounter e channel,thisread/writebit Pin under PortControl; Capture onEdge Rising Only Pin under PortControl; Toggle Compare on Output Toggle Compare on Output Output LevelLow Initialize Timer Output LevelHigh Initialize Timer x pinisstableforat 08AZ60 — Rev 1.1 Rev — 08AZ60 Timer Interface Module A (TIMA) I/O Registers

CHxMAX — Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 24-8 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.

OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW

PERIOD

PTEx/TCHx

OUTPUT OUTPUT OUTPUT OUTPUT COMPARE COMPARE COMPARE COMPARE

CHxMAX

Figure 24-8. CHxMAX Latency

24.9.5 TIMA Channel Registers

These read/write registers contain the captured TIMA counter value of the input capture function or the output compare value of the output compare function. The state of the TIMA channel registers after reset is unknown.

In input capture mode (MSxB–MSxA = 0:0), reading the high byte of the TIMA channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read.

In output compare mode (MSxB–MSxA ≠ 0:0), writing to the high byte of the TIMA channel x registers (TCHxH) inhibits output compares and the CHxF bit until the low byte (TCHxL) is written.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module A (TIMA) 411 ehia aaMC68HC Semiconductor Freescale (TIMA) A Module Interface Timer 412 Technical Data Timer InterfaceModuleA(TIMA) ee:Indeterminateafter Reset Indeterminateafter Reset Reset: Indeterminateafter Reset Reset: Indeterminateafter Reset Reset: Indeterminateafter Reset Reset: Reset: Read: Read: Read: Read: Read: Write: Write: Write: Write: Write: eitrNm n drs TACH2H —$002D Register NameandAddress —$002B TACH1L Register NameandAddress TACH1H —$002A Register NameandAddress —$0028 TACH0L Register NameandAddress TACH0H —$0027 Register NameandAddress Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 9 Bit 10 Bit Bit11 Bit12 Bit13 Bit 14 Bit 15 8 Bit 9 Bit 10 Bit Bit11 Bit12 Bit13 Bit14 Bit 15 8 Bit 9 Bit 10 Bit Bit11 Bit12 Bit13 Bit14 Bit 15 BitBitBit 7654321Bit 7BitBit 7654321Bit 6Bit 0 Bit 5BitBit 7654321Bit 0 7Bit 4BitBit 7654321Bit 6Bit 0 3Bit 5Bit 7654321Bit 2Bit 0 4Bit 1Bit 0 3Bit 0 2Bit 1Bit 0 (TACH0H/L–TACH3H/L) Figure 24-9.TIMA ChannelRegisters (Sheet1of3) 08AZ60 — Rev 1.1 Rev — 08AZ60 Timer Interface Module A (TIMA) I/O Registers

Register Name and Address TACH2L — $002E

Bit 7654321Bit 0

Read: Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Write:

Reset: Indeterminate after Reset

Register Name and Address TACH3H — $0030

Bit 7654321Bit 0

Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write:

Reset: Indeterminate after Reset

Register Name and Address TACH3L — $0031

Bit 7654321Bit 0

Read: Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Write:

Reset: Indeterminate after Reset

Register Name and Address TACH4H — $0033

Bit 7654321Bit 0

Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write:

Reset: Indeterminate after Reset

Register Name and Address TACH4L — $0034

Bit 7654321Bit 0

Read: Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0 Write:

Reset: Indeterminate after Reset Figure 24-9. TIMA Channel Registers (TACH0H/L–TACH3H/L) (Sheet 2 of 3)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Timer Interface Module A (TIMA) 413 ehia aaMC68HC Semiconductor Freescale (TIMA) A Module Interface Timer 414 Technical Data Timer InterfaceModuleA(TIMA) ee:Indeterminateafter Reset Indeterminateafter Reset Reset: Reset: Read: Read: Write: Write: Register Name and Address TACH5L —$0037 TACH5L Register NameandAddress TACH5H —$0036 Register NameandAddress Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 9 Bit 10 Bit Bit11 Bit12 Bit13 Bit14 Bit 15 BitBit 7BitBit 7654321Bit 6Bit 5Bit 7654321Bit 0 4Bit 0 3Bit 2Bit 1Bit 0 (TACH0H/L–TACH3H/L) Figure 24-9.TIMA ChannelRegisters (Sheet3of3) 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 25. Analog-to-Digital Converter (ADC-15)

25.1 Contents

25.2 Introduction...... 418 25.3 Features...... 418 25.4 Functional Description...... 418 25.4.1 ADC Port I/O Pins ...... 419 25.4.2 Voltage Conversion ...... 420 25.4.3 Conversion Time ...... 420 25.4.4 Continuous Conversion...... 421 25.4.5 Accuracy and Precision...... 421 25.5 Interrupts...... 421

25.6 Low-Power Modes ...... 421 25.6.1 Wait Mode ...... 421 25.6.2 Stop Mode ...... 422 25.7 I/O Signals ...... 422 25.7.1 ADC Analog Power Pin (VDDAREF) ...... 422 25.7.2 ADC Analog Ground/ADC Voltage Reference Low Pin (AVSS/VREFL) ...... 422 25.7.4 ADC Voltage In (ADCVIN) ...... 423

25.8 I/O Registers ...... 423 25.8.1 ADC Status and Control Register ...... 423 25.8.2 ADC Data Register ...... 426 25.8.3 ADC Input Clock Register ...... 426

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Analog-to-Digital Converter (ADC-15) 417 ehia aaMC68HC Semiconductor Freescale (ADC-15) Converter Analog-to-Digital 418 Technical Data 25.4 FunctionalDescription 25.3 Features 25.2 Introduction Analog-to-Digital Converter (ADC-15) and setsaflagorgenerat conversion iscompleted, the successiveapproximationr 15 ADCchannelsasvo An analogmultiplexerallo pins PTD6/ATD14/TACLK Fifteen ADCchannelsare Features oftheAD Manual, ADCRM/AD. Freescale microcontrol For furtherinformationregarding bit analog-to-digitalconverter. This sectiondescribestheanalog-to-d Selectable ADCClock • Conversion CompleteFlagor • Single orContinuous Conversion • 8-Bit Resolution • Linear SuccessiveApproximation • 15ChannelswithMultiplexed Input • C moduleinclude: lers, pleaseconsultt ADC placestheresultin es aninterrupt.See ws thesingleADCconve – available forsampling PTD0/ATD8 and PTB7/ATD7 and PTD0/ATD8 ltage in(ADCVIN) egister-based count analog-to-digital converterson Conversion CompleteInterrupt igital converter. he HC08ADCReference . ADCVINisconvertedby Figure 25-1 theADCdataregister external sourcesat ers. Whenthe rter toselectoneof TheADCisan8- 08AZ60 — Rev 1.1 Rev — 08AZ60 – PTB0/ATD0. . Analog-to-Digital Converter (ADC-15) Functional Description

INTERNAL DATA BUS

READ DDRB/DDRB

WRITE DDRB/DDRD DISABLE DDRBx/DDRDx RESET WRITE PTB/PTD PTBx/PTDx PTBx/PTDx

ADC CHANNEL x READ PTB/PTD

DISABLE

ADC DATA REGISTER

CONVERSION ADC VOLTAGE IN COMPLETE ADCVIN ADCH[4:0] INTERRUPT ADC CHANNEL LOGIC SELECT

AIEN COCO ADC CLOCK

CGMXCLK CLOCK GENERATOR BUS CLOCK

ADIV[2:0] ADICLK

Figure 25-1. ADC Block Diagram

25.4.1 ADC Port I/O Pins

PTD6/ATD14/TACLK–PTD0/ATD8 and PTB7/ATD7–PTB0/ATD0 are general-purpose I/O pins that share with the ADC channels.

The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Analog-to-Digital Converter (ADC-15) 419 ehia aaMC68HC Semiconductor Freescale (ADC-15) Converter Analog-to-Digital 420 Technical Data 25.4.3 ConversionTime 25.4.2 VoltageConversion Analog-to-Digital Converter (ADC-15) NOTE: NOTE: $00. InputvoltagesbetweenV Specifications Refer to 60 kHz. 128 buscyclesbetweeneachconversion. one conversionwilltakebetween16and17 MHz, busfrequencyof8 ADIV prescalerbits.Forexampl function ofADICLKselect,CGMX complete. Conversiontimeinterms register, $0038),andre Conversion startsafterawriteto Input voltageshouldnotexceed potential conver guaranteed. Avoidcurrent linear conversion.Conversi scale). Iftheinput When theinputvoltage Timers. 16-bit the for PTD6/ATD14/TACLK orPTD4/ATD12/TBLCK Do notuseADCchannelsATD14 DDR bitisatlogic1, ADC willreturnalogic0 Number ofBusCycles=Co Conversion Time= Electrical Specifications sion error. sion on page423),theADCconverts voltageequalsAV thevalueinport quires between16and17ADCclockcyclesto to theADCequalsV if thecorrespondingDDRbit MHz, andfixedADCcloc 16 to 17 ADC Clock Cycles to17 16  injection onunusedA on accuracyofallothe nversion TimexBusFrequency ADC ClockFrequency REFH e, withaCGMXCL the ADSCR (ADC status control ADSCR(ADCstatuscontrol the the analogsupplyvoltages. CLK frequency,bus or ATD12whenusingthe on page423. andAV of thenumber SS /V datalatchisread. REFL, REFL, Samplerateisapproximately µ SS/ REFH s andtherewillbebetween

V pins astheclockinputs the ADCconvertsitto REFL DC inputstoprevent the signalto$FF(full (see k frequencyof1MHz, r inputvoltagesisnot K frequencyof4 areastraight-line bus cyclesisa is atlogic0.Ifthe frequency,and Electrical 08AZ60 — Rev 1.1 Rev — 08AZ60 Analog-to-Digital Converter (ADC-15) Interrupts

25.4.4 Continuous Conversion

In the continuous conversion mode, the ADC data register will be filled with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit (ADC status control register, $0038) is cleared. The COCO bit is set after the first conversion and will stay set for the next several conversions until the next write of the ADC status and control register or the next read of the ADC data register.

25.4.5 Accuracy and Precision

The conversion process is monotonic and has no missing codes. See Electrical Specifications on page 423 for accuracy information.

25.5 Interrupts

When the AIEN bit is set, the ADC module is capable of generating a

CPU interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit (ADC status control register, $0038) is at logic 0. If the COCO bit is set, an interrupt is generated. The COCO bit is not used as a conversion complete flag when interrupts are enabled.

25.6 Low-Power Modes

The following subsections describe the low-power modes.

25.6.1 Wait Mode

The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the ADCH[4:0] bits in the ADC status and control register before executing the WAIT instruction.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Analog-to-Digital Converter (ADC-15) 421 ehia aaMC68HC Semiconductor Freescale (ADC-15) Converter Analog-to-Digital 422 Technical Data 25.7.3 ADCVoltageReferencePin(V 25.7.2 ADCAnalogGround/ADC 25.7.1 ADCAnalogPowerPin(V 25.7 I/OSignals 25.6.2 StopMode Analog-to-Digital Converter (ADC-15) NOTE: be necessarytoensurecleanV V V The ADCanalogportionusesA present foroperat capacitors asclos Route V The ADCanalogportionusesV referenced below. to D. Refer The ADCmodulehas15channelsthat mode. circuitry beforeattemptinganew MCU exitsstopmode.Allowoneconver Any pendingconversionis The ADCmoduleisinactive the A the V DDAREF REFH REFL VSS isthelowerrefer isthehighreference DDAREF pintothesamevo /VREFL pintothe samevoltage potential asV VoltageReferenceLowPin(A DDAREF Electrical S carefullyformaximumnoise REFH ion oftheADC. e aspossibletothepackage.V ) ) ence supplyfortheADC. pecifications aborted.ADCconver ltage potentialasV voltage forallanalog-to aftertheexecutionof DDAREF VSS DDAREF ADC conversionaf /VREFL asitsgr on page423forvoltages forgoodresults. sion cycletostabilizetheanalog asitspowerpin.Connectthe are sharedwithI/OportsBand immunityandplacebypass VSS DD /VREFL) sions resumewhenthe . Externalfilteringmay DDAREF aSTOPinstruction. -digital conversions. ound pin.Connect ter exitingstop SS 08AZ60 — Rev 1.1 Rev — 08AZ60 must be mustbe . Analog-to-Digital Converter (ADC-15) I/O Registers

25.7.4 ADC Voltage In (ADCVIN)

ADCVIN is the input voltage signal from one of the 15 ADC channels to the ADC module.

25.8 I/O Registers

These I/O registers control and monitor ADC operation:

• ADC status and control register (ADSCR) • ADC data register (ADR) • ADC clock register (ADICLK)

25.8.1 ADC Status and Control Register

The following paragraphs describe the function of the ADC status and control register.

Address: $0038

Bit 7654321Bit 0

Read: COCO AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Write: R

Reset:00011111

R= Reserved Figure 25-2. ADC Status and Control Register (ADSCR)

COCO — Conversions Complete Bit When the AIEN bit is a logic 0, the COCO is a read-only bit which is set each time a conversion is completed. This bit is cleared whenever the ADC status and control register is written or whenever the ADC data register is read.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Analog-to-Digital Converter (ADC-15) 423 ehia aaMC68HC Semiconductor Freescale (ADC-15) Converter Analog-to-Digital 424 Technical Data Analog-to-Digital Converter (ADC-15) NOTE: ADCO —ADCContinuous stabilize. Recovery fromthedisabledstat Bit AIEN —ADCInterruptEnable ADCH[4:0] — ADC Channel SelectBits —ADC Channel ADCH[4:0] MCU whentheADCisnotused set toone.Thisfeatureallowsfo The ADCsubsystemisturnedoffw switching noisefromcorr pin asbothananalog detailed inthefollowi ADR registerattheend When set,theADCwillconvertsa read orthestatus/control conversion. Theinterruptsignaliscl When thisbitisset,aninterrupt ADCinterrupt servicethe CPUto the If theAIENbitisalogi which isusedtoselectoneof15 ADCH4, ADCH3,ADCH2, allowed whenthisbitiscleared. 0 =ADCinterruptdisabled 1 =ADCinterruptenabled 0 =conversionnotco 1 =conversioncompleted(AIEN0) 0 =OneADCconversion 1 =ContinuousADCconversion CPU interrupten or ng table.Careshould c 1,theCOCOisaread/ and adigitalinputsimu ofeachconversion. abled (AIEN=1) ConversionBit mpleted (AIEN=0) mpleted upting theanal register iswritten.Re ADCH1, and ADCH0fo ADCH1, and e requiresoneconversioncycleto isgeneratedat Reset clears the ADCO bit. theADCO clears Reset r reducedpowerconsumptionforthe . Resetsetsthesebits. ADCchannels.Cha mples continuouslyandupdatethe hen thechannelselectbitsareall eared whenthedat request. Reset clears this bit. this clears Reset request. og signal.See be takenwhenusingaport Only oneconversionis ltaneously toprevent set clearstheAIENbit. write bitwhichselects the endofanADC rm a5-bitfield nnel selectionis 08AZ60 — Rev 1.1 Rev — 08AZ60 Table 25-1 a registeris . Analog-to-Digital Converter (ADC-15) I/O Registers

Table 25-1. Mux Channel Select

ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Select

00000 PTB0/ATD0

00001 PTB1/ATD1

00010 PTB2/ATD2

00011 PTB3/ATD3

00100 PTB4/ATD4

00101 PTB5/ATD5

00110 PTB6/ATD6

00111 PTB7/ATD7

01000 PTD0/ATD8

01001 PTD1/ATD9

01010PTD2/ATD10

01011PTD3/ATD11

01100PTD4/ATD12/TBLCK

01101PTD5/ATD13

01110PTD6/ATD14/TACLK

Unused (see Note 1) Range 01111 ($0F) to 11010 ($1A) Unused (see Note 1)

11011 Reserved

1 1 1 0 0 Unused (see Note 1)

1 1 1 0 1 VREFH (see Note 2)

1 1 1 1 0 AVSS/VREFL (see Note 2) 1 1 1 1 1 [ADC power off] NOTES: 1. If any unused channels are selected, the resulting ADC conversion will be unknown. 2. The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the ADC converter both in production test and for user applications.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Analog-to-Digital Converter (ADC-15) 425 ehia aaMC68HC Semiconductor Freescale (ADC-15) Converter Analog-to-Digital 426 Technical Data 25.8.3 ADCInput 25.8.2 ADCDataRegister Analog-to-Digital Converter (ADC-15) ClockRegister drs:$003A Address: $0039 Address: This registerselectsthe an ADCconversioncompletes. One 8-bitresultregisterisprovi ADIV2–ADIV0 —ADCCl ADIV2–ADIV0 Reset: Reset: Read: AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Read: Write: RRRR Write:RRRRRRRR set toapproximately1MHz. 2 ratio usedbytheA ADIV2, ADIV1,andADIV0 showstheavailableclockconfi DV DV DV ADICLK ADIV0 ADIV1 ADIV2 Bit 7654321BitBit 0 7654321Bit 0 Figure 25-4.ADCI R= Reserved R= Reserved 0 Figure 25-3.ADCData 0000000 DC togeneratethein clock frequencyfortheADC. ock PrescalerBits nput ClockRegister Indeterminate afterReset form a3-bitfieldwh ded. Thisregisterisupdatedeachtime gurations. TheADCclockshouldbe Register(ADR) 0000 ternal ADCclock. ich selectsthedivide (ADICLK) 08AZ60 — Rev 1.1 Rev — 08AZ60 Table 25- Analog-to-Digital Converter (ADC-15) I/O Registers

Table 25-2. ADC Clock Divide Ratio

ADIV2 ADIV1 ADIV0 ADC Clock Rate

0 0 0 ADC Input Clock /1

0 0 1 ADC Input Clock / 2

0 1 0 ADC Input Clock / 4

0 1 1 ADC Input Clock / 8

1 X X ADC Input Clock / 16

X = don’t care

ADICLK — ADC Input Clock Register Bit ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source. If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the clock source for the ADC. If

CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the clock source. As long as the internal ADC clock is at approximately 1 MHz, correct operation can be guaranteed. See Electrical Specifications on page 423. 1 = Internal bus clock 0 = External clock (CGMXCLK)

fXCLK or Bus Frequency 1 MHz =  ADIV[2:0]

NOTE: During the conversion process, changing the ADC clock will result in an incorrect conversion.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Analog-to-Digital Converter (ADC-15) 427 ehia aaMC68HC Semiconductor Freescale (ADC-15) Converter Analog-to-Digital 428 Technical Data Analog-to-Digital Converter (ADC-15) 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 26. Electrical Specifications

26.1 Contents

26.2 Electrical Specifications ...... 430 26.2.1 Maximum Ratings ...... 430 26.2.3 Functional Operating Range...... 431 26.2.4 Thermal Characteristics ...... 431 26.2.5 5.0 Volt DC Electrical Characteristics ...... 432 26.2.6 ADC Characteristics ...... 434 26.2.7 5.0 Vdc ± 0.5 V Serial Peripheral Interface (SPI) Timing435 26.2.8 CGM Operating Conditions...... 438 26.2.9 CGM Component Information...... 438 26.2.10 CGM Acquisition/Lock Time Information...... 439 26.2.11 Timer Module Characteristics...... 440 26.2.12 Memory Characteristics ...... 440 26.2 Mechanical Specifications...... 441 26.3.1 64-Pin Quad Flat Pack (QFP)...... 441

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Electrical Specifications 429 ehia aaMC68HC Semiconductor Freescale Specifications Electrical 430 Technical Data 26.2.1 MaximumRatings 26.2 Electrical Specifications Electrical Specifications NOTE: NOTE: example, eitherV unused inputsareco range V operation, itis maximum-rated voltagestothishi precautions betakentoavoidapplic to highstaticvoltagesor This devicecontainscirc guaranteed operatingconditions. to Refer ratings. This deviceisnotguar exposed withoutperman aret ratings Maximum NOTE: Voltages are referenced to V Storage Temperature Input VoltageInput Maximum Current out of V Reset IRQ Maximum Current into V Supply Voltage Maximum Current Per Pin Excluding V SS Input Voltage Input

≤ (V DD aigSmo au Unit Value Symbol Rating and V recommended thatV IN 5.0 Volt DCElectrica Volt 5.0 orV SS orV SS nnected toanappropriate DD OUT he extremelimitstowhichtheMCUcanbe anteed tooperateproperly SS electricfields;however, uitry toprotectthei ently damagingit. DD ) ≤ ). V DD SS . Reliability . gh-impedance circui I I T MVDD MVSS V V V IN STG ation ofanyvoltagehigherthan DD I IN HI andV l Characteristics V nputs againstdamagedue OUT of operation SS V DD –0.3 to V to –0.3 03t 60V +6.0 to –0.3 –55 to to +150 –55 logic voltagelevel(for it isadvisedthatnormal beconstrained tothe +2 to V to +2 atthemaximum ± 0 mA mA 100 100 2 mA 25 t. Forproper DD DD 08AZ60 — Rev 1.1 Rev — 08AZ60 on page432for + 4 + is enhancedif +0.3 ° V V C Electrical Specifications Electrical Specifications

26.2.2 Functional Operating Range

Rating Symbol Value Unit

(1) Operating Temperature Range TA –40 to TA(MAX) °C

Operating Voltage Range VDD 5.0 ± 0.5v V

1. TA(MAX) = 125°C for part suffix MFU 105°C for part suffix VFU 85°C for part suffix CFU

NOTE: For applications which use the LVI, Freescale guarantee the functionality of the device down to the LVI trip point (VLVI).

26.2.3 Thermal Characteristics

Characteristic Symbol Value Unit

Thermal Resistance θ 70 °C/W QFP (64 Pins) JA

I/O Pin Power Dissipation PI/O User Determined W

PD = (IDD x VDD) + Power Dissipation (see Note 1) PD W PI/O = K/(TJ + 273 °C

PD x (TA + 273 °C) Constant (see Note 2) K 2 W/°C + (PD x θJA)

Average Junction Temperature TJ TA = PD x θJA °C

NOTES: 1.Power dissipation is a function of temperature. 2.K is a constant unique to the device. K can be determined from a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Electrical Specifications 431 ehia aaMC68HC Semiconductor Freescale Specifications Electrical 432 Technical Data 26.2.4 5.0VoltDCElec Electrical Specifications Capacitance Input Current I/O Ports Hi-Z Leakage Current o-otg ee nii (trip) Low-Voltage ResetInhibit POR ReArm VoltagePOR ReArm Note5) (see Total source current POR Rise Time Ramp Rate (see Note 7) Note (see Rate Ramp Time Rise POR POR ResetVoltage (see Note 6) High COP DisableHigh Voltage8) Note (see V Low Input Voltage Input High Voltage Output LowVoltage Output High Voltage Total sink current DD Ports (As Input or Output) or Input (As Ports Stop (see Note 4) Wait 9) 3 and Notes (see Run (see2 Notes9) and LVI–40 disabled, LVI disabled,T LVI enabled, –40 (I All Ports,IRQ All Ports,IRQ (I (I (I LVI enabled, T Supply Current SupplyCurrent LOAD LOAD LOAD LOAD =–. A l ot V AllPorts mA) 10.0 = =1.6mA) AllPorts AllPorts mA) –5.0 = AllPorts mA) –2.0 = trical Characteristics s s A A hrceitcSmo i a Unit Max Min Symbol Characteristic , RESET, OSC1 , RESET, OSC1 =25 =25 ° ° C to +125C to C to +125C to ° ° C C (recover) ° ° C C V IOH PORRST IOL R C V V V V C V V I V I POR POR OUT DD I OH IN LVI OL L IH HI IN IL tot tot 0.7 x V 0.7 x V DD DD .2—V/ms — 0.02 V V 4.0 —15mA—0.4V—10mA — — — — — — — — — — —1.5V 0800mV0200mV DD –1.5 –0.8 SS DD 0.3 xV V 08AZ60 — Rev 1.1 Rev — 08AZ60 DD V 100 500 400 4.4 ± ± 12 50 20 35 —V —V 8 DD +2 1 1 DD mA mA µ µ µ µ µ µ pF V V V V A A A A A A Electrical Specifications Electrical Specifications

NOTES:

1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +TA (MAX, unless otherwise noted. 2. Run (Operating) IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 3. Wait IDD measured using external square wave clock source (fOP = 8.0 MHz). All inputs 0.2 Vdc from rail. No dc loads. Less than 100 pF on all outputs, CL = 20 pF on OSC2. All ports configured as in- puts. OSC2 capacitance linearly affects wait IDD. Measured with all modules enabled. 4. Stop IDD measured with OSC1 = VSS. 5. Maximum is highest voltage that POR is guaranteed. 6. Maximum is highest voltage that POR is possible. 7. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 8. See COP Module During Break Interrupts on page 176. 9. Although IDD is proportional to bus frequency, a current of several mA is present even at very low frequencies.

26.2.5 Control Timing

Characteristic Symbol Min Max Unit

Bus Operating Frequency (4.5–5.5 V — VDD Only) fBUS —8.4MHz

RESET Pulse Width Low tRL 1.5 — tcyc

IRQ Interrupt Pulse Width Low (Edge-Triggered) tILHI 1.5 — tcyc

IRQ Interrupt Pulse Period tILIL Note 4 — tcyc

16-Bit Timer (see Note 2) Input Capture Pulse Width (see Note 3) tTH, tTL 2 — tcyc Input Capture Period tTLTL Note 4 —

MSCAN Wake-up Filter Pulse Width (see Note 5) tWUP 25µs

NOTES:

1.VDD = 5.0 Vdc ± 0.5v, VSS = 0 Vdc, TA = –40 °C to TA(MAX), unless otherwise noted. 2.The 2-bit timer prescaler is the limiting factor in determining timer resolution. 3.Refer to Table 24-2 and supporting note. 4.The minimum period tTLTL or tILIL should not be less than the number of cycles it takes to execute the capture interrupt service routine plus TBD tcyc. 5. The minimum pulse width to wake up the MSCAN module is guaranteed by design but not tested.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Electrical Specifications 433 ehia aaMC68HC Semiconductor Freescale Specifications Electrical 434 Technical Data 26.2.6 ADCCharacteristics Electrical Specifications Conversion Range (see Note1) eouin88Bits 8 8 Absolute Accuracy Resolution ulSaeRaigF FHex Hex — Inherent within Total FF Error 01 5 FE 17 00 NOTES: 16 17 16 2) Note (see Time Sample Full-Scale Reading Zero Input Reading Monotonicity Conversion Time 3) Note (see Leakage Input Time Power-Up nu aaiac FNot Tested pF Tested Onlyat 1 MHz Hz 8 1.048M 500 k — Voltage Input Analog Clock Internal ADC Input Capacitance (V 1.V Portsand D B 3.The external system error caused by input leakage by caused system 3.The external leakage error input greater 10 k than 2.Source impedances 0.5v) source and input current. source and input REFL DD =5.0 Vdc =0V,V ± DDA hrceitcMnMxUi Comments Unit Max Min Characteristic 0.5v, V /V DDAREF SS =0Vdc, V = V = REFH DDA Ω adversely affect internal RC charging time during input sampling. input adversely time during RCcharging affect internal =5V /V DDAREF ± =5.0 Vdc current isapproximatelycurrent ofR to theproduct equal V V REFL REFL 1+ LSB +1 –1 — ± 0.5v, V SSA V V REFH REFH ± 1 =0Vdc, V Cycles Cycles Clock Clock REFH ADC ADC ADC µ µ V V A s =5.0Vdc Includes Sampling Conversion Time ± 08AZ60 — Rev 1.1 Rev — 08AZ60 V Quantization V V 0.5v REFL REFL IN IN Includes Period =V =V Time = V REFH REFL SSA Electrical Specifications Electrical Specifications

26.2.7 5.0 Vdc ± 0.5 V Serial Peripheral Interface (SPI) Timing

Num Characteristic Symbol Min Max Unit Operating Frequency (see Note 3) Master fBUS(M) fBUS/128 fBUS/2 MHz Slave fBUS(S) dc fBUS Cycle Time 1 Master tcyc(M) 2 128 tcyc Slave tcyc(S) 1 —

2 Enable Lead Time tLead 15 — ns

3 Enable Lag Time tLag 15 — ns Clock (SCK) High Time 4 Master tW(SCKH)M 100 — ns Slave tW(SCKH)S 50 — Clock (SCK) Low Time 5 Master tW(SCKL)M 100 — ns Slave tW(SCKL)S 50 — Data Setup Time (Inputs) 6 Master tSU(M) 45 — ns Slave tSU(S) 5 —

Data Hold Time (Inputs) 7 Master tH(M) 0 — ns Slave tH(S) 15 — Access Time, Slave (see Note 4) CPHA = 0 t 0 40 ns 8 A(CP0) CPHA = 1 tA(CP1) 0 20

9 Slave Disable Time (Hold Time to High-Impedance State) tDIS —25ns Enable Edge Lead Time to Data Valid (see Note 6) 10 Master tEV(M) — 10 ns Slave tEV(S) — 40 Data Hold Time (Outputs, after Enable Edge) 11 Master tHO(M) 0 — ns Slave tHO(S) 5 — Data Valid 12 t 90 — ns Master (Before Capture Edge) V(M) Data Hold Time (Outputs) 13 t 100 — ns Master (Before Capture Edge) HO(M) NOTES:

1. All timing is shown with respect to 30% VDD and 70% VDD, unless otherwise noted; assumes 100 pF load on all SPI pins. 2. Item numbers refer to dimensions in Figure 26-1 and Figure 26-2. 3. fBUS = the currently active bus frequency for the microcontroller. 4. Time to data active from high-impedance state. 5. With 100 pF on all SPI pins

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Electrical Specifications 435 ehia aaMC68HC Semiconductor Freescale Specifications Electrical 436 Technical Data Electrical Specifications NOTE: This last clock edge is generated inte edgeisgenerated clock last NOTE: This SCK (CPOL =1) SCK (CPOL =0) SCK NOTE: This firstcloc NOTE: This SCK (CPOL =1) SCK (CPOL =0) SCK (OUTPUT) (OUTPUT) (OUTPUT) (OUTPUT) (OUTPUT) (OUTPUT) (INPUT) (INPUT) (INPUT) (INPUT) MOSI MISO MOSI MISO SS SS 10 10 NOTE NOTE k edge is generated internally, but is not seen at the SCKpin. isnotseenatthe isgeneratedinternally,but k edge SS SS pin of master pinof heldhigh. pin of master pinof heldhigh. Figure 26-1.SPIMast 4 5 12 MASTER MSB OUT 12 MSB IN MASTER MSB OUT 1 MSB IN b) SPI Master Timing (CPHA = 1) = b) SPIMasterTiming(CPHA a) SPI Master Timing (CPHA = 0) (CPHA Timing SPI a) Master rnally, butisnotseenattheSCKpin. 4 5 11 13 4 5 11 13 1 4 5 er TimingDiagram BITS 6–1 BITS 6–1 BITS 6–1 BITS 6–1 10 10 6 MASTER LSB OUT 6 MASTER LSB OUT LSB IN LSB IN 7 11 7 11 08AZ60 — Rev 1.1 Rev — 08AZ60 NOTE NOTE Electrical Specifications Electrical Specifications

SS (INPUT)

1 3 SCK (CPOL = 0) 115 (INPUT) 4 2

SCK (CPOL = 1) 5 (INPUT) 4 8 9 MISO (INPUT) SLAVE MSB OUT BITS 6–1 SLAVE LSB OUT NOTE

6 7 10 11 11 MOSI (OUTPUT) MSB IN BITS 6–1 LSB IN

NOTE: Not defined but normally MSB of character just received

a) SPI Slave Timing (CPHA = 0)

SS (INPUT)

1 SCK (CPOL = 0) 5 (INPUT) 4 2 3 SCK (CPOL = 1) 5 (INPUT) 4 10 8 9 MISO (OUTPUT) NOTE SLAVE MSB OUT BITS 6–1 SLAVE LSB OUT

6 7 10 11 MOSI (INPUT) MSB IN BITS 6–1 LSB IN

NOTE: Not defined but normally LSB of character previously transmitted

b) SPI Slave Timing (CPHA = 1)

Figure 26-2. SPI Slave Timing Diagram

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Electrical Specifications 437 ehia aaMC68HC Semiconductor Freescale Specifications Electrical 438 Technical Data 26.2.9 CGMComponentInformation 26.2.8 CGMOper Electrical Specifications Bypass Capacitor rsa uigCpctneC L— — x CL 2 x CL 2 — — C2 C1 MultiplyFactorFilter Capacitor TuningCrystal Capacitance Fixed Capacitance Crystal VCO Operating Frequency (MHZ) VCO Center-of-Range Frequency Operating Voltage Crystal ReferenceCrystal Frequency Filter Capacitor Range Nom. Multiplier (MHz) Range Nom.Multiplier Crystal Load Capacitance Crystal Module Crystal Reference Module Crystal (MHz) Frequency hrceitcSmo i y a Comments Max Typ Min Symbol Characteristic ecito yblMnTpMxComments Max Typ Min Symbol Description ating Conditions C f f f C f f RCLK VCLK XCLK V NOM VRS FACT C C BYP DD F L .12—32.0 32.0 — — 4.9152 4.9152 . 5.5V — 4.5 V .12Mz— —4.9152 4.9152 MHz — — —0.1— — —— .12Mz8 4.9152 MHz 1 C 0.0154 F/s V F/s 0.0154 (V f XCLK FACT DDA µ F— x ) / — 4.5–5.5 V, V 4.5–5.5 V, V Same Frequency as CBYP must provide must CBYP Consult Crystal Consult Crystal Consult Crystal Consult Crystal See 134 (CGMXFC) Pin Capacitor considered. resistance must be f from f = f f = from low ACimpedance Manufacturer’s Data Manufacturer’s Data Manufacturer’s Data 100 xf RCLK External Filter 08AZ60 — Rev 1.1 Rev — 08AZ60 VCLK XCLK DD DD on page , so series so , series only only /100 to Electrical Specifications Electrical Specifications

26.2.10 CGM Acquisition/Lock Time Information

Description Symbol Min Typ Max Notes

If C Chosen Manual Mode Time to Stable t — (8 x V )/(f x K — F ACQ DDA XCLK ACQ) Correctly

If C Chosen Manual Stable to Lock Time t — (4 x V )/(f x K ) — F AL DDA XCLK TRK Correctly

Manual Acquisition Time tLOCK — tACQ+tAL — Tracking Mode Entry D 0—± 3.6% Frequency Tolerance TRK

Acquisition Mode Entry D ± 6.3% — ± 7.2% Frequency Tolerance UNT

LOCK Entry Freq. Tolerance DLOCK 0—± 0.9%

LOCK Exit Freq. Tolerance DUNL ± 0.9% — ± 1.8% Reference Cycles per Acquisition Mode nACQ —32— Measurement

Reference Cycles per

Tracking Mode nTRK —128— Measurement

Automatic Mode Time If C Chosen t n /f (8 x V )/(f x K F to Stable ACQ ACQ XCLK DDA XCLK ACQ) Correctly

Automatic Stable to Lock If C Chosen t n /f (4 x V )/(f x K ) — F Time AL TRK XCLK DDA XCLK TRK Correctly

Automatic Lock Time tLOCK — tACQ+tAL —

PLL Jitter, Deviation of ± (fCRYS) N = VCO Average Bus Frequency 0—x (.025%) Freq. Mult. over 2 ms x (N/4) (GBNT)

NOTES: 1.GBNT guaranteed but not tested

2.VDD = 5.0 Vdc ± 0.5v, VSS = 0 Vdc, TA = –40 °C to TA(MAX), unless otherwise noted.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Electrical Specifications 439 ehia aaMC68HC Semiconductor Freescale Specifications Electrical 440 Technical Data 26.2.12 MemoryCharacteristics 26.2.11 TimerModuleCharacteristics Electrical Specifications EEPROM enable recovery time EEPROM Data Retention EEPROMstop recovery time EEPROM Write/Erase Cycles Input Clock Width Pulse Input EEPROM Programming Volt EEPROM Erasing Time perBulk EEPROM Erasing Time perBlock EEPROM Erasing Time perByte InputCapture Pulse Width EEPROMProgramming TimeperByte RAM Data Retention Voltage Retention RAM Data After 10,000Write/Erase Cycles @ 10 ms Write Time +125 ms@ 10 Write hrceitcSmo i a Unit Max Min Symbol Characteristic hrceitcSmo i a Unit Max Min Symbol Characteristic ° age DischargePeriod C t t EEBLOCK t t t t EESTOP t EEBYTE EEBULK EEPGM V EEOFF EEFPV RDR t TCH, TCH, t TIH, t t TCL TIL (1/f OP 2 ns — 125 000—Cycles — 10,000 0 — — 600 600 — 100 . V — 0.7 0—Years — 10 0—ms ms — ms — 10 — 10 10 0—ms — 10 ) + 5 ) + 08AZ60 — Rev 1.1 Rev — 08AZ60 —ns µ µ µ s s s Electrical Specifications Mechanical Specifications

26.3 Mechanical Specifications

26.3.1 64-Pin Quad Flat Pack (QFP)

L B

48 33 B P 49 32 S S D D

S - A, B, D - S

- A - - B - Detail A

L B – HA

B B – CA V

M F M 0.20 0.20 0.05 A – B Detail A 64 17 J N 1 16 - D - D Base A Metal 0.20 M CA – B S D S 0.20 M CA – B S D S 0.05 A – B Section B–B

S U 0.20 M HA – B S D S T Detail C

M E R

Q C Datum -H- Plane -C- K H G 0.01 Seating M W Plane X Detail C

Dim. Min. Max. Notes Dim. Min. Max. A 13.90 14.10 1. Dimensions and tolerancing per ANSI Y 14.5M, 1982. M5° 10° B 13.90 14.10 2. All dimensions in mm. N 0.13 0.17 3. Datum Plane –H– is located at bottom of lead and is coincident with C 2.15 2.45 P 0.40 BSC the lead where the lead exits the plastic body at the bottom of the part- D 0.30 0.45 ing line. Q0° 7° E 2.00 2.40 4. Datums A–B and –D to be determined at Datum Plane –H–. R 0.13 0.30 F 0.30 0.40 5. Dimensions S and V to be determined at seating plane –C–. S 16.95 17.45 G 0.80 BSC 6. Dimensions A and B do not include mould protrusion. Allowable T0.13— mould protrusion is 0.25mm per side. Dimensions A and B do include H — 0.25 U0° — mould mismatch and are determined at Datum Plane –H–. J 0.13 0.23 7. Dimension D does not include dambar protrusion. Allowable dam- V 16.95 17.45 K 0.65 0.95 bar protrusion shall be 0.08 total in excess of the D dimension at max- W 0.35 0.45 imum material condition. Dambar cannot be located on the lower L12.00 REF X1.6 REF radius or the foot.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Electrical Specifications 441 ehia aaMC68HC Semiconductor Freescale Specifications Electrical 442 Technical Data Electrical Specifications 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC08AZ60

Section 27. Appendix: Future EEPROM Registers

NOTE: The following are proposed register addresses. Writing to them in current software will have no effect.

27.1 EEPROM Timebase Divider Control Registers

To program or erase the EEPROM content, the EEPROM control hardware requires a constant timebase of 35µs to drive its internal timer. EEPROM Timebase Divider EEDIV is a clock-divider which divides the selected reference clock source to generate this constant timebase. The reference clock input of the EEDIV is driven by either the CGMXCLK or the system bus clock. The selection of this reference clock is defined by

the EEDIVCLK bit in the Configuration Register.

EEPROM Timebase Divider EEDIV are defined by two registers (EEDIVH and EEDIVL) and must be programmed with a proper value before starting any EEPROM erase/program steps. EEDIV registers must be re-programmed when ever its reference clock is changed. The EEDIV value can be either pre-programmed in the EEDIVHNVR and EEDIVLNVR non-volatide memory registers, (which upon reset will load their contents into the EEDIVH and EEDIVL registers,) or programmed directly by software into the EEDIVH and EEDIVL registers at system initialization . The function of the divider is to provide a constant clock source with a period of 35µs (better be within ± 2ms) to the internal timer and related EEPROM circuits for proper program/erase operations. The recommended frequency range of the reference clock is 250KHz to 32MHz.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Appendix: Future EEPROM Registers 443 ehia aaMC68HC Semiconductor Freescale Registers EEPROM Future Appendix: 444 Technical Data 27.2 EEDIVHand Appendix: FutureEEPROM Registers drs:$FE1B Address: $FE1A Address: Reset:EEDIVH-NVRxxxx ee:EDV-V EIHNREDV-V EIHNREDV-V EIHNREDV-V EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR EEDIVH-NVR Reset: Read: Read: Write: Write: EEDIVSECD EI7EDV EI5EEDIV4 EEDIV5 EEDIV6 EEDIV7 Bit 7654321BitBit 7654321Bit 0 0 Figure 27-1.EEPROM- Figure 27-2. EEPROM-2 Divi EEPROM-2 27-2. Figure EEDIVL Registers Programming/erasing the in period. EEDIV value(172),whichequalsto of thedivider,ReferenceFreq value intheaboveformulawillbe result indatalost For example,iftheReference interger value. Where theresultinsidebracke calculated bythefollowingformula: if theEEDIVSECDbi can beprogrammedbysoftwareatsyst EEDIVH andEEDIVLareusedtostor EI N Reference INT EEDIV Unimplemented = Unimplemented = = andreduceendurance [] 2 DividerHighR t intheEEDIVH EEPROM withanimpro der LowRegister(EEDIVL) Frequency is4.9152 rqec H)3 10 35 Frequency (Hz) EI3EDV EI1EEDIV0 EEDIV1 EEDIV2 EEDIV3 172.Toexaminet uency isdividedbythecalculated t []isroundeddowntothenearest 28.577KHzinfrequencyor34.99 is notcleared.The e the11-bitEED egister (EEDIVH) em initializationorduringruntime of theEEPROMdevice. EI1 EI9EEDIV8 EEDIV9 EEDIV10 EEDIVH- NVR × per EEDIVvaluemay MHz, theEEDIV he timebaseoutput EEDIVH- × NVR IV valuewhich 08AZ60 — Rev 1.1 Rev — 08AZ60 EEDIV valueis – 6 + EEDIVH- 0.5 NVR µ s Appendix: Future EEPROM Registers EEDIV Non-volatile Registers

EEDIVSECD — EEPROM Divider Security Disable This bit enables/disables the security feature of the EEDIV registers. When EEDIV security feature is enabled, the state of the registers EEDIVH and EEDIVL are locked (inclucding this EEDIVSECD bit). Also the EEDIVHNVR and EEDIVLNVR non-volatile memory registers are protected from being erased/programmed. 1 = EEDIV security feature disabled 0 = EEDIV security feature enabled

EEDIV10–EEDIV0 — EEPROM timebase prescalar. These prescalar bits store the value of EEDIV which is used as the divisor to derive a timebase of 35µs from the selected reference clock source for the EEPROM related internal timer and circuits. EEDIV0–10 are readable at any time. They are writable when EELAT is not set and EEDIVSECD is not cleared.

27.3 EEDIV Non-volatile Registers

Address: $FE10 Bit 7654321Bit 0 Read: EEDIVSECD EEDIV10 EEDIV9 EEDIV8 Write: Reset: PV PV PV PV PV PV PV PV = Unimplemented Figure 27-3. EEPROM-2 Divider High Non-volatile Register (EEDIVHNVR)

Address: $FE11 Bit 7654321Bit 0 Read: EEDIV7 EEDIV6 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0 Write: Reset: PV PV PV PV PV PV PV PV = Unimplemented Figure 27-4. EEPROM-2 Divider Low Non-volatile Register (EEDIVLNVR)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Appendix: Future EEPROM Registers 445 ehia aaMC68HC Semiconductor Freescale Registers EEPROM Future Appendix: 446 Technical Data Appendix: FutureEEPROM Registers NOTE: care shouldbetakenbeforeprogra the EEDIVHandEE modes aredisabledforEEDIVHNVR thereafter. Oncethis Once EEDIVSECDint into theEEDIVH& EEPROM DividerSecurityDisable volatile registers(EEDIVHNVRand in theEEDIVHisnot normal EEPROMbytesiftheDivider The EEDIVHNVRandEEDIV corresponding volatile two specialregisters bits whicharenon-volatileandnot EEDIVLNVR) storetheresetval The EEPROMDivider PV =ProgrammedValueor because theEEDIVSECDbit system reset,theEEDIVsecurity EEDIVL registerswi DIVL registersarealso load theEEDIV0–10 security featureisar cleared. Thenew11-bit EEDIVregisters( non-volatileregi he EEDIVHNVRis ’1’intheerasedstate. LNVR canbeprogram in theEEDIVHisalwa ues oftheEEDI feature isperma bit (EEDIVSECD) mming avalueinto EEDIVLNVR) togetherwiththe Security Disable and EEDIVLNVR.M modified byreset.Onreset,these sters (EEDI th asystemreset. EEDIVH and EEDIVL). EEDIVH and med, eraseandprogram programmed to‘0’andaftera and EEDIVSECDbitsintothe disabled. Therefore,great EEDIV valueinthenon- V0–10 andEEDIVSECD nently enabled VHNVR and ys loadedwitha‘0’ med/erased like will onlybeloaded the EEDIVHNVR. the bit (EEDIVSECD) 08AZ60 — Rev 1.1 Rev — 08AZ60 odifications to Technical Data — MC68HC08AZ60

Section 28. Appendix: HC08AZ48 Memory Map

28.1 Contents

28.2 Introduction...... 447 28.3 I/O Section...... 450

28.2 Introduction

The MC68HC08AZ48 can address 48 Kbytes of memory space. It is basically identical to the MC68HC08AZ60 part except that ROM and EEPROM size are smaller. The memory map, shown in Figure 28-1, includes:

• 48 Kbytes of ROM • 1536 Bytes of RAM • 768 Bytes of EEPROM with Protect Option • 52 Bytes of User-Defined Vectors • 224 Bytes of Monitor ROM

The following definitions apply to the memory map representation of reserved and unimplemented locations.

• Reserved — Accessing a reserved location can have unpredictable effects on MCU operation. • Unimplemented — Accessing an unimplemented location causes an illegal address reset if illegal address resets are enabled.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Appendix: HC08AZ48 Memory Map 447 ehia aaMC68HC Freescale Semiconductor Appendix: HC08AZ48 Memory Map 448 Technical Data Map Appendix: HC08AZ48Memory 0F $0DFF $0DFF 0F $0BFF $0BFF $0C00 0F $05FF $05FF 0F $07FF $06FF $04FF $07FF $06FF $04FF 0F $09FF $0A00 $09FF 07 $057F $057F 04 $044F $044F 04 $004F $004F 03 $003F $003F $0600 $0580 $0800 $0700 $0500 $0450 $0050 $0040 $0000 ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ ↓↓ Figure 28-1.MemoryMap CAN CONTROL AND MESSAGE I/O REGISTERS I/O REGISTERS (64 BYTES) I/O REGISTERS, 16BYTES REGISTERS, I/O EEPROM-2, 256BYTES EEPROM-2, EEPROM-1, 512BYTES EEPROM-1, BUFFERS, 128BYTES BUFFERS, RAM-1, 1024 BYTES RAM-2, 512 BYTES RESERVED RESERVED RESERVED RESERVED 08AZ60 — Rev 1.1 Rev — 08AZ60 $0C00 $0A00 $0580 $0600 $0700 $0500 $0450 $0800 $0050 $0040 $0000 Appendix: HC08AZ48 Memory Map Introduction

Figure 28-1. Memory Map (Continued)

$0E00 $0E00 ↓↓RESERVED $3FFF $3FFF $4000 $4000 ↓↓ROM-2, 16384 BYTES $7FFF $7FFF $8000 $8000 ↓↓ROM-1, 32,256BYTES $FDFF $FDFF $FE00 SIM BREAK STATUS REGISTER (SBSR) $FE00 $FE01 SIM RESET STATUS REGISTER (SRSR) $FE01 $FE02 RESERVED $FE02 $FE03 SIM BREAK FLAG CONTROL REGISTER (SBFCR) $FE03 $FE04 RESERVED $FE04 $FE05 RESERVED $FE05 $FE06 UNIMPLEMENTED $FE06

$FE07 RESERVED $FE07 $FE08 RESERVED $FE08 $FE09 RESERVED $FE09 $FE0A RESERVED $FE0A $FE0B RESERVED $FE0B $FE0C BREAK ADDRESS REGISTER HIGH (BRKH) $FE0C $FE0D BREAK ADDRESS REGISTER LOW (BRKL) $FE0D $FE0E BREAK STATUS AND CONTROL REGISTER (BSCR) $FE0E $FE0F LVI STATUS REGISTER (LVISR) $FE0F $FE10 RESERVED $FE10 $FE11 RESERVED $FE11 $FE12 $FE12 ↓↓UNIMPLEMENTED (5BYTES) $FE17 $FE17 $FE18 EEPROM NON-VOLATILE REGISTER (EENVR2) $FE18 $FE19 EEPROM CONTROL REGISTER (EECR2) $FE19 $FE1A RESERVED $FE1A

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Appendix: HC08AZ48 Memory Map 449 ehia aaMC68HC Freescale Semiconductor Appendix: HC08AZ48 Memory Map 450 Technical Data 28.3 I/OSection Map Appendix: HC08AZ48Memory addresses: control, status,anddata Addresses $0000–$003F,shownin $FE18(EEPROM non-volati • $FE0F (LVI status • $FE0E (break statusand • $FE0Cand$FE0D(bre • $FE09(configurationwrite- • $FE03(SIMbreakflag • $FE01(SIMresetstat • $FE00(SIMbreakst • $FFCC FC $FFCB $FFCB F1 ERMCNRLRGSE EC1 $FE1D (EECR1) REGISTER EEPROMCONTROL $FE1C REGISTER(EENVR1) NON-VOLATILE EEPROM $FE1D $FE1C FF $FEFF $FEFF F1 EEVD$FE1E RESERVED $FE1E $FE1B (EEACR2) CONFIGURATION EEPROMARRAY $FE1B F1 ERMARYCNIUAIN(EC1 $FE1F (EEACR1) CONFIGURATION EEPROMARRAY $FE1F FF $FFFF $FFFF $FF7F $FE20 F8 EEVD$FF81 $FF80 RESERVED RESERVED $FF82 $FF81 $FF80 $FF00 ↓ ↓↓ ↓↓ ↓↓ Figure 28-1.Memory UNIMPLEMENTED (128BYTES) registers.Additional register,LVISR) MONITOR ROM(224BYTES) RESERVED (75BYTES) atus register,SBSR) VECTORS (52BYTES) us register,SRSR) control register,SBFCR) ak addressregister control register,BRKSCR) once register,CONFIG-2) le register,EENVR2) Figure 28-2 Map(Continued) I/O registershavethese , containmostofthe s, BRKHandBRKL) 08AZ60 — Rev 1.1 Rev — 08AZ60 $FFCC $FF7F $FE20 $FF00 $FF82 ↓ Appendix: HC08AZ48 Memory Map I/O Section

• $FE19 (EEPROM control register, EECR2) • $FE1B (EEPROM array configuration register, EEACR2) • $FE1C (EEPROM non-volatile register, EENVR1) • $FE1D (EEPROM control register, EECR1) • $FE1F (EEPROM array configuration register, EEACR1) • $FFFF (COP control register, COPCTL) • Table 28-1 is a list of vector locations.

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Appendix: HC08AZ48 Memory Map 451

dr eitrNm i Bit0 1 2 3 4 5 6 Bit7 Name Register Addr. $000D $000C $000E Port HDataRegister(PTH) PortGDataRegister (PTG) $000B $000A $000F $0010 SPI SPI Control Register(SPCR) $0010 EDataRegister(PTE) Port $0008 $0007 Port DData Register(PTD) $0003 $0000 Port AData Register(PTA) Port $0000 $0006 $0005 00 PortFDataRegister(PTF) $0009 $0004 $0001 Port BDataRegister(PTB) Port $0001 00 Port CDataRegister(PTC) $0002 ehia aaMC68HC Freescale Semiconductor Appendix: HC08AZ48 Memory Map 452 Technical Data Map Appendix: HC08AZ48Memory Data DirectionRegister G Data DirectionRegisterD Data DirectionRegisterH Data DirectionRegisterC Data DirectionRegisterE Data DirectionRegisterB Data DirectionRegisterA Data DirectionRegisterF Figure 28-2.Control, Status,and (DDRG) (DDRD) (DDRH) (DDRC) (DDRE) (DDRB) (DDRA)

(DDRF) ed 0 Read: Read: ed 0 0 0 0 0 0 Read: ed 0 0 0 0 0 0 0 0 0 Read: 0 0 0 0 0 0 Read: 0 Read: Read: Read: Read: Read: Read: Read: Read: Read: ed 0 Read: Read: ed 0 0 Read: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: DD DD DD DD DD D2DR1DDRD0 DDRD1 DDR2 DDRD3 DDRD4 DDRD5 DDRD6 DDRD7 MCLKE DE DE DE DE DE DE DE DDRE0 DDRE1 DDRE2 DDRE3 DDRE4 DDRE5 DDRE6 DDRE7 DB DB DB DB DB DB DB DDRB0 DDRB1 DDRB2 DDRB3 DDRB4 DDRB5 DDRB6 DDRB7 DA DA DA DA DA DA DA DDRA0 DDRA1 DDRA2 DDRA3 DDRA4 DDRA5 DDRA6 DDRA7 PI PSRCO PASWMSESPTIE SPE SPWOM CPHA CPOL SPMSTR R SPRIE T7PD T5PD T3PD T1PTD0 PTD1 PTD2 PTD3 PTD4 PTD5 PTD6 PTD7 T7PE T5PE T3PE T1PTE0 PTE1 PTE2 PTE3 PTE4 PTE5 PTE6 PTE7 T7PA T5PA T3PA T1PTA0 PTA1 PTA2 PTA3 PTA4 PTA5 PTA6 PTA7 T7PB T5PB T3PB T1PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 N = Unimplemented R = Reserved = R = Unimplemented DF DF DF DF DF DF DDRF0 DDRF1 DDRF2 DDRF3 DDRF4 DDRF5 DDRF6 T6PF T4PF T2PF PTF0 PTF1 PTF2 PTF3 PTF4 PTF5 PTF6 0 Data Registers(Sheet 1of6) DC DC DC DC DC DDRC0 DDRC1 DDRC2 DDRC3 DDRC4 DDRC5 T5PC T3PC T1PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 DG DG DDRG0 DDRG1 DDRG2 T2PG PTG0 PTG1 PTG2 08AZ60 — Rev 1.1 Rev — 08AZ60 DH DDRH0 DDRH1 T1PTH0 PTH1 Appendix: HC08AZ48 Memory Map I/O Section

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 SPI Status and Control Read: SPRF OVRF MODF SPTE MODFE $0011 ERRIE SPR1 SPR0 Register (SPSCR) Write: N Read: R7 R6 R5 R4 R3 R2 R1 R0 $0012 SPI Data Register (SPDR) Write: T7 T6 T5 T4 T3 T2 T1 T0 Read: $0013 SCI Control Register 1 (SCC1) LOOPS ENSCI TXINV M WAKE ILTY PEN PTY Write: Read: $0014 SCI Control Register 2 (SCC2) SCTIE TCIE SCRIE ILIE TE RE RWU SBK Write: Read: R8 $0015 SCI Control Register 3 (SCC3) T8 R R ORIE NEIE FEIE PEIE Write: Read: SCTE TC SCRF IDLE OR NF FE PE $0016 SCI Status Register 1 (SCS1) Write: Read: 0 0 0 0 0 0 BKF RPF $0017 SCI Status Register 2 (SCS2) Write: Read: R7 R6 R5 R4 R3 R2 R1 R0 $0018 SCI Data Register (SCDR) Write: T7 T6 T5 T4 T3 T2 T1 T0 Read: 0 0 $0019 SCI Baud Rate Register (SCBR) SCP1 SCP0 SCR2 SCR1 SCR0 Write:

IRQ Status and Control Read: 0 0 0 0 IRQF 0 $001A IMASK1 MODE1 Register (ISCR) Write: ACK1 Keyboard Status and Control Read: 0 0 0 0 KEYF 0 $001B IMASKK MODEK Register (KBSCR) Write: ACKK Read: PLLF 1111 $001C PLL Control Register (PCTL) PLLIE PLLON BCS Write: PLL Bandwidth Control Read: LOCK 0000 $001D AUTO ACQ XLD Register (PBWC) Write: PLL Programming Register Read: $001E MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4 (PPG) Write: LVISTO Mask Option Read: ROMSEC LVIRST LVIPWR SSREC COPS STOP COPD $001F P Register (MOR) Write:RRRR RRRR Timer A Status and Control Read: TOF 00 $0020 TOIE TSTOP PS2 PS1 PS0 Register (TASC) Write: 0 TRST Keyboard Interrupt Enable Read: 0 0 0 $0021 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 Register (KBIE) Write: Figure 28-2. Control, Status, and Data Registers (Sheet 2 of 6)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Appendix: HC08AZ48 Memory Map 453

dr eitrNm i Bit0 1 2 3 4 5 6 Bit7 Name Register Addr. $002D $002C $002A $002B $002E $002F $0030 $0027 $0024 $0023 $0022 $0033 $0026 $0025 $0031 $0028 $0032 $0029 ehia aaMC68HC Freescale Semiconductor Appendix: HC08AZ48 Memory Map 454 Technical Data Map Appendix: HC08AZ48Memory Timer AChannel4RegisterHigh Timer AChannel 0Statusand Timer AChannel 4Statusand Timer AChannel 1Statusand Timer AChannel 2Statusand Timer AChannel 3Statusand Timer A Timer A Channel 3Register Timer A Channel 0Register Timer A Timer A Channel 1Register Timer A Timer A Channel 3Register Timer A Channel 0Register Timer A Timer A Channel 2Register Timer A Timer A Channel 1Register Timer A Timer A Channel 2Register Control Register (TASC0) Control Register (TASC4) Control Register (TASC1) Control Register (TASC2) Control Register (TASC3) Timer ACounterRegister Timer ACounterRegister Timer AModuloRegister Timer AModuloRegister Figure 28-2.Control, Status,and High (TAMODH) High (TACNTH) High High (TACH3H) High (TACH0H) High (TACH1H) High (TACH2H) Low (TAMODL) Low (TACNTL) Low (TACH3L) Low (TACH0L) Low (TACH1L) Low (TACH2L) (TACH4H) ed i 51 31 11 Bit 8 9 10 11 12 13 14 15 Bit Read: Read: ed i Bit0 1 2 3 4 5 Read: 6 Read: 7 Bit Read: Read: Read: CH0F Read: Read: ed CH4F Read: CH1F Read: Read: Read: Read: CH2F Read: Read: Read: ed CH3F Read: rt:0 Write: Write: Write: rt:0 Write: 0 Write: Write: Write: Write: Write: Write: rt:0 Write: Write: Write: Write: Write: rt:0 Write: Write: Write: i 51 31 11 Bit 8 9 10 11 12 13 14 15 Bit i 51 31 11 Bit 8 9 10 11 12 13 14 15 Bit i 51 31 11 Bit 8 9 10 11 12 13 14 15 Bit Bit 8 9 10 11 12 13 14 15 Bit i 51 31 11 Bit 8 9 10 11 12 13 14 15 Bit i 51 31 11 Bit 8 9 10 11 12 13 14 15 Bit i Bit0 1 2 3 4 5 6 7 Bit i Bit0 1 2 3 4 5 6 7 Bit Bit0 1 2 3 4 5 6 7 Bit i Bit0 1 2 3 4 5 6 7 Bit i Bit0 1 2 3 4 5 6 7 Bit HI SBM0 L0 L0 O0CH0MAX TOV0 ELS0A ELS0B MS0A MS0B CH0IE HI SBM4 L4 L4 O4CH4MAX TOV4 ELS4A ELS4B MS4A MS4B CH4IE CH1IE HI SBM2 L2 L2 O2CH2MAX TOV2 ELS2A ELS2B MS2A MS2B CH2IE CH3IE Data Registers(Sheet 3of6) 0 0 SAESBESATV CH1MAX TOV1 ELS1A ELS1B MS1A SAESBESATV CH3MAX TOV3 ELS3A ELS3B MS3A 08AZ60 — Rev 1.1 Rev — 08AZ60 Appendix: HC08AZ48 Memory Map I/O Section

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Timer A Channel 4 Register Low Read: $0034 Bit 7 6 5 4 3 2 1 Bit 0 (TACH4L) Write: Timer A Channel 5 Status and Read: CH5F 0 $0035 CH5IE MS5A ELS5B ELS5A TOV5 CH5MAX Control Register (TASC5) Write: 0 Timer A Channel 5 Register Read: $0036 Bit 15 14 13 12 11 10 9 Bit 8 High (TACH5H) Write: Timer A Channel 5 Register Read: $0037 Bit 7 6 5 4 3 2 1 Bit 0 Low (TACH5L) Write: Analog-to-Digital Status and Read: COCO $0038 AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Control Register (ADSCR) Write: R Analog-to-Digital Data Register Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 $0039 (ADR) Write: Analog-to-Digital Input Clock Read: 0000 $003A ADIV2 ADIV1 ADIV0 ADICLK Register (ADICLK) Write: Timer B Status and Control Read: TOF 00 $0040 TOIE TSTOP PS2 PS1 PS0 Register (TBSCR) Write: TRST Timer B Counter Register High Read: Bit 15 14 13 12 11 10 9 Bit 8 $0041 (TBCNTH) Write:

Timer B Counter Register Low Read: Bit 7 6 5 4 3 2 1 Bit 0 $0042 (TBCNTL) Write: Timer B Modulo Register High Read: $0043 Bit 15 14 13 12 11 10 9 Bit 8 (TBMODH) Write: Timer B Modulo Register Low Read: $0044 Bit 7 6 5 4 3 2 1 Bit 0 (TBMODL) Write: Timer B CH0 Status and Control Read: CH0F $0045 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX Register (TBSC0) Write: 0 Timer B CH0 Register High Read: $0046 Bit 15 14 13 12 11 10 9 Bit 8 (TBCH0H) Write: Timer B CH0 Register Low Read: $0047 Bit 7 6 5 4 3 2 1 Bit 0 (TBCH0L) Write: Timer B CH1 Status and Control Read: CH1F 0 CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX $0048Register (TBSC1) Write: 0 Timer B CH1 Register High Read: $0049 Bit 15 14 13 12 11 10 9 Bit 8 (TBCH1H) Write: Timer B CH1 Register Low Read: $004A Bit 7 6 5 4 3 2 1 Bit 0 (TBCH1L) Write: Figure 28-2. Control, Status, and Data Registers (Sheet 4 of 6)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Appendix: HC08AZ48 Memory Map 455

dr eitrNm i Bit0 1 2 3 4 5 6 Bit7 Name Register Addr. $FE0C $FE0D F0 RESERVED $FE0B F1 Reserved $FE1A $FE0E $FE0F LVI StatusRegister(LVISR) LVI $FE0F F1 RESERVED $FE18 $FE11 RESERVED $FE09 $FE03 $004D $004C F0 SIM ResetStatusRegister(SRSR) $FE01 $FE00 $FE19 $004E $004B $004F ehia aaMC68HC Freescale Semiconductor Appendix: HC08AZ48 Memory Map 456 Technical Data Map Appendix: HC08AZ48Memory SIM Break FlagControlSIM Break Register TIM StatusandControl Register EEPROM NonvolatileRegister EEPROM Break AddressRegisterHigh Break Break AddressRegisterLow TIM CounterRegisterHigh SIM BreakStatusRegister TIM CounterRegisterLow TIM ModuloRegisterHigh TIM ModuloRegisterLow Break Statusand Control Figure 28-2.Control, Status,and Register (BRKSCR) Register (EECR2) EEPROM Control EEPROM (EENVR2) (TMODH) (TMODL) (SBFCR) (TCNTH) (TCNTL) (BRKH) (SBSR) (BRKL) (TSC) Read: Bit 8 9 Read: 10 11 12 13 14 15 Bit Read: Read: Bit0 1 Read: 2 3 4 5 6 7 Bit Read: ed VOT0000000 0 0 0 0 0 0 LVIOUT Read: ed TOF Read: Read: Read: Read: ed O I O LPIA V 0 LVI 0 ILAD ILOP COP PIN POR Read: Read: Read: Read: Read: Read: Read: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: Write: EEBCLK REBRKA BRKE EACN CON1 CON2 EERA BCFERR RRRR R i 51 31 11 Bit 8 9 10 11 12 13 14 15 Bit i 51 31 11 Bit 8 9 10 11 12 13 14 15 Bit i Bit0 1 2 3 4 5 6 7 Bit i Bit0 1 2 3 4 5 6 7 Bit R RRRR R RRR R RRRR R RRR RRRR R RRR R RRRR R RRR BWR SBSW R R R R R R OETSTOP TOIE 0 Data Registers(Sheet 5of6) EF EA1ERS EELAT EERAS0 EERAS1 EEOFF 0000 0 0 EEPRTC TRST T 00 EP EP EP EEBP0 EEBP1 EEBP2 EEBP3 S S PS0 PS1 PS2 08AZ60 — Rev 1.1 Rev — 08AZ60 0 EEPGM Appendix: HC08AZ48 Memory Map I/O Section

Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 EEPRTC EEPROM Array Control Register Read: EERA CON2 CON1 EEBP3 EEBP2 EEBP1 EEBP0 $FE1B T (EEACR2) Write: EEPROM Nonvolatile Register Read: EEPRTC $FE1C EERA CON2 CON1 EEBP3 EEBP2 EEBP1 EEBP0 (EENVR1) Write: T EEPROM Control Read: 0 0 $FE1D EEBCLK EEOFF EERAS1 EERAS0 EELAT EEPGM Register (EECR1) Write: Read: $FE1E Reserved RRR R RRRR Write: EEPRTC EEPROM Array Control Register Read: EERA CON2 CON1 EEBP3 EEBP2 EEBP1 EEBP0 $FE1F T (EEACR1) Write: Read: RRRR $FF80 RESERVED Write: Read: RRRR $FF81 RESERVED Write:

Read: LOW BYTE OF RESET VECTOR $FFFF COP Control Register (COPCTL) Write: WRITING TO $FFFF CLEARS COP COUNTER Figure 28-2. Control, Status, and Data Registers (Sheet 6 of 6)

Table 28-1. Vector Addresses

Address Vector $FFCC TIMA Channel 5 Vector (High) $FFCD TIMA Channel 5 Vector (Low) Low $FFCE TIMA Channel 4 Vector (High) $FFCF TIMA Channel 4 Vector (Low) $FFD0 ADC Vector (High) $FFD1 ADC Vector (Low)

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Appendix: HC08AZ48 Memory Map 457 ehia aaMC68HC Freescale Semiconductor Appendix: HC08AZ48 Memory Map 458 Technical Data Map Appendix: HC08AZ48Memory

Priority Table 28-1.Vector Addresses (Continued) drs Vector Address $FFDD CAN Receive CAN Vector (Low) Receive$FFDD CAN Vector (High) $FFDC $FFED TIMA Overflow TIMA Vector(Low) TIMA Overflow$FFED Vector(High) $FFEC Vector Error CAN (High) $FFDE Transmit CAN Vector (Low) $FFDB $FFDA CAN Transmit CAN Vector (High) $FFDA $FFEE TIMA CH3 Vector CH3 TIMA (High) $FFEE Vector CH0 TIMB (Low) Vector CH0 TIMB (High) $FFEB $FFEA Vector Error CAN (Low) $FFDF $FFEF TIMA CH3 Vector CH3 TIMA (Low) $FFEF Vector Error SCI (Low) Vector Error SCI (High) $FFD9 SCIReceive Vector$FFD8 (Low) Receive SCI Vector$FFD7 (High) Transmit SCI $FFD6 Vector (Low) Transmit SCI $FFD5 Vector (High) Keyboard$FFD4 Vector(Low) Keyboard Vector$FFD3 (High) $FFD2 $FFE9 TIMB CH1 Vector CH1 TIMB (Low) Vector CH1 TIMB (High) $FFE9 Overflow TIMB Vector(Low) $FFE8 TIMB Overflow Vector$FFE7 (High) Receive SPI Vector (Low)$FFE6 SPIReceiveVector (High) $FFE5 SPITransmit$FFE4 Vector(Low) SPITransmit$FFE3 Vector(High) CAN Wakeup Vector$FFE2 (Low) CAN Wakeup Vector$FFE1 (High) $FFE0 $FFF1 TIMA CH2 Vector TIMACH2 (Low) Vector CH2 TIMA (High) $FFF1 $FFF0 08AZ60 — Rev 1.1 Rev — 08AZ60 ehia aaMC68HC Freescale Semiconductor Appendix: HC08AZ48 Memory Map 459 Technical Data Map Appendix: HC08AZ48Memory vector addressesaredefined. account whendefiningvectoraddre 83) –see by default,befilledwith Note thatallavailable Central ProcessingUnit(CPU)

High Priority Table 28-1.Vector Addresses (Continued) ROM locationsthatnotde drs Vector Address FF SWI Vector (Low) SWI Vector (High) $FFFD $FFFC FF ResetVector (High) $FFFE FF IRQ1Vector(Low) $FFFB FF Reset Vector (Low) $FFFF the softwareinterruptinstruction(SWI,opcode FF IRQ1 Vector(High) $FFFA $FFF9 PLL Vector PLL (Low) Vector PLL (High) $FFF9 TIMVector(Low) $FFF8 TIM Vector(High) $FFF7 Vector TIMACH0 (Low) $FFF6 Vector CH0 TIMA (High) $FFF5 Vector TIMACH1 (Low) $FFF4 Vector CH1 TIMA (High) $FFF3 $FFF2 sses. Itisrecommendedthatall . Please take this into . Pleasetakethis fined bytheuserwill, 08AZ60 — Rev 1.1 Rev — 08AZ60 ehia aaMC68HC Freescale Semiconductor Appendix: HC08AZ48 Memory Map 460 Technical Data Map Appendix: HC08AZ48Memory 08AZ60 — Rev 1.1 Rev — 08AZ60 Technical Data — MC68HC908AZ60A

Glossary

A — See “accumulator (A).” accumulator (A) — An 8-bit general-purpose register in the CPU08. The CPU08 uses the accumulator to hold operands and results of arithmetic and logic operations. acquisition mode — A mode of PLL operation during startup before the PLL locks on a frequency. Also see "tracking mode." address bus — The set of wires that the CPU or DMA uses to read and write memory locations. addressing mode — The way that the CPU determines the operand address for an instruction. The M68HC08 CPU has 16 addressing modes. ALU — See “arithmetic logic unit (ALU).”

arithmetic logic unit (ALU) — The portion of the CPU that contains the logic circuitry to perform arithmetic, logic, and manipulation operations on operands. asynchronous — Refers to logic circuits and operations that are not synchronized by a common reference signal. baud rate — The total number of bits transmitted per unit of time. BCD — See “binary-coded decimal (BCD).” binary — Relating to the base 2 number system. binary number system — The base 2 number system, having two digits, 0 and 1. Binary arithmetic is convenient in digital circuit design because digital circuits have two permissible voltage levels, low and high. The binary digits 0 and 1 can be interpreted to correspond to the two digital voltage levels. binary-coded decimal (BCD) — A notation that uses 4-bit binary numbers to represent the 10 decimal digits and that retains the same positional structure of a decimal number. For example,

234 (decimal) = 0010 0011 0100 (BCD) bit — A binary digit. A bit has a value of either logic 0 or logic 1.

MC68HC908AZ60A — Rev 1.1 Technical Data

Freescale Semiconductor Glossary 461

462 Glossary Freescale Semiconductor Freescale MC68HC908AZ60A1.1 —Rev Glossary 462 Technical Data computer operatingproperly module(COP) comparator clock generatormodule(CGM) clock clear CGM central processorunit(CPU) CCR C byte bus clock bus break interrupt breakpoint break module branch instruction Glossary — Thecarry/borrowbitinthe —Asetofwiresthat —Asetof —See“condition —Tochangeabitfrom —Asquarewavesignalusedto — See“clockgeneratormodule(CGM).” resets the MCUifa the resets the equalityorrelati crystal oscillatorcircuitandor base clocksignalfromwhichthesystemcl ofinstructions. execution the CPU controls shifts androtates). instructions alsoclear subtraction operationrequires when anadditionoperat four. frequency, f of thesamevaluethat address registers,theCPU number appearsontheinternaladdressbusthat program executionataprogrammablepoint location otherthanthe —Thebusclockisderived —Anumberwrittenintoth —Adevicethatcomparest —AmoduleintheM68HC0 —Asoftwareinterrupt eight bits. op —AninstructionthatcausestheCPU , isequaltothefrequencyofo code register.” llowed tooverflow. transfers logicsignals. ve differencesbetween or setthecarry/borrowbit(asin iswritteninthebr next sequentialaddress. logic 1to0; —Theprimaryfuncti ion producesacarry condition coderegist —Amoduleint executes thesoftwarein phase-lockedloop(PLL)circuit. a borrow.Somelogicalopera from theCGMOUToutputfr e breakaddressregistersof synchronize eventsinacomputer. caused bytheappearanceon he magnitudeoftwo 8 Family.Thebreakmodulea —Acountermodulein eak addressregisters. the oppositeofset. ocks arederived.TheCGMmayincludea he M68HC08Family.T twobinarynumbers. inordertoenter out ofbit7the oning unitof er. TheCPU08setsth scillator output,CGMXCLK,dividedby isthesameasnumberinbreak tocontinueprocessingatamemory terrupt instruction(SWI). bittestandbranc inputs. Adigitalco anycomputersystem.The om theCGM.Thebusclock tions anddata thebreakmodule.Whena a backgroundroutine. the M68HC08Familythat accumulator orwhena the internaladdressbus he CGMgeneratesa llows softwaretohalt e carry/borrowbit h instructionsand mparator defines manipulation Glossary

condition code register (CCR) — An 8-bit register in the CPU08 that contains the interrupt mask bit and five bits that indicate the results of the instruction just executed. control bit — One bit of a register manipulated by software to control the operation of the module. control unit — One of two major units of the CPU. The control unit contains logic functions that synchronize the machine and direct various operations. The control unit decodes instructions and generates the internal control signals that perform the requested operations. The outputs of the control unit drive the execution unit, which contains the arithmetic logic unit (ALU), CPU registers, and bus interface. COP — See "computer operating properly module (COP)." counter clock — The input clock to the TIM counter. This clock is the output of the TIM prescaler. CPU — See “central processor unit (CPU).” CPU08 — The central processor unit of the M68HC08 Family. CPU clock — The CPU clock is derived from the CGMOUT output from the CGM. The CPU clock frequency is equal to the frequency of the oscillator output, CGMXCLK, divided by

four. CPU cycles — A CPU cycle is one period of the internal bus clock, normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal. The length of time required to execute an instruction is measured in CPU clock cycles. CPU registers — Memory locations that are wired directly into the CPU logic instead of being part of the addressable memory map. The CPU always has direct access to the information in these registers. The CPU registers in an M68HC08 are: • A (8-bit accumulator) • H:X (16-bit index register) • SP (16-bit stack pointer) • PC (16-bit program counter) • CCR (condition code register containing the V, H, I, N, Z, and C bits) CSIC — customer-specified integrated circuit

cycle time — The period of the operating frequency: tCYC =1/fOP.

decimal number system — Base 10 numbering system that uses the digits zero through nine.

MC68HC908AZ60A — Rev 1.1 Technical Data

Freescale Semiconductor Glossary 463

duty cycle DMA servicerequest 464 Glossary Freescale Semiconductor Freescale MC68HC908AZ60A1.1 —Rev Glossary 464 Technical Data high byte hexadecimal H H full-duplex transmission free-running counter firmware fetch external interruptmodule(IRQ) exception EPROM EEPROM DMA direct memoryaccessmodule(DMA) Glossary —Thehalf-carrybitintheconditioncoderegist —Theupperbyteof —See"directmemory —Tocopydatafromamemory module to transfer data. transfer to module through F. appropriate corr accumulator (DAA)instructio bit isrequiredforbinary- the low-orderfourbitsoft received simultaneously. over tozeroand external interruptpinsa instructions in be erasedbyexposuretoanultraviolet memory thatcanbeel usually representedbyapercentage. and morecode-efficient transmitting orreceivingblocks transfers betweenanytwoCPU —Erasable,programmable, —Instructionsanddataprogram —Electricallyerasable, —Themostsignificant —Aneventsuchasaninte — Aratiooftheamount —Base16numberingsystem the mainprogram. —Adevicethatcounts —Asignalfromaper ection factor. the 16-bitindexregister begins countingagain. — Communicationon accessmodule(DMA)." ectrically reprogrammed. nd portpinsthatcanbe thanCPUinterrupts. coded decimalarithmeticope he accumulatorvaluetothehigh- —AmoduleintheM68HC0 programmable,read-onlyme eight bitsofaword. n usesthestateofH of timethesignalisonversust read-only memory.Anonvolatile locationintotheaccumulator. of datatoorfromperiphera rrupt oraresetthatstopsth -addressable locationswit —AM68HC08Fami med intononvolatilememory. ipheral totheDMAmodu that usesthedigits0 lightsourcea from zerotoapredeter (H:X)intheCPU08. er oftheCPU08.Thisbit a channelinwhichdatacanbesentand enabled asinterruptpins. nd thenreprogrammed. rations. Thedecimaladjust and Cbitstodeterminethe ly modulethatcanperformdata 8 Familywith mory. Anonvolatiletypeof hout CPU interv CPU hout order fourbits.Thehalf-carry ls, DMAtransfersarefaster e sequentialexecutionofthe he timeitisoff.Dutycycle through 9andthelettersA mined number,thenrolls typeofmemorythatcan le thatenablestheDMA indicates acarryfrom both dedicated ention. For Glossary

illegal address — An address not within the memory map illegal opcode — A nonexistent opcode. I — The interrupt mask bit in the condition code register of the CPU08. When I is set, all interrupts are disabled. index register (H:X) — A 16-bit register in the CPU08. The upper byte of H:X is called H. The lower byte is called X. In the indexed addressing modes, the CPU uses the contents of H:X to determine the effective address of the operand. H:X can also serve as a temporary data storage location. input/output (I/O) — Input/output interfaces between a computer system and the external world. A CPU reads an input to sense the level of an external signal and writes to an output to change the level on an external signal. instructions — Operations that a CPU can perform. Instructions are expressed by programmers as assembly language mnemonics. A CPU interprets an opcode and its associated operand(s) and instruction. interrupt — A temporary break in the sequential execution of a program to respond to signals from peripheral devices by executing a subroutine.

interrupt request — A signal from a peripheral to the CPU intended to cause the CPU to execute a subroutine. I/O — See “input/output (I/0).” IRQ — See "external interrupt module (IRQ)." jitter — Short-term signal instability. latch — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power is applied to the circuit. latency — The time lag between instruction completion and data movement. least significant bit (LSB) — The rightmost digit of a binary number. logic 1 — A voltage level approximately equal to the input power voltage (VDD). logic 0 — A voltage level approximately equal to the ground voltage (VSS). low byte — The least significant eight bits of a word. low voltage inhibit module (LVI) — A module in the M68HC08 Family that monitors power supply voltage.

MC68HC908AZ60A — Rev 1.1 Technical Data

Freescale Semiconductor Glossary 465

466 Glossary Freescale Semiconductor Freescale MC68HC908AZ60A1.1 —Rev Glossary 466 Technical Data nibble N multiplexer most significant MOR ROM monitor modulo counter microcontroller map memory memory location MCU mask optionregister(MOR) mask option mask mark/space M68HC08 LVI Glossary —Thenegativebitintheconditi —See"lowvoltage — Microcontroller unit. —See"maskoption —1.Alogiccircuitt —Asetoffourbi result. when anarithmetico input ontotheoutput. purposes. maximum possiblemodulus. memory, aclockoscillato the selectedmemorylocationplac location ontheaddressbusandasserts signal. Toreadinformat location ontheaddressbus, address. Tostoreinformationin certain MCUfeatures. disable. in integratedcircuitfabricati — A Freescale family of 8-bit MCUs. of8-bit family —AFreescale —Thelogic1/logic0conv — Adevicethatcanselectoneofanumber —Aoptionalmicrocontrolle —Apictorialrepresentati —AsectionofROMthatcanexecuteco —Microcontrollerunit(MCU).Acomp —Acounterthatcanbeprogrammedto bit(MSB) —EachM68HC08memorylocation inhibit module(LVI)." ts (halfofabyte). hat forcesabitorgro register (MOR)." register peration, logicaloperat —Theleftmostdigi See“microcontroller.” — AnEPROMlocation ion fromamemorylo r, andinput/output(I/O)on on coderegisterof on totransferan the datainformationondat amemorylocation, ention usedinformattingdat on ofallmemorylocations es itsdataontothebus. r featurethatthecustom up ofbitstoadesiredst t ofabinarynumber. ion, ordatamanipulationproducesanegative read signal.Inrespons image ontosilicon. cation, theCPUplaces theCPU08.TheCPU containing bitsthatenableordisable mmands fromahostcomputerfortesting holds onebyteofdataandhasaunique lete computersystem,includingaCPU, inputsandpassthelogiclevelofthat theCPUplaces count toanynumberfromzeroits a singleintegratedcircuit. er choosestoenableor inacomputersystem. a bus,andassertsthewrite a inserialcommunication. ate. 2.Aphotomaskused e tothereadsignal, sets thenegativebit theaddressof the addressof Glossary

object code — The output from an assembler or compiler that is itself executable machine code, or is suitable for processing to produce executable machine code. opcode — A binary code that instructs the CPU to perform an operation. open-drain — An output that has no pullup transistor. An external pullup device can be connected to the power supply to provide the logic 1 output voltage. operand — Data on which an operation is performed. Usually a statement consists of an operator and an operand. For example, the operator may be an add instruction, and the operand may be the quantity to be added. oscillator — A circuit that produces a constant frequency square wave that is used by the computer as a timing and sequencing reference. OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that cannot be reprogrammed. overflow — A quantity that is too large to be contained in one byte or one word. page zero — The first 256 bytes of memory (addresses $0000–$00FF). parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted. In a system that uses odd parity, every byte is expected to have an odd number of logic

1s. In an even parity system, every byte should have an even number of logic 1s. In the transmitter, a parity generator appends an extra bit to each byte to make the number of logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts the number of logic 1s in each byte. The parity checker generates an error signal if it finds a byte with an incorrect number of logic 1s. PC — See “program counter (PC).” peripheral — A circuit not under direct CPU control. phase-locked loop (PLL) — A oscillator circuit in which the frequency of the oscillator is synchronized to a reference signal. PLL — See "phase-locked loop (PLL)." pointer — Pointer register. An index register is sometimes called a pointer register because its contents are used in the calculation of the address of an operand, and therefore points to the operand. polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different

voltage levels, VDD and VSS. polling — Periodically reading a status bit to monitor the condition of a peripheral device. port — A set of wires for communicating with off-chip devices.

MC68HC908AZ60A — Rev 1.1 Technical Data

Freescale Semiconductor Glossary 467

ROM reset reserved memorylocation register read RC circuit serial SCI RAM PWM period push pulse-width modulation(PWM) pulse-width pullup pull program counter(PC) 468 Glossary Freescale Semiconductor Freescale MC68HC908AZ60A1.1 —Rev Glossary 468 Technical Data program prescaler Glossary —See"serialcommunicati —Aninstructionthatcopiesintotheaccu —Tocopythecontentsofamemo —Randomaccessmemory.All —Read-onlymemory.Atypeof —Aninstructionthatcopies —Toforceadeviceto —Pertainingtos unpredictable value. Writing toareservedloca until poweris The contentsofROMmustbespecif contents ofaRAMmemorylocationremainvali RAM addressisin signal withaconstantfrequency. of thepowersupply. —Atransistorintheoutputofalogicgateth stack RAMaddressisin the nextinstructio or operations. scale factorsuchas —Acircuitthatst —Asetofcomputerinstruct —Acircuitthatgenerates — Acircuitconsistingofcapacitorsand —Theamountofti —Thetimerequiredforonecomp turned off. turned —A16-bitregisterin equential transmission n oroperandthat the stackpointer. ores agroupofbits. 1/2,1/8,1/10etc. —Amemorylocationthatisused aknowncondition. thestackpointer. on interfacemodule(SCI)." tion hasnoeffect.Readingareservedlocation returnsan me asignalison — Controlledvariation(modulati thecontentsofaccumulatortostackRAM.The an outputsignalrelatedtothe RAMlocationscan ions thatcauseacomputerto memory thatcanbereadbut ry locationtotheaccumulator. the CPUwilluse. ied beforemanufacturingtheMCU. mulator thecontentsof the CPU08.ThePCregist over asingleline. lete cycleofaPWMwaveform. as opposedtobeing at connectstheoutput resistors havingade d untiltheCPUwrites be readorwritten only inspecialfa cannotbechanged(written). on) ofthepulsewidtha performadesi input signalbyafractional a stackRAMlocation.The in itsoffstate. er holdstheaddressof fined timeconstant. to thelogic1voltage by theCPU.The a differentvalueor ctory testmodes. red operation Glossary

serial communications interface module (SCI) — A module in the M68HC08 Family that supports asynchronous communication. serial peripheral interface module (SPI) — A module in the M68HC08 Family that supports synchronous communication. set — To change a bit from logic 0 to logic 1; opposite of clear. shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to them and that can shift the logic levels to the right or left through adjacent circuits in the chain. signed — A binary number notation that accommodates both positive and negative numbers. The most significant bit is used to indicate whether the number is positive or negative, normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the magnitude of the number. software — Instructions and data that control the operation of a microcontroller. software interrupt (SWI) — An instruction that causes an interrupt and its associated vector fetch. SPI — See "serial peripheral interface module (SPI)." stack — A portion of RAM reserved for storage of CPU register contents and subroutine return addresses. stack pointer (SP) — A 16-bit register in the CPU08 containing the address of the next available storage location on the stack. start bit — A bit that signals the beginning of an asynchronous serial transmission. status bit — A register bit that indicates the condition of a device. stop bit — A bit that signals the end of an asynchronous serial transmission. subroutine — A sequence of instructions to be used more than once in the course of a program. The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each place in the main program where the subroutine instructions are needed, a jump or branch to subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the flow of the main program to execute the instructions in the subroutine. When the RTS instruction is executed, the CPU returns to the main program where it left off. synchronous — Refers to logic circuits and operations that are synchronized by a common reference signal. TIM — See "timer interface module (TIM)."

MC68HC908AZ60A — Rev 1.1 Technical Data

Freescale Semiconductor Glossary 469

470 Glossary Freescale Semiconductor Freescale MC68HC908AZ60A1.1 —Rev Glossary 470 Technical Data toggle timer timer interfacemodule(TIM) Glossary tracking mode Z X write word wired-OR waveform voltage-controlled vector VCO variable V unimplemented memorylocation unbuffered two’s complement —Thezerobitinthecondition —Thelowerbyteoftheindex —Theoverflowbitinthecondi —See"voltage-controlledoscillator." —Thetransferofabyte — A set of two bytes (16 bits). (16 bytes setoftwo —A —Amoduleusedtorelateevents —Tochangethestateof high. frequency thatisc to serviceaninterruptorreset. —Amemorylocationthatco and BLTusetheoverflowbit. a two'scomplementoverflowoccurs.Thesi address reset. unpredictable value.Executing unimplemented locationhas each bitinthenumberand indicates negative).Thetwo’s most significantbitofatw frequency. Alsosee"acquisitionmode." an arithmeticoperation, —Avaluethatchangesduringt — Connectionofcircuit — Agraphicalrepresentationin — Utilizesonlyoneregist —Modeoflow-jitterPLLoperation —Ameansofperformingbi oscillator (VCO) ontrolled byadcvoltageap ofdatafromtheCPU logicaloperation,or — Amoduleusedtorelateevents tion coderegisterof register(H:X)intheCPU08. code registeroftheCPU08. Th o’s complementnumberindicate an outputfromalogic0 then adding1totheresult. outputs sothatifan —Amemorylocationthat no effect.Readinganunimple ntains theaddressofbeginni complement negativeofanum an opcodeatunimplementedlo — Acircuitthatpr er fordata;newdataov in asystemtopointtime. he courseofprogramexecution. whichtheamplitudeofawa nary subtractionusingaddi gned branchinstructi datamanipulationprodu theCPU08.TheCPU08 during whichthePLLislockedona toamemorylocation. plied toacontrolinput. y outputishigh,t oduces anoscillating to alogic1orfrom erwrites currentdata. is notused.Writingtoan e CPU08setsthezero bitwhen s thesignofnumber(1 in asystem toapointintime. mented locationreturnsan ber isobtainedbyinverting ng ofasubroutinewritten ve isplottedagainsttime. ons BGT,BGE,BLE, he connectionpointis cation causesanillegal tion techniques.The a logic1to0. ces aresult sets theVbitwhen output signalofa of$00. Technical Data — MC68HC08AZ60

Revision History

This section contains the revision history for the MC68HC08AZ60 advance information data book.

Revision Page Date Description Level Number(s)

July, 1.1 Updated to meet Freescale identity guidelines Throughout 2005

MC68HC08AZ60 — Rev 1.1 Technical Data

Freescale Semiconductor Revision History 471

472 Revision History Freescale Semiconductor Freescale MC68HC History Revision 472 Technical Data Revision History 08AZ60 — Rev 1.1 Rev — 08AZ60

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Rev. 1.1 MC68HC08AZ60/D July 14, 2005