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PCI Express (Pcie) for Keystone Devices User's Guide

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PCI Express (Pcie) for Keystone Devices User's Guide KeyStone Architecture Peripheral Component Interconnect Express (PCIe) User Guide Literature Number: SPRUGS6D September 2013 www.ti.com Release History Release Date Description/Comments D September 2013 Added "Byte Strobe Requirements" section (Page 2-25) Corrected "Endian Mode" column in "Big Endian Byte Swap for Outbound Transactions" table (Page 2-26) Updated description in "POSTED_WR_EN" field of CMD_STATUS register (Page 3-6) Added section of Power Domain and Module State Transitions Considerations (Page 2-34) Updated description of ACK_FREQ field in ACK_FREQ register. (Page 3-124) Updated description of MSI_IRQ register (Page 3-13) Updated PCIe local configuration registers offset to take account of 0x1000 address space offset (Page 3-62) Updated the description of REPLAY_TIMER bif field in SYS_NUM register (Page 3-127) Added one note in Inbound Translation section for 64-bit addressing usage in RC mode (Page 2-13) Added PHY loopback configuration steps for KeyStone I devices (Page 2-32) Corrected RX_LOS field description in SERDES_CFG0/1 registers: set 4h to be Enabled instead of 1h (Page 3-59) C November 2012 Added note for the SerDes related registers that are available only in KeyStone I devices (Page 3-4) Added SerDes configuration for KeyStone II devices section (Page 2-9) Updated FUNC field description in PID register (Page 3-5) Updated the description of BAR mask register usage (Page 2-16) Updated the description of BAR usage in RC mode (Page 2-16) Corrected the byte swapping in mode D and mode C in big endian byte swap table for outbound transaction (Page 2-26) Updated field descriptions of SERDES_CFG0 and SERDES_CFG1 registers. (Page 3-58) B March 2012 Corrected the description of CFG_TX_SWING (bit[18]) in PL_GEN2 register to be 0=Full Swing; 1=Low Swing (Page 3-133) Updated sticky field in the Registers section (Page 3-1) Corrected that the "soft reset resets the entire PCIESS except the sticky bits in MMRs" instead of "except the MMRs" (Page 2-34) Added one ECRC usage note in ECRC Generation and Checking section (Page 2-48) Added the common clock descriptions to the clock control section (Page 2-4) Deleted the statements of 100 MHz and 250 MHz in the clock section (Page 1-5) Corrected MSIn_IRQ_STATUS description from "write with a 0 to clear" to "write with 1 to clear" (Page 3-17) Deleted "250 MHz functional clock frequency operation (PIPE clock frequency)" from Features section to avoid confusion (Page 1-2) Added BAR Mask Registers to Configuration Type 1 Registers section (Page 3-79) Added BAR Mask Registers to Configuration Type 0 Registers section (Page 3-65) Modified master port and slave port access descriptions (Page 1-5) Added pcieAddr definition to EDMA transfer examples (Page 2-23) Modified buffer offset computation in EDMA transfer examples (Page 2-23) Added descriptions and examples of BAR Mask registers (Page 2-16) Modified MST_PRIV field description in PRIORITY register (Page 3-12) A December 2010 Added SERDES Configuration section (Page 2-5) Modified the Clock Control description (Page 2-4) Modified the Initialization Sequence for EP mode (Page 2-28) Modified the Initialization Sequence for RC mode (Page 2-27) Modified the Reset Consideration description (Page 2-34) SPRUGS6 November 2010 Initial Release ø-ii KeyStone Architecture Peripheral Component Interconnect Express (PCIe) User Guide SPRUGS6D—September 2013 Submit Documentation Feedback www.ti.com Contents Contents Release History. ø-ii List of Tables . ø-xii List of Figures . .ø-xvi List of Examples. ø-xx Preface ø-xxi About This Manual. ø-xxi Notational Conventions. ø-xxi Related Documentation from Texas Instruments . .ø-xxii Trademarks. .ø-xxii Chapter 1 Introduction 1-1 1.1 Purpose of the Peripheral . 1-2 1.2 Terminology Used in This Document . 1-2 1.3 Features . 1-2 1.4 Functional Block Diagram . 1-4 1.4.1 PCI Express Core Module . .1-4 1.4.2 PCI Express PHY Interface . .1-4 1.4.3 VBUSM (Configuration and DMA Access Interface) . .1-5 1.4.4 Clock, Reset, Power Control Logic. .1-5 1.4.5 Interrupts. .1-5 1.4.6 PCIe Power/Ground/Termination . .1-5 1.4.7 Differential Data Lines. .1-5 1.5 Supported Use Case Statement. 1-5 1.6 Industry Standard(s) Compliance Statement . 1-5 Chapter 2 Architecture 2-1 2.1 Protocol Description(s). 2-2 2.1.1 PCI Express Topology . .2-2 2.1.2 Serial Link. .2-2 2.1.3 Supported PCI Express Transactions . .2-3 2.2 Clock Control . 2-4 2.3 SerDes Configuration for KeyStone I Devices. 2-5 2.3.1 SerDes Configuration Registers . .2-5 2.3.1.1 PCIe SerDes Configuration Register (PCIE_SERDES_CFGPLL). .2-5 2.3.1.2 PCIe SerDes Status Register (PCIE_SERDES_STS) . .2-6 2.3.2 Enabling the PLL . .2-7 2.3.3 Reference Clock Multiplication . .2-8 2.4 SerDes Configuration for KeyStone II Devices . 2-9 2.5 Signal Descriptions . 2-9 2.6 Pin Multiplexing . 2-9 2.7 Address Translation . 2-9 2.7.1 Outbound Address Translation . .2-10 2.7.1.1 Transactions Violating Address Translation Boundaries . .2-12 2.7.2 Inbound Address Translation . .2-12 2.7.2.1 Mapping Multiple Non-Contiguous Memory Ranges To One Region. .2-14 2.7.2.2 BAR0 Exception for In-Bound Address Translation . .2-15 2.7.2.3 Using BAR1 Value As Start Address ..
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