Appendix A Example for Up-Down Counter

This appendix contains the source files used in the up-down counter studied in Example 4.4, as well as the resulting output produced by MBAC. The counter to be verified is shown below in the Verilog language in the file udcounter.v. The as- sertions used to verify the counter are coded in PSL in the udcounter.psl file that follows. Additionally, the set of SVA assertions is added inline to the design file. These as- sertions were used in Subsection 9.3.1 for benchmarking the SVA checkers. MBAC can concurrently process both PSL and SVA assertions that are simultaneously present in the same design. The third file in this example contains the assertion checkers produced by the checker generator (udcounter psl.v). The file contains two Verilog modules with four checkers each, corresponding to SVA assertions and the PSL assertions respec- tively. The checkers are also expressed in Verilog HDL, and allow the assertions to be embedded in the design under verification during hardware emulation in the veri- fication stages, or in the fabricated integrated circuit for at-speed silicon debugging. The command given to the checker generator in this example is as follows:

MBAC udcounter.psl udcounter.v

udcounter.v:

//---MBAC example--- //This is a simple up-down counter that we want to verify //The PSL assertions for this example are in udcounter.psl //The SVA assertions are in the module below //To produce the checkers run: "mbac udcounter.psl udcounter.v" //The result is udcounter_psl.v, containing two Verilog modules: // one module contains SVA checkers, the other has PSL checkers module udcounter(cnt, load, en_load, en_ud, up_ndown, clk,reset); parameter width = 8;

259 260 A Example for Up-Down Counter

output reg [width-1:0] cnt; input [width-1:0] load; input en_load, en_ud, up_ndown, clk, reset;

always @(posedge clk) if (!reset) cnt <= 0; else if (en_load) cnt <= load; else if (en_ud) if (up_ndown) cnt <= cnt+1; else cnt <= cnt-1;

//if no count nor load, value should not change assert property (@(posedge clk) (!en_ud && !en_load) |=> stable(cnt));

//ensure load works assert property (@(posedge clk) (en_load) |-> ##1 (cnt == $past(load)));

//no roll-over assert property (@(posedge clk) (!en_load) |-> ##1 (!(cnt == ˜$past(cnt) && cnt[width-1]==cnt[0])));

//no inactivity assert property (@(posedge clk) not (!en_load && !en_ud)[*10]); endmodule //udcounter udcounter.psl: vunit vu1(udcounter){ default clock = (posedge clk);

//if no count nor load, value should not change assert always {!en_ud && !en_load} |=> stable(cnt);

//ensure load works assert always en_load -> next (cnt == prev(load));

//no roll-over assert always !en_load -> next (!(cnt == ˜prev(cnt) && cnt[width-1]==cnt[0]));

//no inactivity assert never (!en_load && !en_ud)[*10]; } A Example for Up-Down Counter 261 udcounter psl.v:

//Generated by MBAC v2.01 //23-3-2008, 22h 13m 19s //------

//RESET_POLARITY_SYMBOL, set to ! (blank) for active low (high) ‘define MBACRPS !

//Assertion circuit for vunit: inline //vunit is bound to module: udcounter module udcounter_psl_inline (udc_inline_out, reset, en_ud, en_load, cnt, clk, load); parameter width = 8; output [4:1] udc_psl_inline_out; input reset, en_ud, en_load, clk; input [width - 1:0] cnt; input [width - 1:0] load;

reg [width - 1:0] s1; wire [2:0] s3s; reg [2:0] s3sq; reg [width - 1:0] s4; wire [2:0] s5s; reg [2:0] s5sq; reg [width - 1:0] s6; wire [2:0] s7s; reg [2:0] s7sq; wire [10:0] s8s; reg [10:0] s8sq; wire s2; reg ASR_1, ASR_2, ASR_3, ASR_4;

assign udc_psl_inline_out={ASR_4, ASR_3, ASR_2, ASR_1};

//------//ASR_1 : assert property ( @(posedge clk) // ( ! en_ud && ! en_load ) |=> stable(cnt) ); //------always @(posedge clk) s1<=cnt; assign s2 = s1 == cnt; always @(posedge clk) if (‘MBACRPS reset) s3sq<=3’h4; else s3sq<=s3s; assign s3s={1’b1, ((! en_ud) && (! en_load)), (s3sq[1] && !(s2))}; always @(posedge clk) if (‘MBACRPS reset) ASR_1<=0; else ASR_1 <= (s3s[0]);

//------//ASR_2 : assert property ( @(posedge clk) ( en_load ) |-> ##1 // ( cnt == $past(load) ) ); //------262 A Example for Up-Down Counter

always @(posedge clk) s4<=load; always @(posedge clk) if (‘MBACRPS reset) s5sq<=3’h4; else s5sq<=s5s; assign s5s={1’b1, en_load, (s5sq[1] && !((cnt == s4)))}; always @(posedge clk) if (‘MBACRPS reset) ASR_2<=0; else ASR_2 <= (s5s[0]);

//------//ASR_3 : assert property ( @(posedge clk) ( !en_load ) |-> ##1 // ( ! ( cnt == ˜$past(cnt) && cnt[width-1] == cnt[0] ) ) ); //------always @(posedge clk) s6<=cnt; always @(posedge clk) if (‘MBACRPS reset) s7sq<=3’h4; else s7sq<=s7s; assign s7s={1’b1, !(en_load), (s7sq[1] && ((cnt == (˜ s6)) && (cnt[width-1] == cnt[0])))}; always @(posedge clk) if (‘MBACRPS reset) ASR_3<=0; else ASR_3 <= (s7s[0]);

//------//ASR_4 : assert property ( @(posedge clk) // not ( ! en_load && ! en_ud )[*10] ); //------always @(posedge clk) if (‘MBACRPS reset) s8sq<=11’h400; else s8sq<=s8s; assign s8s={1’b1, ((! en_load) && (! en_ud)), (s8sq[9] && ((! en_load) && (! en_ud))), (s8sq[8] && ((! en_load) && (! en_ud))), (s8sq[7] && ((! en_load) && (! en_ud))), (s8sq[6] && ((! en_load) && (! en_ud))), (s8sq[5] && ((! en_load) && (! en_ud))), (s8sq[4] && ((! en_load) && (! en_ud))), (s8sq[3] && ((! en_load) && (! en_ud))), (s8sq[2] && ((! en_load) && (! en_ud))), (s8sq[1] && ((! en_load) && (! en_ud)))}; always @(posedge clk) if (‘MBACRPS reset) ASR_4<=0; else ASR_4 <= (s8s[0]); endmodule //udcounter_psl_inline /*Instantiation code: udcounter_psl_inline #(width) i_udcounter_psl_inline ( udc_psl_inline_out, reset, en_ud, en_load, cnt, clk, load); */ //End of circuit(s) for vunit: inline

//Assertion circuit for vunit: vu1 //vunit is bound to module: udcounter A Example for Up-Down Counter 263 module udcounter_psl_vu1 (udcounter_psl_vu1_out, reset, clk, en_ud, en_load, cnt, load); parameter width = 8; output [4:1] udcounter_psl_vu1_out; input reset, clk, en_ud, en_load; input [width - 1:0] cnt; input [width - 1:0] load;

reg [width - 1:0] s1; wire [2:0] s3s; reg [2:0] s3sq; reg [width - 1:0] s4; wire [2:0] s5s; reg [2:0] s5sq; reg [width - 1:0] s6; wire [2:0] s7s; reg [2:0] s7sq; wire [10:0] s8s; reg [10:0] s8sq; wire s2; reg ASR_1, ASR_2, ASR_3, ASR_4;

assign udcounter_psl_vu1_out={ASR_4, ASR_3, ASR_2, ASR_1};

//------//ASR_1 : assert always {! en_ud && ! en_load} |=> stable(cnt); //------always @(posedge clk) s1<=cnt; assign s2 = s1 == cnt; always @(posedge clk) if (‘MBACRPS reset) s3sq<=3’h4; else s3sq<=s3s; assign s3s={1’b1, ((! en_ud) && (! en_load)), (s3sq[1] && !(s2))}; always @(posedge clk) if (‘MBACRPS reset) ASR_1<=0; else ASR_1 <= (s3s[0]);

//------//ASR_2 : assert always en_load -> next ( cnt == prev(load) ); //------always @(posedge clk) s4<=load; always @(posedge clk) if (‘MBACRPS reset) s5sq<=3’h4; else s5sq<=s5s; assign s5s={1’b1, en_load, (s5sq[1] && !((cnt == s4)))}; always @(posedge clk) if (‘MBACRPS reset) ASR_2<=0; else ASR_2 <= (s5s[0]);

//------//ASR_3 : assert always !en_load -> next // ( !( cnt == ˜prev(cnt) && cnt[width - 1] == cnt[0] ) ); 264 A Example for Up-Down Counter

//------always @(posedge clk) s6<=cnt; always @(posedge clk) if (‘MBACRPS reset) s7sq<=3’h4; else s7sq<=s7s; assign s7s={1’b1, !(en_load), (s7sq[1] && ((cnt == (˜ s6)) && (cnt[width-1] == cnt[0])))}; always @(posedge clk) if (‘MBACRPS reset) ASR_3<=0; else ASR_3 <= (s7s[0]);

//------//ASR_4 : assert never ( ! en_load && ! en_ud )[*10]; //------always @(posedge clk) if (‘MBACRPS reset) s8sq<=11’h400; else s8sq<=s8s; assign s8s={1’b1, ((! en_load) && (! en_ud)), (s8sq[9] && ((! en_load) && (! en_ud))), (s8sq[8] && ((! en_load) && (! en_ud))), (s8sq[7] && ((! en_load) && (! en_ud))), (s8sq[6] && ((! en_load) && (! en_ud))), (s8sq[5] && ((! en_load) && (! en_ud))), (s8sq[4] && ((! en_load) && (! en_ud))), (s8sq[3] && ((! en_load) && (! en_ud))), (s8sq[2] && ((! en_load) && (! en_ud))), (s8sq[1] && ((! en_load) && (! en_ud)))}; always @(posedge clk) if (‘MBACRPS reset) ASR_4<=0; else ASR_4 <= (s8s[0]); endmodule //udcounter_psl_vu1 /*Instantiation code: udcounter_psl_vu1 #(width) i_udcounter_psl_vu1 ( udcounter_psl_vu1_out, reset, clk, en_ud, en_load, cnt, load); */ //End of circuit(s) for vunit: vu1 References

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A for SVA properties 219 for SVA sequences 212 abort 65, 132 for SVA verification statements 225 ABV methodology 17 Automaton flushing 161 Accepting state 39 Activations 29, 65, 156, 159, 169 B Activity monitoring 163 AddLiteral algorithm 132 Buchi¨ automaton 45 Alphabet 38, 46 BaseCase automata algorithm 110 power set 52, 84 before family of operators 66 semantic 46 rewrite rules 136, 137 symbolic 84, 86 Binary decision diagram 90 syntactic 46 Booleans Alternating in PSL 58, 106 automaton 45 in SVA 73, 209 Buchi¨ automaton 45 Branching time logic 28 always 65, 81 Built-in functions 58, 107 rewrite rule 135 and see Conjunction of SVA properties, C Intersection of SVA sequences assert 14, 68, 81, 152, 225 Checker 20 Assertion 4, 16 creating from automata 100 -based verification 4 generator 20 adoption 16 FoCs 51, 180 as documentation 17 MBAC 6 grouping 27, 176 in formal verification 240 partitioning algorithm 177 output signal 88, 101, 180 in software 13 Choice signal 20, 101 automata algorithm 113 Automata splitting 156, 218 of automata 39 Automated theorem proving 140 of SEREs 60, 113 Automaton construction Clock declaration 255 for PSL Booleans 110 in PSL 68, 106, 152 for PSL properties 124 in SVA 81, 225 for PSL sequences 111 Collapsing final states 95 for PSL verification directives 152 algorithm 96 for SVA Booleans 211 Compilation strategies 157, 160

275 276 Index

Complementation of automata 42, 98 E algorithm 98 Complete ε DFA 40 closure 41 transition relation 86 removal 41 Completion of assertions 165, 227 symbol 39 Computation tree logic 30 transition 39, 87 Concatenation Edge 39, 86 automata algorithm 113 Empty of automata 39, 119 automaton 39, 115 of SEREs 60, 112 language 38 Concurrent assertions 208 sequence 62, 78, 115 Conjunction SERE 61 of PSL properties 65, 133 Emulation 19, 26 of SVA properties 80, 221 End of execution 24, 33, 51, 66, 115, 131, Counters 161, 227, 249 for assert 167 End of simulation 23, 51 for cover 167 ended 58, 74, 108, 211 countones 59 Equivalence cover 68, 81, 152, 160, 226 of Booleans 58, 107 automaton algorithm in SVA 226 of checkers 180 Coverage 19, 168 of PSL properties 65, 127 of PSL properties see Completion of eventually! 66 assertions more efficient implementation 160 Cycle delay in SVA sequences 76, 213 rewrite rules 137, 138, 160 automaton algorithm 214 Executable specification 3 rewrite rules 216 Existential automaton 45 Extended symbol 87 D F De Morgan’s law 133, 221 Degenerate sequences 62, 137 Failure matching 127, 220 Dependencies, reporting signal 163 algorithm 129 Deterministic finite automaton 40 false 58, 74, 107, 209 Determinization Fault 3 of automata 41 $fell 75, 210 strong 91, 95 fell 58, 108 algorithm 93 Final state 39 strong with completion 98 Finite automaton algorithm 99 as used in MBAC 86 weak 91, 93, 95 classical definition 38 algorithm 92 first match 78, 216 Dff() 108, 210 automaton algorithm 166 disable iff 80, 211, 224 forall 64 Disjunction Fusion of automata see Choice of automata automata algorithm 116 of literals 87 of SEREs 60, 115 of PSL properties 65 of SVA sequences 77 rewrite rule 134 of SEREs see Choice of SEREs G of SVA properties 80, 221 of SVA sequences 78, 215 Goto repetition Dispatcher circuit 169 of SEREs 60 Dynamic verification 18 rewrite rules 122 Index 277

of SVA sequences 77 Liveness property 31 rewrite rules 217 bounded liveness 32 Local variables 256 H in PSL 256 in SVA 72, 256 HDL construction for automata 101 M for PSL Booleans 106 for SVA Booleans 209 Minimization algorithm 95 I of automata 94 Miter approach 181 if / else 80, 224 Model checking 15, 44, 180, 240 Immediate assertions 208 Monitoring, with checkers 173, 175 Implication in Booleans 58, 107 N in PSL properties 65 rewrite rule 135 Negation initial 81, 228 algorithm 98 Initial state(s) 39, 86, 88, 101 for failure matching 128 Inline assertions 259 of a PSL property 65, 127 intersect see Intersection of SVA Network on Chip 185, 257 sequences never 65 Intersection rewrite rule 135 automata algorithm 117 next! 66 of automata 43 rewrite rule 139 of PSL properties see Conjunction of PSL next 59, 65 properties rewrite rule 139 of regular expressions 43 next (extended forms) 66 of SEREs 60, 116 rewrite rules 136, 137, 139, 140 rewrite rule 120 Nonconsecutive repetition of SVA properties see Conjunction of of SEREs 61 SVA properties rewrite rules 123 of SVA sequences 78, 215 of SVA sequences 77 automata algorithm 215 rewrite rules 217 isunknown 59 nondet 59 nondet vector 59 K Nondeterminism 84, 95, 221 Nondeterministic finite automaton 40 Kleene closure not 79, 220 automaton algorithm 115 Null of a regular expression 38 automaton 39, 115, 130 of a SERE 60, 113 language 38 of an automaton 39 sequence 62, 79, 115 SERE 62 L O Label of a state 86, 92 Language 38 $onehot 75, 210 Letter 39 onehot 58, 108 Linear temporal logic 28 $onehot0 75, 210 in PSL 64 onehot0 58, 108 in SVA 256 Open Vera assertions 53 Literal 87 Open verification library 54, 184 278 Index

Order Repetition partial 92 automaton algorithm 119 total 87, 92 of SEREs 60, 118 rewrite rules 121 P of SVA sequences 77, 215 Replication $past 75, 210 of a PSL property 64, 126 Path 28 automata algorithm 127 Pattern matching 39, 44 Reversal Polarity algorithm 94 in automata for SVA properties 218, 223, of an automaton 94 225 Reversible circuits 257 of a literal 87 Rewrite rules 69, 134 of checker outputs 180 $rose 75, 210 of signals 88 rose 58, 108 Post-fabrication debugging 16, 19, 27 with checkers 173 S Precedence of PSL property operators 64 Safety property 31 of PSL sequence operators 60 Satisfaction of SVA property operators 79 levels of properties 33 of SVA sequence operators 76 Satisfiability 257 of Verilog operators 56 Self-test, with checkers 174 Precondition automaton 156, 169, 218 Semantics prev 58, 108 of LTL 29 Primary symbol 86 run time 23, 26, 35, 68, 202, 221 Product Sequence automaton 43, 116 in PSL 59 construction 43 in SVA 75 Programmable logic 19, 27, 175 instantiation 63, 79 Property Sequent 143 in PSL 62 SERE 59 in SVA 79 Silicon debugging see Post-fabrication instantiation 63, 79 debugging specification language 55 Simple subset 56, 218, 255 layers 57 Simulation 19 Propositions acceleration 26 atomic 29 of assertions 25 Skolem constants 143 Q Skolemizing 143, 145 Software testing 257 Quality 2 Specification 3 Quality improvement 3 $stable 75, 210 stable 58, 108 R Static verification 18 Status monitoring 19 Range Repetition automaton algorithm see Strength Repetition automaton algorithm of an operator 33 RDRD algorithm 94 of satisfaction 33 Recursive compilation strategies see Strong Compilation strategies failure matching 131 Redundancy control using checkers 175 automata algorithm 131 Regular expressions 38 properties 66 derivatives 52 sequence 64, 220 Index 279

Subset U -sum 177 construction 41, 91, 93 Unconnected states 94 Suffix implication Universal automaton 45 in PSL 67, 133 until family of operators 66 rewrite rule 135 rewrite rules 136, 138 in SVA 80, 222, 223 Sugaring V in LTL 30 in SEREs 61, 111, 120 in SVA sequences 78, 212 Vacuity 46, 165 System Vacuous success 46 functions 75, 209 Validation 2 on Chip 16 Verification 3 SystemVerilog 71 directives (PSL) 68 SystemVerilog assertions 70 gap 2 statements (SVA) 81 T Verilog arithmetic operators 56 Temporal logic 28 bitwise operators 57 Terminating (rewrite rule) 69 constants 56 Test language 56 pattern generation 174 logical operators 57 sequence generation 174 Void precondition 157 Testing 2 vunit 68, 152, 180 Threading, of assertions 168 throughout 78 W rewrite rule 217 Trace 28, 86, 141 within 60, 78 distance 201 PSL rewrite rule 121 Transaction level modeling 257 rewrite rule 217 Transition see Edge Word 39 relation 39, 86 Trivial validity 46, 165 true 58, 74, 87, 107, 209 Z automaton 130 Truth assignment ω 87 Zero Defects 3