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Example for Up-Down Counter Appendix A Example for Up-Down Counter This appendix contains the source files used in the up-down counter studied in Example 4.4, as well as the resulting output produced by MBAC. The counter to be verified is shown below in the Verilog language in the file udcounter.v. The as- sertions used to verify the counter are coded in PSL in the udcounter.psl file that follows. Additionally, the set of SVA assertions is added inline to the design file. These as- sertions were used in Subsection 9.3.1 for benchmarking the SVA checkers. MBAC can concurrently process both PSL and SVA assertions that are simultaneously present in the same design. The third file in this example contains the assertion checkers produced by the checker generator (udcounter psl.v). The file contains two Verilog modules with four checkers each, corresponding to SVA assertions and the PSL assertions respec- tively. The checkers are also expressed in Verilog HDL, and allow the assertions to be embedded in the design under verification during hardware emulation in the veri- fication stages, or in the fabricated integrated circuit for at-speed silicon debugging. The command given to the checker generator in this example is as follows: MBAC udcounter.psl udcounter.v udcounter.v: //---MBAC example--- //This is a simple up-down counter that we want to verify //The PSL assertions for this example are in udcounter.psl //The SVA assertions are in the module below //To produce the checkers run: "mbac udcounter.psl udcounter.v" //The result is udcounter_psl.v, containing two Verilog modules: // one module contains SVA checkers, the other has PSL checkers module udcounter(cnt, load, en_load, en_ud, up_ndown, clk,reset); parameter width = 8; 259 260 A Example for Up-Down Counter output reg [width-1:0] cnt; input [width-1:0] load; input en_load, en_ud, up_ndown, clk, reset; always @(posedge clk) if (!reset) cnt <= 0; else if (en_load) cnt <= load; else if (en_ud) if (up_ndown) cnt <= cnt+1; else cnt <= cnt-1; //if no count nor load, value should not change assert property (@(posedge clk) (!en_ud && !en_load) |=> stable(cnt)); //ensure load works assert property (@(posedge clk) (en_load) |-> ##1 (cnt == $past(load))); //no roll-over assert property (@(posedge clk) (!en_load) |-> ##1 (!(cnt == ˜$past(cnt) && cnt[width-1]==cnt[0]))); //no inactivity assert property (@(posedge clk) not (!en_load && !en_ud)[*10]); endmodule //udcounter udcounter.psl: vunit vu1(udcounter){ default clock = (posedge clk); //if no count nor load, value should not change assert always {!en_ud && !en_load} |=> stable(cnt); //ensure load works assert always en_load -> next (cnt == prev(load)); //no roll-over assert always !en_load -> next (!(cnt == ˜prev(cnt) && cnt[width-1]==cnt[0])); //no inactivity assert never (!en_load && !en_ud)[*10]; } A Example for Up-Down Counter 261 udcounter psl.v: //Generated by MBAC v2.01 //23-3-2008, 22h 13m 19s //-------------------------------------------- //RESET_POLARITY_SYMBOL, set to ! (blank) for active low (high) ‘define MBACRPS ! //Assertion circuit for vunit: inline //vunit is bound to module: udcounter module udcounter_psl_inline (udc_inline_out, reset, en_ud, en_load, cnt, clk, load); parameter width = 8; output [4:1] udc_psl_inline_out; input reset, en_ud, en_load, clk; input [width - 1:0] cnt; input [width - 1:0] load; reg [width - 1:0] s1; wire [2:0] s3s; reg [2:0] s3sq; reg [width - 1:0] s4; wire [2:0] s5s; reg [2:0] s5sq; reg [width - 1:0] s6; wire [2:0] s7s; reg [2:0] s7sq; wire [10:0] s8s; reg [10:0] s8sq; wire s2; reg ASR_1, ASR_2, ASR_3, ASR_4; assign udc_psl_inline_out={ASR_4, ASR_3, ASR_2, ASR_1}; //--------------- //ASR_1 : assert property ( @(posedge clk) // ( ! en_ud && ! en_load ) |=> stable(cnt) ); //--------------- always @(posedge clk) s1<=cnt; assign s2 = s1 == cnt; always @(posedge clk) if (‘MBACRPS reset) s3sq<=3’h4; else s3sq<=s3s; assign s3s={1’b1, ((! en_ud) && (! en_load)), (s3sq[1] && !(s2))}; always @(posedge clk) if (‘MBACRPS reset) ASR_1<=0; else ASR_1 <= (s3s[0]); //--------------- //ASR_2 : assert property ( @(posedge clk) ( en_load ) |-> ##1 // ( cnt == $past(load) ) ); //--------------- 262 A Example for Up-Down Counter always @(posedge clk) s4<=load; always @(posedge clk) if (‘MBACRPS reset) s5sq<=3’h4; else s5sq<=s5s; assign s5s={1’b1, en_load, (s5sq[1] && !((cnt == s4)))}; always @(posedge clk) if (‘MBACRPS reset) ASR_2<=0; else ASR_2 <= (s5s[0]); //--------------- //ASR_3 : assert property ( @(posedge clk) ( !en_load ) |-> ##1 // ( ! ( cnt == ˜$past(cnt) && cnt[width-1] == cnt[0] ) ) ); //--------------- always @(posedge clk) s6<=cnt; always @(posedge clk) if (‘MBACRPS reset) s7sq<=3’h4; else s7sq<=s7s; assign s7s={1’b1, !(en_load), (s7sq[1] && ((cnt == (˜ s6)) && (cnt[width-1] == cnt[0])))}; always @(posedge clk) if (‘MBACRPS reset) ASR_3<=0; else ASR_3 <= (s7s[0]); //--------------- //ASR_4 : assert property ( @(posedge clk) // not ( ! en_load && ! en_ud )[*10] ); //--------------- always @(posedge clk) if (‘MBACRPS reset) s8sq<=11’h400; else s8sq<=s8s; assign s8s={1’b1, ((! en_load) && (! en_ud)), (s8sq[9] && ((! en_load) && (! en_ud))), (s8sq[8] && ((! en_load) && (! en_ud))), (s8sq[7] && ((! en_load) && (! en_ud))), (s8sq[6] && ((! en_load) && (! en_ud))), (s8sq[5] && ((! en_load) && (! en_ud))), (s8sq[4] && ((! en_load) && (! en_ud))), (s8sq[3] && ((! en_load) && (! en_ud))), (s8sq[2] && ((! en_load) && (! en_ud))), (s8sq[1] && ((! en_load) && (! en_ud)))}; always @(posedge clk) if (‘MBACRPS reset) ASR_4<=0; else ASR_4 <= (s8s[0]); endmodule //udcounter_psl_inline /*Instantiation code: udcounter_psl_inline #(width) i_udcounter_psl_inline ( udc_psl_inline_out, reset, en_ud, en_load, cnt, clk, load); */ //End of circuit(s) for vunit: inline //Assertion circuit for vunit: vu1 //vunit is bound to module: udcounter A Example for Up-Down Counter 263 module udcounter_psl_vu1 (udcounter_psl_vu1_out, reset, clk, en_ud, en_load, cnt, load); parameter width = 8; output [4:1] udcounter_psl_vu1_out; input reset, clk, en_ud, en_load; input [width - 1:0] cnt; input [width - 1:0] load; reg [width - 1:0] s1; wire [2:0] s3s; reg [2:0] s3sq; reg [width - 1:0] s4; wire [2:0] s5s; reg [2:0] s5sq; reg [width - 1:0] s6; wire [2:0] s7s; reg [2:0] s7sq; wire [10:0] s8s; reg [10:0] s8sq; wire s2; reg ASR_1, ASR_2, ASR_3, ASR_4; assign udcounter_psl_vu1_out={ASR_4, ASR_3, ASR_2, ASR_1}; //--------------- //ASR_1 : assert always {! en_ud && ! en_load} |=> stable(cnt); //--------------- always @(posedge clk) s1<=cnt; assign s2 = s1 == cnt; always @(posedge clk) if (‘MBACRPS reset) s3sq<=3’h4; else s3sq<=s3s; assign s3s={1’b1, ((! en_ud) && (! en_load)), (s3sq[1] && !(s2))}; always @(posedge clk) if (‘MBACRPS reset) ASR_1<=0; else ASR_1 <= (s3s[0]); //--------------- //ASR_2 : assert always en_load -> next ( cnt == prev(load) ); //--------------- always @(posedge clk) s4<=load; always @(posedge clk) if (‘MBACRPS reset) s5sq<=3’h4; else s5sq<=s5s; assign s5s={1’b1, en_load, (s5sq[1] && !((cnt == s4)))}; always @(posedge clk) if (‘MBACRPS reset) ASR_2<=0; else ASR_2 <= (s5s[0]); //--------------- //ASR_3 : assert always !en_load -> next // ( !( cnt == ˜prev(cnt) && cnt[width - 1] == cnt[0] ) ); 264 A Example for Up-Down Counter //--------------- always @(posedge clk) s6<=cnt; always @(posedge clk) if (‘MBACRPS reset) s7sq<=3’h4; else s7sq<=s7s; assign s7s={1’b1, !(en_load), (s7sq[1] && ((cnt == (˜ s6)) && (cnt[width-1] == cnt[0])))}; always @(posedge clk) if (‘MBACRPS reset) ASR_3<=0; else ASR_3 <= (s7s[0]); //--------------- //ASR_4 : assert never ( ! en_load && ! en_ud )[*10]; //--------------- always @(posedge clk) if (‘MBACRPS reset) s8sq<=11’h400; else s8sq<=s8s; assign s8s={1’b1, ((! en_load) && (! en_ud)), (s8sq[9] && ((! en_load) && (! en_ud))), (s8sq[8] && ((! en_load) && (! en_ud))), (s8sq[7] && ((! en_load) && (! en_ud))), (s8sq[6] && ((! en_load) && (! en_ud))), (s8sq[5] && ((! en_load) && (! en_ud))), (s8sq[4] && ((! en_load) && (! en_ud))), (s8sq[3] && ((! en_load) && (! en_ud))), (s8sq[2] && ((! en_load) && (! en_ud))), (s8sq[1] && ((! en_load) && (! en_ud)))}; always @(posedge clk) if (‘MBACRPS reset) ASR_4<=0; else ASR_4 <= (s8s[0]); endmodule //udcounter_psl_vu1 /*Instantiation code: udcounter_psl_vu1 #(width) i_udcounter_psl_vu1 ( udcounter_psl_vu1_out, reset, clk, en_ud, en_load, cnt, load); */ //End of circuit(s) for vunit: vu1 References 1. Yael Abarbanel, Ilan Beer, Leonid Glushovsky, Sharon Keidar, and Yaron Wolfsthal. FoCs: Automatic Generation of Simulation Checkers from Formal Specifications. In Proceedings of the 12th International Conference on Computer Aided Verification (CAV’00), pages 538–542, 2000. 2. Miron Abramovici, Paul Bradley, Kumar Dwarakanath, Peter Levin, Gerard Memmi, and Dave Miller. A Reconfigurable Design-for-Debug Infrastructure for SoCs. In Proceedings of the 43rd Design Automation Conference (43rd DAC), pages 7–12, 2006. 3. Miron Abramovici, Melvin Breuer, and Arthur Friedman. Digital Systems Testing & Testable Design. Computer Science Press, New York, 1990. 4. Hussain Al-Asaad, Brian Murray, and John P. Hayes. Online BIST for Embedded Systems. IEEE Design & Test of Computers, 15(4):17–24, 1998. 5. Paul Ammann and Jeff Coffutt. Introduction to Software Testing. Cambridge University Press, New York, 2008. 6. Roy Armoni, Limor Fix, Alon Flaisher, Rob Gerth, Boris Ginsburg, Tomer Kanza, Avner Landver, Sela Mador-Haim, Eli Singerman, Andreas Tiemeyer, Moshe Y. Vardi, and Yael Zbar. The ForSpec Temporal Logic: A New Temporal Property-Specification Language. In Proceedings of the 2002 International Conference on
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