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Design of Fractional-Order Circuits with Reduced Spread of Element Values

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Design of Fractional-Order Circuits with Reduced Spread of Element Values Design of Fractional-Order Circuits with Reduced Spread of Element Values Stavroula Kapoulea (RN: 1058034) Department of Physics University of Patras This dissertation is submitted for the degree of Master of Science Supervisor: Costas Psychalinos, Professor Electronics Laboratory March 2018 Design of Fractional-Order Circuits with Reduced Spread of Element Values MSc Thesis Stavroula Kapoulea R.N. 1058034 Examination Committee: C.Psychalinos G.Economou S.Vlassis Approved by the three-member examination committee on March 29, 2018 C.Psychalinos G.Economou S.Vlassis Professor Professor Associate Professor Acknowledgements The present Master Thesis has been performed within the MSc curriculum in “Electronics and Communications (Radioelectrology)”, offered by the Department of Physics of the University of Patras,Greece, during the academic year 2017-2018. This work is a result, not only of personal effort and dedication, but also enormous support from my family, friends and especially my supervisor and the laboratory staff. Therefore, I would like to thank the people who, each one in their own special way, contributed to the process of achieving my goals. First of all, I would like to express my sincere gratitude to the man who believed in me and provided me with the necessary qualifications in order to accomplish my goals, my supervisor Pro- fessor Costas Psychalinos. He gave me the opportunity to deal with an interesting and novel subject, encouraging also the personal research and intervention during the whole process. Most important of all, I consider, his influence on my way of thinking as he taught me to set high goals, believing in myself and leaving the fear of failure in the background. Besides my supervisor, I would also like to thank the rest of my thesis committee: Professors S. Vlassis and G. Economou, for their encouragement, insightful comments and guidance through all these years. A special reference worth my colleagues Costas Vastarouchas and Panagiotis Bertsias for their invaluable help and suggestions throughout the whole process. They were by my side all these months sharing their knowledge and ideas with me, but most of all their love for research which leads to new paths in science. In addition, I would like to thank Professor Ahmed Elwakil for his collaboration during the framework of this Thesis. The most heartfelt thanks I owe to my parents and my entire family environment, that con- tributed to the development of my character and the cognitive background which led me to complete my advanced studies. Their spiritual, psychological and economical support helped me make my ambitions and dreams come true, always having a family by my side. Last but not least, I could not help but mention my second family, my friends. All together and each one separately stood beside me in easy and difficult moments, in successes and failures, a factthat makes me feel very lucky. Stavroula Kapoulea Patras, March 2018 Abstract This MSc Thesis deals with a novel concept that suggests a new way of constructing a fractional-order differentiator/integrator. This approach offers several benefits, with the most important being the apparent reduced spread of time-constants and scal- ing factors. This leads into differentiator/integrator realizations with capability for implementation in fully integrated form. The approximations of fractional-order differentiator/integrator transfer functions are currently performed using integer-order rational functions, which are in general implemented through appropriate multi-feedback topologies. The spread of the values of time-constants as well of scaling factors in these topologies increase as the order of the differentiator/integrator and/or the order of the approximation increases. This could lead to non-practical values of capacitances and resistances/transconductances needed for the implementation. A possible solution to overcome this obstacle is intro- duced in this thesis and is based on the employment of a combination of fractional- and integer-order integrators and differentiators for implementing the desired function. The main concept is to construct a fractional-order integrator/differentiator that, even for high orders, will present low values of spreads. This could be achieved by com- bining a fractional-order part of low order with an integer-order part, a connection that leads to the implementation of a fractional-order integrator/differentiator of high order. Two methods of approximation are used for this purpose; 2nd− to 5th− order Continued Fraction Expansion and 3rd− and 5th− order of Oustaloup approximation. The performance of the proposed scheme is verified through post-layout simulations using Cadence and the Design Kit provided by the Austria Mikro Systems (AMS) 0.35µm CMOS technology process. Keywords: Fractional-order circuits, Fractional-order integrators, Fractional-order differentiators, Operational Transconductance Amplifiers, CMOS analog integrated circuits PerÐlhyh H παρούσvα Metαπτυχιακή Διπλωμτική ErgasvÐa πραγματεύετai mia kainotόmo idèa svton τρόπο ulopoÐhsvhc ενός diaforiσvτή/oλοκληρωτή κλασvματικής tάξης. Αυτή h nèa prosvèggisvh παρουσvιάζει poλλά pleoνεκτήματa, kaj¸c prosvfèrei èna πλήρwc oloklhrwmèno κύκλωμα, koiνό gia thn ulopoÐhsvh oλοκληρωτή kai diaforiσvτή, όπου h διασvπορά twn tim¸n twn svtoiqeÐwn (spread) eÐnai χαμηλή tόsvo gia tic svtajerèc χρόnou όσvο kai gia touc παράγοntec kèrdouc. Oi prosveggÐsveic twn σvυναρτήσvεων metafoράς twn oloklhrwt¸n/diaforisvt¸n klasv- ματικής tάξης pragmatopoiούντai mèsvw thc χρήσvης σvυναρτήsvewn akèraiac tάξης, oi opoÐec ulopoiούντai mèsvw katάλληλων topologi¸n pollαπλής ανάδραsvhc. H διασvπορά twn tim¸n (spread) twn svtajer¸n χρόnou kai twn παραγόntwn kèrdouc svtic svugkekrimènec topologÐec αυξάνετai me thn αύξησvη thc tάξης tou diaforiσvτή/oλοκληρωτή, αλλά kai me thn αύξησvη thc tάξης prosvèggisvhc. Autό odhgeÐ sve mh praktikèc timèc χωρητικόth- tac kai antÐsvtasvhc/διαγωγιμόthtac katά thn ulopoÐhsvh. Sthn παρούσvα ErgasvÐa pro- teÐnetai mia λύσvη svto πρόβλημα autό, h opoÐa basvÐzetai svth χρήσvη ενός σvυνδυασvμού oloklhrwt¸n kai diaforisvt¸n klasvmatikhc kai akèraiac tάξης me σvκοπό thn ulopoÐhsvh thc epiθυμητής σvυνάρτηsvhc. H basvική idèa eÐnai h katασvκευή enός diaforiσvτή/oλοκληρωτή κλασvματικής tάξης, o opoÐoc, ακόμα kai gia μεγάλες tάξειc, ja παρουσvιάζει qamhlèc timèc spread. H dedomènh leitourgÐa mporeÐ na epiteuqjeÐ mèsvw tou σvυνδυασvμού ενός sv- toiqeÐou κλασvματικής, μικρής tάξης ki ενός akèraiac tάξης, mia σvύνδεσvη pou odhgeÐ athn ulopoÐhsvh ενός diaforiσvτή/oλοκληρωτή μεγάλης, κλασvματικής tάξης. Qrhsvimopoiούν- tai duo mèjodoi prosvèggisvhc tou σvυσvτήματoc: Continued Fraction Expansion 2ης − èwc 5ης − tάξης kai Oustaloup 3ης − kai 5ης − tάξης. H ορθή leitourgÐa tou proteiνόμενου kukl¸matoc επαληθεύετai mèsvw exomoi¸svewn metά από σvχεδιασvμό sve epÐpedo layout, me th βοήθεια logiσvμικού Cadence kai Design Kit pou prosvfèrontai aπό thn teqnologÐa Austria Mikro Systems (AMS) 0.35µm CMOS. Lèxeic κλεδιά: Kukl¸mata κλασvματικής tάξης, Oloklhrwtèc κλασvματικής tάξης, Diaforisvtèc κλασvματικής tάxhc, TelesvtikoÐ Enisvqutèc Διαγωγιμόthtac, CMOS analoγικά oloklhrwmèna kukl¸mata vii Contents Contents ix List of Figures xi List of Tables xv 1 Introduction1 1.1 Fractional-order calculus . .1 1.2 Fractional-order integrators/differentiators . .2 1.3 Thesis objectives . .3 1.4 Thesis overview . .3 2 Approximation of fractional-order integrators/differentiators5 2.1 Introduction . .5 2.2 Approximation tools . .5 2.2.1 Continued Fraction Expansion approximation . .5 2.2.2 Oustaloup approximation . .6 2.2.3 Spread of time-constants and scaling factors . 14 2.3 Fractional-order integrator/differentiator designs . 18 2.4 Simulation results . 20 2.4.1 Fractional-order integrator/differentiator using 2nd−order CFE approximation . 22 2.4.2 Fractional-order integrator/differentiator using 5th−order Oustaloup approximation . 25 2.5 Comparison results . 28 3 Proposed method for reducing the spread of element values in fractional- order circuits 29 3.1 Introduction . 29 Contents 3.2 Proposed concept . 29 3.3 Fractional-order integrator/differentiator designs . 31 3.4 Simulation results . 33 3.4.1 Fractional-order integrator/differentiator using 2nd−order CFE approximation . 34 3.4.2 Fractional-order integrator/differentiator using 5th−order Oustaloup approximation . 36 3.5 Comparison results . 43 4 Layout design of the proposed fractional-order integrator/differen- tiator topologies 49 4.1 Introduction . 49 4.2 Basic building blocks . 50 4.3 Post-layout simulation results . 53 5 Conclusions and future work 61 5.1 Conclusions . 61 5.2 Proposals for future work . 62 References 63 A Matlab Codes 69 B Transfer Functions 93 x List of Figures 2.1 Functional Block Diagrams of (a) Follow-the-Leader, (b) Inverse-Follow- the-Leader Feedback structures . 14 2.2 Spread of time-constants for variable order fractional-order differentia- tors (q > 0)and integrators (q < 0) derived using the CFE and Oustaloup’s approximations . 15 2.3 Spread of scaling factors of the FLF structure in Fig.2.1, for variable order fractional-order differentiators (q > 0) and integrators (q < 0) de- rived using the CFE and Oustaloup approximations . 16 2.4 Spread of scaling factors of the IFLF structure in Fig.2.1 versus q using (a) 2nd−, (b) 3rd−, (c) 4th−, and (d) 5th−order CFE approximation . 17 2.5 Spread of scaling factors of the IFLF structure in Fig.2.1 versus q using (a) 3rd−, (b) 5th−order Oustaloup approximation . 18 2.6 IFLF OTA-C structure
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