The Essential Guide to Data Conversion

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The Essential Guide to Data conversion

“Real-World” Sampled Data Systems Consist of ADCs and DACs

ANALOG DIGITAL

ADC Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC)

SENSOR CHANNEL DSP MEMORY allow DSPs to interact with real-world signals. Real-world signals are continuous (analog) signals. Pressure sensor DAC Temperaturese sensoensorre, ettcc. DE

G Real-world signal processing allows for efficient and cost effective E AL U U O T L

GI extraction of information from a signal. VA DI ANAL

AMPLIT Signal amplitude TIME TIME Phase, etc. ADC SAMPLEDSAMPLED AND DAC RECONSTRUCTED QUANTIZED WAVEFORM WAVEFORM Digital information differs from real-world information in two important respects…it is sampled, and it is quantized. Both of these restrict how muchih inftformatiidon a diiigittlal silignal can contitain.

Converter Resolution, INL, and DNL

Converter resolutionr epresentst he analog signal at an umbero fd iscrete levels IDEAL or steps. The smallest resolvable signal is 1 Least Significant Bit (LSB), which is equal FS to FS/8 in this example. 7/8 IDEAL ItIntegralNl Nonlinearity (INL)i) is a measure oftf thhe maximum dideviation iLin LSSBBs, from 6/8 INL a straight line passing through negative full-scale and positive full-scale.

Good INL is required for open-loop systems and many closed-loop systems. 5/8 G DNL Differential Nonlinearityy( (DNL) is the difference between the actual step size and 4/8 the ideal 1 LSB change between two adjacent codes. ACTUAL 1 LSB ANALO DNLerror results in: ANALO G 3/8 QUANTIZATION Smaller or larger step sizes than the ideal 2/8 UNCERTAINTY Additive noise/spursb eyondt he effectso fq uantization NON-MONOTONIC 1/8 A DAC is monotonic if its output increases or remains the same for an increment in the digital code, i.e., DNL > –1 LSB(a key requirement in a control system). Conversely, a DAC is nonmonotonic if the output decreases for an increment 000 001 010 011 100 101 11 0 111 000 001010 011100 101110 111 in theed digitaigitall code. DIGITAL INPUT An ADC has no missing codes if the input voltage is swept over the entire input DIGITAL range and all output code combinations appear at the converter output. A DNL error of > –0.99 LSB guarantees that the converter will have no missing codes.

Converter Errors (Unipolar)

DAC Definitions POSITIVE GAIN AND GAIN ERROR FULL-SCALE OFFSET Zero-Code Error is the measured output voltage from VOUT of the DAC ERROR NEGATIVE ERROR when zero code (all zeros) is loaded to the DAC register. GAIN ERROR Zero-Code Error is typically expressed in LSBs. DAC Offset Error is a measure of the difference between the actual VOUT OUTPUT VOLTA GE OUTPUT and the ideal VOUT in the linear region of the transfer function. Offset error ACTUAL VOLTA GE can be negative or positive in the DAC and output amplifier. IDEAL ACTUAL Offset Errorir isst typicallyypically expresseexpressedd in mV or mA. IDEAL ZERO-CODE DAC Gain Error is a measure of the span error of the DAC. It is the deviation ERROR in slope of the actual DAC transfer characteristic from the ideal.

POSITIVE Gain Errosor is usuallyey expressedessed as apa peecrceetntageageo of tethe full-scaaele ragangee. DAC CODE OFFSET DAC CODE Full-Scale Erroris a measure of the output error when full-scale code (0xFFFF) is loaded into the DAC register. Ideally, the output should be VREF − 1 LSB. (Full-Scale Error = Offset Error + Gain Error) Full-Scale Error is typically expressed as a percentage of the full-scale range.

GAIN AND Deadband Errors, DACs with integrated output amplifiers will have OFFSET ERROR DEADBAND CODES performance degradation, deadbands, at codes outside of the linear region of ththee output amplifier. AMPLIFIER FULL-SCALE FOOTROOM The number of deadband codes depends on the DAC output voltage span, the OUTPUT ERROR headroom and footroom of the amplifier, and the power supply rails used. VOLTA GE ZERO-CODE ACTUAL NEGATIVE ERROR OFFSET IDEAL ADCCe Definitotions ADC Offset Error is the deviation of the first code transition, for example (000…000) to (000…001) from the ideal (AGND + 1 LSB). Offset error is NEGATIVE typically expressed in LSBs. OFFSET DAC CODE ADC Gain Error is the deviation of the last code transition, for example (111…110) to (111…111) from the ideal (VREF –1 LSB) after the offset error is adjusted out. Gain error for an ADC does not include the reference error andid isst typicallyypically expressedexpressedi inn LSBs.

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Time Domain DAC Output

OVERSHOOT CLOCK / DATA GLITCH FEEDTHROUGH IMPULSE Clock to output delay ENERGY Group delay due to DAC propagation delay NON-IDEAL RESPONSE Settling time SETTLING DNL ERROR 1LSB Measured relative to output signal alone ERROR

T BAND Time between when signal leaves ±0.5 LSB error band to when it

PU IDEAL T remains within ±0.5 LSB error band of final value RESPONSE NONLINEAR OU SLEWING

OG Slew rate

AL Defined as maximum rate of change of voltage or current at output AN

C CLOCK / DATA Specifiedad assV V/se/secc or A/sec dependingdependingo onnD DACAC outpuoutputts stagtagee DA FEEDTHROUGH Typically measured for full-scale step size with 10% to 90% error band

CLOCK TO Glitch impulse energy OUTPUT DELAY CdCaused by unequal propagation dldelays within DAC CODE = CODE = CODE = CODE = CODE = ZEROSCALE ZEROSCALE MIDSCALE MIDSCALE MIDSCALE + 1 Often measured for midscale LSB transition (011..111 to 100..000) TIME T1 T2 T3 T4 T5 Measured as “area” of glitch impulse with units p/nV-s or p/nA-s

Frequency Domain DAC Output

FULL-SCALE Sinc(x) –x dB FROM FULL-SCALE (dBFS) SINC ATTENUATION DAC’s time domain step response (zero-order hold) modifies DAC –3.9dBc @ FDAC/2 frequency response FUNDAMENTA L DAC output signals are attenuated by sin(πf/f )/(π f/f ) envelope SIGNAL DESIRED SIGNAL IMAGES dac dac Harmonics Created by DAC’s static and dynamic nonlinearities SFDR (dBc) Images (dB)

B) DAC CLOCK FEEDTHROUGH

(d nd rd 2 AND 3 Duplicate of the desired signal (and its DAC induced harmonics) at de tu li ITUDE HARMONICS p higher Nyquist zones

Am DESIRED SIGNAL AMPL 2nd AND 3rd IMAGE HARMONICS Images are predicted by sampling theory SFDR NSDD( (dBm/HzdBm/Hz) Measured with single-tone output in first Nyquist band (unit is dBc) Difference between single-tone amplitude to the next highest spurious tone FDAC/2 FDAC Noise Spectral Density (NSD) FREQUENCFrequency Y Integration of the noise floor in a small frequency band (unit is dBm/Hz or nV/rtHz)

Nyquist’s Criteria

AMPLITUDE

fa IMAGE NYQUISTZONE1 (BASEBAND) Undersampledanalog signal fa sampled @ Fs has images (l(alii)ases) at|t | ± KFs ± fa|K|, K = 050.5, 111, 1.5 … FREQUENCY 0 NYQUISTZONE2 0.5Fs A signal with a maximum frequency fa must be sampled at a rate Fs > 2fa or information about the signal will be lost because of aliasing.

Aliasing occurs whenever Fs < 2fa. Fs NYQUISTZONE3 The concept of aliasing is widely used in communications

fa applications such as direct IF-to-digital conversion.

A signal that has frequency components between fa and fb must NYQUISTZONE4 1.5Fs be sampled at a rate Fs > 2 (fb –fa) in order to prevent alias components from overlapping the signal frequencies.

2Fs

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Analog-to-Digital Converter AC Performance Specifications

SNR (Signal-to-Noise Ratio, dB or dBFS) FULL-SCALE (()FS) The ratio of the RMS value of the measured output signal (peak or full scale) to the RMS sum of all other spectral components excluding the first 6 harmonics and DC. INPUT SIGNAL LEVEL (CARRIER) RMSSignal = (FSR / 2) / √(2), RMSNoise = Qn = q / √(12) SNR(dB) = RMSSignal / RMSNoise = 20 ×log(2(n –1) × √6)) = 6.02 ×n + 1.76 SFDR (dBFS) SINAD (Signal-to-Noise Ratio and Distortion, dB) SFDR (dBc) dB The ratio of the RMS signal amplitude to the RMS value of the sum of all other spectral components including harmonics, but excluding DC. SINAD (dB) = –20 ×log (√(10(–SNRW/O DIST/10) + 10(THD/10))) WORST SPUR LEVEL ENOB (BITS) = (SINAD –1.76 + 20 ×log (FSR/Actual FSR)) / 6.02 THD (Total Harmonic Distortion, dBc) The ratio of the RMS sum of the first 6 harmonics to the RMS value of the measured fundamental. THD (–dB)=) = 20 × log(g (√((√((10(–2ND HAR/20))2 +(+ (1100(–3RD HAR/20))2 +(+… (1100(–6TH HAR/20))2 ) SFDR (Spurious-Free Dynamic Range, dB or dBFS) f The ratio of the RMS value of the peak signal amplitude (or full-scale) to 0, DC FREQUENCY s 2 the RMS value of the amplitude of the peak spurious spectral component. The peak spurious component may or may not be a harmonic.

Oversampling Relaxes Requirements on Baseband Antialiasing Filter Oversampling Relaxes Requirements on Baseband Antialiasing Filter

A B f a fs – fa fa Kfs– fa Generally an antialiasing filter is required on the analog front end of an ADC.

If the sampling frequency is not much greater than the max input frequency fa, then the requirements on an antialiasing filter can be severe, as in (A). The dotted regions indicate where the dynamic range can be limited by signals DR outside the bandwidth of interest. Oversampling relaxes the requirements of the analog antialiasing filter as shown in (B). Sigma-deltaca convertersonvertersa arree aag goodood example. Outputs of DACs need filtering also, and these are called “anti-imaging” filters. They serve essentially the same purpose as the antialiasing filter f f s s Kfs Kfs ahead of an ADC. 2 2 STOPBAND AT TENUATION = DR STOPBANDATTENUATION = DR

TRANSITION BAND: fa to fs – fa TRANSITION BAND: fa to Kfs – fa CORNER FREQUENCY: fa CORNER FREQUENCY: fa

Theoretical SNR and ENOB Due to Jitter vs. Full-scale Sinewave Analog Input Frequency

Theoretical SNR and ENOB Due to Jitter vs. Full-Scale Sine Wave AlAnalog ItInput Frequency 130

120 RMSJITTER TOTA L JITTER = t j (RMS) The total amount of jitter is dependent on 0.125 ps theee effectivffectiveae apertureperture jitterjitter within the 11 0 1 converter, as well as the external jitter 0.25 ps SNR = 20log π 10 2 ftj generated by the sampling clock circuit. 100 0.5 ps 16 BITS 1 ps These terms are root sum squared to determine B thete totaotall amountto offj jitteitterra appliedpplied to thees signaignall d 90 2 ps 14 BITS chain. dV IN 80 12 BITS TOTA L JITTER = ENOB NR 70 (ADC APERTURE JITTER) 2 + (SAMPLING CLOCK JITTER) 2 S 10 BITS 60 ERROR VOLTAGE In this example, if a 12-bit ENOB, 74 dB SNR 50 is desired for the design with an analog inpuinputtf frequencrequencyyo off1 10000 MHztz, thenhent thhee total 40 jitter required must be 0.5 ps or less. 30

110 100 1000 ENCODE

FULL-SCALE ANALOG INPUT FREQUENCY IN MHz dt

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Analog Input/Output Configurations

VIN UNIPOLAR SINGLE-ENDED FS

0V Single-ended signalingis most common. Example: UnipolarDifferential VIN− Differential signals measure the difference in voltage between the UNIPOLAR DIFFERENTIAL VIN+ VIN– FS VIN+ 1.5V positive and negative input terminals. VIN+ The inputs are 180 degrees out of phase with each other. 0V 1V p-p +FS/2 Vcm Many benefits in using differential inputs. BIPOLAR SINGLE-ENDED VIN Vcm= 1 VDC 1V 0V + Input transient reduction – 1V p-p Input noise reduction −FS/2 VIN– 050.5V Signal swing is doubled VIN− +FS/2 BIPOLAR DIFFERENTIAL Pseudo differential is a single-ended/differential hybrid. 0V Separation of signal ground from ADC ground for the ADC conversion VIN+ −FS/2 VIN(adc) = VIN+ –VIN–= 2 V p-p Consider ADC common-mode requirements Vcm= (Vp + Vn) / 2. Consider differential common-mode requirements PSEUDO DIFFERENTIAL VIN+ The ADC converts VIN+ –VIN–. FS LOW DC VIN− INPUT 0V

What Resolution Do I Need? Dynamic Range vs. Signal-to-Noise Ratio Requirements

Dynamic Range (DR) is the difference in level between the highest signal peak that can be reproduced byyy the system and the amplitude of the Signal-to-NiNoise RtRatiio (SNR) itis thhe difference in lllevel btbetween the RMS highest spectral component of the noise floor. signal level and the RMS level of the noise floor, except the first six

DR provides amplitude range so the converter can “see” the signal of interest. harmonics and DC. ADC FULL-SCALE (dBFS) 0 Converter DR is limited by SFDR and, theoretically, by its resolution. SNR limits the capability offt thhe 20 N=12 BITS CiConsiddier using analilog gain tito increase DR capability oftf thhte system. converter to see “small” signals. M=4096 #OFFFT PTS FS = 245.76MSPS Converter SNRis, theoretically, 40 74dB=6.02N+1.76dB=SNR FS BINSPA CING = limited by its resolution. 4096

Quantization noise of an ) 60 dB DYNAMIC RMSQUANTIZATIONNOISE LEVEL RANGE ideal ADC will have an E( 74dB 80 SNR= 6.02N + 1.76 (dB), UD M DYNAMIC VGA ADC IT 33dB =10log () AMPLITUDE AMPLITUDE 10 2 =FFTNOISEFLOOR (PER BIN) RANGE AAF N = Number of bits. PL M 100 A SIGNAL CHAIN Effective Number of Bits 107dB (ENOB) is calculated from SNR: 120 FREQUENCY FREQUENCY ENOB = (SNR–1.76) / 6.02 (bits). FS 78 =10log10(FS/2)=NOISEFLOOR(PERHz) 2 140 Example: 10-bit ADC with an FSR = 4 V p-p has an LSB = 3.9 mV p-p or 4/2BITS. 152dB Therefore, 4 V / 3.9 mV = 1024 codes. This can also be expressed in dB or 20 ×log 160 (1024) = 60 dB. FREQUENCY(Hz)

Quantization: Converter Circuits The Size of a Least Significant Bit (LSB)

DAC Amplifier Coupled Circuit 500Ω VDD AV DD 225Ω VOLTA GE IOUTB RESOLUTION N2N ppmFS% FS dBFS (2 V/10 V FS) DAC AMP 225Ω IOUTA 2-bit40.5/2.5 V250,000 25 –12 GND

COPT AVSS 4-bit16125/625 mV 62,500 6.25 –24 ROPT AVDD 25Ω 25Ω 1kΩ 6-bit6431.3/156 mV 15,625 1.56 –36 500Ω 8-bit 256 7.8/39.1m1 mVV 3906 0.39 –48 10-bit 1024 2/9.77 mV 9770.098 –60 12-bit 4096 0.49/2.44 mV 2440.024 –72 14-bit 16,384 122/610 µV 61 0.0061 –84 ADC Amplifier Coupled Circuit

16-bit 65,536 30.5/153 µV 15 0.0015 –96 AMP-AVDD AV DD DRVDD 18-bit 262,144 7.6/38 µV 40.0004 –108 205Ω 0.1µF 20-bit 1,048,576 1.9/9.54 µV 10.0001 –120 24Ω 33Ω VIN+ BUFFERED OR UNBUFFERED ADC ANALOG 200Ω 22-bit 4,194,304 0.47/2.38 µV 0.24 0.000024 –132 INPUT +VS 10kΩ 10kΩ 62Ω VOCM 24-bit 16,777,216 11 9/596 nV*0.060.000006 –144 G=UNITY REQUIRED FOR 2p RC UNBUFFERED ADC 0.1µF 10kΩ 200Ω –VS 10kΩ ADCINTERNAL *600 nV is the Johnson Noise in a 10 kHz BW of a 2.2 kΩ resistor @ 25°C. 33Ω INPUTZ 27Ω VIN– Remember: 10 bits and 10 V FS yields an LSB of 10 mV, 1000 ppm, or 0.1%. 24Ω 0.1µF (All other values may be calculated by powers of 2.) 205Ω VCM

0.1µF