4 IC TECHNOLOGY AND PACKAGING TRENDS

MARKET OVERVIEW

There are a variety of process technologies used in the design and manufacture of integrated cir- cuits, including silicon MOS, bipolar, and BiCMOS, and GaAs (gallium arsenide) MOS and bipo- lar. Within each of these major process segments several variations are available that enable the process to perform most effectively for certain applications.

Figure 4-1 shows that in 1970 bipolar was the major technology of choice, with bipolar ICs repre- senting almost two-thirds of the total IC market. By 1980, that share had fallen to 50 percent. In 1996, bipolar ICs are estimated to have accounted for only about 13 percent of the IC dollar volume shipped.

It is interesting to note that while bipolar ICs represent a small proportion of the IC market, in terms of units they still represent nearly half of the total number of ICs shipped (Figure 4-2). It is also interesting that bipolar linear (or analog) chips easily account for the largest number of units shipped.

No technology of the past has dominated the IC marketplace like CMOS does today. The primary advantages of CMOS that has driven its widespread use are its low power dissipation and small physical geometry. Multi-million transistor ICs are made possible by itÕs high packing density and scalability. Furthermore, advances have resulted in CMOS devices with the speed and output drive capability rivaling that of some bipolar devices. Figure 4-3 offers a comparison of various bipolar TTL and ECL, CMOS, and ABT (Advanced BiCMOS Technology) general-purpose logic devices.

ICE estimates that ICs produced using CMOS technology represented 70 percent of the total IC market in 1996 (Figure 4-4). By the year 2001, the marketshare for CMOS ICs will likely swell to 86 percent of the total IC dollar volume.

BiCMOS offers the IC designer both MOS and bipolar advantages. ICs can be designed with the best devices for each part of the circuit. Complexity and the high cost resulting from a large number of process steps has kept BiCMOS from dominating the IC market.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-1 IC Technology and Packaging Trends

Marketshare (Percent) Process Characteristics Technology 1996 2001 1970 1980 1995 (EST) (FCST) MOS: PMOS Slow, obsolete 31 5 — — —

NMOS/HMOS Obsolete 2 37 1 <1 <1

CMOS Mainstream technology, extensive research 2 10 78 70 86 has solved inherent difficulties (e.g., latch-up, slow operation).

Bipolar:

ECL Fastest silicon-based process, competing 3 3 1 1 <1 with GaAs. Becoming obsolete.

TTL Slow, obsolete. 29 8 <1 <1 —

S/LS TTL Mainstream bipolar logic, under pressure 7 13 1 1 <1 from MOS ASICs.

LINEAR Mainstream analog technology, some 26 24 9 11 8 competition from CMOS, especially in A/D converters and amplifiers, and GaAs.

BiCMOS: Offers both MOS and bipolar advantages. — — 10 16 4 High cost/complexity limits applications.

GaAs: Cost competitive with ECL. Will be used — — <1 1 1 especially for analog applications in the future.

Source: ICE, "Status 1997" 11218U

Figure 4-1. Marketshare Overview of Process Technologies

MOS Logic 24%

Bipolar Analog 1996 MOS* 40% Bipolar 48.8B 52% 48% (EST) MOS Memory 13%

MOS Bipolar Micro Digital 11% 8%

MOS/BiMOS Analog 4% * Includes BiCMOS

Source: ICE, "Status 1997" 21390

Figure 4-2. MOS/Bipolar IC Unit Volume Split

4-2 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

Logic Families Typical Commercial Parameter (0° to 70°C) TTL/ABT CMOS ECL LS ALS ABT FAST MG HC FACT LVC LCX 10KH 100K ECLinPS Lite Speed "OR"-Gate Prop. Delay (tPLH) (ns) 9 7 2.7 3 25 8 5 3.3 3.3 1 0.75 0.33 0.22 D Flip-Flop Toggle Rate (MHz) 33 45 200 125 4 45 160 200 200 330 400 1,000 2,800 Output Edge Rate (ns) 6 3 3 2 100 4 2 3.7 3.6 1 0.7 0.5 0.25 Power Consumption (per gate) Quiescent (mW) 5 1.2 0.005 12.5 0.0006 0.003 0.003 0.0001 0.0001 25 50 25 73 Operating (at 1 MHz) (mW) 5 1.2 1.0 12.5 0.04 0.6 0.8 0.6 0.3 25 50 25 73 Supply Voltage (V) 4.5 to 4.5 to 4.5 to 4.5 to 3 to 2 to 2 to 1.2 to 2 to Ð4.5 to Ð4.2 to Ð4.2 to Ð4.5 to 5.5 5.5 5.5 5.5 18 6 6 3.6 3.6 Ð5.5 Ð4.8 Ð5.5 Ð5.5 Output Drive (mA) 8 8 32/64 20 1 4 24 24 24 50-Ω load 50- Ω load 50-Ω load 50-Ω load DC Noise Margin High Input (%) 22 22 22 22 30 30 30 30 30 28 41 28/41 33 Low Input (%) 10 10 10 10 30 30 30 30 30 31 31 31/31 33 Functional Device Types 190 210 50 110 125 103 80 35 27 64 44 48 40 Price/Gate (relative, 1 to 25 qty) 0.9 1 1.6 1 0.9 0.9 1.4 1.8 1.8 2 10 25 32 (LS) Motorola Low-Power Schottky TTL (FACT) Motorola Advanced CMOS (ALS) Texas Instruments Advanced Low-Power Schottky TTL (LCX) Motorola Low-Voltage CMOS (ABT) Philips Semiconductor Advanced BiCMOS (LVC) Philips Low-Voltage CMOS (FAST) Motorola Advanced Schottky TTL (10KH) Motorola 10KH Series ECL (MG) Motorola 14000 Series Metal-Gate CMOS (100K) National 100K Series ECL (HC) Motorola High-Speed Silicon-Gate CMOS (ECLinPS and ECLinPS Lite) Motorola Advanced ECL Source: Electronic Products/ICE, "Status 1997" 21745

Figure 4-3. Comparison of CMOS, Bipolar, and BiCMOS Logic Families

Other 5%

Bipolar 9%

Other 17% Bipolar 1996 2001 13% $116.9B $283.5B

CMOS 70% CMOS 86%

Source: ICE, "Status 1997" 20282C

Figure 4-4. CMOS Dominant IC Process Technology

For the 1996 to 2001 time period ICE forecasts that BiCMOS ICs will show a Ð8 percent CAGR ($18.7B to $12.2B). The decline is a result of IntelÕs plan to convert its Pentium and Pentium Pro microprocessors from BiCMOS to CMOS technology. At $12.2 billion, BiCMOS ICs will represent only four percent of the forecasted 2001 total IC market and will still be considered a high-perfor- mance niche technology.

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Figure 4-5 shows the major IC process technologies and their positions on the bell-shaped lifecy- cle curve. CMOS technology has been in the ÒmaturityÓ stage since the mid-1980Õs. Moreover, ICE expects that CMOS will still be in the maturity stage well into the twenty-first century. As of 1996, there was no new technology that showed the potential to dethrone CMOS as the main- stream IC process in the foreseeable future. Cost effectiveness, steadily increasing performance, and consistently high levels of investment in research and development by IC manufacturers will keep CMOS the mainstream technology throughout the 1990Õs and beyond.

CMOS

BIPOLAR BiCMOS ANALOG GaAs S/LS TTL

ECL

HMOS TTL Diamond SiGe PMOS NMOS

Introduction Growth Maturity Saturation Decline Obsolete

Source: ICE, "Status 1997" 16809H

Figure 4-5. Process Technology Lifecycle (1996)

Figure 4-6 shows the IC process technology marketshare trends from 1982 through 2001. This illustrates very clearly how CMOS technology has become the dominant process at the expense of NMOS and bipolar digital. CMOS ASICs and standard logic will continue to replace TTL, and CMOS DRAMs and microprocessor products have replaced NMOS DRAMs and most MPU devices. Considering the enormous expense of a fab facility and the increasing complexity of the IC technology, non-CMOS processes have become a luxury that most IC producers cannot afford.

As also shown in Figure 4-6, 1996 was the first in which the marketshare of CMOS ICs slipped from its previous year value. This can be blamed on plunging MOS memory prices (DRAM prices in particular) during the year. It can also be attributed to a growing BiCMOS IC market, a result of the strength in the demand for BiCMOS-based Pentium MPUs.

MOS ICs

Figures 4-7 and 4-8 show the MOS IC market as expressed in dollars. The popularity of CMOS compared to NMOS and PMOS is very evident here. Just as NMOS replaced the slower and more power-hungry PMOS technology in the 1970Õs, CMOS supplanted NMOS in the 1980Õs. CMOS utilizes complementary pairs of NMOS and PMOS transistors, a structure that consumes very little power per function.

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<1% <1% ECL <1% <1% 1% TTL 1% GaAs 100 AND OTHER 4% ECL 4% 8% BIPOLAR TTL AND 12% 1% 1% 90 10% 11% 19% OTHER 2%

80 <1% <1% BIPOLAR 20% 70 ANALOG 22% 60 <1% PMOS 70% 86% 2% 24% 50 77%

PERCENT MOS 40 NMOS 41% 30

20 39%

10 CMOS BiCMOS 16% 12% 10% 4% 0 1982 1987 1996 2001 $10.2B $29.0B $116.9B $283.5B (EST) (FCST) 1995 $128.7B YEAR Source: ICE, "Status 1997" 12070T

Figure 4-6. 1982-2001 IC Technology Trends ($)

ICE forecasts that CMOS will represent basically all of the total MOS market in 2001. CMOS became the technology of choice for MOS memory as density reached and surpassed 1M. All 1M and denser DRAMs have thus far been produced using CMOS technology. ICE projects this to remain true well into the future. In addition, the swelling complexity and density of other IC types like microprocessors and ASICs require the scalability and low power consumption benefits of CMOS.

CMOS technology continues to be much more popular than other technologies due to the follow- ing key reasons.

¥ Experience/inertia. ¥ Low power consumption. ¥ High scalability with improved lithography techniques. ¥ Relatively good noise immunity and soft error protection. ¥ Low threshold bias sensitivity. ¥ Design simplicity and relatively easy layout, especially for ASICs. ¥ Capability for lower power analog and digital circuitry on the same chip.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-5 IC Technology and Packaging Trends

100 4% PMOS <1% <1% <1% <1% 90

80 40% NMOS 70

74% 60 >99% >99% >99% 50 PERCENT 40

30 60%

20 CMOS

10 22%

0 1982 1987 1996 2001 $5.5B $18.4B $83.0B $244.9B 1995 (EST) (FCST) $98.6B

Year Source: ICE, "Status 1997" 12072T

Figure 4-7. 1982-2001 MOS (Excluding BiCMOS) Technology Trends

2001 1987 - 2001 1987 1995 1996 Technology ($M, CAGR ($M) ($M) ($M, EST) FCST) (Percent)

NMOS and PMOS 7,350 645 480 150 Ð24

CMOS 11,050 97,925 82,520 244,790 25

Total 18,400 98,570 83,000 244,940 20

Source: ICE, "Status 1997" 16811L

Figure 4-8. MOS Technology Market Trends (1987-2001)

Because of these advantages, CMOS is expected to continue to be the technology of choice for the VLSI and ULSI products of the future.

CMOS technology continues to advance and evolve to meet the majority of IC performance demands. Figure 4-9 shows the historical trends in CMOS technology. Notice that the power supply used during the 15 year period was typically 5V.

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1977 1980 1983 1986 1989 1992

Gate Length (µm) 3.0 2.0 1.5 1.1 0.9 0.6

µ Channel Length ( m)(Leff) 2.0 1.5 1.2 0.9 0.6 0.4

Gate Oxide (Å) 700 400 250 250 200 150

Junction Depth (µm) 0.6 0.4 0.3 0.25 0.2 0.15

VCC (V) 5 5 5 5 5 5 µ NMOS Idsat @ Vg = 5V (mA/ m) 0.1 0.14 0.23 0.27 0.36 0.56 µ PMOS Idsat @ Vg = 5V (mA/ m) — 0.06 0.11 0.14 0.19 0.27

Gate Delay @ FO = 1 (ps) 800 350 250 200 160 90 Source: UC Berkeley/Semiconductor International/ICE, "Status 1997" 19211A

Figure 4-9. Historical Trends in MOSFET Scaling

As feature sizes shrink below 0.5µm and gate oxides thin to less than 100• (Figure 4-10), a 5V power supply is not practical. Thinner oxides allow transistors to switch faster, but it also reduces voltage tolerance. As a result, devices with 0.35µm geometries are designed for 3.3V power sup- plies (or lower) or for 5V supplies with the signal being converted to a lower voltage internally. When the industry moves to feature sizes of 0.25µm and below, a 3.3V power supply will become impractical and designers will have to design for 2.5V or 1.8V (Figure 4-11).

160

140 Published Data Trend Line 120

100

80

60

Gate Oxide Thickness (Å) 40

20

0 0 0.1 0.2 0.3 0.4 0.5 0.6 Gate Length (µm) Source: Intel/ICE, "Status 1997" 20284A

Figure 4-10. Gate Oxide Versus Gate Length

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-7 IC Technology and Packaging Trends

6

5 Published Data

Trend Line 4

3

2 Operating Voltage (V)

1

0 0 0.1 0.2 0.3 0.4 0.5 0.6 Gate Length (µm)

Source: Intel/ICE, "Status 1997" 20285A

Figure 4-11. Gate Length Versus Operating Voltage

In the transition period from 5V to low-voltage systems, system designers have been using both 5V and low-voltage ICs on the same printed circuit board (Figure 4-12). Targeting such systems, Lucent Technologies offers a standard cell library that allows the user to mix and match 5V and 3V cells on the same chip. Other companies that are helping bridge the 5V to low-voltage gap with Òmixed-voltageÓ ICs include Oki, TI, Toshiba, Atmel, and Symbios Logic. It is estimated that most of the 2001 IC market will be served by 3.3V ICs (up from about 15 percent in 1996).*

One of the drawbacks to moving to lower voltage levels is the difficulty in improving performance at the same rate as was accomplished using 5V. As shown in Figure 4-13, low-voltage technology performance is expected to double every four generations as opposed to every two generations when using 5V. Figure 4-14 looks at some of the driving factors affecting the move to low-voltage device technology.

Figure 4-15 show excerpts from the Semiconductor Industry AssociationÕs National Technology Roadmap for Semiconductors. Because the devices described will most likely be CMOS, it can also be considered a 15-year roadmap for CMOS processing technology.

* In 1996 about 20 percent of 4M DRAMs, 30 percent of 16M DRAMs, and 100 percent of 64M DRAMs used a 3.3V power supply.

4-8 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

100

90

80

70 5V 60

50

40 3V

30 Percentage of Design Starts

20 5/3V 10 2.xV 0 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 Year Source: VLSI Technology/ICE, "Status 1997" 19179A

Figure 4-12. Transition From 5V to 3V Systems

1.0 350 0.9 315 0.8 280 0.7 245 0.6 Speed Doubles Every 210 2 Generations 0.5 175

0.4 140

0.3 105 3.3V 2.2V 1.5V 0.2 5V 70

Gate Delay (Arbitrary Units) (Low Power) 3.3V Unloaded Inverter Delay (ps)

Speed Doubles Every 4 Generations (High Speed) 2.2V 0.1 35 2µm 1µm 0.5µm 0.25µm 0.13µm

Technology Generation Source: ISSCC94/UC Berkeley/ICE, "Status 1997" 19499

Figure 4-13. Low Power Speed Lag

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Primary Feature Feature Driver Products Pros and Cons

Continued requirements for DRAMs Slowest Voltage versus Time higher integration density evolution SRAMs Integration density drives scaling Not a driver for revolutionary Device device technology changes Physics Scaling drives device physics Not a good test bed for non- Device physics limit operating device power reduction voltage, resulting in lower power techniques

High integration density circuits MPUs Basic cell performance may operating at maximum start to diminish; power limited performance bump against DSPs performance not compensated High package power constraint by scaling Performance ASICs Reduced power achieved by Increased performance will lower operating voltage or Full custom require non-device and non- design modifications scaling solutions: systems circuits, . . . .

Battery life as key operator MCUs Fastest Voltage versus Time driver

May compromise integration DSPs Non-traditional technology driver density Portable Frequency Drives revolutionary device Products May not require peak Control technologies: GaAs, modified performance (frequency, CMOS, mixed technologies delays, MIPS,. . . .) RF/An./Dig Lacks industry infrastructure and Some specialized products volume support base

Source: Motorola/ICE, "Status 1997" 20287

Figure 4-14. Voltage Reduction Drivers

The first ICs based on ²0.25µm CMOS technology are expected to be unveiled in 1997. Figure 4- 16 compares several microprocessor-oriented 0.25µm processes. The routing index shown in the figure was calculated by MicroDesign Resources in an attempt to capture the circuit density of the processes. The indexes suggest that IBMÕs CMOS-6X and TIÕs C07 offer the best circuit density, but IBMÕs process is more costly because of its additional metal layer and local interconnect.

While 0.1µm CMOS technology is not expected to be in widespread use before the year 2000, many of the large IC producers with advanced research labs are already releasing data on such devices. Figure 4-17 shows FujitsuÕs preliminary 0.1µm CMOS process parameters.

Bipolar ICs

Figures 4-18 and 4-19 show the bipolar IC market as expressed in dollars. Although the bipolar segment is shrinking in total IC marketshare (from 12 percent in 1996 to only about 7 percent in 2001), the total bipolar dollar volume is forecast to display a 9 percent CAGR from 1996 to 2001.

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Year of first DRAM shipment 1995 1998 2001 2004 2007 2010 Driver

Minimum feature (µm) 0.35 0.25 0.18 0.13 0.10 0.07

Memory Density D Bits/chip (DRAM/flash) 64M 256M 1G 4G 16G 64G

Logic Density (High volume: Microprocessor) L(µP) Logic transistors/cm2 (packed) 4M 7M 13M 25M 50M 90M Bits/cm2 (cache SRAM) 2M 6M 20M 50M 100M 300M

Logic Density (Low volume: ASIC) L(A) Transistors/cm2 (auto layout) 2M 4M 7M 12M 25M 40M

Number of Chip I/Os Chip to package (pads) high performance 900 1,350 2,000 2,600 3,600 4,800 L,A

Chip frequency (MHz) On-chip clock, cost-performance 150 200 300 400 500 625 µP On-chip clock, high-performance 300 450 600 800 1,000 1,100 Chip-to-board speed, high performance 150 200 250 300 375 475 L

Chip size (mm2) DRAM 190 280 420 640 960 1,400 Microprocessor 250 300 360 430 520 620 ASIC 450 660 750 900 1,100 1,400

Oxide Thickness (nm) 7-12 4-6 4-5 4-5 <4 <4 µP

Junction Depth (µm) 0.1-0.2 0.1-0.15 0.07-0.13 0.05-0.1 <0.07 <0.05 µP

Maximum number wiring levels (logic) On-chip 4Ð5 5 5Ð6 6 6Ð7 7Ð8 µP

Minimum mask count 18 20 20 22 22 24 L

Power supply voltage (V) Desktop 3.3 2.5 1.8 1.5 1.2 0.9 µP Battery 2.5 1.8Ð2.5 0.9Ð1.8 0.9 0.9 0.9 A

Maximum power High performance with heatsink (W) 80 100 120 140 160 180 µP Logic without heatsink (W/cm2) 5 7 10 10 10 10 A Battery 2.5 2.5 3.0 3.5 4.0 4.5 L

A=ASIC D=DRAM L=Logic µP=Microprocessor Source: SIA/ICE, "Status 1997" 20286C

Figure 4-15. The 15-Year SIA Roadmap

Bipolar IC technology has survived the onslaught of MOS to remain strong on two frontsÑvery high speed drivers and analog. Fundamentally, both product areas exploit the inherent capabili- ties of the bipolar transistor.

Bipolar technology remains popular in analog ICs because of the better gain and power handling capability of the bipolar transistor, as well as the fact that bipolar analog chips tend to be more rugged than their CMOS counterparts.

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Vendor AMD Digital Fujitsu IBM* IDT Intel TI TI Process Name CS-44 CMOS-7 CS-70 CMOS-6X CEMOS-10+ P856 C07 C07 Example Product K6+ 21264+ n/a PPC 60x+ n/a Deschutes n/a n/a First Production 2H97 1H98 2H97 2H97 1H98 3Q97 3Q97 1Q98 Supply Voltage 2.5V 1.8V 2.5V 1.8V 2.5V 1.8V 1.8V 1.8V I/O Voltage (Max) 3.3V 3.3V 3.3V 3.3V 3.3V 2.5V 3.3V 3.3V Gate length (Drawn) 0.25µm 0.25µm 0.24µm <0.25µm 0.25µm <0.25µm 0.21µm 0.18µm Channel length (Effective) 0.18µm 0.16µm 0.18µm n/a 0.20µm n/a 0.17µm 0.14µm Gate Oxide Thickness n/a 45Å 55Å 40Å 65Å 45Å 40Å 36Å Number of Metal layers 5 metal 6 metal 5 metal 6 metal 4 metal 5 metal 5 metal 5 metal Local Interconnect? yes no yes yes no no no no Stacked Vias? yes yes yes yes yes yes yes yes M1 Contacted Pitch 0.88µm 0.84µm 0.9µm 0.7µm 0.94µm 0.64µm 0.85µm 0.85µm M2 Contacted Pitch 0.88µm 0.84µm 0.9µm 0.9µm 1.1µm 0.93µm 0.85µm 0.85µm M3 Contacted Pitch 0.88µm 1.7µm 0.9µm 0.9µm 1.1µm 0.93µm 0.85µm 0.85µm M4 Contacted Pitch 1.13µm 1.7µm 0.9µm 0.9µm 1.1µm 1.6µm 0.85µm 0.85µm M5 Contacted Pitch 3.0µm 1.7µm 2.7µm 0.9µm 1.4µm 2.6µm 2.5µm 2.5µm SRAM Cell Size n/a 11.5µm2 n/a 8.6µm2 11.2µm2 10.3µm2 10.5µm2 10.5µm2 Routing Index 0.60µm2 1.1µm2 0.62µm2 0.53µm2 1.0µm2 0.67µm2 0.56µm2 0.56µm2 Wafer Cost Index $4.0 $3.5 $4.0 $4.7 $3.6 $4.0 $4.1 $4.2 * Motorola's PPC4 is similar to CMOS-6X but may have smaller gates. + indicates shrink version. Source: MicroDesign Resources/ICE, "Status 1997" 21747

Figure 4-16. A Look at Some 0.25µm Processes

Parameter NMOS PMOS

Starting Material 10Ωcm p-type (100) 10Ωcm p-type (100) Well Twin Well Twin Well Isolation 350nm LOCOS 350nm LOCOS Channel Implant B+ 40keV 7 x 1012 As+ 180keV 5 x 1012 Gate Oxide 3.9nm (800°C) 3.9nm (800°C)

Gate Stack Poly-Si 160nm + SiO2 50nm Poly-Si 160nm + SiO2 50nm 13 14 Shallow Junction Implant As+ 10keV 4 x 10 BF2+ 5keV 1 x 10 Spacer SiN 60nm SiN 60nm 15 15 Deep Junction Implant As+ 30keV 3.2 x 10 BF2+ 20keV 5 x 10 Anneal 850°C, 5 minutes 850°C, 5 minutes Source: Fujitsu/IEDM/ICE, "Status 1997" 19214

Figure 4-17. Process Parameters of 0.1µm CMOS

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1%

100 6% 6% 10% ECL 12% 2% 90 8% 12%

80

TTL AND 32% 70 42% OTHER

60

97% 50 86% Percent 82% 40

30 ANALOG 56% 48% 20

10

0 1982 1987 1995 2001 $4.6B $10.6B $16.2B $24.3B 1996 (FCST) $14.6B (EST) Year Source: ICE, "Status 1997" 12073T

Figure 4-18. 1982-2001 Bipolar Technology Trends ($)

1987 Ð 2001 1987 1995 1996 2001 Technology CAGR ($M) ($M) ($M, EST) ($M, FCST) (Percent)

ECL 1,265 992 815 365 Ð8

TTL and Other 3,400 1,893 1,190 385 Ð14

Bipolar Analog 5,935 13,330 12,600 23,500 10

Total 10,600 16,215 14,605 24,250 6

Source: ICE, "Status 1997" 16812L

Figure 4-19. Bipolar Technology Market Trends (1987-2001)

In digital applications, on the other hand, bipolar technology has lost most of the advantages it once had over CMOS. Bipolar ICs consume a great deal of power per logic function, so when the highest absolute speed is not required, CMOS is the better solution. Bipolar ICs still find design wins in very high speed applications, such as communications in the telecom industry and main- frame computers. Figure 4-20 shows that the market for digital bipolar ICs is declining in each of the product areas listed.

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1995 - 2001 1995 1996 2001 Product CAGR ($M) ($M, EST) ($M, FCST) (Percent)

General Purpose Logic 1,265 890 350 Ð19 Special Purpose Logic 530 370 110 Ð23 Gate Array/Std. Cell 735 530 160 Ð22 MPU/MCU/MPR 10 8 1 Ð32 FPL 115 57 9 Ð35 Memory 230 150 35 Ð27 Total 2,885 2,005 665 Ð22

Source: ICE, "Status 1997" 18881F

Figure 4-20. Digital Bipolar IC Market

Inherently, ECL devices are very uniform, stable, and generate low noise. Also, ECL requires only a 1V swing in 3-4ns compared with a typical TTL chip that requires a 5V swing in the same time- frame. ECL-based ICs include gate array ASICs, standard and special purpose logic devices, and SRAMs (Figure 4-21).

Logic* 15% Memory 1992 19% $1,320M ASIC 66%

Memory Memory 18% 19% 1996 2001 ASIC (EST) ASIC (FCST) 43% Logic* $815M 47% Logic* $365M 35% 38%

*Includes General and Special Purpose Logic Source: ICE, "Status 1997" 21085B

Figure 4-21. ECL IC Market by Product Group

The major ECL IC manufacturers are shown in Figure 4-22. These producers accounted for about 96 percent of the merchant ECL IC market in 1996. The Japanese companies have traditionally had the largest ECL IC marketshare primarily because of their emphasis on mainframe computers.

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1996 Sales Marketshare Company Major Emphasis (EST, $M) (Percent) Fujitsu 215 26 ASICs, SRAMs, Logic Motorola 180 22 ASICs, Logic Hitachi 155 19 SRAMs, Logic NEC 120 15 ASICs, SRAMs Siemens 40 5 ASICs AMCC 35 4 SRAMs, Logic Synergy 30 4 ASICs National 10 1 Logic Others 30 4 — Total 815 100 —

Source: ICE, "Status 1997" 17130K

Figure 4-22. Major ECL IC Suppliers

The movement to using other technologies besides ECL for high-speed systems is especially dev- astating to the large military ECL IC market. The lackluster military IC market coupled with the increasing use of CMOS, GaAs, and BiCMOS ICs will heavily contribute to the declining ECL IC industry in the mid-to-late 1990Õs.

It now appears unlikely that future improvements in ECL technology will come from the purely merchant IC vendors. This is due in some part to the relatively small ECL IC market and the low volume of research money being spent on ECL technology by the open-market vendors.

BiCMOS ICs

Because BiCMOS offers advantages over both bipolar digital and CMOS, it will eventually replace a small portion of the high-end market held by pure ECL and CMOS ICs. Some BiCMOS devices now produced include: MPUs (e.g., the Pentium), smart-power ICs, bus drivers, analog-to-digi- tal converters, track/hold amplifiers, disk-drive controllers, memory controllers, SRAMs, PLDs, gate arrays, and standard cells.

BiCMOS technology has been considered a high-speed replacement for pure CMOS because it offers a performance edge by implementing both CMOS and bipolar transistors on the same chip. Through the selective use of CMOS and bipolar circuitry, high-performance paths can be created with bipolar, while lower-performance, high-density paths can be created with CMOS gates.

BiCMOS architecture that consists of a small percentage of bipolar transistors is called CMOS- based. For this architecture, non-critical paths (the majority of the chip) consist of CMOS gates, while bipolar transistors are used mainly for driving long metal lines and as output buffers (crit- ical paths). This is the most common type of BiCMOS technology.

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Bipolar-based BiCMOS architectures consist of predominantly bipolar transistors with CMOS transistors available for the implementation of large storage elements. The resulting IC offers excellent performance and density with a high level of programmability.

The main disadvantage of BiCMOS is the cost penalty created by the complicated process of build- ing both bipolar and MOS transistors into a single device. It is partly because of this increased complexity that Intel has stated it will move the Pentium MPU from a 20-mask BiCMOS process to a 16-mask pure CMOS technology. The other reason is that while bipolar transistors provide some performance boost at 3.3V, the gain is insignificant at 2.5V and below.

Because the performance advantage of BiCMOS decreases with lower voltage levels, the future of BiCMOS in the systems of the late-1990Õs depends on the ability to economically produce special- ized BiCMOS processes. ToshibaÕs BipnMOS process described above is one example of a spe- cialized complementary BiCMOS process. Motorola also has specialized BiCMOS processes that target ASIC, very high-speed, and low-voltage applications. The supply voltage sub-0.5µm BiCMOS triangle will especially challenge the BiCMOS producers in the mid- to late-1990Õs.

As shown in Figure 4-23, besides the Pentium-dominated microcomponent area, the analog/mixed-signal segment is a strong market for BiCMOS ICs. BiCMOS is also popular for very high-speed SRAMs, with the access times of some BiCMOS SRAMs stated to be half those of most CMOS SRAMs of the same density. Furthermore, ECL SRAMs canÕt match BiCMOS densities.

Standard Standard Standard Cell Logic Logic 2% 1% Gate Arrays Gate 4% Other 3% Other Arrays 1% <1% SRAMs 7% Analog/ 3% Microcomponents Mixed Signal 11% 15% Analog/ 1996 (EST) 2001 (FCST) Mixed Signal Standard Cell $18,665M $12,190M 53% 11% Microcomponents SRAMs 76% 13%

Source: ICE, "Status 1997" 13643Q

Figure 4-23. Worldwide BiCMOS Market Forecast

As shown in Figure 4-24, the BiCMOS market was led by microcomponent (i.e., Pentium) products in 1996. The total BiCMOS IC market is expected to decline at a nine percent average annual rate from 1996-2001, and only represent four percent of the total IC market in 2001. This decline is due to IntelÕs plan to move its advanced MPU products from BiCMOS to CMOS in the late 1990Õs.

4-16 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

Through the end of 1996, all of IntelÕs Pentiums and Pentium Pros were manufactured using BiCMOS technology. IntelÕs first pure-CMOS Pentiums should appear in early 1997 as the com- pany moves to its 0.28µm process. It should be noted that the timing and completeness of IntelÕs conversion will have a tremendous impact on the total BiCMOS market figures in the late 1990Õs!

1995 1996 (EST) 2001 (FCST)

Product Percent of Percent of Percent of $M Product $M Product $M Product Category Category Category

SRAMs 575 9 555 11 1,600 14

Gate Arrays 460 8 475 8 800 8

Microcomponents 9,520 28 14,140 36 1,345 1

Analog/Mixed Signal 2,305 13 2,800 16 6,500 18

Standard Logic 250 7 275 9 415 11

Standard Cell 200 4 350 5 1,380 7

Other 50 <1 70 <1 150 <1

Total 13,360 10 18,665 16 12,190 4 *Assumes some versions of Pentium and Pentium Pro will continue to be produced in BiCMOS and that the P7 family will not be BiCMOS.

Source: ICE, "Status 1997" 16820L

Figure 4-24. Worldwide BiCMOS Marketshare

As shown in Figure 4-25, Intel is by far the largest producer of BiCMOS ICs. Two European com- paniesÑPhilips and SGS-ThomsonÑare also heavily involved in BiCMOS technology, with the focus of both being on analog and mixed-signal ICs. MotorolaÕs BiCMOS ICs encompass a vari- ety of products, including memory, ASIC, logic, and analog devices.

Provided below are a few announcements made in 1996 concerning BiCMOS ICs and technologies.

¥ Startup Exponential Technology Inc. introduced its 533MHz X704, a PowerPC 604 bus-com- patible RISC microprocessor. The X704 is estimated to have a SPECint95 performance rating of 11-13 and a SPECfp95 rating of about 10. The chip is based on a 0.5µm bipolar-based BiCMOS process, with a 0.35µm process shrink scheduled for 1998. Most of the logic is bipo- lar, with CMOS mainly for the dense memory structures and I/O cells (Figure 4-26). ExponentialÕs processor should appear in systems in 2Q97.

¥ NEC announced the development of a mixed-signal ASIC family that uses a 0.6µm BiCMOS process. The MA-8 Series integrates CMOS gate array and analog semicustom IC functions on a single chip with up to 28,000 gates available in the array portion and about 5,000 ele- ments in the analog unit.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-17 IC Technology and Packaging Trends

Company 1995 Sales ($M) 1996 Sales ($M,EST)

Intel 9,440 13,925 SGS-Thomson 993 1,390 Philips 975 1,100 Texas Instruments* 200 370 Motorola 350 350 Fujitsu 190 160 NEC 175 160 Analog Devices 125 130 Alcatel-Mietec 102 110 Others 810 970 Total 13,360 18,665 *Acquired the major BiCMOS IC supplier, Silicon Systems, in 1996. Source: ICE, "Status 1997" 21084B

Figure 4-25. Major BiCMOS IC Suppliers

Bipolar Cells I/O Buffers

CMOS Cells

32Kbyte Level Two Cache Exponential X704 Core

Floating PLL Point & Unit Clocks

2Kbyte 2Kbyte I/O Buffers Level One Branch Level One Instruction Predict Data Bus Cache Cache Control Level Two Cache Tag I/O Buffers ¥ Custom bipolar cell library which allows for high-speed core ¥ High-density CMOS to implement caches Source: Exponential Technology/ICE, "Status 1997" 21748

Figure 4-26. ExponentialÕs Bipolar-Based BiCMOS X704 RISC Microprocessors

¥ Silicon Systems (now owned by Texas Instruments) entered into the 155Mbit/second asyn- chronous transfer mode (ATM) IC market in early 1996 with the introduction of an ATM transceiver IC based on its 1.0µm BiCMOS process technology. The use of BiCMOS technol- ogy allows the device to draw only 65mA from a 5V power supply.

4-18 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

The complexity of the BiCMOS process, especially for low-voltage devices, continues to challenge the IC producer. Some IC manufacturers have been less sure about the future of BiCMOS as fea- ture sizes shrink to less than 0.5µm. In general, it appears that besides the mid-1990Õs Pentium use of BiCMOS, only the very high performance segment (~5-20 percent) of a particular product category will require the use of the typically costly and complex BiCMOS technology.

Gallium-Arsenide (GaAs) ICs

Gallium-Arsenide material has an inherent speed advantage over silicon. However, for years the added cost of the starting material, the problems with breakage (the material is very brittle), and the higher defect density with the corresponding lower device yields have kept the market pene- tration low. The situation is changing. As GaAs device manufacturers convert to 100mm wafers* and continue to shrink device features to as small as 0.3µm, GaAs ICs are becoming more cost competitive with silicon.

The total GaAs market (excluding development funding) is forecast to have a 1996-2001 CAGR of 27 percent, growing to about $2.1 billion in 2001 (Figure 4-27). As also shown in the figure, growth in the demand for analog GaAs ICs is expected to significantly outpace that for digital GaAs ICs during the time period. Analog ICs represented about 75 percent of the GaAs IC market in 1996, and that share is expected to increase to 83 percent by 2001.

Figure 4-28 shows the GaAs IC market by end-use market. At first, the military and aerospace industries were to be big applications for GaAs technology, since customers in those areas would likely pay the higher prices for GaAs device to bypass siliconÕs speed limits in microwave com- munications and radar. However, steep government spending cuts on defense put a damper on that expectation. Then, GaAs was expected to make next-generation supercomputers lightning fast. But advances in silicon allowed multiple-silicon-chip systems to do it, for less. Finally, the booming market for communications equipment has led to the long-awaited commercial success of GaAs IC technology.

Some of todayÕs most attractive market areas for GaAs technology are cellular phones, digital per- sonal communications systems, local networks, satellites, broad-band tuners, automotive sensors, and sophisticated space systems. High-speed computing and fiber-optic applications may offer substantial volumes for high-performance GaAs devices as well. Several applications for analog GaAs ICs are shown in Figure 4-29, while digital GaAs IC applications are shown in Figure 4-30.

* Some leading GaAs IC producers will attempt to move to 150mm wafers in 1997. Sumitomo Electric began shipping samples of 150mm GaAs wafers in 3Q96.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-19 IC Technology and Packaging Trends

2,200 2,130 Analog IC Sales 2,000

Digital IC Sales

1,800 Development Funding 1,660 1,600

1,400 1,305 1,760 1,200 1,035 1,000 1,345 870 800

Millions of Dollars 710 1,035 590 600 520 800 435 625 390 400 490 395

395

180 240

55 6060 350

200 100 20 20 20 295 20 95 120 140 160 185 215 250

110 100 90 0 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001

Year *Includes development funding. Source: ICE, "Status 1997" 17134H

Figure 4-27. Worldwide GaAs IC Merchant Market* Forecast

Military/ Aerospace 9% Other 6% Military/ Computer Computer Aerospace 14% 12% 20% Other 8% 1996 (EST) 2001 (FCST) $650M Telecom $2,110M 73% Telecom 58%

*Not including development funding. Source: ICE, "Status 1997" 13329N

Figure 4-28. Total GaAs IC Market* by End Use

If the GaAs IC market is ever destined to break the $1.0 billion barrier it will be because of a surge in the RF/MMIC analog GaAs marketplace. While there is still some question as to whether there will be significant demand for digital GaAs ICs used in computer systems, high-volume use of analog GaAs ICs in 2.4GHz and higher performance wireless communications is almost guaran- teed. At speeds below 500 to 800MHz, silicon is almost always the better choice. However, begin- ning at 800 to 900MHz and above, the contest is much closer, and above 2.4GHz, GaAs devices are almost always superior. GaAs also offers comparable or better low-noise performance, low-volt- age operation, and system level cost and performance beginning in the gigahertz range.

4-20 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

Mobile Satellite Fiber-Optic Wireless Data Communications Receivers Communications Communications

¥ Cellular Telephones ¥ Global Positioning System ¥ Long-Haul ¥ Wireless LANs ¥ Cordless Telephones ¥ Very Small Aperture Terminals ¥ LANs ¥ WANs ¥ Personal Communications Networks ¥ Mobile Satellite Systems ¥ WANs ¥ Pagers ¥ Microwave Radio Links ¥ Fixed Satellite Systems ¥ Local Loop

Source: Epitaxial Products International/ICE, "Status 1997" 21749

Figure 4-29. Communications Applications for GaAs Analog ICs

High Speed Telecommunications: ¥ DEMUX, MUX, high-speed logic paths, decision circuits, and switching. ¥ Require high-speed, low power for SONET, SDW, ATM, and ISDN (up to 2.5GHz). Data Telecommunications: ¥ High-speed serial data communications between mainframes, servers, workstations, and peripherals. ¥ Standards requiring GaAs performance include HiPPI, FDDI, SCI, ESCON, and FCS. Automatic Test Equipment: ¥ Replaces ECL in applications requiring low power, lower cost, and improved performance. High Speed Computing: ¥ Collapse of Cray Computer was big set back.

¥ Some major players still looking at GaAs, including: Fujitsu, HP, Unisys, ARPA (US), and IBM.

Source: Epitaxial Products International/ICE, "Status 1997" 21750

Figure 4-30. Primary Applications for Digital GaAs ICs

Currently the GaAs IC industry is dominated by planar-type structured circuits, including JFETs and MESFETs. Heterostructure-type circuits, such as HBT, high-electron-mobility transistor (HEMT), and pseudomorphic HEMT (PHEMT) ICs are gaining wider acceptance. HBTs and HEMTs are generally considered more efficient than conventional MESFETs, especially at high fre- quencies, but are more difficult and expensive to manufacture. HBTs and HEMTs are not expected to replace MESFETs, but will be widely used in emerging high-frequency applications.

Strong demand for GaAs ICs in communications applications has allowed many suppliers to endure the recent slump in the semiconductor industry. For example, Vitesse SemiconductorÕs IC sales grew an estimated 58 percent in 1996 (Figure 4-31). The other leading U.S.-based suppliersÑ Anadigics and TriQuint SemiconductorÑposted sales increases in 1996 as well. Moreover, while many silicon IC manufacturers have cut their capital spending budgets, GaAs IC firms are busy with major capacity expansions (Figure 4-32).

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-21 IC Technology and Packaging Trends

1995 Sales* ($M) 1996 Sales* ($M, EST) Company Analog Digital Total Analog Digital Total

Fujitsu 56 36 92 65 35 100 Anadigics 50 — 50 65 — 65 Vitesse 1 38 39 2 58 60 TriQuint 18 28 46 28 30 58 TI 30 5 35 42 3 45 Rockwell 22 6 28 28 7 35 Oki 27 5 32 29 4 33 Thomson/Daimler** 22 — 22 25 — 25 NEC 25 — 25 25 — 25 Mitsubishi 20 — 20 20 — 20 Others 124 22 146 161 23 184 Total 395 140 535 490 160 650 * Not including development funding. ** In early 1996 the GaAs IC businesses of Thomson-CSF, TEMIC, and Daimler-Benz Aerospace were combined to form a new company headquartered in Orsay, France. Source: ICE, "Status 1997" 18111H

Figure 4-31. Major GaAs IC Suppliers

Company Existing Capacity New Capacity

Anadigics 3in wafer fab in Warren, New Jersey, Existing fab is being converted to 100mm with a capacity of 400 wafers per week. wafers for most of the company's products. Also, Anadigics is constructing a new $35 million cleanroom adjacent to its existing fab for the production of 100mm wafers beginning in 4Q97. The new line will be upgradeable to 150mm wafers.

M/A-COM Fab in Lowell, Massachusetts, upgraded Acquired the 100mm wafer line in Colorado over the past two years through the Springs, Colorado, formerly owned by Cray conversion of its 3in wafer line to 100mm. Computer.

RF Micro Devices Currently fabless. TRW is its foundry Building its first fab in Greensboro, North supplier. Carolina. Phase I construction of the $70 million 100mm wafer fab is scheduled to be completed by 1Q98. It will have the capacity to produce 480 wafers per week.

TriQuint Semiconductor 100mm wafer fab in Beaverton, Oregon, Building a $40 million manufacturing and with a capacity of 1,000 wafers per week. office complex in Hillsboro, Oregon. It is scheduled for completion in mid-1997.

Vitesse Semiconductor 100mm wafer fab in Camarillo, California, Building a new $75 million fab in Colorado with a capacity of 1,700 wafers per week. Springs to produce 150mm wafers. The fab will be the company's high volume production center and is planned for completion in 2H98.

Source: ICE, "Status 1997" 21751

Figure 4-32. Expanding to Meet GaAs Demand

4-22 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

Provided below are a number of GaAs-related announcements made in 1996.

¥ Alpha Industries Inc. announced in 4Q96 that it would divest its European ceramics manu- facturing operation and its digital radio subsystem product line as part of a strategic focus on GaAs components for the wireless communications industry. In response to strong orders for its GaAs MMICs, the company is revamping its GaAs fab in Woburn, Massachusetts, to handle 100mm wafers.

¥ Philips Semiconductors announced a complete range of GaAs MMIC power amplifiers that are compatible with all the emerging digital cellular and cordless phone standards. The move establishes Philips as a major supplier of GaAs devices for wireless communications. Philips has been developing and running prototype GaAs chips for several years at its sub- sidiary Philips Microwave Limeil in France (see next bullet). TriQuint Semiconductor is manufacturing the new devices as part of a major wafer sourcing and technology sharing agreement signed by the two companies in March 1996.

¥ TRW and RF Micro-Devices formed a strategic alliance for the development, production, and distribution of HBT-based GaAs ICs for wireless communications systems. RF Micro Devices is also building its first wafer fab, located in Greensboro, North Carolina. The first phase of the fab is scheduled to be completed in 1Q98.

¥ Oki unveiled a new epitaxial-implant GaAs process for producing high-efficiency RF devices for digital communications systems at 3V. The new process results in very low distortion and high gain in driver and power amplifiers.

¥ Vitesse announced in late August 1996 that it had brought out the industryÕs first Gigabit Ethernet transceiver. The single-chip, 1.25Gbit/second transceiver features digital clock and data recovery, on-chip high-speed clock generation for transmission, and 700mW power dissipation.

¥ Thomson-CSF and Daimler-Benz announced in April 1996 that they would link together the GaAs operations of Thomson-CSF in France with the Daimler-Benz research unit in Ulm, Germany, to form a new company to develop, produce, and sell GaAs ICs for both commer- cial and defense electronics applications.

Silicon-Germanium (SiGe) ICs

As semiconductor manufacturers struggle to put more transistors on each chip and increase cir- cuit speed, the physical and electrical limitations of silicon wafers become a major concern. As a result, alternative materials are being considered.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-23 IC Technology and Packaging Trends

For years, it was thought that gallium arsenide would become the new wafer material of choice. It now appears as though GaAs will never be considered more than a niche technology. Even though the GaAs IC market is forecast to grow at an average rate of more than 25 percent per year through the end of the decade, it will still continue to represent only a very small percentage of the total IC market.

In 1991, IBM announced it was dropping its gallium-arsenide efforts in favor of silicon-germa- nium (SiGe) technology. Today, IBM is unquestionably the leader in SiGe research and develop- ment. Research at IBM and other laboratories around the world is seeing promising performance advantages with SiGe. In fact, IBM claims that SiGe technology provides a 200-300 percent increase in transistor speed with a minimal rise in production cost.

The concept behind SiGe is to add (through the doping process) the benefit of germaniumÕs high carrier mobility* to a silicon wafer. The electron mobility in silicon germanium is nearly twice that in pure silicon. High mobility benefits both bipolar and field effect transistor (FET) devices. Shown in Figure 4-33 is a cross section of IBMÕs high-performance FET designed using its new 0.25µm BiCMOS SiGe process. Figure 4-34 provides a list of several SiGe circuits that have been developed.

Source Gate Drain

SiO2

N+ Si

SiGe (30%)

Silicon

Silicon-Germanium (SiGe)

Silicon Channel Two Degree Electron Gas Silicon-Germanium Graded Buffer

Source: IBM Corp./ICE, "Status 1997" 18736

Figure 4-33. IBMÕs High-Performance SiGe FET

* Electron mobility in germanium is 3,900cm2/Vs versus 1,500 in silicon. Hole mobility in germanium is 1,900 versus 450 in silicon.

4-24 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

Circuit Performance Company Year

ECL ring oscillator 19ps, fT=51GHz NEC 1992

ECL ring oscillator 17.2ps, fT=48GHz IBM 1993

ECL ring oscillator 22ps, fT=40GHz TEMIC 1993

DAC 1 GHz, 12bit IBM 1993

2:1 multiplexer 16Gbit/s, fT=40GHz RUB* 1993

D-type F/F 20Gbit/s NEC 1994

Selector 30Gbit/s, 33ps NEC 1994

2:1 multiplexer 20Gbit/s, fT=60GHz NEC 1994

Preamplifier bw=19GHz, 36dBΩ NEC 1994

Gain block bw=18GHz, 9.5dB, Daimler-Benz 1995

Oscillator, coplanar 28GHz, +1dBm Daimler-Benz 1995

VCO, microstrip 40-42GHz, Ð12dBm Daimler-Benz 1995

Mixer 2GHz, fif=150MHz TEMIC 1995

* RUB = Ruhr Universität Bochum

Source: Daimler-Benz/ICE, "Status 1997" 21190

Figure 4-34. Sampling of SiGe ICs That Have Been Developed

IBM has been working with several other IC manufacturers in the industry to commercialize products based on its SiGe process technology. In 4Q93, IBM and Analog Devices began working together to develop SiGe ICs targeting the wireless communications market. These SiGe devices are set to challenge GaAs at frequencies at or above 1GHz.

In mid-1996 IBM announced an agreement with Hughes Electronics to jointly develop commer- cial communications devices based on IBMÕs SiGe technology. The multiyear deal calls for the SiGe devices to reach market as early as 1997.

Telefunken Semiconductors, a part of TEMIC, began volume production of a SiGe analog RF IC in the first half of 1996. The device contains 30 transistors and has a die size of two square millime- ters with feature sizes of 1.0µm. It is in competition with GaAs ICs since it is targeted at 1.8GHz mobile telecom applications as a power amplifier.

SiGe will not only be competing with GaAs but also with BiCMOS and even bipolar technologies in the wireless communications market. The technology that gains the greatest marketshare will be the one that can ÒeconomicallyÓ meet the performance requirements of the growing number of high-performance applications.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-25 IC Technology and Packaging Trends

IC MACROTRENDS

Integration Density Trends

Integration levels have grown continually since the invention of the IC. The MOS integration levels have increased an average of 35 to 50 percent per year for the past 24 years (Figure 4-35). As shown, MOS memory ULSI ICs are expected to contain over 256 million transistors by 1998 and ICs with 1 billion transistors per chip are forecast to appear on the market by the year 2000.

1G 1G

Pentium Pro 256M MPU and Cache Memory Chip 100M 64M P8? 16M P7? 10M Pentium Pentium Pro MPU Only 4M IBM 80486 Gate 1M 1M Array LSI Logic 256K 80386 Gate Array 68020 80286 100K 64K

Number of Transistors per Chip 68000

16K 8086

10K 4K 8085 8080 1K = Microprocessor/Logic 4004 = Memory (DRAM) 1K 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00 02 Year Memory increase = 1.5/year MPU increase = 1.35/year Source: ICE, "Status 1997" 11745P

Figure 4-35. IC Density Trends

Considering that some companies are making significant progress in the 1G DRAM research and the fact that 256M DRAMs are being sampled, it currently appears the DRAM IC density trend line will be intact through at least the early 2000Õs.

4-26 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

IntelÕs Pentium MPU (3.1 million transistors) fell slightly short of the MPU/Logic trend line in 1993, and the Pentium Pro CPU also fell short in 1995 at 5.5 million transistors. It should be noted that Intel initially split the Pentium Pro MPU and its SRAM cache memory (16 million transistors) into separate dice that are packaged in a multichip module. Intel plans to introduce its single-chip version of the Pentium Pro in the first part of 1997.

Die Size Trends

As the number of transistors per die has escalated, average die sizes have also been increasing. Figure 4-36 shows that the die area of leading-edge ICs has increased about 13 percent per year. The trend toward larger die sizes, at least for memory, is forecast to continue at this rate into at least the early 2000Õs.

2,000 P8? P7? Pentium Pro 1,000 MPU and Cache 800 1G IBM 600 Pentium Gate Array Pentium Pro 400 MPU R4000 256M Only 80486 64M P54C 200 16M 80386 68020 80286 4M 100 68000 1M 80

60 256K 8086 Z80 40 16K 64K Chip Area (Thousands of sq mils) 8080 4K 20 = Microprocessor/Logic = Memory 10 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 00 02 Year Memory increase = 1.13/year MPU increase = 1.13/year Source: Intel/ICE, "Status 1997" 11746Q

Figure 4-36. IC Die Size Trends

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-27 IC Technology and Packaging Trends

To illustrate how risky it is to continue to extrapolate current trends far into the future, a look at the die sizes of leading-edge DRAMs introduced at the ISSCC (International Solid-State Circuits Conference) proves interesting.

The die sizes of the 1G DRAMs described at the 1995 and 1996 ISSCCs ranged from 901K sq. mils to 1,451K sq. mils (Figure 4-37). As shown, the NEC 1G DRAM if square (most DRAMs are rec- tangular) would be about 1.2 inches on a side!

Feature Cell Chip Size Access Company Density Organization Conference Size (µm) Size (µm2) (K sq. mils) Time (ns)

Hyundai 256M 0.3 — 561 36 32M x 8 ISSCC '95 Matsushita 256M 0.25 0.72 638 — 16M x 16 ISSCC '94 Mitsubishi1 256M 0.25 0.72 472 34 32M x 8 ISSCC '94 Oki2 256M 0.25 0.72 530 — 32M x 8 ISSCC '94

Mitsubishi3 1G 0.14 0.29 901 32 — ISSCC '96 Samsung4 1G 0.16 — 1,010 — — ISSCC '96 Hitachi 1G 0.16 0.29 1,108 33 64M x 16 ISSCC '95 NEC 1G 0.25 0.54 1,451 — — ISSCC '95 1 Produced using KrF excimer-laser lithography. 2 Packaged in a 64-pin 600-mil TSOP, produced using e-beam lithography. 3 SDRAM produced using synchrotron-generated x-ray lithography. 4 SDRAM produced using KrF excimer-laser lithography. Source: ICE, "Status 1997" 20289A

Figure 4-37. ISSCC Advanced DRAMs

NEC is expected to unveil what it believes is the first 4G DRAM in the industry at the 1997 ISSCC in February. The prototype chip measures 1,527K sq. mils and has a 0.23µm cell that can store four levels of data, compared to two levels in conventional cells (i.e., 1 or 0).

Extrapolating out to 2003 ISSCC announcements, a 6.58M sq. mil 256G DRAM, if square, would be 2.6 inches on a side. Given the typical 2:1 aspect ratio of the DRAM die, the 2003 DRAM die size would be about 3.6 inches by 1.8 inches.

As shown, this die size begins to approach what we would now call wafer-scale integration. What wafer size would be needed for such a huge die to be practicalÐÐ300mm (12 inch), 400mm (16 inch), or larger? What level of redundancy would be needed to keep yields above zero? What about defect density levels?

By 2003 the IC industry may be forced into some type of three-dimensional (stacking one or more transistors on top of each other) technology in an attempt to keep die size manageable. However, three-dimensional technology will come with its own set of constraints and problems that one cannot even fully imagine at this time.

4-28 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

Other economic factors also come into play as a result of increasing die sizes. For example, about 150 Ò1983-describedÓ 256K DRAMs were able to fit on a 100mm (4Ó) wafer (the most popular wafer size at that time). However, only about 68 Ò1994-describedÓ 256M DRAMs could fit on a 200mm wafer today. Using an extrapolated ISSCC 2003 256G DRAM chip size, only about 12 would fit on a 300mm wafer (Figure 4-38)!

Source: ICE, "Status 1997" 19501

Figure 4-38. Twelve 3.6-inch x 1.8-inch Ò2003 256G DRAMsÓ Fit on a 12-inch Wafer

While it is difficult enough to imagine a 3.6Ó x 1.8Ó die, it is even more difficult to imagine the eco- nomic practicalities of producing such a die. As was mentioned earlier, IntelÕs division of the Pentium Pro into an MPU die and cache memory die may signify the ultimate response to con- cerns over huge die sizes.

Wafer Size Trends

The usual IC industry response to ever larger dice has been to increase wafer size. Just as 200mm wafers have become the standard for high-volume advanced IC production, there has been an increased interest in preparing for the next standard wafer sizeÑ300mm (12 inch).

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-29 IC Technology and Packaging Trends

There exist a few fundamentally sound reasons why the IC industry has settled on the 300mm diameter and not another size for wafer processing. A move to 250mm wafers does not yield a significant enough increase in area to justify the much higher equipment investment (Figure 4-39). Also, relatively few cost benefits result from increases to wafer sizes of 350mm or 400mm, because the 350mm/400mm processing equipment will require significantly higher development costs than for 300mm.

56 4" → 5"

→ 4" 6" 125

5" → 8" 156

6" → 8" 78

→ 56 8" 10"

Wafer Diameter Transition → 10" 12" 44

8" → 12" 125

0 50 100 150 200 Percent Increase

Source: EMR/ICE, "Status 1997" 18603

Figure 4-39. Wafer Area Increases (Percent)

It is estimated that the industryÕs cost to develop and perfect the fabrication techniques needed to make 300mm wafers will be in the area of $15 billion to $20 billion. The lack of funding appears to be the greatest barrier to the transition. No one company is stepping up to carry the financial burden, as IBM and Intel did the last two wafer size transitions. Fear of commitment is holding companies back on all sides. Equipment companies are hesitating to building production tools until they receive firm orders, yet IC manufacturers holding back on placing orders until they can evaluate real equipment.

Two major industry consortia were formed in 1996 with the hopes of lowering the barriers to development. One effort is the International 300mm Initiative (I300I) formed by Sematech in January 1996. Participation in I300I is open to U.S. IC manufacturers and foreign companies with wafer fabs located in the U.S. (Figure 4-40). Current funding is said to be $2 million from each of the 13 participants and is expected to sufficiently cover the initial 18 month program. By 3Q97, I300I member companies plan to begin 300mm beta site equipment demonstrations and also begin defining and understanding requirements for 0.18µm manufacturing.

4-30 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

U.S. Companies Advanced Micro Devices IBM Intel Lucent Technologies Motorola Texas Instruments European Companies Philips SGS-Thomson Siemens Korean Companies Hyundai LG Semicon Samsung Other Companies TSMC (Taiwan) Source: ICE, "Status 1997" 21753

Figure 4-40. I300I Member Companies

The Japanese formed their own consortium in February 1996. The Semiconductor Leading Edge Technologies (SELETE) venture is represented by JapanÕs ten largest semiconductor companies (Figure 4-41), which plan to spend about $350 million (´35 billion) over the 1996-2000 timeframe. Like I300I, SELETE will first focus on 0.2µm, 300mm wafer manufacturing and subsequently on 0.18µm fabrication and more stringent requirements. SELETE is constructing a cleanroom within an existing Hitachi fab in Yokohama, Japan.

¥ Fujitsu ¥ Oki ¥ Hitachi ¥ Sanyo ¥ Matsushita ¥ Sharp ¥ Mitsubishi ¥ Sony ¥ NEC ¥ Toshiba

Source: ICE, "Status 1997" 21754

Figure 4-41. SELETE Member Companies

The success in transitioning to 300mm wafers will depend on the level of interaction between organizations like the I300I and SELETE for the purpose of developing global industry standards. Developmental wafer specifications have been drafted and specifications for circuit quality wafers are nearing completion. Device manufacturers have yet to agree as to how standards for wafer carriers and tool interfaces should be defined. There are eight possible combinations of lot size (13 or 25 wafers), integral versus removable cassettes, and front-opening or side-opening boxes that are being proposed.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-31 IC Technology and Packaging Trends

Once standards are in place and equipment is readied, there are additional issues that must be remedied if 300mm wafer processing is to become a reality. A few of the many wafer processing questions or concerns that must be addressed include:

¥ Ensuring uniformity of deposition and etch. ¥ Ensuring the integrity of wafer flatness across a huge diameter. ¥ Will there be only single-wafer implantation processes? ¥ Reduction or elimination of test wafer usage in the coming years. ¥ 300mm wafers will require a far lower furnace operating temperature (900¡C) versus 200mm wafers (1200¡C). ¥ What chemical quantities for processing and cleaning will be needed for 300mm wafers?

Wafer cost is another barrier that stands in the way of moving to 300mm wafer production. In 1996, the approximate price of a 300mm wafer was $1500 (possibly $1000 for larger volumes). In the early years of the next decade, when 300mm wafer usage is expected to be in higher volume, wafer costs are estimated to be in the range of $450 to $600.

Standards, equipment development, and costsÑFigure 4-42 shows SematechÕs estimates of these and other factors relative to 200mm wafers that are significant considerations in the transition to 300mm wafers.

200mm 300mm 350mm 400mm

Total Throughput* 1.00 0.60 0.50 0.40 Tool Cost 1.00 1.50 1.75 2.00 Tool Size 1.00 1.25 1.35 1.50 Wafer Cost $100 $450 $700 $1,100 *Area-based lithography, ion implant, metrology and test. Source: Sematech/ICE, "Status 1997" 19770

Figure 4-42. Considerations in Transitioning to Larger Wafers (Relative to 200mm)

Figure 4-43 compares the development time for each new wafer generation. As shown, the time required has increased significantly over prior generations. While it took five years for 200mm wafers to reach an annual production rate of 100 million square-inches per year (MSI), it has been estimated that eight years will be needed for 300mm wafers.

Early on, semiconductor producers had said they wanted to be in full production of 300mm wafers in 1998. However, issues such as limited funding, the need for longer development time, and the extended lifespan of 200mm wafers have pushed full-scale production out a couple of years. As Figure 4-44 shows, several companies expect pilot or low-volume fabrication on 300mm wafers to start in 1998, with high-volume facilities expected to enter production around the year 2000.

4-32 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

100mm 3 years

125mm 3 years

150mm 3 years

200mm 5 years

300mm 8 years (EST)

Source: Rose Associates/ICE, "Status 1997" 21192

Figure 4-43. Wafer Development Time Requirements (Time to Reach 100 MSI Production Rate)

3 Wafers/month Pilot Line Pilot Line- 500-1,000 Low Volume- 2,000 Medium Volume- 10,000 3 1 High Volume- 20,000 Low Volume

2 Medium Volume

4 2 1 High Volume

'98 '99 '00 '01 '02 '03 Year = Number of companies to start up 300mm wafer production facilities each year. Source: Solid State Technology/SEMI/ICE, "Status 1997" 21755

Figure 4-44. 300mm Wafer Production Schedule, as Reported in SEMIÕs Global 300mm Initiative Survey

Memory IC manufacturers are the most interested in the 300mm conversion. The contenders to be among the first to operate a 300mm fab include Samsung, NEC, Hitachi, Motorola, Texas Instruments, and IBM. Intel may also be one of the first. The major European companies are all planning to adopt 300mm technology, but are in no hurry to be among the pioneers.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-33 IC Technology and Packaging Trends

The general consensus concerning the industryÕs migration to 300mm (and larger) wafers is that it will happen, itÕs just a question of when and how. The technology for 300mm wafer production is proving to be more complex and costly than ever envisioned.

Feature Size Trends

Figure 4-45 shows how the feature sizes for a Òtight production resolutionÓ device have decreased from about 3µm in 1980 to about 0.25µm in 1996. This represents about a 15 percent decrease every year. This trend is expected to continue and feature sizes are forecast to be about 0.15µm by 2000 for tight production resolution. It is interesting to note that in 2000, 0.7µm feature sizes will be considered mundane.

10

Loose Production Resolution

Tight Production Resolution

(2.0µ) 256K DRAM (1.6µ) HMOS II 1M DRAM (2.0µ) (1.2µ) µ WE 32100 4M DRAM (1.0 ) 1 32-Bit MPU (0.8µ) µ HMOS IV (1.5 ) 16M DRAM (1.0µ) 4M DRAM (0.5µ) µ (0.8µ) (0.7 ) 1990 Forecasted Commercial 64M DRAM µ Limit For Optical Lithography (0.35 ) 16M DRAM (0.35µ) 256M (0.5µ) Toshiba Development DRAM 64M DRAM (0.25µ) 1G (0.25µ) (0.35µ) Microns 1992 Forecasted Commercial IBM DRAM 256M Limit For Optical Lithography (0.15µ) (0.25µ) (0.15µ) Gate Array DRAM Bell Labs µ (X-Ray) (0.25 ) (0.14µ) 1G DRAM 0.1 (0.15µ) 1996 Forecasted Commercial Limit for Optical Lithography (0.1µ) Toshiba (0.1µ) 4G MIT (0.06µ) DRAM X-Ray (0.08µ)

Toshiba (0.04µ)

= Laboratory Reasearch 0.01 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 00 02 Year Source: ICE, "Status 1997" 10981Q

Figure 4-45. IC Feature Size Trends

Shown in Figure 4-46 is SGS-ThomsonÕs technology roadmap that it plans to follow through the end of the decade. Figure 4-47 provides a look at several announcements regarding state-of-the- art feature sizes. With the year 2000 still being four years away, it appears 0.1µm lithography will be a production reality by then.

4-34 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

High-performance CMOS 0.5µm 0.35µm 0.25µm 0.18µm

BiCMOS digital/analog 0.7µm 0.5µm 0.35µm 0.25µm

CMOSMx multipurpose 0.8µm 0.6µm 0.5µm 0.35µm 0.25µm

BCD/CD 1.2µm 0.6µm 0.35µm

1994 1995 1996 1997 1998 1999 2000/2001

Source: SGS-Thomson Microelectronics/ICE, "Status 1997" 21193A

Figure 4-46. SGS-ThomsonÕs Technology Roadmap

Lucent Technologies Developed a 0.075µm Leff NMOS transistor using a laser plasma Bell Labs source for X-ray lithography. Tungsten deposited on a polysilicon membrane was used to create the masks.

Lucent Technologies Produced 0.08µm features on silicon using e-beam projection Bell Labs lithography and a silicon nitride mask membrane with a tungsten pattern.

IBM Developed a 0.08µm CMOS IC that operates at 1.8V. The transistors were fabricated using 35Å gate oxides and phase-shift deep-UV lithography, though the researchers believe that X-ray lithography will probably be needed for mass production of ICs below 0.13µm feature sizes.

Sandia Developed an "extreme ultraviolet" lithography tool to produce 0.1µm feature sizes. Instead of optical lenses, Sandia used mirrors with special coatings having a surface precision of one atom.

Toshiba Fabricated an MOS transistor with a gate length of 0.09µm and a gate oxide of only 15Å.

Hitachi Developed a CMOS circuit with a 0.09µm feature size using e- beam lithography.

NEC Developed a CMOS circuit with a 0.07µm feature size using e- beam lithography.

Matsushita Developed a CMOS circuit with a 0.05µm gate length. The device had a propagation delay of 13.1 ps.

Tokyo Institute of Performed physical simulations on what it calls a tunneling FET, Technology or TFET. It was shown to behave very much like a MOSFET down to 0.01µm channel lengths. The proposed design uses electron tunneling to control the flow of electrons.

Source: ICE, "Status 1997" 20293C

Figure 4-47. Leading-Edge Feature Size Announcements

Deep-submicron technology has decreased the significance of gate length when it comes to deter- mining MOS circuit density. A more accurate indicator is metal pitch, which is defined as the sum of the metal line width at a via and the space between the via and an adjacent line. It is a measure

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-35 IC Technology and Packaging Trends

of how closely the metal lines are placed together. Thus, as shown in Figure 4-48, metal pitch sets the drain-to-source pitch in an individual transistor and the drain-to-drain pitch of isolated tran- sistors. Figure 4-49 shows the evolution of minimum first-wiring-level-contacted pitch for IBMÕs logic and memory devices.

Gate Gate

Source Drain Drain Source

Source: Computer Design/ VLSI Technology/ICE, "Status 1997" 21244

Figure 4-48. Influence of Metal Pitch on Deep-Submicron Device Layout

9 m)

µ 8 Metal-gated DRAM 7 Si-gated DRAM Logic Products 6

5

4

3

2

1 Minimum first-wiring-level contacted pitch ( 0 1975 1980 1985 1990 1995 2000 Year of Introduction into Manufacturing Source: IBM/ICE, "Status 1997" 21756

Figure 4-49. IBMÕs Metal Pitch Evolution

4-36 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

Figure 4-45 also shows the forecasted performance limits of the most popular types of lithography equipment. Due to its ÒrelativeÓ low costs and technical advancements (e.g., phase-shift pho- tomasks), optical lithography is now forecast to have a much longer life than originally thought (maybe to 0.1µm). It now appears that optical techniques will be the mainstream of IC lithogra- phy for the rest of this century (Figure 4-50). A significant amount of research is being performed on extreme ultraviolet (EUV) lithography, which is expected to allow for the fabrication of ICs with feature sizes of 0.1µm (and below?). Meanwhile, X-ray exposure techniques continue to be aggressively developed for future lithography needs in the event that optical technology finally reaches its limits.

ARI - annular-ring illumination 16Mb OAI - off-axis illumination I-line PSM - phase-shift masking s - shrink DRAM version 16Mb-s I-line + ARI

I-line + OAI 64Mb Deep-UV Deep-UV + OAI or PSM

DRAM I-line + OAI or PSM 64Mb-s Deep-UV + ARI or OAI

I-line + PSM 256Mb Deep-UV + OAI or PSM

256Mb-s Deep-UV + PSM

0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Minimum Lithography Resolution (µm) Source: Canon/ICE, "Status 1997" 18625

Figure 4-50. Advanced Optical Lithography Scenarios

Wiring Levels

The number of metal wiring levels has tripled in the last decade for both logic and memory prod- ucts. Figure 4-51 shows historical wiring level trends for IBMÕs logic IC products. Five layers is expected to be common among 0.25µm process technologies, with some companies using six. Chemical mechanical polishing (CMP), which smoothes the surface of the chip after each layer is deposited, has been adopted by most manufacturers of high-performance ICs. With CMP, the sur- face of the IC remains planar, and thus, metal layers can be stacked to virtually any height. However, beyond five or six, additional metal layers may not reduce the die size by enough to offset the higher processing cost. In some cases, the extra metal layers improve performance but not cost effectively.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-37 IC Technology and Packaging Trends

7

6

5

4

3

2 Number of Wiring Levels 1

0 '75 '77 '79 '81 '83 '85 '87 '89 '91 '93 '95 Year Source: IBM/ICE, "Status 1997 21757

Figure 4-51. Historical Logic IC Wiring Level Trends

Summary

Gordon Moore, industry veteran and Intel chairman, believes the ultimate question now is not the physical limitations of future ICs but whether the industry can afford to make them.

In general, there are basically two schools of thought concerning turn-of-the-century advanced ICs. The first is that the post-2000 devices will happen as planned and will be economical as well. The reasoning behind this view lies in historical precedent. In other words, since the 1990Õs-type ICs appeared ÒimpossibleÓ in the early 1980Õs, and yet were created with the assistance of signif- icant technological advances, the ÒimpossibleÓ appearing post-2000 devices will follow this same path to fruition.

The second school of thought is that it is not realistic to keep extrapolating historical trends to infinity. At some point, physical or economic limits present themselves.

ICEÕs view is more in line with the second school of thought ideology. While ICE does not expect the technological advances in the IC industry to stop, the pace of the advances (e.g., density, fea- ture size, etc.) should slow. Associated with, and sometimes causing this slowdown, will be the questionable economic feasibility of many of the new technologies.

4-38 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

IC PACKAGING TRENDS

Market Overview

IC packaging is receiving a great deal more attention now than in the past. This is partly due to the increasing percentage of the total system performance picture that IC packaging represents. As system producers soon discover, an IC package can be as much or more a performance limit- ing factor as the IC die itself.

Another reason for the heightening interest in packaging is the rising cost of housing the IC die. ICE forecasts that IC packaging costs will continue to rise significantly throughout the 1990Õs since more and more of the newer IC devices now require high-lead-count (i.e., expensive) packages.

Figures 4-52 and 4-53 show the sizes of the markets for the major package types. The SOP-type package had the greatest share of the 1996 IC market as surface mount (SM) technology continued to make inroads. In fact, 1994 was the first year ever that surface mount ICs outshipped through- hole IC units. It is expected that by 2001, SM devices will have about eight times the unit mar- ketshare of through-hole devices. BGA/CSP, SOP, plastic PGA, and ÒotherÓ packages are anticipated to show the strongest growth through 2001. The dominant package typesÑplastic DIPs, SOPs, and PQFPsÑare forecast to make up about 83 percent of the IC unit market in 2001.

1995 1996 (EST) 1996/1995 2001 (FCST) 1995-2001 Package Percent CAGR Type Units Percent Units Percent Units Percent (M) Of Total (M) Of Total Change (M) Of Total (%) Plastic DIP 15,450 32 13,400 27 Ð13 5,800 8 Ð15 CERDIP 550 1 445 1 Ð19 140 <1 Ð20 Sidebraze DIP 45 <1 40 <1 Ð11 15 <1 Ð17 Ceramic PGA 105 <1 115 <1 10 125 <1 3 Plastic PGA 85 <1 100 <1 18 215 <1 17 BGA/CSP 60 <1 90 <1 50 1,745 3 75 SOP* 21,645 44 23,120 47 7 39,800 58 11 PLCC 2,260 5 2,270 5 — 2,360 3 1 PQFP 6,100 12 6,390 13 5 11,800 17 12 Other** 2,600 5 2,830 6 9 6,500 9 16 Total 48,900 100 48,800 100 — 68,500 100 6 *Includes UTSOPs, QSOPs, TSOPs, and SOJs. **Includes TAB-on-board, COB, flatpacks, metal cans, LLCC, LDCC, etc. Source: ICE, "Status 1997" 14737P

Figure 4-52. Worldwide Merchant IC Package Marketshare (Units)

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-39 IC Technology and Packaging Trends

Plastic DIP Through Hole 8% Other 9% 1%

Plastic Through DIP Surface Hole Mount 27% 1996 (EST) SOP Other 2001 (FCST) SOP 29% 71% 48.8B 47% 33% 68.5B 58% Other 24%

Surface Mount 91%

Other 2% Source: ICE, "Status 1997" 16827L

Figure 4-53. IC Package Marketshare (Units)

ROW 2% As shown in Figure 4-54 most of the North Europe America 8% 5% packaging operations for IC devices are still located in the Asia-Pacific region. The attractiveness of this

48.8B Asia Pacific region of the world for IC assembly Japan 27% Units 58% is due to low labor costs as well as the existing experienced and sophis- ticated packaging infrastructure. ICE forecasts that this situation will Source: Emissarius, Ltd./ICE, "Status 1997" 20312C be little changed in the year 2001. Figure 4-54. Estimated 1996 Final IC Packaging by Location As surface mount packages become more available and SM assembly capabilities continue to improve, SM technology is becoming widely accepted for nearly all IC product types. The primary advantage of SM packaging is the improved performance and savings in space that it affords. Not only are the packages smaller but they can also be placed on both sides of the printed circuit board (PCB). This savings in space can reduce board cost by as much as 60 percent, while offering improved performance. For these rea- sons the SM market is expected to continue growing rapidly in the coming years.

Figure 4-55 shows the 1996 and 2001 IC markets segmented by product type and the respective surface mount unit volumes. As shown, in 1996 the MOS memory segment had a very high pen- etration rate for surface mount (94%). However, the largest unit volume segmentsÑanalog and MOS logicÑwere 64 and 68 percent surface mount in 1996, respectively.

4-40 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

Percent Surface Market ($B) ASP ($) Unit Volume (B) Surface Mount Mount Units (B) Product 1996 2001 1996 2001 1996 2001 1996 2001 1996 2001 (EST) (FCST) (EST) (FCST) (EST) (FCST) (EST) (FCST) (EST) (FCST)

Digital Bipolar 2.0 0.7 0.53 0.35 3.8 2.0 58 75 2.2 1.5

Analog 17.5 36.3 0.84 1.11 21.6 32.8 64 86 13.8 28.2

Microcomponent 38.9 93.4 7.40 11.39 5.3 8.2 85 97 4.5 8.0

MOS Logic 22.2 53.5 1.77 3.07 11.7 17.4 68 94 8.0 16.4

Memory 36.3 99.6 5.67 12.30 6.4 8.1 94 99 6.0 8.0

Total 116.9 283.5 2.40 4.14 48.8 68.5 71 91 34.5 62.0

CAGR 1996-2001 19% 11% 7% — 12%

Source: ICE, "Status 1997" 20313C

Figure 4-55. 2001 Surface Mount IC Unit Forecast

As shown in Figure 4-56, the analog segment will contribute over half of the annual increase in total IC and surface mount unit volume shipments through the year 2001. Since most analog com- ponents are low-density devices, the surface mount trend in this segment is primarily directed at SOP package types. Overall, analog and memory products will represent the majority of SOP usage in the year 2001.

Contribution 1996/2001 Contribution 1996/2001 To Total Surface Mount To Total Product Unit Volume Increase Unit Volume Increase Change (B) (Percent) Change (B) (Percent)

Analog 11.2 57 14.4 52

MOS Logic 5.7 29 8.4 30

Microcomponent 2.9 15 3.5 13

Memory 1.7 9 2.0 7

Bipolar Digital Ð1.8 Ð9 Ð0.7 Ð3

1996/2001 19.7 — 27.6 — Net Increase

Source: ICE, "Status 1997" 20314C

Figure 4-56. Analog and MOS Logic Products Drive Surface Mount Volume

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-41 IC Technology and Packaging Trends

As I/O counts have increased, the industry has gravitated toward fine-pitch lead technology (FPT). The Institute for Interconnection and Packaging Electronic Circuits (IPC) defines FPT as those devices that have lead pitches ranging from 0.1mm to 0.5mm (4mils to 20mils). Below 0.1mm, the term ÒultrafineÓ pitch has been unofficially put forth.

With fine-pitch technology (FPT), the leadsÕ susceptibility to damage is high. Fine-pitch leads cannot be touched before being placed on a board or substrate. In most cases the packaged device must be placed and held in position until soldering of the leads is completed.

Lead coplanarity and integrity are critical. This is why carriers are frequently used to hold the outer leads of the packages until immediately before attachment. The carriers also provide easily accessible test contacts so that chips can be fully tested before board assembly. The delicate nature of fine- or ultrafine-pitched packages has many designers considering the ball grid array (BGA) option for their packages. BGAs are discussed later in this section.

Memory devices packaged in thin small-outline packages (TSOPs) are gaining in popularity. They are finding applications in palmtop and notebook computers and memory cards. Manufacturers of non-portable computers are also looking at the TSOP; it will most likely become the primary memory package for the 16M DRAM. Toshiba estimated that almost 50 percent of its 16M DRAMs were be packaged in TSOPs in 1996.

Fujitsu developed what it calls UTSOP (ultra-thin SOP) package types for memory. The UTSOP-I version has a body thickness of 0.65mm and a PCB mounted height of 0.7mm. UTSOP-II versions have a 0.45mm body thickness and a 0.5mm PCB mounted height.

For logic IC applications in portable systems, Texas Instruments unveiled a new chip package that uses about 40 to 60 percent less board space than a shrink small outline package (SSOP). The thin very small outline package (TVSOP) features a lead pitch of 0.4mm and a height that meets the 1.2mm PCMCIA standard.

The total IC packaging market by material type is shown in Figure 4-57. Because of the move to plastic-packaged flash memory and away from ceramic-packaged EPROMs, as well as the mili- tary implementing plastic IC packages in many of the less-harsh system environments, ceramic IC packages are expected to decrease one point in marketshare between 1996 and 2001. The decline can also be attributed to IntelÕs early-1996 decision to change the packaging on most of its Pentium microprocessors from ceramic to plastic. Plastic package marketshare will maintain more than 90 percent of the market and metal/other packages (which would include bare dice for MCMs) will grow a few points.

4-42 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

Plastic Plastic ≈ ≈93% 91%

1996 (EST) 2001 (FCST) 48.8B 68.5B Ceramic ≈1%

Other* Ceramic Other* ≈ ≈ ≈5% 2% 8% *Includes TAB-on-board, COB, flatpacks, metal cans, bare dice for MCMs, etc. Source: ICE, "Status 1997" 12061S

Figure 4-57. Worldwide Merchant IC Package Marketshare by Material (Units)

Overall, the IC package market as Time CAGR expressed in units is projected to Period (%) display a CAGR of only 7 percent 1981 Ð 1986 18 from 1996 to 2001 (Figure 4-58). The 1986 Ð 1991 11 annual IC unit growth rates have 1991 Ð 1996 7 been steadily shrinking since the mid-1980Õs. 1996 Ð 2001 7 Source: ICE, "Status 1997" 17797H

The IC product mix change (i.e., Figure 4-58. IC Unit Volume CAGRs away from SSI/MSI digital bipolar ICs) has helped cause this unit ship- ment rate decline. Moreover, the density/complexity of advanced 32-bit/64-bit MPUs and ASICs has risen dramatically, and many applications can now use one IC where previously hundreds of IC units were required. This trend is expected to continue into the late 1990Õs and will have a sig- nificant impact on the IC packaging material suppliers.

As was previously mentioned, the increasing density and complexity of ICs is helping to slow unit volume growth rates. However, these high-density devices are also pushing the state-of-the-art in pin count. Figure 4-59 breaks out IC package units shipments by device pin count. High-pin count packages currently represent a very small percentage of the units shipped, but their num- bers are increasing rapidly. Packages with pin counts as high as 1,500 may be in production by the end of the decade (Figure 4-60).

Ball Grid Arrays (BGAs)

One of the most talked about surface mount packages is the ball grid array (BGA), shown in Figure 4-61. A BGA package, rather than using pins for leads, mounts to a board using solder balls located on the underside of the package. The was first introduced by IBM as a ceramic package

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-43 IC Technology and Packaging Trends

for its own internal use. It wasnÕt until Motorola introduced a plastic version of the BGA (labeled OMPAC) that the technology began to take hold commercially. Motorola worked with Compaq Computer on the first implementation of the package into new products.

>208 pins >208 pins 69-208 pins <1% 1% 69-208 pins 7% 10%

1996 (EST) 2001 (FCST) ≤68 pins ≤68 pins 48.8B 68.5B 93% 89%

Source: ICE, "Status 1997" 21777

Figure 4-59. IC Package Unit Shipments by Pin Count

1,800

1,600

1,400

1,200

1,000 er Component 800

600

400

200 Number of I/Os P 0 1994 1995 1996 1997 1998 1999 2000 2001 Year Source: Mentor Graphics/EE Times/ICE, "Status 1997" 21196

Figure 4-60. Pin Count Forecast

Proponents of this package say it provides benefits such as small size, good yields, excellent elec- trical performance, and low profilesÑfeatures that have been demanded by systems designers. By spreading the contacts over the bottom of the packaged device, the size of the package is reduced compared to quad flat packs. No longer are there many small leads jutting out from all edges of the package. The rising number of I/Os per package and lead pitch limitations are the driving forces behind the increasing popularity of BGAs (Figure 4-62).

4-44 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

Molding Compound

Gold Wirebond Epoxy Die Attach IC Die

Gold-plated Die Attach BT Resin Glass Epoxy

Solder Plated-Through Ball Hole Copper Foil Pads Solder Mask Substrate: BT resin glass epoxy & Interconnect Die Attach: Silver-filled epoxy Wire: Gold Cover: Custom molding compound Source: Motorola/ICE, "Status 1997" 18510

Figure 4-61. OMPAC Ball Grid Array From Motorola

1.8

1.6 Ball-Grid Array (BGA)

1.4

1.2 Quad Flat Pack (QFP) Technological jump from QFP to BGA 1.0 Technological limit for QFP Limit of what can Pitch (mm) 0.8 fine pitch be done "simply"

0.6 Limit range of what can be 0.4 reasonably accomplished in light of cost considerations 0.2

0 100 200 300 400 500 600 700 800 900 I/Os Source: IBL-Löttechnik/ICE, "Status 1997" 20315

Figure 4-62. Fine Pitch, High I/Os Push Packaging to Ball-Grid Arrays

One of the biggest concerns of using a BGA are the solder balls, which also happens to be one of the big advantages of the package. While the configuration makes the dimensions smaller, many of the solder joints are hidden beneath the package, making visual inspection impossible (x-ray inspection is required). Another concern is the high costs associated with BGAs. Even with

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-45 IC Technology and Packaging Trends

increased volumes, BGAs will more than likely command a greater price than QFPs since BGAs have a circuit board that holds the chip and fans out the leads. And, though the printed circuit board area may be small, circuit boards that can handle BGAs may well require more layers. From an area standpoint, BGAs take less space, but routing traces to them tend to use more PCB layers. This can serve to increase the cost of the subsystem. Moreover, repairability is also difficult with current BGA packages.

As further experience is gained, BGA packaging is expected to be widely used, especially in high- performance applications and devices, including pagers, cellular phones, microprocessors, ASICs, and SRAM cache memory. A list of some BGA announcements made in 1996 is given in Figure 4-63.

¥ Intel licensed Tessera's microBGA CSP technology in 4Q96 and will use it for flash memories. As an example for choosing the µBGA package, Intel claims that a 0.4µm, 8M flash memory using a 5x8 ball matrix µBGA package is 80 percent smaller and 17 percent thinner than its 40-lead TSOP counterpart.

¥ Chip assembly veteran Robert C. Marrs, founded Abpac Inc. in Phoenix, Arizona, to provide U.S.-based IC assembly using advanced BGA package technology. Abpac's new facility will process a variety of BGA package types, with I/O counts ranging from less than 100 to over 1,500. Full volume assembly operations are expected to begin in 1Q98.

¥ ProLinx Labs Corporation in San Jose is looking to reduce BGA packaging costs to one cent per lead by creating vias with photo imaging instead of drilling. The vias route signals through the substrate to the solder balls rather than around the edge of the board.

¥ Altera began offering versions of its Flex 10K PLDs in Amkor's Super BGA (SBGA) package. The first SBGA packaged unit, the 50,000-gate EPF10K50, entered volume production in November 1996.

¥ Amkor licensed Tessera's Micro Ball Grid Array package technology in 2Q96. The two companies have worked closely for several years.

¥ Packaging material supplier Olin Interconnect Technologies formed a partnership with MicroModule Systems to develop and manufacture metal ball grid array (MBGA) packages.

¥ Sematech and the PCB research consortium Interconnection Technology Research Institute (ITRI) agreed to bolster a joint effort to study and develop the U.S.'s infrastructure for plastic BGA package substrates.

Source: ICE, "Status 1997" 20316C

Figure 4-63. Sampling of 1996 BGA Announcements

4-46 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

Chip-Scale Packages (CSPs)

Chip-scale packaging is also one of the hottest topics in the packaging industry. An example of a chip-scale package (CSP) is shown in Figure 4-64. The CSP is only slightly larger than the die itself (less than 20 percent larger). Peripheral-leaded CSPs are suited for low lead-count packages (50- 100 pins), while area arrays are particularly well suited for high lead-count packages (eventually exceeding 1,000 pins).

Protective Coating Semiconductor Chip

Compliant Layer

Interconnect

Flex Circuit Bump Array Ð Gold Plated

Printed Circuit Board

The bump array, which is mounted on a compliant layer to reduce the mechanical stress of the solder joint and accommodate surface irregularities on the printed circuit board, uses gold plated bumps for reliability. Source: Tessera/ICE, "Status 1997" 19505A

Figure 4-64. Diagram of a Tessera µBGA Package

CSP has been labeled by some to be the solution that offers the size and performance benefits of packageless technologies (e.g., flip chip, chip-on-board, and bare die), but at a lower cost and without requiring custom packaging. CSPs combine the best features of bare die assembly with the numerous advantages of fully packaged ICs (Figure 4-65). Furthermore, CSPs are showing some promise to carry IC packaging costs below the much sought after benchmark price of one cent per I/O.

As shown in Figure 4-66, there are a number of different CSP technologies being offered. However, only a few are known to have been tagged for volume production, including TesseraÕs microBGA (µBGA) CSP, the MSMT package offered by ChipScale (which will be produced by Motorola), the CSBGA package from Amkor, TIÕs MicroStar BGA CSP, and an array CSP from Sharp.

In 1996, most CSP packaged chips went into automotive, watch, and PCMCIA applications. By 2001, the technology should be well distributed among several applications, as shown in Figure 4-67.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-47 IC Technology and Packaging Trends

Bare Chip Chip Scale Packaging Traditional IC Packaging Technologies* Technology Technology

Die Size Die Size Standard Foot Prints Standard Foot Prints Short Electrical Path Short Electrical Path Low Cost Low Cost High I/O Capability High I/O Capability Assembly Infrastructure Assembly Infrastructure Thermal Management Thermal Management** Alpha Particle Protection Alpha Particle Protection Ease of Test Ease of Test Protection for Die Protection for Die Immunity to Die Shrink** Immunity to Die Shrink Reworkable Reworkable

* Flip-chip is generally considered to be superior to chip-and-wire technology in all listed categories and is therefore the primary reference for the chart above. ** Attributes will vary from CSP type to CSP type. Source: Semiconductor International/ICE, "Status 1997" 21775

Figure 4-65. CSP Offers Best of Both

Multichip Modules (MCMs)

Multichip Module (MCM) technology has not been widely accepted yet, but likely will be a strong factor in all electronics applications in the future (Figure 4-68). An MCM has multiple ICs (or bare die) packaged on an insulating substrate that interconnects the ICs or die and provides external connections. This definition of an MCM is similar to the classical definition of a hybrid microcir- cuit. MCMs could be considered as a portion of hybrid microelectronics. The term MCM will rapidly replace the term hybrid to define any assembly of multiple ICs.

It is expected that MCMs will be used in all electronics markets because they can provide improved system performance and smaller size and weight and reduce overall costs. The con- version to MCMs will proceed slowly and steadily like the conversion from through-hole mount to surface mount initially proceeded, not overnight as some forecasters have predicted. The MCM market will build on the currently established hybrid microcircuits market.

MCMs are currently viewed as complex hybrid microcircuits with virtually all of the components mounted to the substrate being semiconductors, not passive components. Figure 4-69(a) shows an example of a relatively low-density hybrid circuit and Figure 4-69(b) shows three MCMs as currently defined.

4-48 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

Individual Chip Wafer Level Primary Package Lead Package Supplier Processing Processing Construction Arrangement Capable? Capable?

Amkor Flexible interposer with Area array Yes No compliant encapsulant

ChipScale Silicon sandwich with Peripheral No Yes chevron beam leads leads

Fujitsu Lead on chip wire bonded Peripheral Yes No and molded leads

Matsushita Flip-chip with underfill on Area array Yes No ceramic carrier

Mitsubishi Redistribution wiring on Area array Yes No chip with transfer bumps

Motorola Flip-chip with underfill on Area array Yes No organic carrier

NEC Flex circuit interposer Area array Yes No with bumped leads

Nitto Denko Flex circuit interposer Area array Yes No with bumped leads

Sandia Rigid polyimide film with Area array No Yes redistribution wiring

Sharp Wire bonding onto flex Area array Yes No carrier

ShellCase Silicon and glass with Peripheral No Yes edge wrapped leads leads

Tessera Flexible interposer with Area array Yes Yes complaint encapsulant

TI Wire bonding onto flex Area array No No carrier Source: Semiconductor International/ICE, "Status 1997" 21776

Figure 4-66. Examples of CSP Technologies

A major segment of MCMs are liquid crystal displays (LCDs). These displays are built on glass substrates and contain millions of interconnects and transistors deposited on the glass. The driver ICs are now being mounted to these substrates using a specialized assembly technique referred to as chip-on-glass (COG). LCDs are some of the most sophisticated MCMs currently in production. Additionally, LCD manufacturing technology shows great promise for reducing the cost of man- ufacturing other MCM substrates.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-49 IC Technology and Packaging Trends

Military LCD 2% 6%

Telecom Automotive 12% 26% Computer 16% IC Card Watch 20% 18%

Source: ICE, "Status 1997" 21197

Figure 4-67. CSP Production in 2001 by End-Use Application

Application Company Product Description Mainframe IBM ES/9000 MLC MCM-C Unisys A16/A19 Multicavity ceramic PGA Siemens 7500 MCM-L with flip-TAB Mid-range Computer IBM AS/400 MLC with flip-chip NCR 3500 Laminate with TAB Workstation Control Data 4680 nCHIP's thin-film process Tadpole Tech. SPARCbook nCHIP's thin-film process Silicon Graph. Iris 4-chip ceramic PGA IBM RS/6000 MLC with flip chip Personal Computer Austek Micro. 486 upgrade MMS's thin-film on aluminum IBM 9095 Four-chip ceramic MCM Telecom AT&T Many PolyHIC thin-film process PMC SONET Thin-film on silicon NEC SONET 2-sided glass ceramic Communication Matsushita Pager Laminated MCM Automotive Mercedes Mercedes 4-chip 2-sided LTCC from MPA Military Rockwell DSP Thin-film on silicon Hughes Processor Thin-film on alumina (HDMI) Honeywell Processor Cofired ceramic MCM Consumer Matsushita VCR MCM-D for CCD driver ICs Medical Medtronic Defibrillator MLC

Source: TechSearch International, Inc./IBM/ICE, "Status 1997" 19484A

Figure 4-68. Examples of MCM Applications

MCM Substrates

MCM substrates are grouped into three major categories Ñ MCM-C, MCM-D, and MCM-L. These designations refer to the substrate and the method of substrate manufacturing. Figures 4- 70 and 4-71 compare these three major substrate types. As shown in Figure 4-72, there can be a dramatic difference in the cost of the various MCM substrate technologies.

4-50 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

(a)

(b)

Photos courtesy of Natel Engineering Co., Inc and CTS Source: ICE, “Status 1997” 19477

Figure 4-69. Examples of Hybrid Circuit (a) and MCMs (b)

MCM-D (deposited) ¥ High resolution (MCM-D/L) ¥ High density capability (MCM-D/C) ¥ Fine via capability ¥ High performance materials

MCM-L (laminated) MCM-C (co-fired) ¥ Large substrate format ¥ Hermetic packaging ¥ Low substrate cost ¥ Area array I/O compatibility ¥ Parallel processing ¥ Parallel processing ¥ Area array I/O capability

(MCM-L/C)

Source: Advanced Packaging/IPC Technology Roadmap/ICE, "Status 1997" 21768

Figure 4-70. MCM Substrate Materials and Processing Procedures

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-51 IC Technology and Packaging Trends

Characteristics MCM-C MCM-D MCM-L

Density Pitch per layer 10 mils (254 µm) 1 mil (25 µm) 8 mils (200 µm) No. of Layers >60 5 5-25 Materials Alumina Silicon FR-4 Aluminum Nitride Alumina Polyimide Beryllium Oxide Glass Power Dissipation High Medium Low Cost Medium High Low Speed Performance Medium High Low

Source: ICE, "Status 1997" 19129

Figure 4-71. MCM Substrate Comparison

MCM Type Materials Cost Ratio

MCM-L Various organic laminates 1.0 MCM-L/D Laminates with deposited polyimide/metal 1.3Ð1.5 MCM-C Low-temperature co-fired ceramic (LTCC) 1.5Ð2.0 MCM-C/D LTCC and polyimide/metal deposition 2.0Ð3.0 MCM-D Silicon and glass substrates 4.0Ð6.0

Source: Consultar/ICE, "Status 1997" 19486

Figure 4-72. Projected MCM Substrate Cost Ratios

MCM-C substrates are cofired (C) ceramic-based multilayer substrates. The metallization layers are deposited and defined by screen printing. This technology was used by IBM to produce the thermal conduction module (TCM), which was the first MCM produced in large volume.

MCM-D substrates use deposited (D) metal and insulating layers to form circuits. These layers can be deposited on a variety of substrates, including silicon. The technology utilized was initially based on semiconductor wafer fabrication techniques but has now evolved to also use technology from LCDs and tape automated bonding (TAB) processes. In all cases the metallization process is subtractive. A layer of metal is deposited, defined by photoresist and then etched to define the required pattern. MCM-D technology yields the highest individual-layer wiring density. MCM- D technology also results in the best high-speed performance. Both of these advantages result in the highest cost.

MCM-L substrates are laminated (L) using techniques from printed wiring board (PWB) and TAB manufacturing. This technology offers low cost but cannot provide extremely high-performance circuits because of the physical properties of the materials used for insulating layers.

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The MCM industry is already combining substrate technologies to optimize the technical solu- tions. In particular, combinations of an MCM-C substrate containing ground and power connec- tions with an MCM-D substrate providing the signal layers have proven viable. ICE expects this trend to continue with the best features of each substrate style used as the application requires (Figure 4-73). Eventually the three current categories of substrates may require modifications as various combinations prove to be more useful.

Application Substrate Type

Notebook/Portable PDA MCM-L, MCM-L/D — initially COB then flip chip

Cellular Phones/Pagers MCM-L, MCM-L/D — rapidly going to flip-chip assembly

Camcorders/Games MCM-L, COB — evaluating flip chip

Military MCM-C, MCM-C/D — still need hermetic packaging, chip-and-wire assembly

Medical MCM-C for implantable products, MCM-L for instruments

Telecommunications MCM-D and MCM-L/D for performance — flip chip will be dominant

High-Performance Computing MCM-D and MCM-L/D — silicon Platforms substrates heavily used

Automotive MCM-L — flip chip, well established for MCM-C, will be used with MCM-L, some MCM-C under hood

Smart Cards MCM-L, strong user of TAB, will migrate to flip chip

Displays MCM-D with glass substrate, TAB and direct chip-on-glass with TAB for flip chip

Source: Consultar/ICE, "Status 1997" 19476

Figure 4-73. MCM Applications by Substrate Type

Known Good Die Issues

The availability of known-good die continues to improve, but is still a big concern in the bare-die- based MCM marketplace. Texas Instruments and MicroModule Systems (MMS) have teamed to offer their solution to the known-good-die issue. The companies have developed a temporary package (DieMate) that allows manufacturers to test bare dice with area pads used in flip-chip technology. MMS will supply the thin-film packages that are custom made for a given chip type. The carrier (Figure 4-74) will have contacts and an interconnect pattern laid on it so that the chip for which it is made can be placed on it upside down, with its bonding pads matching up to con- tacts in the carrier. The chip is held to the carrier with pressure during burn-in and testing, and is then released and removed, with an operator knowing whether the die is good or bad.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-53 IC Technology and Packaging Trends

Force Delivery Mechanism

Die Lid

Die Edge Registration Feature

Carrier

Interconnect Compliant Material

Socket

Source: Semiconductor International/MMS/ICE, "Status 1997" 19228

Figure 4-74. Temporary Carrier for Die-Level Burn-In

Other companies, including Chip Supply, IBM, Intel, Lucent Technologies, Micron, and Motorola, have developed methods of testing known good die as well. Intel claims that revenues from known-good die (called SmartDie) has been increasing an average annual rate of 150 percent in recent years.

The MCM Market

As shown in Figure 4-75, laminate-based MCMs accounted for the majority of MCMs sold in 1995. By the year 2001, MCM-Ls will still make up 55 percent of the multichip module market, but there will be a significant movement to MCM-Ds as pricing becomes more competitive for these parts.

Solutions to better managing known good bare-die issues cannot come soon enough. Several IC manufacturers are expanding further into MCMs and welcome any help they can get to make their job easier.

Figure 4-76 shows ICEÕs forecast for the MCM marketplace. The figures in Figure 4-76 do not include the cost of the dice in the MCM. New standards, CAD tools, consortiums, and an increas- ing supply of tested known-good bare dice should help spur a 29 percent CAGR for the MCM market through the end of the decade. Figure 4-77 shows an MCM forecast from Toshiba that includes the value of the IC dice in the MCM. The $30 billion MCM forecast figure in the year 2000 would represent about 13 percent of the expected $228 billion total IC market at that time.

4-54 INTEGRATED CIRCUIT ENGINEERING CORPORATION IC Technology and Packaging Trends

MCM-C 5%

MCM-C 10% MCM-D 27% 1996 (EST) MCM-D MCM-L 2001 (FCST) $575M 40% $2,500M 63% MCM-L 55%

*Not including components. Source: ICE, "Status 1997" 18526G

Figure 4-75. MCM Market Projections* ($)

2,500

2,000

1,500

1,000

Millions of Dollars

500

0 1991 1992 1993 1994 1995 1996* 1997 1998 1999 2000 2001 Year *About 75% of market was captive Source: ICE, "Status 1997" 18636D

Figure 4-76. MCM Market Forecast

INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-55 IC Technology and Packaging Trends

35

OtherTotal MCM 30

Industrial

Telecommunications 25

Consumer

20 Computer

15

Worldwide MCM Sales

10

5

0 1992 1993 1994 1995 1996 1997 1998 1999 2000 Year Source: Toshiba/EMR/ICE, "Status 1997" 19231

Figure 4-77. Worldwide MCM Forecast (Fully Populated Value)

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