Llllllllllllllllllllllllllllllllllllllllllllllllllllllllllll

lllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllllll USUU5596767A Unlted States Patent n9; [tti Patent Number: 5,596,767 Guttag et a]. |tt5t Date of Patent: Jan. 21, 1997

[54] PROGRAIVIIVIABLE DATA PROCESSING 4.862.150 8/1989 Katsugtl cl al ...... 340/703 SYSTEM AND APPARATUS FOR 4.8731152 10/1989 Pilat et a1...... ‘BM/Slit EXECUTING BOTH GENERAL PURPOSE 5.431.969 7/1‘995 Hcily‘eil et al. . 395/166 INSTRUCTIONS AND SPECIAL PURPOSE 5.437.111] 7/1995 Guttag et a1...... 395/162 GRAPHIC INSTRUCTIONS

7b~ In "nti ..._ Karl M.. (1t tt' 1., K" - C.‘ Primaryr Examiner rAlpesh M. Shah I I W m Mculmuuglilr girgigxgaggi a“ OE- Attorney, Agent, or Firm Lawrence 1. Bassuk; Leo N. Houston Tm‘ ‘ llciting; Richard L. Donaldson

[7-]} 3534'‘:\ssignec "\H‘ [IFZZI‘UHIUHSi - - Incorporated.- r- I57] ABS]Y‘ RAUIr“ The present invention is a programmable data processing {2}] App}, No.; 483.810 system and apparatus which operates as an independent W ‘_ microprocessor. The programmable data processing system [MI Filed: Jun. 7, 1995 ol‘ the present invention stores both general purpose and I g . _ K ‘ special purpose graphic instructions. The programmable Rel‘ittd U'b' Apphmlmn Ddt" data processing apparatus of the present invention has both [63] Continuation ol' SGT. No. 965.561. Oct. 23. 1992. Pat. No. l-l'.pcs.ofinslrumolls within “5 minim?" “1' This pnwlsion. 5.522.082. which is a continuation of Ser. No. 426.~'l8t1.()ct. of a Smglc proccssmg apparatus ‘or prcimmmg holh types 01 21 1939‘ ahanduncdq which K a Continuation or Sup N0‘ instructions enables a highly tlcxiblc solution to hit map 346.388. Apr. 27. 5989. abandoned. which is a continuation graphics problems. This is because the program oi‘ the data ol‘Ser. Nov 2117.034. Jun. 13» 1988. abandoned. which is a _ . . . . t. . , 1 . ,‘ t . t continuation of Ser. No. 821.641. Jan. 23. 1986. abandoned. pmidcmlmc dppdtr‘dluh Ind-y hL aliens‘; m ‘Pun-ML ihL mnbl desirable graphics algorithm without loss 01 the general [51] Int. Cl.“ ...... G06F 9/30; G06F 15/76 purpose calculation and program How capability ol‘ageneral [52} US_ CL ______h 395/300; 395/376; 395/501; purpose data processor. The data processor of the present 354/2235; 364/2313; 364/2634; 364/DIG, i invention may serve as a parallel processor for a host data [5s] Field or Search ...... 395/soa7oo. processing Byslcm For Primarily Control 01‘ bit manned 395/650‘ 500, 375_ mu 1157 M0‘ [44‘ graphics. In addition this same type data processing appa 162; 382/9‘ 10‘ 41; 345/24, 55‘ ill 356 rates may serve an independent microprocessor within a single user computer or graphics terminal. [56} References Cited U.S. PATENT DOCUMENTS

4.799.146 1/1989 Chauvel ...... 364/200 13 Claims, 14 Drawing Sheets

250 720 t» 205 ‘y ‘ tNSTRUCllON "M 7/1 WE 122 220 .1 204 tyl 2.50 REGlSTER MEMORY ‘ FILES <2’ INTERFACE ff5~tL N} \\ i HOSTi w“.2023, (200 ' .INTERFACE\_ 2m H0 H5 720 1150732 M0 150 760 F70 ‘1 V , Whit" , ...~ , ...... r.'__. t" .11. .. .i‘ f. bani. Z40 205*‘ l e t HOST eRiPstes 7.22 i ‘ iSHIFT VtDtO WW vtnro sPrditt PROCESSING 4“ .Q ~ 1' ' i TO \ t HARDWARE 1 A t it t 755 i 55 124 v’ . iNPUT/OUTPUT REGISTERS \ 260 —— ~ <—W VIDEO DlSPLAtt .\ CONTROLtER r270

US. Patent Jan. 21, 1997 Sheet 2 0f 14 5,596,767

500 x Y ADDRESSING MODE H I

AX(W|DTH) 377 575 579 T M Y 574 575 J7751350HEI6HT I +540 571 572 575 I ZDSbTéRERSTS 350 PIXE? DATA

oglég <~*~— SCREEN PITCH 520 -~?_.

aX Fig. 5

LINEAR ADDRESSING MODE I<—~-- LINEAR PITCH 450444 470 447 442 445 % 444f445 446 START '“?AMZOMN P——AX420_____.I ADDRESS (SEGMENT LENGTH) Fig. 4

US. Patent Jan. 21, 1997 Sheet 4 0f 14 5,596,767

2201~SOURCE" SOURCE ADDRESS PITCH ‘I605 DESTINATION ADDRESS I 604 DESTINATION PITCH ‘I605 OFFSET I606 *IAIINDOW START _f607 wINDOw END I608 DEETA Y/DELTAX I609 i‘iwyjgyyCOLOR 0 I670 STACK POINTER if 752 Mg. 6 p05 H SCREEN MEMORY-x YADDRESSINC

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AFR'RAET 750% f750%w750 77041 SOURCE ADDRESS

_ OFF SCREEN MEMORY, UNEAR ADDRESSING SOURCE PITCH 7Z0 %-~—~——+I Fig. 7 US. Patent Jan. 21, 1997 Sheet 5 0f 14 5,596,767

800 807 1 (BEGIN) READ V502 SOURCE ADDRESS

‘ FETCH SOURCE V805 DATA

I READ V504 DESTINATION ADDRESS I FETCH DESTINATION V805 DATA

_ SOURCE T V505 DESTINATION COMBINATION I WRITE DESTINATION 807 DATA 809 H UPDATE SOURCE ADDRESS I UPDATE DESTINATION ADDRESS C 5/0 Fig. 5 US. Patent Jan. 21, 1997 Sheet 6 0f 14 5,596,767

2602 977 975 975 974975972 977 K f f f f 7 3 00 PP PBV PBH w T RR 970 CONVSP I920 CONVDP f930 PIXEL SIZE /'940 PLANE MASK I950 Fig. 9

200 H 202 7070 204 205 @J 7 7 07 5 7050 (é ADDER 7/ INSTRUCTSION PROGRAM coUNTER 64> TEMPORARY REGISTERS A17 020 REGISTER ARITHMETRIC LOGIC UNIT -/7025

I BARREL SHITTER 7 CONYROL 7050) ih'zogl? MP5 7075 REMAEDMSRNYLY MASK/MERGE UNIT 5 LEFT MOST ONE IJETEcToR _/\7040 ' I COLOR EXPAND LOGIC /\7045 / V WINDOW COMPARITORS _A7050 7065 / TRANSPARENCY LOGIC -/\7055 2/0 Fig. 70 US. Patent Jan. 21, 1997 Sheet 7 of 14 5,596,767

TRANSPARENT 50111105 BA1A i 7 7 7 0 1+7 7 72% 1+7 7 7 4~>1 Fig. 7 7A A B 1 O 1 B B B I O 1 0 B B B 1 1 1 0 E TRANSPARENCY MASK 7 720 Fig. 7 7 B A 1 1 1 1 B 0 B B 1 1 1 1 1 1 1 j 1 DESTINATEON BA1A 7 7 50 Fig. 7 7 C A A 7 A A A B B B B c c c c B D B B RESULTANT BA1A WORD 7 7 40 Fig. 7 7 D A 0 1 O 1 B B B B‘ 1 0 B 0 0 1 1 B |<— N+3 —-7<* N+2—~>+<—-N+1~>1<—N——H PIXEL BA1A 72 7 0 Fig. 7 2A A A A A A 1 A A A A B B B B B B B B PLANE MASK DATA 7220 Fig. 7 2B A B B 1 1 B 1 1 1 O B 1 1 O 1 1 1 1‘ RESULTANT DATA WORD 7 25 0 Fig. 7 2C LI 0 B A A B A A A B O B B B B B B B— PIXEL N+1 ?>1<_' PIXEL N H US. Patent Jan. 21, 1997 Sheet 8 0f 14 5,596,767

16 BIT DATAWDRD, TJVI/O 8- BIT PIXELS DESTINATION DATA TO BE ALTERED 75 7 0 Fig. 7 5A A A A A I A A A I A I A B I B SOURCE PIXELS TO BE MOVED 7520 Fig. 7 5B A Y Y Y Y Y O 0 O PLANE MASK 7550 Fig. 7 36 {O I O O O O I I I 1 RESULTANT MASKED SOURCE DATA 7 340 Fig. 7 5D A O O O O O O I O O TRANSPARENCY MASK 7 550 Fig. 75F AI 0 O O O 0 O ‘ O O I I I COMBINED PLANE AND TRANSPARENCY MASK 7 5 60 Fig. 75F A O O O I O 0 O O O RESULTANT DESTINATION DATA 7 5170 Fig. 7 3G AAAAAAAA B B B B B Z Z Z US. Patent Jan. 21, 1997 Sheet 9 0f 14 5,596,767

53 292252 _55 :5 F258 AW\ A023695 052Q?\P $2528 52%?a:3:> 062052063$3ms: Q3\ .mi3 +A>>:5GZEEmEE$5 :3 651525: GEEWEEHm528 x225:8 AIIUFIJVém AH295% Z9556ANW' EE>®Q3@3 M72:is $3 N?Ns3a. :2 Q\w Hg:

.GXE i5 5% US. Patent Jan. 21, 1997 Sheet 10 of 14 5,596,767

7570 O 1 1 O FOUR I— BIT MONOCI-IROME PIXELS Fig. 75A TO BE COLOR EXPANDED 7520 Fig. 75B 00100 PIXEL SIZE DATA 75527 75547 7534775327 Fig. 75C OOOOIIIIIIIIIOOOO P—EXPANDED MONOCHROME WORDI530————-*I 15451 154% 1545? 15451 Fig. I50 O I 0 I O O I O I 0 0 0 I O O O I 0 I<— * COLOR "0“ DATA I540 —*>I 75557 15557 75557 75553 Fig. 75E O I 0 I O I O I O I O I O I O I I<————"—"— COLOR III" DATA I550 ———~"—>I 75621 7564 v 75663 75687 Fig. O O I O O I O I 0 I O I O O I 0 COLOR COLOR COLOR COLOR "0" "I" "I" "O" PIXEL PIXEL PIXEL PIXEL V EXPANDED COLOR WORD I560 US. Patent Jan. 21, 1997 Sheet 11 01 14 5,596,767 7600 1 1 Xmin PX Ymin Py 76077650¢ $7670 7605/6501} $7620 ;J‘+CO¢JIPARAEORV76OS N“ COQPARA§ORVI6O7 Px Xmox F'y Ymox 7670 7540 7620‘ 7660

16027 COMPARATOR‘A; {8}“ “ 7505 150.45%“?T COMPARATOR V 7605 7670 7550

3 L % Z690 “i Fig. 16 - I695

OVER Y OVER Y MAX OVER V max UNDER x OVER Y MAX 1001 1000 1010 7707 1% iii 1720 W'E‘RSW 1()(mclx, Ymux) UNDER 11 1.1111 R(x,V)w11H|R OVER x 11101 0w 0001 OOOOON 0010 L704. 7700 7705 WIN (Xmin, Ymin) OVER x 51 7770 ONOERV MIN UNDERY 0101 0100 0110 7706 [ZQZ 7708 ER )1 MIN ER Y 11111 Hg. 17 US. Patent Jan. 21, 1997 Sheet 12 0f 14 5,596,767

REGTSTER ADDITION, XY MODE REGISTER SUBSTRACTION, XY MODE 7c?” [(512 i870 79]] 7%72 7970 I—W—Y§—W* X5 _ SOURCE fSOURCE Hg. 78A REGISTER REGISTER H527 H522 7520 7920 YD XD JDESTINATIDN I ESTINATIDN Fig. 785 REGTSTER “I H9- 795 REGISTER 75557 71252 K 75557 7992 Fig. 150 Fig. 190

207/ 2072

A S )5 S 12010SOURCE [IT/‘g. 20A REGISTER 2027 2022 I /YD XD/ f2020DESTINATION H9 205 REGISTER 2q51 2q32 r2030 YD _ Y? X5 _ X5 2 gEEIUSLTTER H9. 206 “0" NEGATIVE "O" NEGATIVE \\ \ STATUSA“ REG. ‘ OV2040 / \R 2047 2042 Z045 2044 H9. 200 U.S. Patent Jan. 21, 1997 Sheet 13 0f 14 5,596,767

MOVE X COORDINATE INSTRUCTION MOVE Y COORDINATE INSTRUCTION 21/11 2112 2770 2211 2212 2270 YS XS fsDuRcE YS TEXTS J SOURCE Fig. 2 REGISTER REGISTER Z727 Z722 Z227 2222 I; I )5 2120 I; ; f2220 D I D DESIINAIIDN D I D DESTINATEON Fig. 2 REGISTER / REGISTER 2151 2152 2 730 2251 2252 2230 YD XS fREsDLI YS XD fRESULT Hg. 2 7 C REGISTER Fig 226 REGISTER

DRAW AND ADVANCE INSERDDIIDN 25 7 I 25 72 25 70 ” * DAsE YB XB COORDINATE REGISTER Z521 Z522 \

OFFSET REGISTERYo I 2320JX0 25/31 25252 ADDRESS

RESULTANT REGISTER 2550J 752 60g 254 QK‘ A COLOR 0 W1 PIXEL 2347 I 2 READ / REcALLED PIXEL ~~ vIDED RAM wRIIE H 2542 coNDINED PIXEL E19. 25 US. Patent Jan. 21, 1997 Sheet 14 0f14 5,596,767

750

2407 km DISPLAY2IIA€M0O€Y PITCH —*I SCREEN‘ START ON SCREEN MEM0RY24T74 ADDRESS ON SCREEN VERT 24 7 0 MEMORY EXTENT DISPLAY-M MEMORY l 2472 i103 I+M0RIZ. EXTENT»I 2402 24201 DATA

24501 PRCCRAM 24401 OPERATING SYSTEM/ RUN TIME LIBRARIES Z4501 BOOT STRAP RoM |<_P|TCH Fig. 24 5,596,767 1 2 PROGRAMMABLE DATA PROCESSING cessor. In accordance with the present invention a graphics SYSTEM AND APPARATUS FOR data processor is provided which can execute both general EXECUTING BOTH GENERAL PURPOSE purpose data processing instructions and special purpose INSTRUCTIONS AND SPECIAL PURPOSE graphics data processing instructions. The graphics data GRAPHIC INSTRUCTIONS processor of the present invention is provided with special purpose graphics hardware particularly adapted to data This is a continuation ofappiication Ser. No. 07/965,561. processing tasks required by bit mapped graphics displays. filed Oct. 23. [992, now US Pat. No. 5,522,082; which is a One of the central features of the graphics data processor continuation of application Scr. No. (17/426,480, filed Oct. of the present invention is programmability. In accordance 23, 1989, now abandoned,‘ which is a continuation of with the present invention the graphics data processor can application Ser. No. 07/346,388, filed Apr. 27. i989, now perform general purpose data processing tasks and special abandoned: which is a continuation of application Ser. No. graphics data processing tasks in response to a single set of 07/207034, tiled Jun, l3, I988, now abandoned; which is a program instructions without any required intervention by continuation of application Ser. No. [Io/82Lo4l, filed .Ian. another processor. The general purpose data processing 23, 1986, now abandoned. tasks would typically include register arithmetic and logic BACKGROUND OF TIIE INVENTION operations. memory access operations and program flow control operations. Program flow control operations include The present invention relates to the field of computer conditional and unconditional branch operations, subroutine graphics. In particular, this invention relates to the field of calls and subroutine returns, The graphics operations would bit mapped computer graphics in which the computer include at least the capability to perform pixel array moves memory stores data for each individual picture element or for transferring an array of pixels to a specified location in pixel of the display at memory locations that correspond to the bit map. These pixel array moves preferably also include the location of that pixel on the display. The field of bit the capability to perform a specified combination between mapped computer graphics has bene?ted greatly from the ‘ corresponding pixels of a source array and a destination lowered cost per hit of dynamic random access memory array. This source destination combination may be subject to (DRAM). The lowered cost per hit of memory enables larger transparency and plane maskingv and more complex displays to be formed in the bit mapped These features and other features described in the present mode. application enable a highly ?exible solution to the problem The reduction in the cost per hit of memory and the of controlling bit mapped graphics. The capability for a consequent increase in the capacity of bit mapped computer single program to provide for both general purpose data graphics has led to the need for processing devices which processing and graphic processing is an advance over the can advantageously use the bit mapped memory in computer prior art which required such functions to be separate. graphics applications. In particular. a type of device has arisen which includes the capacity to draw simple figures, 35 such as lines and circles, under the control of the main BRIEF DESCRIPTION OF THE DRAWINGS processor ofthc computer. In addition. some devices of this type include a limited capacity for hit block transfer (known These and other objects of the present invention will be as BIT-BLT or raster operation) which involves the transfer readily understood from the following description, taken in of Image data from one portion of memory to another, conjunction with the drawings in which: together with logical or arithmetic combinations of that data FIG. 1 illustrates a block diagram of a computer with with the data at the destination location within the memory. graphics capability constructed in accordance with the prin These bit-map controllers with hard wired functions for ciples of the present invention; drawings lines and performing other basic graphics opera FIG. 2 illustrates the block diagram of a preferred tions represent one approach to meeting the demanding 45 embodiment of the graphics processing circuit of the present performance requirements of bit maps displays. The built-in invention; algorithms for performing some of the most frequently used FIG. 3 illustrates the manner of specifying individual graphics operations provides a way of improving overall pixel addresses within the bit mapped memory in accor— system performance. However, a useful graphics system dance with the X Y addressing technique; often requires many functions in addition to those few which FIG. 4 illustrates a manner ofspccifying field addresses in are implemented in such a hard wired controller. These accordance with the linear addressing technique; additional required functions must be implemented in soft ware by the primary processor of the computer. Typically FIG. 5 illustrates the preferred embodiment of storage of these hard wired bit-map controllers permit the processor pixel data of varying lengths within a single data word in accordance with the preferred embodiment of the present only limited access to the bitvideo palette 150 via video memory bus 122. Graphics processor 120 controls the data stored within FIG. 12 illustrates an example of the use of plane mask video RAM 132 via video memory bus 122. In addition. ing: graphics processor 120 may be controlled by programs FIG. 13 illustrates an example of the combined use of stored in either video RAM 132 or read only memory 134. transparency and plane masking; Read only memory 134 may additionally include various types of graphic image data. such as alphanumeric charac» FIG. 14 illustrates details of the hardware employed to it] implement transparency and plane masking in accordance tcrs in one or more font styles and frequently used icons. In with the present invention: addition. graphics processor 120 controls the data stored within video palette 150. This feature will be further dis FIG. 15 illustrates an example of color expansion of closed below. Lastly. graphics processor 120 controls digital monochrome pixel data to color pixel data: to video converter 160 via video control bus 124. Graphics FIG. 16 illustrates the hardware for implementing a processor 120 may control the line length and the number of windowing operation; lines per frame of the video image presented to the user by FIG. 17 illustrates the relationship between the window control of digital to video converter 160 via video control detector output and the location of the pixel tested in relation bus 124. to the defined window; Video memory 130 includes video RAM 132 which is FIG. 18 illustrates diagrammatically the operation of the bidircctionally coupled to graphics processor 120 via video add registers instruction in the X Y coordinate mode; memory bus 122 and read only memory 134. As previously FIG. 19 illustrates diagrammatically the operation of the stated. video RAM 132 includes the bit mapped graphics subtract registers instruction in the X Y coordinate mode; data which controls the video image presented to the user. This video data may be manipulated by graphics processor FIG. 20 illustrates diagrammatically the operation of the 120 via video memory bus 122. In addition. the video data compare registers instruction in the X Y coordinate mode; corresponding to the current display screen is output from FIG. 21 illustrates diagrammatically the operation of the video RAM 132 via video output bus 136. The data from move X coordinate instruction; video output bus 136 corresponds to the picture element to FIG. 22 illustrates diagrammatically the operation of the be presented to the user. In the preferred embodiment video move Y coordinate instruction; RAM 132 is formed of a plurality of TMS4I61 64K FIG. 23 illustrates diagrammatically the operation of the dynamic random access integrated circuits available from draw and advance instruction: and Texas Instruments Corporation. the assignee of the present application. The TM 5416] integrated circuit includes dual FIG. 24 illustrates an example of a memory map for the graphics processor of the present invention ports. enabling display refresh and display update to occur 35 without interference. Shift register 140 receives the video data from video DETAILED DESCRIPTION OF TIIE PREFERRED EMBODIMENT RAM 132 and assembles it into a display bit stream. In accordance with the typical arrangement of video random FIG. 1 illustrates a block diagram of graphics computer access memory 132. this memory consists of a bank of system 100 which is constructed in accordance with the several separate random access memory integrated circuits. principles of the present invention. Graphics computer sys The output of each of these integrated circuits is typically tem 100 includes host processing system 110. graphics only a single bit wide. Therefore. it is necessary to assemble processor 120, memory 130, shift register 140. video palette data from a plurality of these circuits in order to obtain a sullieiently high data output rate to specify the image to be 150. digital to video converter 160 and video display 170. 45 Host processing system 110 provides the major compu presented to the user. Shift register 140 is loaded in parallel tational capacity for the graphics computer system 100. Host from video output has 136. This data is output in series on processing system 110 preferably includes at least one line 145. Thus shift register 140 assembles a display bit microprocessor. read only memory. random access memory stream which provides video data at a rate high enough to specify the individual dots within the raster scanned video and assorted peripheral devices for forming a complete 50 computer system. llost processing system 110 preferably display. also includes some form of input device. such as a keyboard Video palette 150 receives the high speed video data from or a mouse. and some form of long term storage device such shift register 140 via bus 145. Video palette 150 also as a disk drive. The details of the construction of host receives data from graphics processor 120 via video memory processing system 110 are conventional in nature and known - bus 122. Video palette 150 converts the data received on bus in the art. therefore the present application will not further 145 into a video level output on bus 155. This conversion is detail this element. The essential feature of host processing achieved by means of a lookup table which is speci?ed by system 110. as far as the present invention is concerned. is graphics processor 120 via video memory bus 122. The that host processing system 110 determines the content of output of video palette 150 may comprise color hue and the visual display to be presented to the user. 60 saturation for each picture element or may comprise red, Graphics processor 120 provides the major data manipu» green and blue primary color levels for each pixel. The table lation in accordance with the present invention to generate of conversion from the code stored within video memory the particular video display presented to the user. Graphics 132 and the digital levels output via bus 155 is controlled processor 120 is bidircctionally coupled to host processing from graphics processor 120 via video memory bus 122. system 110 via host bus 115. In accordance with the present 65 Digital to video converter 160 receives the digital video invention. graphics processor 120 operates as an indepen» information from video palette 150 via bus 155. Digital to dent data processor from host processing system 110. how video converter 160 is controlled by graphics processor 120 5,596,767 5 6 via video control bus 124. Digital to video converter I60 cache 230 via instruction cache bus 204 is much faster than serves to convert the digital output of video palette 150 into access to video memory 130. Thus. the program executed by the desired analog levels for application to video display 170 central processing unit 200 may be specded up by prelimii via video output 165. Digital to video converter 160 is narily loading the repeated or often used sequences of controlled for a specification of the number of pixels per 5 instructions within instruction cache 230. Then these horizontal line and the number of lines per frame. for instructions may be executed more rapidly because they may example. by graphics processor 120 via video controller bus he fetched more rapidly. Instruction cache 230 need not 124. Data within graphics processor 120 controls the gen— always contain the same sets of instructions. but may be cration of the synchronization and blanking signals and the loaded with a particular set of instructions which will he retrace signals by digital to video converter 160. These often used within a particular portion of the program portions of the video signal are not specified by the data executed by central processing unit 200. stored within video memory 132. but rather form the control Host interface 240 is coupled to central processing unit signals necessary for specification of the desired video 200 via host interface bus 206. Most interface 240 is further output. connected to the host processing system 110 via host system bus 115. Host interface 240 serves to control the commu Lastly, video display 170 receives the video output from nication between the host processing system 110 and the digital to video converter 160 via video output line 165. graphics processor 120. llost interface 240 controls the Video display 170 generates the specified video image for timing of data transfer between host processing system 110 viewing by the operator ofgraphics computer system 100. it and graphics processor 120. In this regard. host interface 240 should be noted that video palette 150. digital to video enables either host processing system 110 to interrupt graph~ converter 160 and video display 170 may operate in accor» ics processor 120 or vice versa enabling graphics processor dance to two major video techniques. ln the first. the video 120 to interrupt host processing system 110. In addition. host data is speci?ed in terms of color hue and saturation for each interface 240 is coupled to the major bus 205 enabling the individual pixel. In the other technique, the individual host processing system 110 to control directly the data stored primary color levels of red, blue and green are specified for within memory 130. Typically host interface 240 would each individual pixel. Upon determination of the design communicate graphics requests from host processing system choice of which of these major techniques to be employed, 110 to graphics processor 120. enabling the host system to video palette 150. digital to converter 160 and video display specify the type of display to be generated by video display 170 must be constructed to be compatible to this technique. 170 and causing graphics processor 120 to perform a desired However. the principles of the present invention in regard to graphic function. the operation of graphics processor 120 are unchanged 30 regardless of the particular design choice of video technique. Central processing unit 200 is coupled to speciai graphics hardware 210 via graphics hardware bus 208. Spcciai graph FIG. 2 illustrates graphics processor 120 in further detail. ics hardware 210 is further connected to major bus 205. Graphics processor 120 includes central processing unit 200. Special graphics hardware 210 operates in conjunction with special graphics hardware 210. register files 220, instruction central processing unit 200 to perform special graphic cache 230. host interface 240. memory interface 250, input] processing operations. Central processing unit 200. in addi— output registers 260 and video display controller 270. tion to its function of providing general purpose data pro’ The heart of graphics processor 120 is central processing cessing. controls the application of the special graphics unit 200. Central processing unit 200 includes the capacity hardware 210 in order to perform special purpose graphics to do general purpose data processing including a number of instructions. These special purpose graphics instructions arithmetic and logic operations normaily included in a concern the manipulation of data within the bit mapped general purpose central processing unit. in addition. central portion of video RAM 132. Special graphic hardware 210 processing unit 200 controls a number of special purpose operates under the control of central processing unit 200 to graphics instructions. either alone or in conjunction with enable particular advantageous data manipulations regard’ special graphics hardware 210. 45 ing the data within video RAM 132. Graphics processor 120 includes a major bus 205 which Memory interface 250 is coupled to major bus 205 and is connected to most parts of graphics processor 120 inctud further coupled to video memory bus 122. Memory interface ing the central processing unit 200. Centrai processing unit 250 serves to control the communication ofdata and instruc 200 is bidirectionally coupled to a set of register files. tions between graphics processor 120 and memory 130. including a number of data registers. via bidirectional reg» Memory 130 includes both the bit mapped data to be ister bus 202. Register files 220 serve as the depository ofthe displayed via video display 170 and instructions and data immediately accessible data used by central processing unit necessary for the control of the operation of graphics pro» 200. As will be further detailed below, register files 220 cessor 120. These functions include control of the timing of includes in addition to general purpose registers which may memory access, and control of data and memory multiplex‘ be employed by central processing unit 200. a number of 55 ing. In the preferred embodiment. video memory bus 122 data registers which are employed to store implied operands includes multiplexed address and data information. Memory for graphics instructions. interface 250 enables graphics processor 120 to provide the Central processing unit 200 is connected to instruction proper output on video memory bus 122 at the appropriate cache 230 via instruction cache bus 204. Instruction cache time for access to memory 130. 230 is further coupled to major bus 205 and may be loaded 60 Graphics processor 120 lastly includes input/output reg’ with instruction words from the memory 130 via video istcrs 260 and video display controller 270. Input/output memory has 122 and memory interface 250. The purpose of registers 260 are bidireetionally coupled to major bus 205 to instruction cache 230 is to speed up the execution of certain eriabie reading and writing within these registers. Input] functions of central processing unit 200. A repetitive func output registers 260 are preferably within the ordinary tion or function that is used often within a particular portion memory space of central processing unit 200. Input/output ofthe program executed by central processing unit 200 may registers 260 include data which specifies the control param be stored within instruction cache 230. Access to instruction eters of video display controller 270. in accordance with the 5,596,767 7 8 data stored within the input/output registers 260. video As in the case of X Y addressing. speci?cation of these linear display controller 270 generates the signals on video control addressing parameters enables memory interface 250 to bus 124 for the desired control of digital to video converter generate the proper physical address speci?ed. 160. Data within input/output registers 260 includes data for The two addressing modes are useful for differing pur specifying the number of pixels per horizontal line. the poses. The X Y addressing mode is most useful for that horizontal synchronization and blanking intervals. the num portion of video RAM 132 which includes the bit map data. bcr of horizontal lines per frame and the vertical synchro called the screen memory which is the portion of memory nization blanking intervals. Input/output registers 260 may which controls the display. The linear addressing mode is also include data which specifies the type of frame interlace most useful for off screen memory such as for instructions and specifies other types of video control functions. Lastly. and for image data which is not currently displayed This input/output registers 260 is a depository for other speci?c latter category includes the various standard symbols such as kinds of input and output parameters which will be more alphanumeric type fonts and icons which are employed by fully detailed below the computer system. It is sometimes desirable to be able to Graphics processor 120 operates in two dilfering address convert an X Y address to a linear address. This conversion modes to address memory 130. These two address modes are takes place in accordance with the following formula: X Y addressing and linear addressing. Because the graphics processor 120 operates on both bit mapped graphic data and upon conventional data and instructions. dill'erent portions of the memory 130 may be accessed most conveniently via Where: LA is the linear address; OFF is the screen offset, the differing addressing modes. Regardless of the particular 20 linear address ofthe origin of the X Y coordinate system; Y addressing mode selected. memory interface 250 generates is the Y address; SP is the screen pitch in bits; X is the X the proper physical address for the appropriate data to be address; and PS is the pixel size in bits. Regardless ofwhich accessed. ln linear addressing. the start address of a ?eld is addressing mode is employed. memory interface 250 gen formed of a single multibit linear address. The ?eld size is erates the proper physical address for access to memory 130. determined by data within a status register within central FIG. 5 illustrates the manner of pixel storage within data processing unit 200. In X Y addressing the start address is a words of memory 130. In accordance with the preferred pair of X and Y coordinate values. The ?eld size is equal to embodiment of the present invention. memory 130 consists the size of a pixel. that is the number of bits required to of data words of 16 bits each. These 16 bits are illustrated specify the particular data at a particular pixel. schematically in FIG. 5 by the hexadecimal digits 0 through FIG. 3 illustrates the arrangement of pixel data in accor F In accordance with the preferred embodiment of the dance with an X Y addressing mode. Similarly. FIG. 4 present invention. the number of bits per pixel within illustrates the arrangement of similar data in accordance memory 130 is an integral power of 2 but no more than 16 with the linear addressing mode. FIG. 3 shows origin 310 bits. As thus limited. each 16 bit word within memory 130 which serves as the reference point of the X Y matrix of can contain an integral number of such pixels. FIG. 5 pixels. The origin 310 is speci?ed as a X Y start address and illustrates the ?ve available pixel formats corresponding to need not be the ?rst address location within memory. The pixel lengths of l. 2. 4. 8 and to bits. Data word 510 location of data corresponding to an array of pixels. such as illustrates l6 one bit pixels 511 to 526 thus 16 one bit pixels a particular de?ned image element is speci?ed in relation to may be disposed within each 16 bit word. Data word 530 the origin address 310. This includes an X start address 340 illustrates 8 two bit pixels 531 to 538 which are disposed and a Y start address 330. Together with the origin. X start within the l6 bit data word. Data word 540 illustrates 4 four address 340 and Y start address 330 indicates the starting bit pixels 541 to 544 within the lo bit data word. Data word address of the first pixel data 371 of the particular image S50 illustrates 2 eight bit pixels 551 and 552 within the 16 desired. The width of the image in pixels is indicated by a bit word. Lastly. data word 560 illustrates a single l6 bit quantity delta X 350. The height of the image in pixels is pixel 561 stored within the 16 bit data word. By providing indicated by a quantity delta Y 360. in the example illus pixels in this format. speci?cally each pixel having an trated in FIG. 3. the image includes nine pixels labeled 37] integral power of two number of bits and aligned with the through 379. The last parameter necessary to specify the physical word boundaries. pixel manipulation via graphics physical address for each of these pixels is the screen pitch processor 120 is enhanced. This is because processing each 320 which indicates the width of the memory in number of physical word manipulates an integral number of pixels. It bits. Speci?cation of these parameters namely X starting 50 is contemplated that within the portion of video RAM 132 address 340. Y starting address 330. delta X 350. delta Y 360 which speci?es the video display that a horizontal line of and screen pitch 320 enable memory interface 250 to pixels is designated by a string of consecutive words such as provide the speci?ed physical address based upon the spccia illustrated in FIG. 5. lied X Y addressing technique. FIG. 6 illustrates the contents of some portions of register HO 4 similarly illustrates the organization of memory in 55 ?les 220 which store implied operands for various graphics the linear format. A set of ?elds 441 to 446. which may be instructions. Each of the registers 60] through 611 illus» the same as pixels 371 through 376 illustrated in FIG. 3. is tratcd in FIG. 6 are within the register address space of illustrated in FIG. 4. The following parameters are necessary central processing unit 200 of graphics processor 120. Note. to specify the particular elements in accordance with the these register ?les illustrated in FIG. 6 are not intended to linear addressing technique. Firstly. is the start address 410 60 include all the possible registers within register ?les 220. On which is the linear start address of the beginning of the ?rst the contrary. a typical system will include numerous general field 441 of the desired array. A second quantity delta X 420 purpose undesighated registers which can be employed by indicates the length of a particular segment of ?elds in central processing unit 200 for a variety of program speci» number of hits. A third quantity delta Y (not illustrated in lied functions. FIG. 4,! indicates the number of such segments within the 65 Register 601 stores the source address. This is the address particular array. Lastly. linear pitch 430 indicates the differ of the lower left corner of the source array. This source ence in linear start address between adj accnt array segments. address is the combination of X address 340 and Y address 5,596,767 9 10 330 in the X Y addressing mode or the linear start address the data stack. This stack pointer address thus serves to 410 in the linear addressing mode. indicate the address ol‘thc last entered data in the data stack. Register 602 stores the source pitch or the dill'erence in FIG. 7 illustrates in schematic form the process ol‘ an linear start addresses between adjacent rows ol' the source array move from oil‘ screen memory to screen memory. MG. array. This is either screen pitch 320 illustrated in FIG. 3 or 7 illustrates video RAM 132 which includes screen memory linear pitch 430 illustrated in FIG. 4 depending upon 705 and oil‘ screen memory 715. ln FIG. 7 an array ofpixels whether the X Y addressing format or the linear addressing 780 (or more precisely the data corresponding to an array ol' format is employed. pixels) is transferred from oil‘ screen memory 715 to screen Registers 603 and 604 are similar to registers 601 and memory 705 becoming an array of pixels 790. 602. respectively, except that these registers include the Prior to the performing the array move operation certain destination start address and the destination pitch. The data must be stored in the designated resisters ol' register destination address stored in register 603 is the address of lilcs 220. Register 601 must be loaded with the beginning address 710 of the source array ol‘ pixels. In the example the lower left hand corner ol' the destination array in either illustrated in FIG. 7 this is designated in linear addressing X Y addressing mode or linear addressing mode. Similarly. mode. The source pitch 720 is stored in register 602. the destination pitch stored in register 604 is the dill‘ercnce Register 603 is loaded with the destination address. in the in linear starting address ol' adjacent rows, that is either example illustrated in FIG. 7 this is designated in X Y screen pitch 320 or linear pitch 430 dependent upon the addressing mode including X address 730 and Y address addressing mode selected. ‘740. Register 604 has the destination pitch 745 stored Register 605 stores the oll‘sct. The olTset is the linear hit therein. The linear address of the origin of the X Y coordi address corresponding to the origin of the coordinates of the nate system. oll‘set address 770. is stored in register 605. X Y address scheme. As mentioned above. the origin 310 of Lastly, delta Y 750 and delta X 760 are stored in separate the X Y address system does not necessarily belong to the halves ol“ register 608. physical starting address of the memory. The oll'sct stored in The array move operation illustrated schematically in register 605 is the linear start address ofthe origin 310 of this FIG. 7 is executed in conjunction with the data stored in X Y coordinate system This olTset is employed to convert these registers of register lile 220. In accordance with the between linear and X Y addressing. preferred embodiment the number of bits per pixel is Registers 606 and 607 store addresses corresponding to a selected so that an integral number of pixels are stored in a window within the screen memory. The window start stored single physical data word. By this choice. the graphics in register 606 is the X Y address of the lower left hand processor may transfer the array of pixels 780 to the array 01‘ corner ofa display window. Similarly. register 607 stores the 30 pixels 790 largely by transfer olw whole data words. liven window end which is the X Y address ol‘thc upper right hand with this selection of the number of bits per pixel in relation corner ol‘ this display window. The addresses within these to the number of bits per physical data word. it is still two registers are employed to determine the boundaries of necessary to deal with partial words at the array boundaries the speci?ed display window. ln accordance with the well in some cases. However. this design choice serves to mini» known graphics techniques. images within a window within 35 mine the need to access and transfer partial data words. the graphics display may differ from the images of the In accordance with the prel'crrcd embodiment of the background. The window start and window end addresses present invention. the data transfer schematically repre contained in these registers are employed to designate the sented by FIG. 7 is a special case of a number ol‘ dili‘ering extent of the window in order to permit graphics processor data transformations. The pixel data from the corresponding 120 to determine whether a particular X Y address is inside 40 address locations of the source image and the destination or outside ol‘ the window. image are combined in a manner designated by the instruc— Register 608 stores the delta Y/delta X data. This register tion. The combination of data may be a logical function is divided into two independent halves. the upper half (such as AND or OR) or it may be an arithmetic function (higher order bits} designating the height of the source array (such as addition or subtraction’). The new data thus stored (delta Y) and the lower half (lower order bitsl designating 45 in the array of pixels 790 is a function of both the data of the the width of the source array (delta X). The delta Y/delta X array ol‘ pixels 780 and the current data of pixels 790. The data stored in register 608 may be provided in either the X data transfer illustrated in FIG. 7 is only a special case of this Y addressing format or in the linear addressing format more general data transformation in which the data linally depending upon the manner in which the source array is stored in the destination array does not depend upon the data designated. The meaning ol‘ the two quantities delta X and 50 previously stored there. delta Y are discussed above in conjunction with FIGS. 3 and This process is illustrated by the flow chart 800 in FIG. 8. 4. In accordance with the preferred embodiment the transfer Registers 609 and 610 each contain pixel data. Color 0 takes place sequentially by physical data words. Once the data stored in register 609 contains a pixel value replicated process begins (begin block 801l the data stored in the throughout the register corresponding to a ?rst color desig" register 60] is read to obtain the source address (processing natcd color 0. Similarly. color 1 data stored in register 610 block 802]. Next graphics processor 120 fetches the indi includes a pixel value replicated throughout the register cated physical data word from memory 130 corresponding corresponding to a second color value designated color 1. to the indicated source address (processing block 803i. In Certain ol' the graphics instructions of graphics processor the case that the source address is speci?ed in the X Y 120 employ either or both of these color values within their l'orrnat. this recall of data would include the steps ol~ con’ data manipulation. The use of these registers will be verting the X Y address into the corresponding physical explained further below. address. A similar process of recall of the destination address Lastly. the register tile 220 includes register 611 which from register 603 (processing block 804) and then [etching stores the stack pointer address. The stack pointer address of‘ the indicated physical data word (processing block 805) stored in register 611 specifies the bit address within video 65 takes place for the data contained at the destination location. RAM 132 which is the top of the data stack. This value is This combined data is then restored in the destination adj usted data is pushed onto the data stack or popped from location previously determined (processing block 806). The