Xilinx Xcell Quarterly Newsletter #22 (Q3

FAX RESPONSE FORM-XCELL 22 3Q96

Corporate Headquarters FAX in Your Comments and Suggestions Xilinx, Inc. 2100 Logic Drive To: Brad Fawcett, XCELL Editor Xilinx Inc. FAX: 408-879-4676 San Jose, CA 95124 From: ______Date: ______Tel: 408-559-7778 Issue 22 Fax: 408-559-7114 ❏ Please add my name to the XCELL mailing list. Third Quarter 1996 Europe Xilinx, Ltd. NAME THE QUARTERLYX JOURNALCELL FOR XILINX PROGRAMMABLE LOGIC USERS Suite 1B, Cobb House Oyster Lane COMPANY Byfleet Surrey KT147DU ADDRESS 40 United Kingdom Tel: 44-1-932-349401 R PRODUCT INFORMATION CITY/STATE/ZIP Fax: 44-1-932-349499

PHONE Japan Xilinx, KK The Programmable XC5200 FPGAs: ❏ Daini-Nagaoka Bldg. 2F I’m interested in having my company’s design featured in a future edition of Logic CompanySM 2-8-5, Hatchobori, XCELL as a Customer Feature. Chuo-ku, Tokyo 104 Prices Go Down and Japan Inside This Issue: Tel: 81-3-3297-9191 Comments and Suggestions: ______Performance Goes Up Fax: 81-3-3297-9189 GENERAL ______Asia Pacific Fawcett: Reconfigurable Computing ...... 2 Guest Editorial ...... 3 Xilinx Asia Pacific ______Customer Success Stories Unit 4312, Tower II GPT Video Systems ...... 6-7 TM Metroplaza BICOM ...... 7 family FPGAs, while ______Xilinx Funds Seiko-Epson Foundry ...... 8 Hing Fong Road New Data Book Now Availableboosting ...... 8 performance by as much as 30%... Kwai Fong, N.T. ______What’s New on WebLINX ...... 9 See Page 11 Hong Kong Training Update ...... 9 Tel: 852-2424-5200 Financial Results ...... 10 New Product Literature ...... 10 Fax: 852-2494-7159 ______Upcoming Events ...... Process 10 improvements and record sales ______have helped to knock asSynopsys much as 50% off Introduces the price on XC5200 FPGA Express

PRODUCTS Alliance partner Synopsys has built on the XC5200 Prices Down, Value Up ...... 11 XC7300 Best 44-Pin PLD ...... 12-13 strengths of its FPGA Compiler to create a XC8100 Family Discontinued ...... 13 Windows 95 and NT product that includes all Please use this form to FAX in your comments and suggestions, or to request an addition to the Production Begins for XC4000EX ...... 14 Faster -2 Speed Grade for XC4000E ...... 14 of the hottest new Xilinx products... XCELL mailing list. Please feel free to make copies of this form for your colleagues. See Page 15

DEVELOPMENT SYSTEMS U.S. Postage Synopsys’ FPGA Express ...... 15-16 R LogiCore PCI Initiator Debuts ...... 17 PAID Foundation Introduction Successful ...... 17 First Class 2100 Logic Drive Permit No. 2196 DESIGN TIPS & HINTS HINTS & ISSUES San Jose, CA 95124-3450 San Jose, CA XC9500 CPLD Pin-Locking ...... 18-21 XC9500 Slew Rate Controls ...... 22 Using XC5200 Carry Logic ...... 23-25 Pinlocking & XC9500 CPLDs Advantages of Select-RAM ...... 26-27 Power, Package & Performance ...... 28-29 In further proof that designers must consider more Metastability Recovery in FPGAs ...... 30-31 XACT than just the expected specifications,TM XC9500 CPLDs have proven themselves to be the best choice for step on Alternate Systems ...... 32 E-Mail Group Monitors Xilinx Products . 33 maintaining pinouts during design iterations... New Technical Support Choices ...... 34-35 See Page 18 Questions & Answers ...... 36-37 Component Availability Chart ...... 38-39 Development Systems Chart ...... 40 Programming Support Charts ...... 41-43 Alliance Program Charts ...... 44-46 Reader Survey ...... Using 47 XC5200 FPGA Carry Logic Fax Response Form ...... Tips 48 for using this simple, but flexible, feature... See Page 23 2 property of their respective owners. Inc. All other trademarks are the Company” is a service mark of Xilinx, and “The Programmable Logic Series, and products, HardWire, Foundation trademarks; all XC-designated Xilinx logo and XACT are registered customers of Xilinx, Inc. the XCELL is published quarterly for All rights reserved. ©1996 Xilinx Inc. E-Mail: FAX: Phone: San Jose, CA 95124 2100 Logic Drive Xilinx, Inc. Editor: comments and submissions to: Please direct all inquiries, XCELL 408-879-4676 408-879-5097 Bradly Fawcett [email protected] XACT step are trademarks; R

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○ Several companies brought demonstration ucts it has developed or is developing. gave a short presentation about the prod- cally increasing system performance. off-loading the host processor and dramati- variety of operations directly in hardware, ured during system operation to perform a ers. In these systems, FPGAs are reconfig- ate operations in general-purpose comput- FPGAs as computing elements to acceler- configurable using in-system- the practice of loosely defined as computing is reconfigurable In this context, cial assistance. some cases, finan- marketing and, in commercial companies through technical, page 35) applications and products development of reconfigurable computing mid-1995 to proactively spur commercial Developer’s Program was founded in Reconfigurable Computing Developer’s FROM THE FAWCETT Each company attending the meeting The Reconfigurable Computing (RC) T his past June, Xilinx held its first . The program is designed to aid Developer’s Program. participants in the 20 companies that are from 11 of the more than together representatives conference brought an annual event, the quarters. Planned to be far from company head- hotel in Santa Clara, not Program Conference at a Reconfigurable Computing: Coming of Age provided some valuable insights into the nature of the nascent

(see

but growing market for RC- ❝ The conference XCell By BRADLY FAWCETT based products. #19, video games. sequences to 3-D graphic rendering for cations to automated searches of DNA ing tasks, ranging from satellite communi- wide variety of high-performance comput- systems in their end products to tackle a E-Systems and TRW. Boeing, Ericsson, Loral, NTT, Delco, evaluating those products — names like RC-based hardware platforms and soft- significant strides in the development of Operations (Berkeley, CA). All are making Computer Corp. (Reseda, CA), and Giga Micro Systems (Annapolis, MD), Virtual own specific end applications member companies are develop their own products, while other and software tools to OEM accounts nies specialize two main business models Among this small sampling, there were growing market for RC-based products. insights into the nature of nascent but with Xilinx R&D personnel and each other. tives of the member companies interact was an ideal forum for letting representa- systems to the meeting. The conference Other companies are using RC-based The first category includes Annapolis The conference provided some valuable ◆ ◆ ◆ ◆ ◆

Editor ❞ in providing hardware focused on their . Some compa- Continued on page 4 that are using or OEM accounts large corporate of the types was the mention presentations pects of their interesting as- of the most ware tools. One .

that

✁✁ ✁✁ CUT HERE AND MAIL OR FAX OR MAIL AND HERE CUT .Do you have access to the Xilinx website? 5. 2. What amount of time do you generally spend reading Do you read every issue of 1. COMMENTS: From: Fax: : To 3. How many people read your copy of 2. .Technology makes other 4. ______❏ ______Hard copy (as it is now) ______Faxed to you ______CD-ROM mailed to you ______E-mailed to you ______Access via the Xilinx Website (rank most preferred format as 1, second 2, etc.) an issue of the magazine. Do you receive it consistently? XCell rank these five options according to your preference. 5-15 min. is mainly distributed quarterly as a hard copy

______408-879-4676 Jan Houts, Xilinx Company: off or copy the page and send it to: After marking your choices, please tear most out of Xilinx products and services. is to make to improve the distribution of useful to you. In addition, we’d like your suggestions on how tions, you’ll help us determine which articles are the most ness of this publication. By answering the following ques- this issue, we’d like to get your feedback on the effective- information about Xilinx products and their applications. In XCell Dear Reader, ______❏ XCell 15-30 min.

______is intended to provide you, our users, with the latest Of course, any additional

newsletter? comments are welcome. (optional)

XCell ❏ XCell XCell 30-60 min formats possible. Please ? ❏ a source of information to help you get the XCell 3Q96 Reader Survey XCell Yes ❏ ❏ ? ______❏ ❏ Over 1 hour Yes Yes No ❏ ❏ No No PRODUCT INFORMATION GENERAL FEATURES 6. How would you rank the usefulness of categories

(circle one; 1=not useful at all; 5=extremely useful) and third-party programmers software. Current availability of components, development systems Recurring, informational charts Design hints and issues Additions to our development system product line. Development systems: New product introductions, new speed grades, etc. Components: technical conferences, financial status Updates on new product literature, General interest features: Applications that currently use Xilinx products. Customer success story: the companies strategies and directions. Xilinx senior staff members highlight Guest editorial: in the programmable logic industry. Editorial comments on issues of significance From The Fawcett: information in XCell newsletter. Our goal Fax: 408-879-4676 San Jose, CA 95124 2100 Logic Drive Xilinx Inc. Jan Houts XCell listed below? sfluseful useful useful useful o Very Not Very Not 12345 12345 12345 12345 12345 12345 12345 12345 47 46 iwoi onDb (508) 480-0881 John Dube Loren Lacy (916) 622-7935 (408) 496-4515 Inquiries about the Xilinx Alliance Program can be e-mailed to [email protected]. Zycad Shige Ohtani Rocky Awalt Kathie O’Toole Zuken Visual Software Solutions, Inc. Viewlogic Veribest Richard Jones VEDA DESIGN AUTOMATION INC Trans EDA Limited TopDown Design Solutions Ed (508) 897-0028 Tokyo Electron Limited Luise Markham Marketing Department The Rockland Group Teradyne Synplicity, Inc. Synopsys Frank Meunier Synario Design Automation Summit Design Corporation Sophia Sys & Tech SimuCad Quad Design Technology, Inc. Protel Technology +49-89-839910 (503) 531-2412 OrCAD Model Technology Minelec Christian Kerscher MINC McCollow Marnie Mentor Graphics Logical Devices Logic Modeling Corp. (Synopsis Division) ITS (408) 474-5002 (206) 869-4227 x116 (604) 522-6200 ISDATA INCASES Engineering GmbH IKOS Systems (408) 428-6209 IK Technology Co. Murray Marcia Harmonix Corporation Chris Dewhurst MikeMcClure Fujitsu LSI Flynn Systems David Rinehart Lotz Christopher 656-2189 (510) Henry Verheyen Exemplar Logic (603) 881-8821 Escalade Epsilon Design Systems, Inc. Compass Design Automation CINA-Computer Integrated Network Analysis Hudson Nancy Chronology Corporation Capilano Computing Ray Wei Cadence Aster Ingenierie S.A. Aptix Corporation Alta Group ALPS LSI Technologies, Inc. Aldec Acugen Software, Inc. ACEO Technology, Inc. Accolade Design Automation C OMPANY N AME XILINX ALLIANCE-EDA CONTACTS-AUGUST 1996 ieHni (201) 989-2900 (305) 423-8448 Mike Hannig Makato Ikeda Andy Bloom (617) 422-3753 James Douglas Art Pisani (408) 232-4764 Mike Jew Alisa Yaffa 988-8250 (805) Lynn Fiance Jacquelin Taylor 671-9500 (503) Tom Tilbon Britta Sullivan (303) 279-6868 x209 Mike Jingozian Greg Seltzer Kevin Bush +49-72-1751087 Sam Picken Mot David +81-3-3839-0606 Ralph Remme Brad Roberts (603) 598-4444 Tsutomu Someya (408) 654-1651 Shigeaki Hakusui Masato Tsuru Matt Van Wagner Shubha Shukla Rod Dudzinski Cuong Do (408) 944-7016 Brad Ashmore 441489571562 Ann Heilmann 470-2686 (800) Baruch Deutsch David Blagden Dave Pellerin C ONTACT Sinclair N AME +81-4-594-27787 (303) 581-2330 [email protected] +44-703-255118 (603) 888-8811 +81-3-334-08198 (415) 961-4962 (415) 694-4289 (206) 867-6257 (503) 643-9281 (510) 487-9700 (408) 243-8143 (503) 526-5465 +32-02-4603175 (719) 590-1155 (503) 685-1298 (408) 366-8509 (617) 935-8335 +81-4-4812-8043 (510) 337-3741 (408) 934-1536 (415) 940-1723 +33-99537171 (408) 523-4137 (702) 456-1222 x12 P HONE N UMBER [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] E- MAIL A DDRESS A. The IDCODE and USERCODE registers are a vital part of any ISP device following areas: meaningful. General consensus seems to be forming in the one another for the development of a standard approach to be diagnostics. The vendor approaches to ISP were close enough as diverse emulation technologies and remote field test was great. Immediate applications could be envisioned in fields and HP. GenRad and Teradyne; ISP end-users such as Cisco Systems sultants; automatic test equipment manufacturers such as HP, such as Asset Intertech, Corelis, Intellitech and APG Test Con- Lattice, AMD, Cypress and IBM; third-party tool manufacturers The attendees included PLD manufacturers such as Xilinx, Altera, Hewlett Packard’s Manufacturing Test Division in Loveland, CO. from about 20 companies. This first ‘study group’ meeting was held on April 19 at purview, with Xilinx taking the lead in this effort. group chose to take a active role in bringing an ISP extension 1149.1 under its XC4000 series FPGAs optionally can be programmed through the TAP). The working (For example, XC9500 family CPLDs are always programmed through the TAP, and development is becoming a de facto standard among most PLD manufacturers. that the use of 4-pin 1149.1 test access port (TAP) as platform for ISP programming algorithm re-work. development costs escalate as new devices come on-line, requiring extensive variety of ISP parts available. In addition, their own test and diagnostic software party applications solutions that address the system-level issues for wide manufacturing flows and enable remote system updating. that are already soldered on a system board to facilitate prototyping, streamline GUEST EDITORIAL I tem would be otherwise unobtainable. instructions makes ISP impractical since the revision level and contents of a sys- Indeed, not supporting these part, program content and version identification The XC9500 CPLD architecture already includes these optional 1149.1 functions. will probably be made mandatory. There was broad agreement that the value of standardization Xilinx and Hewlett Packard organized a meeting of more than 30 participants At the last IEEE 1149.1 (JTAG) working group meeting, it was recognized As ISP proliferates, end-users are strained by the difficulty of finding third Xilinx T n-system programming (ISP) allows users to program and re-program parts Standardization Effort By NEIL G. JACOBSON akes the Lead in ISP ◆

Manager, JTAG Research & Development Continued on the next page

of finding third party applications users are strained by the difficulty solutions that addresss the system- level issues for the wide variety ❝ As ISP of ISP parts available

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○ proliferates, end-

. ❞ R 3 THE FAWCETT

Continued from page 2 is targeting the ‘music enthusiasts’ RS6000 HP7 market with this product, and is UN developing a lower-cost version for ✓✓✓ the consumer market. PLATFORMS ✓ ✓✓ ✓ ✓ ✓ ✓ ✓✓ ✓ ✓ ✓✓✓✓ ✓ ✓ ✓✓ ✓ • TSI Telsys recently sold several of its PC S Products that have already reached thesatellite ‘gateway’ systems to NASA’s NI IB ✓✓✓ ✓ ✓✓✓ ✓ ✓✓✓✓✓✓ ✓ ✓ ✓✓✓ ✓ marketplace include Digital Wings for Marshall Space Flight Center, where it L 4 Audio from Metalithic Systems (Sausalito,will support programs such as the Space K

Station project. 9 K 7k 7k 7k 7k 7k 7k 7k 7k ❝ CA), satellite ground station communica- 7k 7k,9k The enormous 7k,9k tions systems from TSI Telsys (Columbia,• Time Logic’s DeCypher II system, MD), the DeCypher II ‘Ge- ✓✓ designed for screening DNA sequence ✓✓✓✓✓ ✓✓✓✓✓ ✓✓✓✓✓ ✓✓✓✓✓ potential of reconfigurable netics Supercomputing PC’ 5200 7 data, is proving popular with both phar- / XC CPLD U K

from Time Logic (Incline K /3 ✓✓✓ ✓ ✓✓✓ ✓✓ ✓ ✓ ✓ ✓✓ ✓✓✓✓ ✓✓ ✓✓ ✓✓✓✓ ✓✓✓✓ ✓✓✓ ✓✓ ✓ ✓✓ ✓✓✓ ✓✓✓ ✓✓✓✓ ✓ ✓✓✓✓✓✓ ✓ ✓✓✓✓✓✓ ✓✓✓ ✓✓✓✓ ✓ ✓✓✓✓ ✓✓ ✓ ✓✓✓✓ 4 computing is beginning to maceutical companies and medical ✓ K 3k,4k 3k,4k 3k,4k 3k,4k 3k,4k 3k,4k 3k,4k 3k,4k 3k,4k Village, NV), and the X-CIMresearch facilities, where it outperforms 2 attract the attention of the line of DSP acceleration multi-million-dollar supercomputers. modules from MiroTech CAE tool vendors. Microsystems (Saint Laurent,• MiroTech Microsystems is addressing Proven Xilinx compatibility

❞ Quebec, Canada). the FPGA-based DSP market. Its DSP These partners have a high degree of compatibility and acceleration modules are fully

• Available soon in retail IT K

music equipment stores, Ruby: have repeatedly shown themselves to be significant contribu- tors to our users’ development solutions. Emerald:

Digital Wings is a 128-track ESIGN XNFGEN Xilinx Library Interface XNF Axess 2.Yes Xilinx Kit Xilinx Kit Xilinx Design Module Xilinx I/F Kit XNF Interface XNF Xilinx Kit XILINX Tool Kit Included Included AALCA interface Xilinx FPGA Design Kit Xilinx Kit audio authoring system that operates in D Xilinx FPGA Design Kit Xilinx FPGA Design Kit Xilinx FPGA Design Kit Xilinx FPGA Design Kit Xilinx FPGA Design Kit Xilinx FPGA Design Kit the Windows environment on a PC (see XCell #20, page 42). Metalithic Systems

GUEST EDITORIAL

Continued from the previous page B. The system-level issues related to ISP overall standard. Serial vector format (i.e., safe pin states during ISP (SVF), suitably modified, might best operations, describing how parts can serve as that vehicle. safely initialize after ISP is completed, The EZTag software generates SVF files etc.) must be addressed. to describe all XC9500 ISP operations.

The XC9500 ISPEN and ISPEX instruc- UNCTION Rapid Prototyping Design Capture Synthesis/Simulation LASAR model generationTiming Specification and Analysis Included Worst Case Simulation Testability Analysis Test Vector GenerationLogic Analysis Top-Down Design SystemSynthesis Xilinx Kit Simulation Included 4k 7k Schematic Simulation Gate-level Sim HDL, Synthesis, SimulationASIC to FPGA Netlist Mapping Included Schematic Entry Synthesis Testability Analysis Design Management Synthesis Synthesis F D. The RUN-TEST/IDLE state is the Simulation Design Entry Synthesis 45 tions provide a framework for protecting “action” state in which programming the user’s system during ISP operations. or erase latency times are spent. This type of functionality is absolutely This is exactly the way XC9500 parts critical for developing a truly workable software for these products. 14.x 1.0c 2.60 Automatic Test Generationinterface AALCA 2.60 14.0 12.2 12.0 function. ERSION

standard. RODUCT Paradigm RP TransPROTsutsuji 1.2 Synthesis PROVERD PARTHENONPLDesigner-XLLasar 2.3 3.3 Synthesis 6 System ExplorerASIC ExplorerXILLASTimingDesigner 2.1 2.3 System Emulation Logic Compressor 3.0 ASIC EmulationFS-ATG 4.1 CKTSIM Synthesis optimization Axess 2.3 3.0 3.0 4K One-Hot State Machine Lib.Paradigm XP Graphic Design for One-Hot State Machines QuickBenchSmartViewer 1.0FS-SIM Generator Visual Test Bench Included 3.0 VulcanVerBest Design Capture 4.5Peak FPGA Plus Simulation Gatran 2.2 ATGEN 3.3 P Veribest VHDL 14.0 AsynSoftwireSharpeye 3.3 3.3 Multi-FPGA Partitioning Included D M MVeriBest Synthesis Synovation 14.x Veribest VerilogVeriBest SimulatorPLDSyn 14.0 14.0 Simulation Either way, Xilinx has already equipped XILINX the new XC9500 family with the industry’s

❝ NC Either way, Xilinx has best JTAG/ISP capabilities and is spearhead- I already equipped the new XC9500 family with ing the next generation of programming and testing standards. UTOMATION

the industry’s best JTAG/ISP capabilities and is AME A spearheading the next generation of N These partners have strong strategic relationships with Xilinx and have ESIGN Computer

programming and testing standards. D

OMPANY

❞ EDA Zycad Tokyo Electron LimitedTrans EDA Limited ViewCADZuken 1.2 FLDL to XNF translator Fujitsu LSI Harmonix Corporation MINC Teradyne The Rockland Group Integrated Network Analysis Epsilon Design Systems ALPS LSI Technologies, Inc. Edway Design SystemsAptix Corporation Aptix Corporation Aster Ingenierie S.A. Chronology Corporation Synthesis/Simlulation Flynn Systems Probe 3.0 Accolade Design Automation C V CINA- Veribest ACEO Technology, Inc. Acugen Software, Inc.

EMERALD ◆ RUBY Alliance Program Categories: Diamond: a direct impact on our releases. Typically, Xilinx is directly involved in the development and testing of the interface to XACT RS6000 HP7 compliant with Texas Instrument to attract the attention of the CAEContinued tool from the Modules (TIM) specifications and are vendors. For many of these vendors,previous pagethis UN ✓✓ ✓✓

PLATFORMS supported by a library of common DSP conference was their first chance to talk functions. MiroTech has signed an OEM with the early adopters of reconfigurable ✓✓✓ ✓ ✓ ✓ ✓✓✓✓ PC S agreement with a major manufacturer of computing technology; it is certainly not DSP boards. inconceivable that some cooperative prod- NI IB uct development efforts will eventually ✓✓✓ ✓✓✓ ✓✓ ✓✓✓ ✓✓✓ ✓✓ ✓✓✓ ✓✓✓ ✓✓ ✓✓ ✓ ✓✓✓✓ ✓ ✓✓✓✓ ✓ ✓✓✓✓ ✓✓✓✓✓✓ ✓ ✓ ✓✓✓ ✓ ✓✓✓ ✓ ✓✓✓✓ ✓✓✓ ✓✓✓ ✓✓✓ ✓✓✓ L The remaining companies at the confer- result from this meeting. ence previewed products in development. K 5 9 ✓✓ ✓ ✓✓ ✓✓✓✓ K 7k 7k 7k 7k 7k 7k 7k 7k 7k 7k 7k 7k 7k 7k 7k 9k 9k 7k 7k 7k 7k enVia Inc. (Menlo Park, CA) is developing 7k,9k 7k,9k consumer telecommunications equipment that uses reconfigurable FPGAs to address 5200 7

XACT6 XACT6 7k XACT6 7k XACT6 7k the growing problem of incompatible / XC CPLD U K K

/3 wireless telecommunications standards. ✓✓✓ ✓ ✓✓ ✓✓✓✓ ✓ ✓✓✓✓ ✓✓ ✓✓✓ ✓✓ ✓✓✓✓ ✓ ✓✓✓ ✓✓✓ ✓✓ ✓✓✓ ✓✓✓✓ ✓✓✓✓ ✓✓ ✓ ✓ ✓✓ ✓✓ ✓✓ ✓✓ ✓✓ ✓ ✓✓ ✓ ✓ ✓✓✓ ✓ ✓ ✓ ✓✓✓✓ ✓ ✓✓✓ ✓✓ ✓✓ ✓ ✓✓ ✓✓ ✓✓ ✓✓✓✓ ✓✓✓✓ ✓ ✓✓✓✓✓✓✓✓✓✓✓✓ ✓✓✓ ✓✓✓ ✓✓✓ ✓✓✓✓ ✓✓✓✓ ✓✓ ✓✓✓✓ ✓ ✓✓ ✓ ✓✓ ✓✓ 4 K 2 Octree Corp. (Cupertino, CA) has imple- ❝this conference was their first mented 3D volume rendering systems onchance to talk with the early adopters of Annapolis Micro Systems and Giga Opera- tions platforms, and is developing productsreconfigurable computing technology; it is for both medical equipment and videocertain not inconceivable that some cooperative game manufacturers. Start-up Adaptive IT product development efforts will eventually

K CAD Technologies (Sunnyvale, CA) and In summary, reconfigurable computing consulting firm Memec Design Services result from this meeting.

ESIGN technology is continuing to ‘come of age,’ Xilinx Tool Kit XNF2MTV I/F Kit Xilinx interface XNF XD-1 Included Xilinx Design Kit included Xilinx Front End Xilinx Synthesis Lib. Call Xilinx Call Xilinx Call Xilinx Call Xilinx Call Xilinx Call Xilinx Call Xilinx Call OrCAD Call Xilinx Call Xilinx Call Xilinx Call Xilinx Xilinx Kit LCA-PP Xilinx Mapper Xilinx Design Kit Call Xilinx Call Xilinx Call Xilinx EDIF Interface Mapper Xilinx SYN-LCA D Included Xilinx Front End Call Xilinx Call Xilinx (Garden Valley, CA) also attended, and with several companies already garnering❞ are applying RC technology in some new revenue from a wide variety of RC-based application areas (but it’s too early to products, penetration of RC technology reveal them). into large, well-known electronic equip- Another encouraging sign was the ment manufacturers, and the attention presence of representatives from several of of leading design tool vendors. I’m the CAE companies in the Xilinx Alliance already looking forward to next Program. The enormous potential of year’s conference. reconfigurable computing is beginning UNCTION Timing Analysis Simulation Entry Schematic translator to VHDL XNF Included Schematic Entry/Sim Synthesis Synthesis Synthesis Schematic Entry Simulation Simulation Schematic Entry Schematic Entry Synthesis Synthesis, SimulationSchem/Sim/Synth Fitter XEPLD Synthesis Simulation, Timing Analysis Call Xilinx Schematic Entry Synthesis Synthesis Simulation Graphical Design Entry/Simulation/Debug Graphical Schematic Entry, Synthesis & Simulation F Schematic Entry & Simulation & HDL Editor Synthesis Synthesis Synthesis 44 SimulationSchematic Entry Topdown FPGA Synthesis Xilinx Front End

◆ 2.11 Simulation 5.31 5.02 ERSION 9504 1.05.02 Schematic Entry/Simulation V 4.4j (PC) Simulation 4.6a (WS)

Sharp-eyed readers may notice a slight change to the format of XCell in ALLIANCE-EDA COMPANIES & PRODUCTS-AUGUST 1996-1 OF 2 COMPANIES ALLIANCE-EDA AME

N this issue. The tables listing component availability, Xilinx software status, Alliance ROFESSIONALS

P partner information, and device programmer status have been moved from the “General Information” section to the last few pages of the newsletter. As a few RODUCT SHIZUE V-System/VHDL Silos IIIVanguard V-BAK 95.100 1.1 Voyager LM1200Modeler Hardware Xilinx Logic Module DesignBook 2.0 Design Entry Active-CAD 2.0 ASIC NavigatorX-Syn Entry Schematic Synplify 2.6a QSimThedaLOG/iC2 Simulation 4.0 4.2 Design ArchitectQuickSim IISimulate (Win)VST 386+ (DOS) B.x Capture (Win)SDT 386+ (DOS)PLD 386+ (DOS) B.x ABEL 6.10 1.2Synario 1.2 7.0 Simulation 2.0 Simulation FPGA ExpressProSynthesis ProSim 6.2 2.2 ProCapturePowerView 1.0 Synthesis 6.1 6.1 6.0 Schematic Entry Schem/Sim/Synth/Timing AnalLOG/iC Classic Call Xilinx 4.2 P ComposerQuickHDL 4.4 Schematic Entry B.x FPGA CompilerVSSDesign Compiler 3.4b 3.4b 3.4b Simulation Synplify-Lite 2.6a VerilogConceptFPGA Designer Synergy 2.4 2.1 2.3 FPGA Synthesis readers have suggested, this will make the tables easier to find as well as providing XILINX for better continuity for those who read the whole journal front-to-back. We are always interested in reader feedback. This issue includes a short reader survey on page 47. We would greatly appreciate if you would take a few minutes to fill out this questionnaire and mail or FAX it back to us. Alternatively, you can send

AME your comments directly to me via E-mail at [email protected]. We’re looking N forward to hearing from you.

OMPANY

Model Technology Design Corp.Summit HDL Visual Solutions Design TopDown 3.0 Protel Technology TechnologyQuad Design SimuCad Motive Sys & Tech Sophia Schematic Advanced 3.1 Server Schematic Entry/Client 4.3 Xilinx Interface IK Technology Co.IKOS Systems INCASES Engineering GmbH I (Synopsis Division) Capilano Computing Design WorksEscalade Exemplar Logic 3.1 Galileo 3.2 Synthesis/Timing Analysis Simulation C Aldec Compass Design Automation Mentor GraphicsOrCAD AutologicSynario Design Automation B.x Viewlogic Office WorkView 7.1.2/7.2 ISDATA Logic Modeling Corp.Model Smart Models Simulation Lib. In Smart Model Synopsys Inc. Synplicity, Cadence ◆

RUBY DIAMOND CUSTOMER SUCCESS STORIES PROGRAMMER SUPPORT FOR XILINX XC7300 CPLDS-AUGUST 1996

MANUFACTURER MODEL 7318 7336 7336Q 7354 7372 73108 73144 Videoconferencing with XC4000 FPGAs ADVANTECH PC-UPROG LABTOOL-48 V1.31A V1.31A V1.31A V1.31A V1.31A V1.31A GPT Video Systems (Maidenhead, ADVIN SYSTEMS PILOT-U40 10.84B 10.84B 10.84B 10.84B Berks, U.K.) designs and manufactures PILOT-U84 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B high-quality videoconferencing solutions B&C MICROSYSTEMS, INC. PROTEUS Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 under the brand name FOCUS. GPT Video after committing to custom silicon. Further- BP MICROSYSTEMS BP-1200 V3.15 V3.18 V3.15 V3.15 V3.15 V3.15 Systems is a long time user of Xilinx prod- more, this development route allowed beta BP-2100 V3.15 V3.18 V3.15 V3.15 V3.15 V3.15 6 ucts; its designers use FPGA technology to versions of the system to be shipped with DATAMAN DATAMAN-48 V1.30 V1.30 V1.30 V1.30 V1.30 V1.30 maintain the flexibility and rapid time-to- the FPGA solution before production vol- DATA I/O 2900 Aug-96 Aug-96 Aug-96 Aug-96 market required in the fast moving multi- umes of the ASIC were available, further 3900/AUTOSITE Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 media market. accelerating time-to-market. UNISITE Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 The flexibility of FPGA technology Three XC4010 FPGAs hold the majority DEUS EX MACHINA was evident in the design of the latest of the logic in the video processing mod- ENGINEERING XPGM V1.40 V1.40 V1.40 V1.40 V1.40 V1.40 FOCUS videoconferencing systems, where ule in the main codec design. Two of the E E TOOLS ALLMAX/ALLMAX+ V2.4U V2.4U V2.4U V2.4U V2.4U V2.4U XC4000 FPGAs share a common design and act as MEGAMAX V1.1E V1.1E V1.1E V1.1E V1.1E V1.1E video routers, passing CCIR601 digital ELAN 6000 APS 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96 video data from various input sources to HI-LO SYSTEMS RESEARCH ALL-03A V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 TM series FPGAs were used for both the desired outputs. Each device is de- ALL-07 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 prototyping and production applications. signed to route data in the form of an 8-bit ICE TECHNOLOGY LTD Micromaster 1000/E V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 During system proto- data bus, requiring two to be used for the Speedmaster 1000/E V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 typing, three 16-bit data in the CCIR601 format. Thus, Micromaster Lv V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 XC4013 one device handles the routing and control Speedmaster Lv V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 V1.1 devices of the luminance data, and the other LEAP ELECTRONICS LEAPER-10 V2.0 V2.0 V2.0 V2.0 V2.0 V2.0 V2.0 were handles the chrominance data. LP U4 V2.0 V2.0 V2.0 V2.0 V2.0 V2.0 V2.0 used to These two devices also perform the LOGICAL DEVICES ALLPRO-88 develop and task of overlaying the graphical user inter- ALLPRO-88XR test the function- face directly onto the video outputs. This ALLPRO-96 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 Chipmaster 2000 V2.4U V2.4U V2.4U V2.4U V2.4U V2.4U ality required for a includes a patented function that produces Chipmaster 6000 V1.31A V1.31A V1.31A V1.31A V1.31A V1.31A large ASIC device. Mean- semi-transparent video, allowing on-screen while, XC4010 FPGAs were text to be displayed in an easily-readable XPRO-1 73108.304 used to implement key data rout- format while not obscuring the live video MICROPROSS ROM9000 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96 ing and timing generation functions in beneath. The design makes specific use of MQP ELECTRONICS SYSTEM 2000 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 the production version of the video pro- the XC4000 architecture’s on-chip RAM PINMASTER 48 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 cessing module. capability to implement fast look-up tables. NEEDHAM’S ELECTRONICS EMP20 V3.10 V3.10 V3.10 V3.10 V3.1043 V3.10 An audio, video and data multiplexer The third XC4010 FPGA in the video SMS EXPERT 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96 design targeted for a semi-custom gate processing module is a timing generator, OPTIMA 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96 3Q96 array implementation was prototyped with providing all the timing functions for the STAG ECLIPSE 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 6.4.26 three XC4013 devices. The development various video field store read and write SUNRISE T-10 UDP Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 was carried out using Cadence Verilog operations. This FPGA also contains the software running on a Sun SparcStation. state machines that control the reading and T-10 ULC Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 SUNSHINE ELECTRONICS POWER-100 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 The FPGAs provided a fast and flexible writing of captured video images to and development route, culminating in a fully- from the graphics frame stores. EXPRO-60/80 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 functional ASIC on the first try. The ASIC The XC4010 designs were entered using SYSTEM GENERAL TURPRO-1/FX Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 device holds about 30,000 gates of logic, a combination of schematic capture and MULTI-APRO Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 TRIBAL MICROSYSTEMS Flex-700 V3.09 V3.09 V3.09 V3.09 V3.09 V3.09 with a 20 MHz system clock rate. Verifying ABEL hardware descriptions and verified TUP-300 V3.09 V3.09 V3.09 V3.09 V3.09 the design with the FPGAs saved signifi- with the ViewSim simulator, using a cant additional NRE costs and development PC-based Viewlogic environment. All TUP-400 V3.09 V3.09 V3.09 V3.09 V3.09 XELTEK SUPERPRO time that would have been incurred if three FPGAs are about 80% full and run SUPERPRO II 2.4B 2.4B 2.4B 2.4B changes to the design had been required at a system clock speed of 13.5 MHz, a SUPERPRO II/P 2.4B 2.4B 2.4B 2.4B XILINX HW-130 1.15 1.15 1.06 1.16 1.07 1.07 1.02

WHITE=changed since last issue PROGRAMMER SUPPORT FOR XILINX XC7200 CPLDS —AUGUST 1996

MANUFACTURER MODEL XC7236A XC7272A ADVANTECH PC-UPROG LabTool-48 V1.31A V1.31A ADVIN SYSTEMS Pilot-U40 10.84B 10.84B performance level that was easily reached Pilot-U84 10.84B 10.84B using timing constraints and automatic Video Systems, “The HardWire conversion B&C MICROSYSTEMS INC. Proteus Aug-96 Aug-96 placement and routing tools. went extremely well, with very GPTlittle engi- BP MICROSYSTEMS BP-1200 3.15 3.15 To further reduce hardware costs during neering effort required at all, and they BP-2100 3.15 3.15 volume production of the codecs, the XC4010 came in on time! In fact, it surprised us FPGA designs were frozen and converted into DATAMAN DATAMAN-48 V1.30 V1.30 how little engineering effort was needed.” 7 DATA I/O UniSite Aug-96 Aug-96 HardWire 2900 Aug-96 Aug-96 As noted by McCandless, “These video 3900 Aug-96 Aug-96 TM XC4310 devices. Since the Hard- interface designs were fairly complex, but Wire devices are pin and function compatible the FPGAs proved to be very flexible and AutoSite Aug-96 Aug-96 with the FPGAs that they replace, system easy to work with. The high level of inte- DEUS EX MACHINA ENGINEERING XPGM V1.40 V1.40 flexibility is maintained; the HardWire devices gration provided by the FPGA devices has E E TOOLS ALLMAX/ALLMAX+ V2.4U V2.4U can be replaced with newly-designed FPGAs helped to create the most user-friendly MEGAMAX V1.1E V1.1E if the design evolves at a later date. According graphical user interface in the video- ELAN DIGITAL SYSTEMS 6000 APS 3Q96 3Q96 to Richard McCandless, Project Leader at GPT conferencing industry.” HI-LO SYSTEMS RESEARCH All-03A V3.09 V3.09 ◆ All-07 V3.09 V3.09 ICE TECHNOLOGY LTD Micromaster 1000/E V1.1 V1.1 Speedmaster 1000/E V1.1 V1.1 Micromaster LV V1.1 V1.1

Speedmaster LV V1.1 V1.1 LEAP ELECTRONICS LEAPER-10 V2.0 V2.0 Video Processing With XC7300 CPLDs LP U4 V2.0 V2.0 LOGICAL DEVICES ALLPRO-88 ALLPRO-88XR BICOM, Inc., (Monroe, CT) is a provider of hard- ALLPROF-96 6.4.26 6.4.26 ware and software “building blocks” for developing a Chipmaster 2000 V2.4U V2.4U Chipmaster 6000 V1.31A V1.31A wide range of voice processing applications. BICOM’s products are used in the develop- passed two boards rather than one. XPRO-1 ment of systems for voice mail, interactive The design was entered and implemented on a PC MICROPROSS ROM9000 3Q96 3Q96 voice response, audiotex, dictation and call using OrCAD schematic entry tools. The com- MQP ELECTRONICS SYSTEM 2000 Aug-96 Aug-96 center management. plexity of the design (which included a mix of PIN-MASTER 48 Aug-96 Aug-96 The recent design of their new Gemini analog and digital technologies) and tight devel- series of high-density computer telephony opment schedules dictated the use of program- 42 NEEDHAM’S ELECTRONICS EMP20 V3.10 V3.10 SMS Expert 3Q96 3Q96 platforms required a high-performance CPLD to integrate mable devices with predictable performance and Optima 3Q96 3Q96 a variety of logic functions. With cost and ease-of-use good pin-locking capabilities. The XC7336 CPLD Multisyte 3Q96 3Q96 considerations in mind, the Xilinx fulfilled both these needs. Pinouts were pre- XC7300 assigned and maintained throughout multiple design STAG Eclipse 6.4.26 6.4.26 iterations. This allowed the designers to concentrate on SUNRISE ELECTRONICS T-10 UDP Aug-96 Aug-96 the more difficult architectural aspects of the design. T-10 ULC Aug-96 Aug-96 TM CPLD family was chosen. As first-time Xilinx users, BICOM engineers were SUNSHINE ELECTRONICS POWER-100 Aug-96 Aug-96 The voice processing board impressed with the level of technical support EXPRO-60/80 Aug-96 Aug-96 contains 14 XC7336 devices. provided by the Xilinx team. SYSTEM GENERAL TURPRO-1/FX Aug-96 Aug-96 The XC7336-5 CPLDs are used In summary, by MULTI-APRO Aug-96 Aug-96 to hold a variety of logic functions, in- using the TRIBAL MICROSYSTEMS TUP-300 V3.09 V3.09 TUP-400 V3.09 V3.09 cluding address decoders, state machines, I/O func- XC7300 CPLD tions and glue logic, with XC7336-15 CPLDs for the com- family, BICOM FLEX-700 V3.09 V3.09 plicated timing associated with engineers were XELTEK SUPERPRO SUPERPRO II 2.4B 2.4B the telecommunications channel. able to meet their If BICOM had used traditional performance needs, reduce design complexity and cost, SUPERPRO II/P 2.4B 2.4B PALs for these logic functions, and save valuable board space as well. XILINX HW-130 1.14 1.04 the design would have encom- WHITE=changed since last issue ◆ Note:The XC7236 and XC7272 columns have been eliminated Xilinx Helps Fund New Seiko-Epson Foundry 2.4B 2.4B 1.00 V1.16 6.5.10 6.5.10 Aug-96 Aug-96 Aug-96 Aug-96 V2.26H V2.26H XC17256L XC17128L Xilinx has announced its funding of our competitive position and allow us to SPROM.310 up to $300 million for the construction of a design products with ever higher densities 2.4B 2.4B 2.25 6.46 5.00 2.01 V2.7 V2.7 V1.16 V5.61 V3.10 3Q96 3Q96 3Q96 3Q96 6.5.10 6.5.10 V2.4U Aug-96 Aug-96 Aug-96 Aug-96 Aug-96

new semiconductor manufacturing facility. and faster performance, “ stated Xilinx Aug-96 Aug-96 Aug-96 V1.31A V2.26H V2.26H SPROM.310 XC17256D The facility will be built and operated by Chief Executive Officer Willem Roelandts. XC17128D Seiko-Epson Corp. in Sakata, Japan (about “Just as important, it will help us meet 2.4B 2.25 6.46 2.4B 5.00 2.01 3Q96 V1.16 3Q96 6.5.10 6.5.10 Aug-96 Aug-96 200 miles north of Tokyo). Xilinx will growing customer demand worldwide for Aug-96 Aug-96 Aug-96 XC1765L XC1718L 8 make incremental advance payments over our products into the next century.” SPROM.310 the next two and one-half years to help This investment agreement further 2.4B 2.25 6.46 2.4B 5.00 2.01 V2.7 V2.7 V5.61 V3.10 3Q96 3Q96 3Q96 3Q96 V1.16 3Q96 3Q96 V1.24 6.5.10 6.5.10 V2.4U Aug-96 Aug-96 finance construction of the facility. In strengthens the close relationship between Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 V1.31A V2.26H V2.26H XC1765D XC1718D XC1736D return, Xilinx will receive a specified num- Xilinx and Seiko-Epson; Seiko-Epson has SPROM.310 ber of wafers from the new line through been a supplier to Xilinx for more than a the year 2002. decade. Xilinx also will maintain its exist-

The new operation will manufacture 8" ing foundry partnerships with Yamaha, 5000 B wafers using advanced 0.35 to 0.25 micron Taiwan Semiconductor Manufacturing CLK-3100 EMP20 Expert CHIPMASTER 6000 SYSTEM 2000 CHIPMASTER 2000 ALLPRO-88 ALLPRO-88XR ALLPRO-96 MODEL MODEL 200 IQ-180 IQ-280 Uniwriter 40 TUP-400 SuperPRO SuperPRO II HW-112 POWER-100 TUP-300 XPRO-1 PIN-MASTER 48 ROM9000 Chipmaster 5000 Optima Multisyte Sprint Plus48 Quasar T-10 UDP T-10 ULC EXPRO-60/80 TURPRO-1 MULTI-APRO FLEX-700 SuperPRO II/P HW-130 ROM Eclipse ROM 3000 U TURPRO-1 F/X TURPRO-1 T/X APRO ALLPRO-40 CMOS technology. In time, these advanced Company (TSMC), United Microelectronics PROMS-AUGUST 1996 processes will enable the development of Corporation (UMC) and IC Works. As programmable logic devices with capacities reported in XCell #20, Xilinx owns a 25% reaching 500,000 gates. Production at the equity stake in a new foundry being con- facility is expected to begin in early 1998. structed by UMC in Taiwan and scheduled “We’re confident that our continuing to come on-line in the first half of 1997. ◆

partnership with Seiko-Epson will enhance S M MANUFACTURER LINK COMPUTER GRAPHICS LOGICAL DEVICES MQP ELECTRONICS NEEDHAM’S ELECTRONICS RED SQUARE XELTEK XILINX SUNSHINE TRIBAL MICROSYSTEMS S SUNRISE SYSTEM GENERAL MICRO PROSS STAG V1.40 V3.17 V3.17 V3.17 V3.17 V3.17 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 XC17256L New Data Book Now Available XC17128L

oth CD-ROM and printed versions of files) and its installer are included on the V2.0 V2.0 B 3.7Q V1.1E 3Q96 V1.30 V3.15 V3.15 V1.40 V3.17 V3.17 V3.17 V3.17 V3.17 V2.4U Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B XC17256D the new “Xilinx Programmable Logic Data CD-ROM. The main table of contents, XC17128D 41 Book” are now available. The material in chapter tables of contents and the index all the new data book also is available on include hypertext links to immediately V1.1E 3Q96 V1.30 V3.15 V3.15 V1.40 V3.17 V3.17 V3.17 V3.17 V3.17 V2.4U Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 XC1765L WebLINXTM, the Xilinx World jump to the appropriate pages in the book. XC1718L Wide Web site At 900 pages, the data book includes (www.xilinx.com), in the data sheets for the XC7300, XC9500, V2.0 V2.0 3.7Q V1.1E 3Q96 V1.30 V3.15 V3.15 V1.40 V3.17 V3.17 V3.17 V3.17 V3.17 V2.4U Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B Aug-96 10.84B Aug-96 Aug-96 XC1765D form of individual prod- XC3000A/L, XC3100A/L, XC4000E, XC1718D XC1736D uct specifications. XC4000EX/XL, XC5200, XC6200, and The CD-ROM, a first XC1700D device families. Product specifi- 0 with this edition, works cations for the older XC2000, XC3000, 0 0 0 2 1 1 2 - with PCs, Sun worksta- XC3100, and XC4000/A/H/D/L families are - P P Proteus-UP40 DATAMAN-48 LEAPER-10 ChipLab AutoSite 3900 PC-UPROG MODEL CP-1128 EP-1140 B XPGM 2900 PILOT-U28 PILOT-U32 PILOT-U40 PILOT-U84 PILOT-142 PILOT-143 PILOT-144 PILOT-U24 All-03A LABTOOL-48 PILOT-145 B 135H-FT/U MTK-1000 MTK-2000 MTK-4000 2700 ALLMAX/ALLMAX+ MEGAMAX 6000 APS All-07 Micromaster 1000/E Speedmaster 1000/E Speedmaster LV LP U4 3000-145 5000-145 Micromaster LV LV40 Portable tions, and HP worksta- not included, but are still available on UniSite tions. Detailed tables of WebLINX. The military/high-reliability and TM contents and the ability to search for HardWire product lines are overviewed, PROGRAMMER SUPPORT FOR XILINX XC1700 SERIAL keywords makes the CD-ROM a valuable but detailed product specifications are still tool. The entire data book resides in a found in separate, dedicated documents. single “.pdf” file. The Acrobat™ Reader To obtain a copy, contact your local program (that allows users to view .pdf Xilinx sales representative. ◆ E TOOLS LEAP ELECTRONICS ADVANTECH BP MICROSYSTEMS MANUFACTURER B&C MICROSYSTEMS INC. DATAMAN DEUS EX MACHINA DATA I/O ICE TECHNOLOGY LTD ADVIN HI-LO SYSTEMS RESEARCH BYTEK ELAN DIGITAL SYSTEMS WHITE=changed since last issue; 1736A, 1765 and 17128 columns eliminated issue What’s New on WebLINXTM Xilinx Home Page • www.xilinx.com

/ WebLINX was recently named ◆ Product Spotlights an Infoworld HotSite! Here are a few of Examine a showcase of our latest prod- OTES 9 EATURES Includes 502/550/380 & Foundry PC, Sun, HP kits now available PC, Customer w/v6.0 will receive v6.0.1 update Customer w/v6.0 will receive v6.0.1 update Includes PROSeries 6.1 Includes PROSeries 6.1 Incl PROSeries 6.1/PROsynth 5.02X and XC9500 Includes support for XC4000E and XC9500 Includes support for XC4000E and XC9500 Includes support for XC4000E and XC9500 Includes support for XC4000E lic agreement Initiator and target; Req signed Support for SDT+, VST+ v1.2 New version w/XC9500; First ship 4/29/96 version w/XC9500; First New Includes PRO Series 6.1 Includes PRO Series 6.1 with v5.2.1 and v6.0.1 N F the reasons why: ucts, currently featuring the XC4000EX and XC9500 device families and the ◆ TM Foundation Series software, with its 5.20 Includes DS-401 v5.2 5.20 Includes XC5200 X-BLOX Support 5.20 5.20 6.10 5.20 ELEASE

ERSION SmartSearch Agents Released REVIOUS 5.2/6.05.2/6.0 Now available on HP7 5.2/6.0 Includes 502/550/380 5.2/6.0 PC update by request only 5.2/6.0 R V P Come visit the industry-wide search en- easy-to-use, low-cost VHDL synthesis gine made specifically for topics involv- solution. AST PDT OMP ing programmable logic. You can create L 7/967/96 7/96 6.0 7/967/967/96 6.0 6.0 7/967/96 6.0 7/96 6.0 7/967/96 6.0 6.0 7/96 6.0 7/96 6.0 7/967/967/96 6.0 7/96 6.0 6.0 8/96 6.0 1.0 7/967/96 6.0 7/96 7/96 7/96 7/96 7/96 6.0 7/96 7/96 7/96 6.0 C your own agents to notify you by e-mail as material you want becomes available◆ On-Line Net Seminars in any of multiple sites on the web. In cooperation with Marshall Industries, 9.01 Xilinx holds live seminars on the

LATFORM Internet, complete with an on-line slide P X BY ◆ Xilinx Guided Tour and audio presentation and a live chat- 7.00 7.007.00 na 7.00 na na na Includes DS-401 v5.2 1.00 1.00 na na Sun and HP 5.2.1 5.2.1 5.2.1 5.2.1 5.2.15.2.1 5.2.1 5.2.1 5.2.1 5.2.1 response forum for asking questions.

ERSION Check out this on-line company and V product overview covering topics such Recordedas seminars on the XC5200 and Xilinx corporate and product strategies,XC9500 device families also are avail- URRENT 6.2 4.1. 7.007.00 7.00 7.001.101.10 1.10 na na 1.10 1.10 na na 1.10 na na lic agreement Target only; Req signed 6.007.00 6.0.1 7.00 7.00 na na 2.00 2.00 2.00 na na 6.016.11 5.2.1 5.2.1 PC1 SN2 HP7 U 6.0.16.0.16.0.1 5.2.1 5.2.1 5.2.1 5.2.1 5.2.1 5.2.1 6.0.1 6.0.1 6.0.1 6.0.1 6.0.1 6.0.1 6.0.1 6.0.16.0.1 5.2.16.0.1 6.0.1 5.2.1 6.0.1 6.0.1 6.0.1 6.0.1 6.0.1 6.0.1 6.0.1 C device selection, XACTstep able to review at your convenience. TM software ◆ solutions, quality assurance and Xilinx technical support services.

ART TECHNICAL TRAINING UPDATE P UMBER ILINX EFERENCE DS-391-xxx DS-VLS-BAS-PC1 DS-VLS-STD-PC1 DS-VLS-EXT-PC1 DS-VLS-ADV-PC1 DS-3PA-BAS-xxx DS-3PA-STD-xxx DS-3PA-ADV-xxx DS-FND-BAS-PC1 DS-FND-BSV-PC1 DS-FND-STD-PC1 DS-FND-STV-PC1 LC-DI-PCIS-C LC-DI-PCIM-C DS-371-xxx DS-380-xxx DS-MN8-ADV-xxx DS-OR-STD-PC1 DS-SY-STD-xxx DS-SY-ADV-xxx DS-VL-BAS-PC1 DS-VL-STD-xxx DS-VL-ADV-xxx DS-35-PC1 DS-401-xxx DS-CDN-STD-xxx DS-MN8-STD-xxx DS-EVAL-XXX-C DS-550-xxx DS-571-PC1 DS-560-xxx ES-VERILOG-xxx X R N 40 DS-344-xxx DS-390-PC1 DS-290-PC1 Both Schematic- and Synthesis-Based Classes Offered

Two basic classes are available from Xilinx, a schematic-based and a synthe- aries aries aries aries aries sis-based class. SUPPORT

Actually, both classes focus more on explaining and demonstrating the basic overall design methodologies for using concepts behind HDL-based design by

SILICON Xilinx devices, rather than the specific

XILINX RELEASED SOFTWARE STATUS-AUGUST 1996 STATUS-AUGUST XILINX RELEASED SOFTWARE examining many of the specific language RODUCT UNCTION Entry,Simulation,Lib, Optimizer Module Generator & Optimizer P F Core Implementation Entry/Simulation/Core Core + Interface Models & XNF Translator front-end tools. (The tutorials shipped with constructs that should be used when de- the development systems provide the XXXXX XXXXX signing with these tools. specific tool training for the new user.) All designers can benefit from taking The schematic-based class has traditionally XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX DS-OR-BAS-PC1 XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX one of these classes. Even designers al- 2K 3K 4K 5K 7K 9K utilized ViewLogic tools in the examples ready familiar with Xilinx technology can and labs. However, with the introduction learn some new methods to reduce design ESCRIPTION RODUCT of XACTstep version 6.0.1, the class has P D XC7K Support XC7K, XC9500 Support XC7K, XC9500 Support 8.4=A.4PROcapturePROsim Interface and Libraries Interface and Libr Interface and Libr time and increase device performance. been updated to use the Foundation Remember, either class (and even customized classes) can be presented right at your own facility. Please contact your local TM Sales office or our training registrar with ATEGORY RODUCT Development System and its front-end your needs. The latest schedule of classes Foundation Series Foundation Series LogiCore-PCI SlaveLogiCore-PCI Master X X Viewlogic/S Viewlogic/S Viewlogic/S Viewllogic/S 3rd Party Alliance 3rd Party Alliance Foundation Series Foundation Series Mentor OrCAD Synopsys Synopsys Viewlogic Viewlogic ViewlogicXABEL XBLOX Cadence Mentor Libr and Interface Evaluation CORE XEPLD XABEL-CPLD XACT-CPLD Mentor OrCADSynopsysViewlogic Viewlogic Libr and Interface Interface and Libr P C

: only, only, U= Update by request users by request E= Engineering software for in-warranty N=New Product, tools from Aldec. and contact information is always available EY E Verilog 2K,3K,4K,7K Libraries U 3rd Party Alliance

U OrCAD U Viewlogic The synthesis-based class uses the on WebLINX, our World Wide Web site K

KEY PR = Pre-release requiring in-warranty status or Product Marketing apporval status or Product Marketing requiring in-warranty PR = Pre-release XILINX PACKAGES XILINX

XILINX INDIVIDUAL PRODUCTS INDIVIDUAL XILINX Synopsys tools. The course goes beyond (www.xilinx.com).◆ AUGUST 1996 New Product earn about the newest Xilinx products and services through our extensive library of product literature. The most recent pieces are listed below. To order or to obtain a com- Literatureplete list of all available literature, please contact your local Xilinx sales◆ representative.

TITLE DESCRIPTION NUMBER XC7372 XC73108 XC73144 XC9536 XC95108 XC95216 PINS TYPE CODE XC4005L XC4010L XC4013L XC5202 XC5204 XC5206 XC5210 XC5215 XC7236A XC7272A XC7318 XC7336 XC7336Q XC7354

1996 Programmable Logic Data Book Technical Data 0010303 PLASTIC LCC PC44 ◆ ◆◆◆◆ ◆ L 1996 Programmable Logic Data Book on CD-ROMTechnical Data 500360 PLASTIC QFP PQ44 ◆◆◆ ◆◆ Product Overview Brochure Features & Benefits 0010130-05 44 PLASTIC VQFP VQ44 ◆ ◆◆◆ Software Selector Guide Features & Benefits 0010304 CERAMIC LCC WC44 10 FPGA Brochure Features & Benefits 0010305 48 PLASTIC DIP PD48 ◆◆◆ 64 PLASTIC VQFP VQ64 ◆◆◆ PLASTIC LCC PC68 68 UPCOMING EVENTS CERAMIC LCC ◆◆WC68 ◆◆◆◆ ◆ ◆◆ ◆ CERAMIC PGA PG68 ◆◆◆ PLASTIC LCC PC84 ◆ Look for Xilinx technical papers and/or product exhibits at these upcoming industry fo- rums. For further information about any of these conferences, please contact Kathleen 84 CERAMIC LCC WC84 ◆◆◆ ◆◆ ◆ Pizzo (Tel: 408-879-5377 FAX: 408-879-4676).◆ CERAMIC PGA PG84 ◆ CERAMIC QFP CQ100 ◆◆◆ PLASTIC PQFP PQ100 EuroDAC & EuroVHDLDSP World/ICSPAT Electronica Sept. 16-20 Oct. 8-10 Nov. 12-15 100 PLASTIC TQFP TQ100 Geneva, Switzerland Boston, MA Munich, Germany PLASTIC VQFP VQ100 ◆◆◆◆ International WorkshopSilicon Design Photonics East TOP BRZ. CQFP CB100 on Field ProgrammableConference Nov. 18-22 120 CERAMIC PGA PG120 ◆ Logic and ApplicationsOct. 9-10 Boston, Massachusetts ◆◆ 132 PLASTIC PGA PP132 Sept. 23-25 Birmingham, ◆◆◆◆ ◆◆ ◆◆ Darmstadt, Germany United Kingdom BIAS & DSP Italy CERAMIC PGA PG132 Nov. 26-29 PLASTIC TQFP TQ144 144 PCI Europe WESCON Milan, Italy CERAMIC PGA PG144 Oct. 1-2 Oct. 22-24 Paris, France Anaheim, California DSP UK 156 CERAMIC PGA PG156◆◆◆ Dec. 3-4 160 PLASTIC PQFP PQ160 DSP Germany DSP France London, United Kingdom CERAMIC QFP CQ164 ◆ Please note that the XC8100 family Oct. 1-2 Oct. 22-24 164 has been discontinued. TOP BRZ. CQFP CB164 Munich, Germany Paris, France ◆◆◆ ◆◆ PLASTIC PGA PP175 See page 13. 175 39 CERAMIC PGA PG175 ◆◆ 176 PLASTIC TQFP TQ176 ◆ 184 CERAMIC PGA PG184◆◆◆ ◆◆ 191 CERAMIC PGA PG191 196 TOP BRZ. CQFP CB196◆◆ FINANCIAL RESULTS PLASTIC PQFP PQ208 208 METAL MQFP MQ208 ◆ ◆ Quarterly Sales revenues rose to $150.2 million in growth. The bright spot was the North HI-PERF QFP HQ208 ◆ the first fiscal quarter of 1977 (ending June American distribution channel, which 223 CERAMIC PGA PG223 ◆ Revenue30, 1996), a 19% increase over the same grew 10% over the prior quarter.” 225 PLASTIC BGA BG225 quarter one year ago and a 0.3% increase The XC5000 FPGA family continued WINDOWED BGAWB225 Topsfrom the immediately preceding quarter. its torrid growth rate, with sales up 30% 228 TOP BRZ. CQFP CB228 “The June quarter was a difficult quarter over the previous quarter. Recently an- $150M PLASTIC PQFP PQ240 for the semiconductor industry,” noted nounced price cuts (see page 11) should 240 Xilinx Chief Executive Officer Willem even further expand the market for this METAL MQFP MQ240 Roelandts. “Although Xilinx was not cost-optimized FPGA family. HI-PERF QFP HQ240 immune to this widespread slowdown, we Xilinx stock is traded on the NASDAQ 299 CERAMIC PGA PG299 did experience minor sequential revenue exchange under stock symbol XLNX. 304 HI-PERF. QFP HQ304 352 PLASTIC BGA BG352 ◆ 411 CERAMIC PGA PG411 432 PLASTIC BGA BG432 ◆ = Product currently shipping or planned 499 CERAMIC PGA PG499 ❖ = New since last issue of XCELL 596 PLASTIC BGA BG596 (none appear in this issue) 38 596 499 432 411 352 304 299 240 228 225 223 208 196 191 184 176 175 164 160 156 144 132 120 100 84 68 64 48 44 PINS PLASTIC BGA PG499 CERAMIC PGA PLASTIC BGA PG411 CERAMIC PGA PLASTIC BGA HI-PERF PG299 CERAMIC PGA HI-PERF QFP METAL MQFP PLASTIC PQFP CB228 TOP BRZ. CQFP BGA WINDOWED PLASTIC BGA PG223 CERAMIC PGA HI-PERF QFP METAL MQFP PLASTIC PQFP CB196 TOP BRZ. CQFP PG191 CERAMIC PGA PG184 CERAMIC PGA PLASTIC PG175 PP175 CERAMIC PGA PLASTIC PGA CB164 TOP BRZ. CQFP CERAMIC QFP PLASTIC PQFP PG156 CERAMIC PGA PG144 CERAMIC PGA PLASTIC PG132 PP132 CERAMIC PGA PLASTIC PGA PG120 CERAMIC PGA CB100 TOP BRZ. CQFP PLASTIC VQFP PLASTIC PLASTIC PQFP CERAMIC QFP PG84 CERAMIC PGA CERAMIC LCC PLASTIC LCC PG68 CERAMIC PGA CERAMIC LCC PLASTIC LCC PLASTIC VQFP PLASTIC DIP CERAMIC LCC PLASTIC VQFP PLASTIC QFP PLASTIC LCC F HQ304 . QFP TQFP TQFP TQFP TYPE TQ176 TQ144 TQ100 WB225 BG596 BG432 BG352 HQ240 MQ240 PQ240 BG225 HQ208 MQ208 PQ208 CQ164 PQ160 VQ100 PQ100 CQ100 WC84 PC84 WC68 PC68 VQ64 PD48 WC44 VQ44 PQ44 PC44 CODE

◆◆◆ ◆◆◆ ◆◆◆ ◆◆ ◆◆ ◆◆◆ ◆◆◆ ◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆ ◆◆ XC3020A ◆◆ ◆◆ ◆ ◆◆ ◆◆ ◆ ◆◆ ◆◆ XC3030A ◆◆◆ ◆◆ ◆◆ ◆◆◆◆◆ ◆◆◆ ◆◆ ◆◆ XC3042A COMPONENT AVAILABILITYCHART ◆◆◆◆ ◆◆ XC3064A ◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆ XC3090A XC3020L XC3030L XC3042L XC3064L XC3090L XC3142L XC3190L XC3120A ◆◆ XC3130A XC3142A XC3164A XC3190A ◆ XC3195A ◆ ◆ ◆◆ ◆◆◆◆◆ XC4003E ◆◆◆◆◆ ◆◆◆◆◆ ◆◆ ◆◆ XC4005E XC4006E ◆◆ XC4008E ◆◆ XC4010E ◆◆◆◆ ◆ ◆◆◆ ◆ ◆◆ XC4013E XC4020E ◆◆◆ ◆◆ XC4025E ◆ XC4028EX ◆◆◆ ◆◆◆ XC4036EX XC4044EX ◆◆ XC4052XL ◆ XC4062XL ary scan logic for increased testability, and signment flexibility, dedicated JTAG bound- maximizes overall utilization and pin as- such as the VersaRing 23,000 usable gates and robust features, -5 speed grade performance improvement over the -3 speed-grade that offers up to a 30% metal technology, the result is a new shrink from 0.6µm to 0.5µm triple-layer combined with a semiconductor process been added to the XC5200 family. When patented charge-pump transistor design has low component costs. array die sizes — lead to correspondingly some cases even approaching today’s gate tectures. The family’s small die sizes — in technological advantage over other archi- the XC5200 FPGA family has a significant micron, triple-layer metal (TLM) process, and an architecture optimized for its sub- With its segmented interconnect structure are being passed on directly to our users. significant cost advantages; these savings a shift to 0.5 µ process have resulted in pace. The rapid increase in shipments and ments for the XC5200 FPGA family, further price reductions and performance improve- Performance Improved by 30% Prices Reduced by up to 50% Lower Prices & Higher Performance XC5200 Family: PRODUCT INFORMATION-COMPONENTS The XC5200 family delivers 2,000 to In addition to price reductions, a XC5200 sales have risen at a record X ilinx recently announced significant (see table). TM I/O interface that year from now. volume pricing and projected one gate programmable logic solution. ues to lead the industry as lowest cost/ functions. The XC5200 FPGA family contin- fast carry logic for high speed arithmetic most cost-effective FPGA family. advancing its position as the industry’s * Plastic package, -6 speed grade, 25,000 unit quantity, U.S. direct pricing only The chart below shows current high- 6BtAdr2 s15 ns 9 20 ns ns 6 ns MHz 65 50 MHz MHz 50 13 ns 8 ns 16-Bit Up/Down Counter 39 MHz Adder 16-Bit 16-to-1 Multiplexer 24-Bit Accumulator Decoder 16-Bit C2523K 16K 10K XC5215 6K XC5210 3K XC5206 XC5204 XC5202 D EVICE L M OGIC AXIMUM XC5200 Performance Benchmarks G XC5200 Family Volume Pricing* ATES C205XC5210-3 XC5210-5 ◆ E ND $47.00 $27.00 $17.00 $10.00 $5.00

OF 1996

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○ % Improvement $33.00 $18.00 $12.00 2H97 30% 25% 31% 28% 25% $8.00 $4.50 R 11 XC7300 CPLDs & XABEL-CPLD: The Industry’s After running Fncsim -o Synopsys he combination of ultra-low-cost signaling levels and 100% PCI compliance Q(use original schematic) on a 44-pin XC7300 CPLDs and easy-to-use provide support for the newest CPUs and design that contains X-BLOX How can I prevent FPGA XABEL-CPLD development software pro- high-performance memories. components, I see no-connect Compiler from writing my vides users withT the best value in program- 44-pin CPLDs also have proven ex- symbols on certain pins in the Qtiming constraints into the mable logic. Three XC7300 family members tremely adept at fixing “ broken” ASICs. simulation schematic. What’s .sxnf file? are now available in 44-pin PLCC, PQFP or ASIC users are discovering that 44-pin happening? VQFP packages — the XC7336, XC7336Q CPLD solutions can be used to safeguard and XC7354 devices. or repair ASIC functionality. Sometimes During its optimization process, These no-connects will appear in theSynopsys’ FPGA Compiler attempts to Xilinx 44-pin XC7300 CPLDs provide a fixed-function ASICs can be rendered simulation schematic any place where two greater range of performance and signifi- “unusable” by specification changes, pro- meet the timing constraints issued by you; pin vertices are laying on top of each and subsequently writes out the timing cantly lower costs than PALs and GALs. In cess variations that disrupt system timing other. In the original schematic, the pins fact, the logic from several PAL /GAL de- or design errors. Planning ahead by reserv- constraints into the netlist (.sxnf) file for would be connected by a zero-length net.the Xilinx tools to use. You may want to vices can be integrated into a single ing board space for a small form factor, 44- In the simulation schematic, however, the XC7300 CPLD at a lower device cost than pin CPLD can provide ASIC designers with issue these constraints to the Xilinx tools 12 coincident pins will not be connected in a separate constraints file, where you the replaced PALs/GALs (and sometimes at “system insurance.” The CPLD can be used (hence, the no-connect symbol). a component cost equivalent to a single to implement control circuitry or correct have the ablility to be more specific about The best fix for this problem is to goparticular paths that you want to constrain. high-speed PAL). The XC7300 CPLDs also sensitive timing paths. In this way, the back to the original schematic and move can replace TTL bus drivers, further reduc- flexibility to fix unwanted surprises is built- To do this, issue the following any coincident vertices apart, so that thecommand just prior to writing out the ing component count and cost. Advanced in to the design. net between them may be seen. system features such as 3.3V or 5V I/O .sxnf file:

xnfout_constraints_per_ endpoint = 0

This will result in a netlist (.sxnf) that does not contain any timing constraints. 37 XC7336 XC7336Q XC7354 BENEFITS You may then issue XACT Performance 22V10 equiv. 335lower inventory & production costs constraints in a .cst which will be used by 16V8 equiv. 446 the Xilinx tools. For more information on macrocells 36 36 54 XACT Performance, see the Development Systems Reference Guide. usable gates 800 800 1500 ◆ t PD 5.0 ns 10 ns 7.5 ns XC7336-world’s fastest CPLD I CC(typ.) 126 mA 50 mA 140 mA Significant power savings over multiple PALs/GALs 3.3V/5V I/O Y Y Y Interface with high performance memories and MPUs 24 mA high drive I/O Y Y Y PCI Bus compliance packages PC44, PC44, PC44 VQ44 53% smaller than PC44 PQ44 PQ44, VQ44

Push-Button Software Gets the Job Done

Low-cost XABEL-CPLD software obso- The combination of highly-capable, letes all PAL/GAL and low-end CPLD tools low-cost silicon and software makes Xilinx and provides push-button ease of use. 44-pin CPLD solutions the best choice in a Based on ABEL 6.0, XABEL-CPLD offers world where product development sched- instant productivity enhancement to all ules and system component budgets are PAL/GAL users and makes the migration to shrinking at an ever-accelerating pace. higher-density, cost-effective CPLD technology quick and easy. continued TECHNICAL QUESTIONS & ANSWERS Best 44-Pin PLD Value Mentor Graphics I have an Autologic design that, While compiling my AutologicQduring Men2XNF8, gives me the FEATURES BENEFITS Qdesign through Timsim8, following error in EDIF2XNF: Familiar Data I/O ABEL, Windows-based environ- Push button design flow improves productivity PLD_DVE_BA returns the Error: 5 No direction/pintype ment for design entry, simulation and fitting following warning, that may repeat for port:PINBALL/WIZARD Industry-standard-ABEL- HDL supports state ABEL-HDL familiar to PAL users, optimized several times: machines, high level logic descriptions, truth for PAL and CPLD development What’s happening and how tables and equation entry # WARNING: Unknown design can I fix this? Hierarchical design entry and JEDEC file Enables reuse of existing PAL codes, object: /JE/I1101S$37$5 conversion for integration of existing PAL designs simplifying design effort The pin in question does not have a What does this mean and how into Xilinx CPLDs can I fix it? PINTYPE property associated with it. The Functional simulation with graphical Waveform Facilitate rapid design verification PINTYPE property indicates a pin’s direction- Viewer and Static Timing Reports ality, and is required in XACT 5.x by Autologic may write out percent signs Advanced XACTstep v6 XC7K & XC9K fitter with auto- Fitter’s architecture-specific knowledge frees EDIF2XNF and XNFMerge. Autologic may (%) in its instance names. Although this is omatic device selection, multiple pass optimization, the user to focus on design functionality omit PINTYPE properties when synthesizing legal in Mentor schematics, it is not legal in partitioning and mapping, and timing driven fitting 13 hierarchical symbols, following the rules of Xilinx netlists. To remedy this, EDIF2XNF Animated tutorial and on-line help Reduces learning curve: pre-XACT 5.0 software. • tutorial leads users through entire changes each “%” in a netlist to “$37$” (so If the offending symbol was created by design process in minutes used because 37 is the ASCII code for the - extensive on-line help places all Autologic II, a patch is available on Mentor percent sign). Unfortunately, the Mentor Graphics’ FTP site at supportnet.mentorg.com documentation a mouse-click away back-annotation file is written with this (137.202.128.4). ◆ change, so that I1101S$37$5 in the MBA Autologic II version A.x requires Patch file does not match up with the true 244, located in the directory: I1101S%5 in the schematic. The problem may be fixed by modify- ANNOUNCEMENT ing the mbapp.nawk script, which processes the MBA file for use in PLD_DVE_BA, to change the $37$’s back /pub/patches/release_A/ XC8100 FPGA Product Family is Discontinued 36 to %’s. For more information, send E-mail autologic2 to [email protected] with send 618 in iting the strong market succcess of the subject line. Once this modification withis the filenames: C SRAM and FLASH technologies, Xilinx this difficult technology,” stated Xilinx CEO made, Timsim8 should run smoothly. README_P244 Wim Roelandts. (patch information) announced on Aug. 31, 1996, that it will discontinue the XC8100 “But, compared to SRAM development, INSTALL_P244 TM (installation instructions) family of one- there are very few people working in sg_p244.sss.tar.Z time programmable antifuse FPGA devices. antifuse. As a result, antifuse will lag be- (SunOS 4.x) The XC8100 family, first introduced last hind SRAM, entail dispro- sg_p244.ss5.tar.Z autumn, was just entering production. portionately large develop- (Solaris 2.x) No layoffs or reductions in R&D spend- ment costs, and be sg_p244.hpu.tar.Z ing are associated with this decision. Xilinx relegated to limited mar- ❝ to (HP-UX) employees involved with antifuse develop- kets. For these reasons we compared ment are taking on new duties in other believe further investmentSRAM development, there are areas of the company. Resources and in antifuse product devel- Autologic II version B.x requires Patch very few people working in 320, located in the directory: research and development spending are opment are too large to be /pub/patches/release_B/ being redirected to focus more effectively justified.” antifuse. As a result, antifuse autologic2 on SRAM-based FPGAs, CPLDs and new A number of options are opportunities more closely aligned with available to supportwill current lag behind SRAM, entail those products, such as LogiCore modules. XC8100 users, includingdisproportionately large with the filenames: “The XC8100 team successfully developed assistance in moving de- README_P320 a number of patented, industry-first innova- signs to other pin-compat-development costs, and be (patch information) tions in antifuse architecture, design, pro- ible Xilinx devices, software INSTALL_P320 relegated to limited markets. (installation instructions) gramming and processes — accomplishments upgrades to support other sg_p320.sss.tar.Z no one else in the entire semiconductor programmable logic products and refunds (SunOS 4.x) industry has been able to achieve so far with for XACTstep ❞ sg_p320.ss5.tar.Z (Solaris 2.x) sg_p320.hpu.tar.Z (HP-UX) TM 8000 software.◆ The XC4000EX family elevates the Xilinx has started sample shipments of XC4000EX XC4000Family series to newFPGAs heights in density Enteringthe first two members Production of the high-density and performance, with up to 125,000 logicXC4000EX family. The XC4036EX, with a gates and 66 MHz system speeds.typical gate range of 22,000 to 65,000 Increased On-Line Technical Information Designed “from the ground up”gates, and the XC4028EX, with a typical for speed and density using agate range of 18,000 to 50,000 gates, will The Xilinx BBS mirrored on the World Wide Web. deep-submicron, triple-layer- enter volume production in the fourth Xilinx Bulletin Board Service files and resources can now be accessed through the metal process, the XC4000EX quarter of this year. Xilinx Internet FTP site. family has abundant routing The next member of the family to be resources for high utilization andintroduced is the XC4062XL, featuring a Xilinx offers increased on-line support resources and choices. buffered interconnect to providetypical gate range of 40,000 to 130,000 In the coming months, keep an eye on the Xilinx Technical Support resources on maximum performance. (See gates. The XC4062XL will begin sampling WebLINX, the Xilinx web site (www.xilinx.com). In addition to the above mentioned BBS XCell #20, page 21.) in December. resources, you will see increased access to applications materials, product support materials, and commonly asked questions and solutions. 14 ◆

TECHNICAL SUPPORT RESOURCES Faster XC4000E FPGAs Now Available HOTLINE SUPPORT, U.S. HOTLINE SUPPORT, EUROPE

ontinuing process improvements havemum chip-to-chip system speeds of the Customer Support Hotline: UK, London Office C telephone: (44) 1932 820821 led to the release of a new, faster speedXC4000 and XC4000E devices for their 800-255-7778 fax: (44) 1932 828522 grade for XC4000E available speed grades. Hrs: 8:00 a.m.-5:00 p.m. Pacific time Bulletin Board Service: (44) 1932 333540 TM FPGAs, available now The XC4000 series (i.e., the XC4000, e-mail: [email protected] for every member of the device family. XC4000E and XC4000EX families) incorpo- Customer Support Fax Number:France, Paris Office The new -2 speed grade achieves a rates the world’s most widely used FPGA 408-879-4442 telephone: (33) 1 3463 0100 15-20 percent performance improvement fax: (33) 1 3463 0959 35 architecture with advanced features such as Avail: 24 hrs/day-7 days/week over the -3 speed grade as a result of a e-mail: [email protected] Select-RAM logic block propagation time (T Germany, Munich Office E-mail Address: telephone: (49) 89 991 54930 ) of 1.6 TM memory, wide edge decod- ILO [email protected] fax: (49) 89 904 4748 ns, clock-to-output delays (T ) of underers, internal three-state buffers and multiple e-mail: [email protected] OKPOF 5 ns and global-clock-to-out, pin-to-pin global clock distribution networks. The Customer Service*: Japan, Tokyo Office delays (T high performance levels offered from the telephone: (81) 3 3297 9163 ) ranging from 8.7 ns for the 408-559-7778, ask for customer service ICKOF -2 speed grade, when combined with these fax: (81) 3 3297 0067 * Call for software updates, authorization XC4003E to 10.7 ns for the XC4025E . Seeleading-edge architectural features, further e-mail: [email protected] codes, documentation updates, etc. Figure 1 for a comparison of the maxi-extends the range of possible applications for these popular devices. For example, the capabilities of the Figure 1: Speed Grade Comparisons for XC4000 and XC4000EXC4000E-2 device enable the delivery of the LogiCore X-TALK: The Xilinx Network of Electronic Services 70 MHz 65 MHz 60 MHz 56 TM PCI Initiator module — • Xilinx home page on the World Wide Web ...... www.xilinx.com. 50 MHz MHz an implementation that requires extremely • Electronic Technical Bulletin Board (U.S.) ...... 408-559-9327 • XDOCS E-mail document server- 38 40 high performance levels, especially for 40 MHz 32 MHz send an E-mail to [email protected] with ‘help’ as the only item in the subject header. MHz FIFO buffer and registered I/O operations You will automatically receive full instructions via E-mail. 30 MHz 27 MHz (see page 17). MHz • XFACTS fax document server ...... available by calling 408-879-4400. 20 MHz For further technical information, E-mail addresses for questions related to specific applications: 10 MHz please refer to the product specifica- Digital Signal Processing applications...... [email protected]

PRODUCT INFORMATION-DEVELOPMENT SYSTEMS New Technical Support Choices ○○○○○○○○ Synopsys Introduces Callers to the Technical Support Hotline munications system that allows better access at the Xilinx headquarters in San Jose now to the resources and solutions needed to encounter a friendly, ease-to-use telecom- ensure design progress and success. FPGA Express Efficient and Speedy Access to Engineers on the New Logic Synthesis Tool Targets Xilinx FPGA Families Hotline Through Increased Choices Xilinx Alliance member Synopsys Compiler). FPGA Express was designed We are continuously investing in state- unveiled its first entry into the Win95/ “from the ground up” with PC users of-the-art customer support systems to Windows NT market at the Design Automa- specifically in mind. provide customers with choices, efficient tion Conference in Las Vegas on June 3. The Xilinx/Synopsys relationship was access to support resources and reliable “FPGA Express” is a PC-based FPGA key in the development of this product. connections. “This is an excellent example of Xilinx and When contacting the Technical and one of its Alliance partners working to- the support process. Once the telecommu- Applications Support Hotline in San Jose, gether to meet user requirements with a nications system receives your ID number, you will be prompted to input the purpose quality product,” noted Wallace Westfeldt, you will skip directly to a menu of topics of your inquiry to ensure that you reach the manager of the Xilinx Alliance program. to choose from so that your call can be most appropriate person as soon as pos- Xilinx supplied architectural information routed to the most helpful resource or sible. In addition, you will be asked to and assisted in the market research, defini- 15 qualified support engineer available. provide your “personal ID number” or your tion and development of FPGA Express. Cases opened under your ID number “case ID number.” As a result, FPGA Express makes optimum are tracked under your name. If your col- Anytime during the process, you can use of Xilinx device features to maximize leagues wish to contact Xilinx, advise them bypass the automated inquiries to speak density and performance. For example, it Whatthat is they my cancase receive ID number? their own personal ID directly with a live support representative includes an automatic module generator numbers by calling the hotline directly. 34 or leave a voicemail message for a support Each time you call with a new support that can infer various operations within the engineer. need, a case ID number will be assigned HDL source, such as adders, comparators and communicated to you by a support and multipliers, as professional. If you have further need to synthesis tool for leading FPGA architec- well as automati- contact the hotline regarding an open case, tures. The first version has Xilinx XC3000 cally build the you can speed your access to your case family, XC4000 series and XC5200 family circuits using the worker by inputting the case number di- support. It is scheduled for production dedicated carry rectly into the telecommunications system. What is my shipment in September. Later versions will logic in the personal ID support the XC9500 CPLD family, as well as XC4000 series and number? other programmable logic vendors. XC5200 family What is the fastest way to reach an FPGA Express is unique in its knowl- architectures. ❝FPGA Express is The first time engineer with a new question? edge of Xilinx architectures and tools, FPGA Express you contact the allowing designers who are new to HDL to also uniquemakes full in its knowledge of Xilinx Xilinx hotline, On a typical day, the fastest path to get high-quality results. The expert user use of complex your personal ID reach a support engineer is through the will find the sophisticated controls needed I/O structuresarchitectures present in and the Xilinx tools, allowing telecommunications system using your number will be to work with very challenging designs. devices,designers including whothe clock are enable new feature to HDL to assigned by our personal ID number: FPGA Express is not a rewrite of of the XC4000E IOB registers. Global clock customer case • Select your situation: New Case or FPGA Compiler, although for compatibility buffers areget assigned high-quality based on an intelli-results.❞ management sys- Existing Open Case. it uses the same VHDL and Verilog com- gent algorithm that allocates the available tem. On subse- piler technology as Synopsys’ workstation buffers based on clock signal fanout while quent calls, you • Enter your Personal ID or the Open tools (Design Compiler and FPGA may use this num- Case ID ber to speed up • For a new case, you will be prompted to select a product topic area. • Your call is directed to the most appropriate available resource.

R Continued on the next page PHOTO FOR ILLUSTRATION PURPOSES ONLY filtering out gated clocks. If desired, usersconstraints that directly translates to the can specify specific input pins that needXACT to step TIMESPEC format. All netlist and New, Independent E-Mail User Group be connected to a global buffer. constraint translation is done by FPGA Synopsys revised the mapping and Express, eliminating the need for external Dedicated to Xilinx Technology Continued from the previous pageoptimization algorithms to provide all HDLtranslators. The tool outputs Unified Library users with the best possible synthesis XNF with group TIMESPECS. The result is results for area, performance and predict-a “plug & play” interface between FPGA XUMA: Xilinx User MAiling list FPGA ability. Testing has shown that FPGA Ex-Express and the XACTstep tools (v6.0.x Express press can improve area and performanceand beyond). by up to 25% over existing PC-based syn- Alain Arnaud of ECLA, Inc. (Newton,signing with a range of Xilinx parts and is thesis tools. Run times are excellent — a Massachusetts), a design consultant andup-to-date on Xilinx products. 3,000-gate design compiled in under a experienced FPGA and ASIC designer, wasXUMA is completely independent fromRemember, Xilinx users Pricing and Availability pondering how to best field his customers’Xilinx, Inc. Many engineers want an inde- minute and a 20,000-gate design required can contact the Xilinx approximately 10 minutes using a Pentium-Sold by Synopsys, FPGA Express starts questions — a mix that included both pendent technical forum for openly dis-Technical Support Hotline class computer. at $12,000 (one HDL language and support system-level and FPGA-level issues. To cuss key concerns and issues, both at the Xilinx also collaborated with Synopsysfor one FPGA vendor). It will be available assist in this task, Alain started an e-mailsystem- and device-level, and get objective(see page 35) with to integrate FPGA Express into the in full production in September, running address list of colleagues and industry answers from others in their professionaltechnical questions on XACTstep on Windows 95 and Windows NT-based contacts. This effort has grown into XUMAcommunity. — the Xilinx User MAiling List — a new, Xilinx products. personal computers. ◆ For more information about FPGA independent forum for the communication Express contact Bruce Jorgens, Prod- of technical subjects across the Xilinx user community. XUMA, initiated in May,1996, TM system. FPGA Express uses auct Line Manager for FPGA Products currently has over 250 subscribers and is sophisticated constraint-entry GUI, with atan Synopsys 415-528-4955. growing rapidly. “XACTstep-like” from/to syntax for timing 16 ◆ XUMA mailings are e-mails of technical TO: [email protected] questions and answers sent to Alain by anybody and forwarded to everyone on CC: the XUMA mailing list. TOPIC: Xilinx mailing list Xilinx users can subscribe to the list, unsubscribe from the list or submit a MESSAGE: Alain -- please add my name to the XUMA change of address by sending mail to: list for Xilinx technical issues. 33

[email protected]

To send a technical question, answer or related information to the list, mail it to: FPGA Express provides a smooth interface to other Xilinx FPGA [email protected] development tools Mention in your mail if you would like TO: [email protected] to remain anonymous. Alain sends out digests of messages sent to him about CC: twice each week. XC4000 Series tip XUMA is more focused than the TOPIC: “comp.arch.fpga” news group (see XCell MESSAGE: #21, page 41). Comp.arch.fpga is a general Alain -- I think I have discovered a way to use an XC4025E as a barrier to FPGA forum that typically deals with protect my desk from the harmful broad-based questions and issues, while effects of excess moisture building up XUMA is dedicated to trading technical on the bottom of my coffee mug. information regarding Xilinx devices and software. As a result, it takes less time to review XUMA digests for pertinent information. Furthermore, Alain is actively de- XACTstep and Alternate LogiCoreTM PCI Intitiator Debuts Operating Systems Xilinx recently announced the deliveryin XC4013-2 FPGAs. These devices operate of its second, 100% compliant PCI core,at 33 MHz and include high-speed burst the LogiCore synchronous FIFOs. The modules can be he Xilinx XACTTMstep development the Sun-based version for the Sun OS. How- TM PCI “Master” (Initiator/ T customized to fit individual design require- system software is available for both work- ever, with some exceptions as detailed Target) module. Previously, the LogiCore ments, resulting in a cost-effective, single- station and PC platforms. The PC-based below, XACTstep software can run on some PCI “Slave” (Target only) module could chip solution. version is designed for Windows 3.1, and variants of these popular operating systems. only perform slave functions. With the new The LogiCore PCI Master module (LC- module, a user can now complete a master DI-PCIM-C) for Xilinx FPGA and HardWire interface design in which the Master mod- devices, complete with a data sheet, com- ule acts as a controller for the PCI bus. prehensive user guide and PCI Systems Running XACTstep v6.0.1 in Windows 95 The implementation of critical paths in the Architecture textbook, is available for core are pre-defined to ensure PCI compli- • The Hardware Debugger does not run. designing with Viewlogic schematics, The majority of the XACTstep 6.0.1 ance. As a result, designers can reduce There is no known workaround. VHDL and Verilog for $8,995. The PCI software will run in Windows 95. However, design risk and cut development time by at there are some known compatibility issues: Slave module (LC-DI-PCIS-C) is available • The ProSeries software does not run least nine months. for $4,995. under Windows 95. WorkView Office is The new -2 speed grade for the • The Design Manager will cause a For further information about the available on an as-needed basis. Contact XC4013E FPGA enables the delivery of the General Protection fault when it is LogiCore PCI Interface or other mod- the Xilinx Technical Hotline for more PCI Master module, which requires a high closed. This causes no system problems ules in the program, please contact information. level of design complexity and perfor- and can be ignored. your local Xilinx representative or mance (see article about -2 speed grade on visit the LogiCore section of the page 14). The LogiCore PCI modules were WebLINX World Wide Web site. closely developed with beta users who 17 Running XACTstep v5.2.1 in Windows NT have successfully implemented the design

The XACTstep v6.0.1 GUI tools (DM,tion of RAINPORT.EXE, available in the Floorplanner, Prom File Formatter, Hard-SWHLP\XACTFPGA directory of the Bulle- ◆ ware Debugger) will not run in Windowstin Board Service (BBS). This program fixes 32 NT, but the v5.2.1 executables can be parallel port access problems that occur made to run in a DOS box with the addi-when the security key is checked.

Solaris Support for XACTstep v5.2.1 Install problem, a script called cdi.csh has Foundation Series Enjoys Successful Introduction been developed that will install the soft-

Although not officially supported and ware in a non-graphical mode. This script TM The number of Foundation implementa- tested by Xilinx, most of the XACTstep can be found on the Xilinx BBS (408-559- the Xilinx XACTstep SeriesTM users has been growing tionrapidly tools, it includes an HDL editor, tools work with Solaris 2.5. The XChecker 9327) and on the Xilinx FPT site since the inaugural release of thissynthesis fully compiler, schematic editor program, which did not work with Solaris (xilinx.com). Unfortunately, the Xilinx- ❝ has integrated PLD design software pack-and simulator. Xilinx version 2.4, will run under 2.5 when the Mentor Graphics interface (DS-344) does age in 2Q96. User feedback has beenXilinx has added more features SunOS 4.1.3 backwards-compatibility op- not work under Solaris, so Mentor Graph- added more features extremely positive, especially regardingto the Foundation packages in the tion is used. However, the Install ics’ users should stay with SunOS 4.1.X. the ease-of-use resulting from thev6.0.1 tight release, which is now ship- to the Foundation program still does not work in integration of all the design tools.ping. Features in this release include Solaris. As a workaround to the There also has been high praise supportfor the for the latest Xilinx device packages in the ◆ HDL Wizard, including the HDL families:Editor, the XC9500 CPLDs and v6.0.1 release, which with color coding, and the LanguageXC4000E FPGAs. Both device fami- Assistant, with templates for easylies and are integrated into the easy-to- is now shipping.❞ quick coding of VHDL and ABEL-HDL.use, shrink-wrapped solution, mak- The Foundation Series developmenting it simple to access and convert designs tools for FPGA and CPLD designfor in- these new families. All users who pur- clude a highly integrated set of Win-chased Foundation v6.0 will automatically dows-based design tools. Along receivewith this new update.

◆ DESIGN HINTS AND ISSUES XC4005E-3 and the XC3142A-09; and, forK2 is an exponent that describes the speed comparison purposes, two older-technol- with which the metastable condition is being resolved.

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○ ogy devices, the XC4005-6 and the XC3042- K1 represents the metastability-catching 70. In each device, two different implemen-setup time window that describes the tations test the IOB and CLB flip-flops. Thelikelihood of going metastable Benchmarks Confirm XC9500 CPLDXC5200-5 CLB flip-flop was also tested.F1 is the frequency of the asynchronous data (There is no IOB flip-flop in XC5200 archi-input tecture.) F2 is the flip-flop clock frequency The Xilinx XC9500 CPLD family pro- The XC4000E amd XC4000 devices t is the settling time vides the most-advanced, most-reliable pin- showed little difference between IOB andK2 is an indication of the gain-bandwidth CLB behavior, but in the XC3000-series product in the feedback path of the locking capability in the industry. This master latch in the flip-flop. A small devices, the IOB flip-flops showed dramati- important feature allows designers to main- impacting both design performance and decrease in the time constant 1/K2 results cally better metastable performance than in an enormous improvement in MTBF. tain pinouts after making design changes, resource utilization. the CLB flip-flops. This difference can be eliminating costly, time-consuming PC Logic requirements also affect the ability traced to subtle differences in circuit design board re-work. CPLDs that do not have of the fitter to place and route the design and layout and will guide us to further adequate pin-locking capability often re- when the pinout is locked. Slow speed improvements in metastable performance quire pinout changes even after minor designs with simple, narrow logic functions of future designs. design changes, leaving no room for error requiring few inputs, feedbacks and prod- Metastable measurement results are With F1 = 1 MHz, F2 = 10 MHz and and no possibility for field upgrades or uct terms are inherently easier to pinlock listed in the table and plotted in the figure.K1 = 0.1 ns, field customization. than high speed designs with wide fan-in The results for XC4000E-3 IOB and CLB MTBF (in seconds) = 10 × and product term intensive logic functions. -3 × eK2 t The Keys to Reliable Pin-Locking flip-flops, XC5200-5 CLB flip-flops and XC3100A-09 IOB flip-flops are outstanding, To address these pin-locking issues, The values of K2 under these condi- far superior to most metastability data Xilinx XC9500 CPLDs feature abundant tions — expressed as 1/K2 in the table — Pin-Locking Issues published anywhere else. When granted 2 routing resources, wide function block fan- were experimentally derived (as described In most CPLDs, each I/O pin is driven or 3 ns of extra settling delay, these devices in and flexible product term allocation. The in the “1996 Programmable Logic Data directly by a macrocell through an I/O come close to eliminating the problems XC9500 fitter also optimizes the initial Book,” page 14-41). block, as shown in Figure 1. When the caused by metastability, since their mean- placement to maximize the design’s pin- The MTBF under other operating condi- time-between-failure exceeds millions of locking capability. tions can be estimated using the data in years. The older-technology devices are Pin-locking restricts the fitter’s capability the diagram. Simply divide the appropriate slightly less impressive, but still show very 18 to place design resources; therefore, good MTBF from the diagram by the product of 31 acceptable performance, especially the IOB routability is crucial. The routing resources the two relative frequencies. For example, input flip-flops that are normally used to of a CPLD determine how much of the for a 10 MHz asynchronous input synchro- synchronize asynchronous input signals. logic block resources (inputs, product nized by a 40 MHz clock, the MTBF is 40 terms and registers) can be used to accom- times shorter than plotted, and for a 50 modate design changes after the pins are KHz signal and a 1 MHz clock, the MTBF locked in a design. In a fully routable is 200 times longer than plotted here. CPLD, buried logic can be moved without regards to routing restrictions, freeing function block resources that may be needed ◆ by the logic that drives the I/O pins. design is pinlocked, the fitter is forced to The XC9500 family provides the most map logic into specific macrocells to main- routing resources of any available CPLD tain the pinout. If the device architecture is Metastability Calculations family. All devices in the XC9500 family are limited, with inadequate routing in the 100% routable; if there are enough function The Mean Time Between Failures Metastability Measurement Results Figure 1: Simplified central switch matrix, the fitter may not be XC9500 I/O Architecture block resources to implement the design, it (MTBF) can only be defined statistically. It able to place and route the design when will route. is inversely proportional to the product of TESTED FLIP-FLOP VALUE OF 1/K2IN PICOSECONDS the pins are locked. Wide function block fan-in is another the two frequencies involved, the clock Some CPLDs use an output routing pool XC4005E-3 CLB 52 important requirement for pin-locking. frequency and the average frequency of the to compensate for their primary routing IOB 62 Since CPLDs typically are used for high- asynchronous data changes, provided that deficiencies. However, output routing pools XC4005-6 CLB 127 speed, signal-intensive logic functions, these two frequencies are independent and introduce additional delays and do not IOB 118 wide function block fan-in is a requirement have no correlation. The generally accepted prevent the fitter from having to consume XC3142A-09 CLB 208 for implementing functions in a single logic equation for MTBF is logic resources as routing feedthroughs, IOB 79 e MTBF = XC3042-70 CLB 385 IOB 238 K2 × t XC5200-5 CLB 73 F1 × F2 × K1

R Metastability Recovery in Xilinx FPGAs

Whenever a clocked flip-flop syn- on how perfect the balance was and on the chronizes an asynchronous input, there is noise level within the circuit; the delay can, Pin-Locking Capabilities a small probability that the flip-flop output therefore, only be described in statistical will exhibit an unpredictable delay. This terms. The problem for the system designer happens when the input transition not only is not the illegal logic level in the balanced level. The number of available functionmance of the XC9500 CPLDs and two violates the setup and hold-time specifica- state (it’s easy enough to translate that block inputs affects the fitter’s ability tocompetitor’s add ISP CPLD families. These tions, but actually occurs within the tiny arbitrarily to either a 0 or a 1), but the more signals to any logic that must remainbenchmarks are based on typical applica- timing window where the flip-flop accepts unpredictable timing of the final change to in that function block (because it drivestions such as address decoders, datapath the new input. Under these circumstances, a valid logic state. If the metastable flip-flop I/O pins). Wide fan-in capability also helpsdesigns and address counters. They illus- the flip-flop can enter a symmetrically- drives two destinations with differing path the fitter implement that logic in a singletrate the CPLD device’s capability to ac- balanced transitory state, called a meta- delays, one destination might clock in the pass though the device. commodate design changes while main- stable state. final data state while the other does not. Each XC9500 function block has 36 taining an acceptable level of design While the slightest deviation from per- inputs from the switch matrix. Competingperformance; not only must the iterated fect balance will cause the output to revert in-system programmable CPLDs have asdesign reroute when the pinout is main- to one of its two stable states, the delay in few as 16 inputs. tained, it must do so with minimal impact Figure: Mean Time doing so depends not only on the gain- Product term allocation is important onto design performance. Therefore, all of Metastability Measurements Between Failure for bandwidth product of the circuit, but also pin-locking because it allows design the benchmark data is normalized to the various IOB and CLB Recently, the metastable delays of four changes that increase the product termdesign performance that is achieved when flip-flop outputs when different Xilinx FPGA devices were mea- requirement. All XC9500 devices allocatethe fitters are free to choose the pinouts synchronizing a 1 MHz sured: two cutting-edge devices using 0.5 individual product terms from anywherewithout in restrictions. asynchronous input with micron, 3-layer-metal technology, the the function block to the macrocell that a 10 MHz clock. needs them, accommodating logic changes when the design is pinlocked. In the XC9500 family, up to 90 product terms can be allocated to any macrocell in the function block. This is in contrast to 30 competing CPLDs that restrict the product 19 term availability (from 5 to 32 pterms) on ❝The benchmark results confirm the basis of macrocell location in the function block. the superior pin-locking performance of the Fitter software is a key component Xilinxof XC9500 family. This performance is any successful CPLD pin-locking solution. The fitter must work in conjunctionconsistent with across all devices and package types. the device architecture, spreading the out- ❞ puts to accommodate design changes when the design is pinlocked. The XC9500 fitter is optimized to take full advantage of the hardware resourcesAddress of Decoder the XC9500 family. The Xilinx fitter is ca-Benchmark pable of intelligently utilizing all available device resources to retain pinouts and stillThis benchmark maintain the required performance, evendesign contains two after significant design changes. 16-, 32- or 36-bit bus- ses which are decoded to generate two chip select outputs and is intended to measure the effect of routing resources and function block fan-in on the CPLD’s pin-locking capability. A typical design change involves the correction of an error in which the outputs are decoded incorrectly. The Pin-locking Benchmarks The following three sets of benchmark Continued on data show the relative pin-locking perfor- the next page XC9500 Benchmarks Continued from the previous page Figure 1: Maximum acceptable power consumption as a function of ambient tempera- The benchmark results in Figure 2 ture and package thermal resistance, demonstrate that both the Xilinx XC9500 assuming full performance (i.e. 85° C junction temperature). family and the Vendor A devices were able to accommodate the design changes without any impact on design performance. Vendor L devices maintained the same pinout, but with a significant (up to 60%) performance penalty. Since the Vendor L devices have 16 input logic blocks, the performance degradation of the 16-bit address decoder can be attributed to poor routing resources while the performance of the 32 and 36-bit decodes is degraded by both poor routing and narrow logic block fan-in.

Datapath Benchmark This benchmark design measures the affect of routing resources on the CPLD’s Figure 2: Address Decoder-Normalized Benchmark Resultspin-locking capability. This design contains a single 16-, 32- or 36-bit wide data bus. A typical design change involves the reor- 20 dering of data bits. 29 The benchmark results shown in Figure 3 show that both the Xilinx XC9500 family and Vendor A devices were able to Figure 2: accommodate the design changes without Maximum acceptable power any impact on design performance. consumption as a function of ambient temperature and package thermal Vendor L devices sacrificed performance resistance, at reduced performance (up to 80%) to reroute the design when (14% longer delay, 12% lower speed pinlocked. Since only one logic block at 125° C junction temperature). input was required for each output, this performance degradation can be attributed to poor routing resources, or fitter performance, or both, but cannot be attributed to logic block fan-in.

Address Counter Benchmark This benchmark design contains two 16-, 24- or 32-bit loadable address counters loaded from separate buses but with common clock and hold signals. A typical design change alters the initial count load value. This benchmark measures the effect of routing resources and function block fan-in on the CPLDs pin-locking capability

Figure 3: Data Path-Normalized Benchmark Results Trading Off Among the Three PsPower, Package &P erformance

here are well-defined relationships Θ is expressed in degrees C of junc- T J-A between chip power consumption, pack-tion temperature rise over the ambient age thermal characteristics, ambient andtemperature for every Watt dissipated in the junction temperature, and device perfor-device. Θ is primarily a function of the mance. J-A In many cases, the user has no controlpackage and the airflow, with die size a over the maximum ambient temperature,secondary factor. (Larger die have a lower but can choose the device and package, Θ value). See Table 1. and then strive for an acceptable power J-A When the junction is hotter than 85°C, consumption. where Xilinx tests and guarantees perfor- In other cases, mance param- chip, package, eters, delays power con- increase 0.35% sumption and The governing equation is for every addi- ambient tem- tional degree C. perature are T = T + P × Θ J A J-A At 125°C, the given, and the where T = junction temperature maximum al- resulting J lowed junction achievable T Figure 4: Address Counter-Normalized Benchmark Results = ambient temperature temperature in a performance A Θ plastic package, level must be J-A (Theta J-A) = Thermal resistance delays are 14% calculated. If performanceof thecannot package-die be sacri- combination longer, and ficed, thermal managementP = techniquespower dissipation (e.g, speed is thus 12% lower than the guaran- stressed, performance didn’t just degrade, 28 airflow and heat sinks) can be used to 21 teed values in the data book and the soft- when macrocell feedbacks and other the devices completely failed to route. lower the thermal resistance. ware. In ceramic packages, the maximum high fan-out signals are involved. Vendor L devices used several layers of allowed junction temperature is 150°C. The benchmark results shown in logic in the initial design, with corre- Figure 4 demonstrate the superiority of spondingly low f the XC9500 CPLD architecture. All This enabled the MAX. XC9500 devices were able to accommo- fitter to reroute the design using alternate ◆ date the design changes without any routing paths, with less performance impact on design performance. When degradation (20%) than designs initially Vendor A’s routing resources were requiring only one logic level.

Typical thermal resistance for various packages with and without airflow

Designers need options for managing vided by the Xilinx FPGA development the many signal switching conditions that tools. To obtain faster switching speeds, occur in their systems. One simple but the designer must configure the appropri- effective option is the output slew rate ate output buffers for the fast slew rate. control provided in the XC9500 family Since the slower slew rate is the default, CPLDs. This feature permits the simple reported timing for an implemented design selection between a slew-rate-limited output may be slower than expected for a given Figure 1: XC4000 Series drive and a high-speed output drive. The speed grade. This is simply due to the fact Conceptual Model for Edge- result is easy, convenient control of switch- that a slower slew rate output crosses the Triggered Memory ing characteristics on a pin-by-pin basis. switching threshold at a later time than a Currently, the default condition of the faster slewing signal (see Figure 1). The design software provides a slew-rate-limited Xilinx timing report simply adds a small configuration on all output pins. This is time delay to the output signal, accounting consistent with the default condition pro- for the added delay.

A number of methods are available for specifying the fast slew rate, Shorter Design Cycles dependent on the design style chosen. The ease-of-use associated with edge- in effective data rates. These results are • For XABEL-CPLD, include one or more of the following directives: triggered memory design results in shorter demonstrated in a simple FIFO design in design cycles as compared to using level- the Xilinx application note “Implementing XEPLD Property ‘FAST ON’; sensitive RAM. The design, simulation and FIFOs in XC4000 Series RAM.” Sets all pins to fast slew rate testing steps are all simplified. Distributed RAM provides an additional 22 XEPLD Property ‘FAST ON A B C’; speed advantage: locating RAM blocks 27 Pins A,B and C will be fast & all others remain slew rate limited Performance closer to related logic minimizes routing • For schematic entry, attach a FAST attribute to the appropriate output pad symbol. As mentioned above, level-sensitive RAM delays on critical paths. • For Synopsys VHDL, use the following DC Shell commands to set all outputs designs may require both a 2X clock andUses of Select-RAM Memory for the fast slew rate: significant signal manipulation to meet the The edge-triggered RAM capability can stringent timing requirements on the Write and should be used in all new designs Enable signal. The Address and Data inputs set_port_is_pad “*” requiring RAM. These applications include set_pad_type -slewrate NONE all_outputs() must be set-up at the RAM input pins by register files, FIFO buffers, multipliers, shift insert_pads the time the Write Enable signal arrives, registers and pseudo-random sequence typically halfway through the write cycle. Alternatively, the fast slew rate can be specified for individual outputs by replacing the generators. When the same design is implemented second line above with commands of the form: The dual-port option adds the ability to using edge-triggered RAM, Address and read and write simultaneously from two set_pad_type -slewrate NONE port_name Data may change in response to (for ex- different addresses. This ability consider- ample) the rising edge of the input clock. • For Metamor VHDL, add the Metamor library to your VHDL file with the commands: ably simplifies FIFO designs and is useful The Write can occur on the next rising library metamor; for constructing dual-port register files. edge of the same clock. Therefore, the use metamor.attributes.all Address and Data have the full write cycle Then, after your signal declarations, assign the fast attribute to a signal with the command: to set-up at the RAM input pins. The result ◆ attribute property of port_name : signal is “Fast” is a memory block that operates at approximately twice the speed of the level-sensitive version of the design. When the simul- taneous read/write capability of the The Application Notes Figure 1: Effect dual-port Select-RAM option is taken into referenced in this article are of slew rate account, data throughput can be doubled available on the Xilinx control on output again, resulting in a total four-fold increase WebLINX web site at switching times www.xilinx.com, or by contacting the Xilinx Technical Hotline. XC4000 Series Select-RAM Memory: Designing With XC5200 Carry Logic Advantages and Uses Simple design makes XC5200 carry logic even more flexible The XC4000 Series of FPGA devices than that of XC4000 Series (i.e., the XC4000E and XC4000EX families, and their low-voltage counterparts, the XC4000L and XC4000XL families) includes he XC5200 FPGA’s carry logic is several architectural improvements over Easethe of Use highly-successful XC4000 FPGA family. One deceptively simple. While this architecture Traditional RAM capability, now referred of the most important new features is Se- “mix and match” RAM modes. Select-RAM only provides a series of multiplexers inter- to as the level-sensitive or asynchronous lect-RAM is the most flexible memory implementa- connected by dedicated carry nets, the use option to Select-RAM memory, has never T of function generators to control these tion available in an FPGA today. Since a single function generator can TM memory. Select-RAM memorybeen simple to use. Meeting the required multiplexers makes the XC5200 FPGA’s both select the carry and complete the can be defined as the capability of pro- timing relationships often involved careful carry logic extremely flexible — more sum, the incremental cost over the basic gramming the look-up tables in layout and detailed timing analysis. To flexible, in fact, than the XC4000 carry adder is only 25%. The direct access to the Configurable Logic Blocks (CLBs) as ROMguarantee correct behavior, a 2X clock is logic with its multiplicity of modes. carry chain minimizes the timing overhead or as single- or dual-port RAM, with edge-typically required, in order to generate the In the XC5200 architecture, one bit of a associated with this technique, which is triggered (synchronous) or level-sensitiveWrite Enable during the third quadrant of simple adder uses two function generators effective even for relatively short adders. (asynchronous) timing. Select-RAM memorythe write clock cycle. This type of RAM is and a carry chain multiplexer, as shown in also can be initialized to a known value thein only available option in the original Figure 1. However, not all of the function all RAM and ROM modes. XC4000 family devices. generator’s capability is utilized in the basic Select-RAM memory is unique in its None of these delicate timing relation- adder. In the input function generator, the range of options and ability to deliver high-ships need be maintained when using one adder input, b speed dual-port memory. The advantagesof the edge-triggered Select-RAM modes of the Select-RAM capability include flex-available in XC4000-Series devices. Instead, ibility, increased ease-of-use, shorter designwriting to a memory block is just like writing to a data register: set up the address , can be any function of the 26 cycles and increased performance. i 23 and data, enable the RAM and apply the three inputs that are available. For example, effective clock edge. A conceptual model one of these inputs could be used as an for a Select-RAM block in edge-triggered add/subtract control, inverting b in an XOR mode is shown in the Figure 1. i The ability to initialize RAM, as well as gate when necessary. The corresponding acceleration tech-Figure 1: Flexibility ROM, as part of device configuration elimi- Similarly, the adder output can be com- nique for long adders in the XC4000 archi-XC5200 Carry Structure Clearly, the options of edge-triggerednates or the need for logic to perform that bined in any way with the two remaining tecture is the conditional-sum technique. level-sensitive and single-port or dual-portinitialization. Reduced logic results in function generator inputs. In a typical In the upper half of a conditional-sum RAM provide a wide selection of choicessmaller, simpler and more reliable designs. counter application, these might be used adder, two complete adders are imple- for the designer. The distributed nature of for a multiplexer to load the counter or, All of the Select-RAM options are di- mented with ‘0’ and ‘1’ carry inputs, andContinued on the RAM, which is implemented in indi-rectly and easily implemented using any of alternatively, for an AND gate to provide a the next page vidual CLBs, also contributes to the flexibil-the schematic entry, MemGen memory synchronous clear. ity of Select-RAM memory. Only sufficientblock generator tool, X-BLOX A more complex example uses this CLBs to implement a given memory block additional capability in a carry-select adder need be allocated as RAM: the memory that trades additional logic for higher per- block size can be scaled to exactly match formance (Figure 2). The adder is divided the requirements of the application. Each into two sections. The lower half operates RAM block can be placed close to related normally, but in the upper half two carry logic. There is no need to consume a large chains are used in parallel, one initialized block of dedicated memory to implement a with a ‘0’ and the other with a ‘1.’ The carry TM small RAM function, nor to route control schematic- output of the lower half is used to select and data lines across the device tobased reach synthesis, or HDL synthesis design which carry chain is used to complete the such dedicated blocks. Each CLBenvironments. can be Detailed information on how sum. The carry propagates simultaneously individually configured, so the designerto use thesecan tools to implement Select-RAM in the upper and lower halves of the adder; is available in the new Xilinx application thus, the settling time is reduced. note “Using Select-RAM Memory in XC4000 Series FPGAs.” Figure 2: XC5200 Carry-Select Adders additional CLBs are required to select In a simple multiplier, the product is XC5200between the outputs of these adders ac-computed using a cascade of gated adders cording to the carry output from the lowertogether with appropriate shifts (Figure 3). Carry Logichalf. The technique is only effective forA more detailed view of a single bit slice relatively long adders; the incremental throughcost the first two adders of this multi- Continued from the previous pageis 100%. plier is shown in Figure 4. One of the two It is interesting to note that, in the AND gates that precedes the first adder is XC5200 architecture, the carry-select andcombined into the function generator that conditional-sum techniques cannot alwayscontrols the carry multiplexer. The other

inputs, the XOR gates would have required function generators. In this case, the resource utilization would have been the same, but the delay longer. Only in the final adder is a separate function generator needed for the XOR gate. The speed of the multiplier can be increased by rearranging the cascade of adders into a tree, as in Figure 5. After the first set of adders, the input of each adder can absorb the output XOR gate of one of the two preceding adders, as described in A bit slice of this more efficient approachFigure is 5: the cascade multiplier. The other preceding AND gate, however, must use a separate shown in Figure 6. The carry chain is Adder-Treeonly Multiplier adder, however, must use a separate func- function generator because there is a fan- used to add X and 2X when the 3X output tion generator for its XOR gate. out point at the second input to the adder. is required. Otherwise, 0, X or 2X is se- In the first set of adders, the objective is In the second and subsequent adders, lected in the first function generator and to multiply the X input by bit pairs of Y, the AND gates again use separate function routed to the second function generator creating products that are 0X, 1X, 2X or 3X. generators. This permits the XOR gates that where it passes through unaltered. While Figure 3: be distinguished. Both sums of the condi- This is usually achieved by gating X and 2X 4-Bit Cascade Multiplier complete the previous sums to be merged the carry chain continues to operate in a tional-sum adder can be completed in the into an adder, as is shown in Figure 5. 24 adder inputs, thus saving both logic re- meaningless way, it cannot damage itself, 25 same function generator. This function However, a different, more direct sources and critical-path delay. If, instead, and its outputs are not required. When 3X generator can be further used to select approach may be used in XC5200 FPGA. the AND gates had been merged into the is required, the first function generator between them. If this is done, all the func- XORs X and 2X to control the carry chain tion-generator truth tables and all the inter- in a normal addition. The sum is completed connections become identical to the carry- in the XOR gate that precedes the multi- select adder. This should not be surprising, plexer in the second function generator. however, since both techniques implement Figure 6: Figure 4: the same uniquely defined adder function. First Stage of a Tree-Adder Bit-Slice of First Multiplier Two Adders ◆ XC4000 Series Select-RAM Memory: Designing With XC5200 Carry Logic Advantages and Uses Simple design makes XC5200 carry logic even more flexible The XC4000 Series of FPGA devices than that of XC4000 Series (i.e., the XC4000E and XC4000EX families, and their low-voltage counterparts, the XC4000L and XC4000XL families) includes he XC5200 FPGA’s carry logic is several architectural improvements over Easethe of Use highly-successful XC4000 FPGA family. One deceptively simple. While this architecture Traditional RAM capability, now referred of the most important new features is Se- “mix and match” RAM modes. Select-RAM only provides a series of multiplexers inter- to as the level-sensitive or asynchronous lect-RAM is the most flexible memory implementa- connected by dedicated carry nets, the use option to Select-RAM memory, has never T of function generators to control these tion available in an FPGA today. Since a single function generator can TM memory. Select-RAM memorybeen simple to use. Meeting the required multiplexers makes the XC5200 FPGA’s both select the carry and complete the can be defined as the capability of pro- timing relationships often involved careful carry logic extremely flexible — more sum, the incremental cost over the basic gramming the look-up tables in layout and detailed timing analysis. To flexible, in fact, than the XC4000 carry adder is only 25%. The direct access to the Configurable Logic Blocks (CLBs) as ROMguarantee correct behavior, a 2X clock is logic with its multiplicity of modes. carry chain minimizes the timing overhead or as single- or dual-port RAM, with edge-typically required, in order to generate the In the XC5200 architecture, one bit of a associated with this technique, which is triggered (synchronous) or level-sensitiveWrite Enable during the third quadrant of simple adder uses two function generators effective even for relatively short adders. (asynchronous) timing. Select-RAM memorythe write clock cycle. This type of RAM is and a carry chain multiplexer, as shown in also can be initialized to a known value thein only available option in the original Figure 1. However, not all of the function all RAM and ROM modes. XC4000 family devices. generator’s capability is utilized in the basic Select-RAM memory is unique in its None of these delicate timing relation- adder. In the input function generator, the range of options and ability to deliver high-ships need be maintained when using one adder input, b speed dual-port memory. The advantagesof the edge-triggered Select-RAM modes of the Select-RAM capability include flex-available in XC4000-Series devices. Instead, ibility, increased ease-of-use, shorter designwriting to a memory block is just like writing to a data register: set up the address , can be any function of the 26 cycles and increased performance. i 23 and data, enable the RAM and apply the three inputs that are available. For example, effective clock edge. A conceptual model one of these inputs could be used as an for a Select-RAM block in edge-triggered add/subtract control, inverting b in an XOR mode is shown in the Figure 1. i The ability to initialize RAM, as well as gate when necessary. The corresponding acceleration tech-Figure 1: Flexibility ROM, as part of device configuration elimi- Similarly, the adder output can be com- nique for long adders in the XC4000 archi-XC5200 Carry Structure Clearly, the options of edge-triggerednates or the need for logic to perform that bined in any way with the two remaining tecture is the conditional-sum technique. level-sensitive and single-port or dual-portinitialization. Reduced logic results in function generator inputs. In a typical In the upper half of a conditional-sum RAM provide a wide selection of choicessmaller, simpler and more reliable designs. counter application, these might be used adder, two complete adders are imple- for the designer. The distributed nature of for a multiplexer to load the counter or, All of the Select-RAM options are di- mented with ‘0’ and ‘1’ carry inputs, andContinued on the RAM, which is implemented in indi-rectly and easily implemented using any of alternatively, for an AND gate to provide a the next page vidual CLBs, also contributes to the flexibil-the schematic entry, MemGen memory synchronous clear. ity of Select-RAM memory. Only sufficientblock generator tool, X-BLOX A more complex example uses this CLBs to implement a given memory block additional capability in a carry-select adder need be allocated as RAM: the memory that trades additional logic for higher per- block size can be scaled to exactly match formance (Figure 2). The adder is divided the requirements of the application. Each into two sections. The lower half operates RAM block can be placed close to related normally, but in the upper half two carry logic. There is no need to consume a large chains are used in parallel, one initialized block of dedicated memory to implement a with a ‘0’ and the other with a ‘1.’ The carry TM small RAM function, nor to route control schematic- output of the lower half is used to select and data lines across the device tobased reach synthesis, or HDL synthesis design which carry chain is used to complete the such dedicated blocks. Each CLBenvironments. can be Detailed information on how sum. The carry propagates simultaneously individually configured, so the designerto use thesecan tools to implement Select-RAM in the upper and lower halves of the adder; is available in the new Xilinx application thus, the settling time is reduced. note “Using Select-RAM Memory in XC4000 Series FPGAs.” Figure 2: XC5200 Carry-Select Adders Using XC9500 Slew Rate Controls

Typical thermal resistance for various packages with and without airflow

250 FT/MIN 500 FT/MIN 750 FT/MIN PACKAGE STILL AIR (1.3M /S) (2.5M/S) (3.8M/S) Conclusions HQ304 11 7 6 5 °C/W The benchmark results confirm the superior pin-locking performance of the HQ240 12 9 7 6 °C/W Xilinx XC9500 family. This performance is consistent across all devices and pack- HQ208 14 10 8 7 °C/W age types. The wide function block fan-in enables pin-locking of wide, high-speed MQ240 17 12 11 10 °C/W logic functions. Furthermore, because feedthroughs are not needed for routing, MQ208 18 14 13 12 °C/W there is no performance degradation due to routing congestion. This timing consis- PQ240 23 17 15 14 °C/W tency is as important as routing ability for maintaining pin-locked designs. PQ208 32 23 21 19 °C/W The XC9500 CPLD devices feature the industry’s best pin-locking capability, PQ160 32 24 21 20 °C/W eliminating the need for PCB modifications due to design changes. This feature not PQ100 33 29 28 27 °C/W only shortens design cycles and decreases design costs but also facilitates the use of in-system programmability to upgrade or modify systems in the field. PC84 33 25 21 17 °C/W TQ100 31 26 24 23 °C/W ◆ VQ100 38 32 30 29 °C/W XC9500 Benchmarks Continued from the previous page Figure 1: Maximum acceptable power consumption as a function of ambient tempera- The benchmark results in Figure 2 ture and package thermal resistance, demonstrate that both the Xilinx XC9500 assuming full performance (i.e. 85° C junction temperature). family and the Vendor A devices were able to accommodate the design changes without any impact on design performance. Vendor L devices maintained the same pinout, but with a significant (up to 60%) performance penalty. Since the Vendor L devices have 16 input logic blocks, the performance degradation of the 16-bit address decoder can be attributed to poor routing resources while the performance of the 32 and 36-bit decodes is degraded by both poor routing and narrow logic block fan-in.

Figure 3: Data Path-Normalized Benchmark Results Metastability Recovery in Xilinx FPGAs

Whenever a clocked flip-flop syn- on how perfect the balance was and on the chronizes an asynchronous input, there is noise level within the circuit; the delay can, Pin-Locking Capabilities a small probability that the flip-flop output therefore, only be described in statistical will exhibit an unpredictable delay. This terms. The problem for the system designer happens when the input transition not only is not the illegal logic level in the balanced level. The number of available functionmance of the XC9500 CPLDs and two violates the setup and hold-time specifica- state (it’s easy enough to translate that block inputs affects the fitter’s ability tocompetitor’s add ISP CPLD families. These tions, but actually occurs within the tiny arbitrarily to either a 0 or a 1), but the more signals to any logic that must remainbenchmarks are based on typical applica- timing window where the flip-flop accepts unpredictable timing of the final change to in that function block (because it drivestions such as address decoders, datapath the new input. Under these circumstances, a valid logic state. If the metastable flip-flop I/O pins). Wide fan-in capability also helpsdesigns and address counters. They illus- the flip-flop can enter a symmetrically- drives two destinations with differing path the fitter implement that logic in a singletrate the CPLD device’s capability to ac- balanced transitory state, called a meta- delays, one destination might clock in the pass though the device. commodate design changes while main- stable state. final data state while the other does not. Each XC9500 function block has 36 taining an acceptable level of design While the slightest deviation from per- inputs from the switch matrix. Competingperformance; not only must the iterated fect balance will cause the output to revert in-system programmable CPLDs have asdesign reroute when the pinout is main- to one of its two stable states, the delay in few as 16 inputs. tained, it must do so with minimal impact Figure: Mean Time doing so depends not only on the gain- Product term allocation is important onto design performance. Therefore, all of Metastability Measurements Between Failure for bandwidth product of the circuit, but also pin-locking because it allows design the benchmark data is normalized to the various IOB and CLB Recently, the metastable delays of four changes that increase the product termdesign performance that is achieved when flip-flop outputs when different Xilinx FPGA devices were mea- requirement. All XC9500 devices allocatethe fitters are free to choose the pinouts synchronizing a 1 MHz sured: two cutting-edge devices using 0.5 individual product terms from anywherewithout in restrictions. asynchronous input with micron, 3-layer-metal technology, the the function block to the macrocell that a 10 MHz clock. needs them, accommodating logic changes when the design is pinlocked. In the XC9500 family, up to 90 product terms can be allocated to any macrocell in the function block. This is in contrast to 30 competing CPLDs that restrict the product 19 term availability (from 5 to 32 pterms) on ❝The benchmark results confirm the basis of macrocell location in the function block. the superior pin-locking performance of the Fitter software is a key component Xilinxof XC9500 family. This performance is any successful CPLD pin-locking solution. The fitter must work in conjunctionconsistent with across all devices and package types. the device architecture, spreading the out- ❞ puts to accommodate design changes when the design is pinlocked. The XC9500 fitter is optimized to take full advantage of the hardware resourcesAddress of Decoder the XC9500 family. The Xilinx fitter is ca-Benchmark pable of intelligently utilizing all available device resources to retain pinouts and stillThis benchmark maintain the required performance, evendesign contains two after significant design changes. 16-, 32- or 36-bit bus- ses which are decoded to generate two chip select outputs and is intended to measure the effect of routing resources and function block fan-in on the CPLD’s pin-locking capability. A typical design change involves the correction of an error in which the outputs are decoded incorrectly. The Pin-locking Benchmarks The following three sets of benchmark Continued on data show the relative pin-locking perfor- the next page DESIGN HINTS AND ISSUES XC4005E-3 and the XC3142A-09; and, forK2 is an exponent that describes the speed comparison purposes, two older-technol- with which the metastable condition is being resolved.

R XACTstep and Alternate LogiCoreTM PCI Intitiator Debuts Operating Systems Xilinx recently announced the deliveryin XC4013-2 FPGAs. These devices operate of its second, 100% compliant PCI core,at 33 MHz and include high-speed burst the LogiCore synchronous FIFOs. The modules can be he Xilinx XACTTMstep development the Sun-based version for the Sun OS. How- TM PCI “Master” (Initiator/ T customized to fit individual design require- system software is available for both work- ever, with some exceptions as detailed Target) module. Previously, the LogiCore ments, resulting in a cost-effective, single- station and PC platforms. The PC-based below, XACTstep software can run on some PCI “Slave” (Target only) module could chip solution. version is designed for Windows 3.1, and variants of these popular operating systems. only perform slave functions. With the new The LogiCore PCI Master module (LC- module, a user can now complete a master DI-PCIM-C) for Xilinx FPGA and HardWire interface design in which the Master mod- devices, complete with a data sheet, com- ule acts as a controller for the PCI bus. prehensive user guide and PCI Systems Running XACTstep v6.0.1 in Windows 95 The implementation of critical paths in the Architecture textbook, is available for core are pre-defined to ensure PCI compli- • The Hardware Debugger does not run. designing with Viewlogic schematics, The majority of the XACTstep 6.0.1 ance. As a result, designers can reduce There is no known workaround. VHDL and Verilog for $8,995. The PCI software will run in Windows 95. However, design risk and cut development time by at there are some known compatibility issues: Slave module (LC-DI-PCIS-C) is available • The ProSeries software does not run least nine months. for $4,995. under Windows 95. WorkView Office is The new -2 speed grade for the • The Design Manager will cause a For further information about the available on an as-needed basis. Contact XC4013E FPGA enables the delivery of the General Protection fault when it is LogiCore PCI Interface or other mod- the Xilinx Technical Hotline for more PCI Master module, which requires a high closed. This causes no system problems ules in the program, please contact information. level of design complexity and perfor- and can be ignored. your local Xilinx representative or mance (see article about -2 speed grade on visit the LogiCore section of the page 14). The LogiCore PCI modules were WebLINX World Wide Web site. closely developed with beta users who 17 Running XACTstep v5.2.1 in Windows NT have successfully implemented the design

Solaris Support for XACTstep v5.2.1 Install problem, a script called cdi.csh has Foundation Series Enjoys Successful Introduction been developed that will install the soft-

◆ filtering out gated clocks. If desired, usersconstraints that directly translates to the can specify specific input pins that needXACT to step TIMESPEC format. All netlist and New, Independent E-Mail User Group be connected to a global buffer. constraint translation is done by FPGA Synopsys revised the mapping and Express, eliminating the need for external Dedicated to Xilinx Technology Continued from the previous pageoptimization algorithms to provide all HDLtranslators. The tool outputs Unified Library users with the best possible synthesis XNF with group TIMESPECS. The result is results for area, performance and predict-a “plug & play” interface between FPGA XUMA: Xilinx User MAiling list FPGA ability. Testing has shown that FPGA Ex-Express and the XACTstep tools (v6.0.x Express press can improve area and performanceand beyond). by up to 25% over existing PC-based syn- Alain Arnaud of ECLA, Inc. (Newton,signing with a range of Xilinx parts and is thesis tools. Run times are excellent — a Massachusetts), a design consultant andup-to-date on Xilinx products. 3,000-gate design compiled in under a experienced FPGA and ASIC designer, wasXUMA is completely independent fromRemember, Xilinx users Pricing and Availability pondering how to best field his customers’Xilinx, Inc. Many engineers want an inde- minute and a 20,000-gate design required can contact the Xilinx approximately 10 minutes using a Pentium-Sold by Synopsys, FPGA Express starts questions — a mix that included both pendent technical forum for openly dis-Technical Support Hotline class computer. at $12,000 (one HDL language and support system-level and FPGA-level issues. To cuss key concerns and issues, both at the Xilinx also collaborated with Synopsysfor one FPGA vendor). It will be available assist in this task, Alain started an e-mailsystem- and device-level, and get objective(see page 35) with to integrate FPGA Express into the in full production in September, running address list of colleagues and industry answers from others in their professionaltechnical questions on XACTstep on Windows 95 and Windows NT-based contacts. This effort has grown into XUMAcommunity. — the Xilinx User MAiling List — a new, Xilinx products. personal computers. ◆ For more information about FPGA independent forum for the communication Express contact Bruce Jorgens, Prod- of technical subjects across the Xilinx user community. XUMA, initiated in May,1996, TM system. FPGA Express uses auct Line Manager for FPGA Products currently has over 250 subscribers and is sophisticated constraint-entry GUI, with atan Synopsys 415-528-4955. growing rapidly. “XACTstep-like” from/to syntax for timing 16 ◆ XUMA mailings are e-mails of technical TO: [email protected] questions and answers sent to Alain by anybody and forwarded to everyone on CC: the XUMA mailing list. TOPIC: Xilinx mailing list Xilinx users can subscribe to the list, unsubscribe from the list or submit a MESSAGE: Alain -- please add my name to the XUMA change of address by sending mail to: list for Xilinx technical issues. 33

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R Continued on the next page PHOTO FOR ILLUSTRATION PURPOSES ONLY PHOTO FOR ILLUSTRATION The XC4000EX family elevates the Xilinx has started sample shipments of XC4000EX XC4000Family series to newFPGAs heights in density Enteringthe first two members Production of the high-density and performance, with up to 125,000 logicXC4000EX family. The XC4036EX, with a gates and 66 MHz system speeds.typical gate range of 22,000 to 65,000 Increased On-Line Technical Information Designed “from the ground up”gates, and the XC4028EX, with a typical for speed and density using agate range of 18,000 to 50,000 gates, will The Xilinx BBS mirrored on the World Wide Web. deep-submicron, triple-layer- enter volume production in the fourth Xilinx Bulletin Board Service files and resources can now be accessed through the metal process, the XC4000EX quarter of this year. Xilinx Internet FTP site. family has abundant routing The next member of the family to be resources for high utilization andintroduced is the XC4062XL, featuring a Xilinx offers increased on-line support resources and choices. buffered interconnect to providetypical gate range of 40,000 to 130,000 In the coming months, keep an eye on the Xilinx Technical Support resources on maximum performance. (See gates. The XC4062XL will begin sampling WebLINX, the Xilinx web site (www.xilinx.com). In addition to the above mentioned BBS XCell #20, page 21.) in December. resources, you will see increased access to applications materials, product support materials, and commonly asked questions and solutions. 14 ◆

TECHNICAL SUPPORT RESOURCES Faster XC4000E FPGAs Now Available HOTLINE SUPPORT, U.S. HOTLINE SUPPORT, EUROPE ontinuing process improvements havemum chip-to-chip system speeds of the Customer Support Hotline: UK, London Office C telephone: (44) 1932 820821 led to the release of a new, faster speedXC4000 and XC4000E devices for their 800-255-7778 fax: (44) 1932 828522 grade for XC4000E available speed grades. Hrs: 8:00 a.m.-5:00 p.m. Pacific time Bulletin Board Service: (44) 1932 333540 TM FPGAs, available now The XC4000 series (i.e., the XC4000, e-mail: [email protected] for every member of the device family. XC4000E and XC4000EX families) incorpo- Customer Support Fax Number:France, Paris Office The new -2 speed grade achieves a rates the world’s most widely used FPGA 408-879-4442 telephone: (33) 1 3463 0100 15-20 percent performance improvement fax: (33) 1 3463 0959 35 architecture with advanced features such as Avail: 24 hrs/day-7 days/week over the -3 speed grade as a result of a e-mail: [email protected] Select-RAM logic block propagation time (T Germany, Munich Office E-mail Address: telephone: (49) 89 991 54930 ) of 1.6 TM memory, wide edge decod- ILO [email protected] fax: (49) 89 904 4748 ns, clock-to-output delays (T ) of underers, internal three-state buffers and multiple e-mail: [email protected] OKPOF 5 ns and global-clock-to-out, pin-to-pin global clock distribution networks. The Customer Service*: Japan, Tokyo Office delays (T high performance levels offered from the telephone: (81) 3 3297 9163 ) ranging from 8.7 ns for the 408-559-7778, ask for customer service ICKOF -2 speed grade, when combined with these fax: (81) 3 3297 0067 * Call for software updates, authorization XC4003E to 10.7 ns for the XC4025E . Seeleading-edge architectural features, further e-mail: [email protected] codes, documentation updates, etc. Figure 1 for a comparison of the maxi-extends the range of possible applications for these popular devices. For example, the capabilities of the Figure 1: Speed Grade Comparisons for XC4000 and XC4000EXC4000E-2 device enable the delivery of the LogiCore X-TALK: The Xilinx Network of Electronic Services 70 MHz 65 MHz 60 MHz 56 TM PCI Initiator module — • Xilinx home page on the World Wide Web ...... www.xilinx.com. 50 MHz MHz an implementation that requires extremely • Electronic Technical Bulletin Board (U.S.) ...... 408-559-9327 • XDOCS E-mail document server- 38 40 high performance levels, especially for 40 MHz 32 MHz send an E-mail to [email protected] with ‘help’ as the only item in the subject header. MHz FIFO buffer and registered I/O operations You will automatically receive full instructions via E-mail. 30 MHz 27 MHz (see page 17). MHz • XFACTS fax document server ...... available by calling 408-879-4400. 20 MHz For further technical information, E-mail addresses for questions related to specific applications: 10 MHz please refer to the product specifica- Digital Signal Processing applications...... [email protected]

System Speed* tions and application notes on 0 MHz PCI-bus applications ...... [email protected] WebLINX, the Xilinx web site Plug and Play ISA applications ...... [email protected] -6 -5 -4 -4 -3 -2(www.xilinx.com). For pricing and PCMCIA card applications ...... [email protected] availability, contact your local Xilinx Asynchronous Transfer Mode applications ...... [email protected] XC4000 Family XC4000E Familysales representative. Reconfigurable Computing applications ...... [email protected] (3,000-25,000 gates) 3,000-25,000 gates) *Maximum chip-to-chip system speed ◆ TECHNICAL QUESTIONS & ANSWERS Best 44-Pin PLD Value Mentor Graphics I have an Autologic design that, While compiling my AutologicQduring Men2XNF8, gives me the FEATURES BENEFITS Qdesign through Timsim8, following error in EDIF2XNF: Familiar Data I/O ABEL, Windows-based environ- Push button design flow improves productivity PLD_DVE_BA returns the Error: 5 No direction/pintype ment for design entry, simulation and fitting following warning, that may repeat for port:PINBALL/WIZARD Industry-standard-ABEL- HDL supports state ABEL-HDL familiar to PAL users, optimized several times: machines, high level logic descriptions, truth for PAL and CPLD development What’s happening and how tables and equation entry # WARNING: Unknown design can I fix this? Hierarchical design entry and JEDEC file Enables reuse of existing PAL codes, object: /JE/I1101S$37$5 conversion for integration of existing PAL designs simplifying design effort The pin in question does not have a What does this mean and how into Xilinx CPLDs can I fix it? PINTYPE property associated with it. The Functional simulation with graphical Waveform Facilitate rapid design verification PINTYPE property indicates a pin’s direction- Viewer and Static Timing Reports ality, and is required in XACT 5.x by Autologic may write out percent signs Advanced XACTstep v6 XC7K & XC9K fitter with auto- Fitter’s architecture-specific knowledge frees EDIF2XNF and XNFMerge. Autologic may (%) in its instance names. Although this is omatic device selection, multiple pass optimization, the user to focus on design functionality omit PINTYPE properties when synthesizing legal in Mentor schematics, it is not legal in partitioning and mapping, and timing driven fitting 13 hierarchical symbols, following the rules of Xilinx netlists. To remedy this, EDIF2XNF Animated tutorial and on-line help Reduces learning curve: pre-XACT 5.0 software. • tutorial leads users through entire changes each “%” in a netlist to “$37$” (so If the offending symbol was created by design process in minutes used because 37 is the ASCII code for the - extensive on-line help places all Autologic II, a patch is available on Mentor percent sign). Unfortunately, the Mentor Graphics’ FTP site at supportnet.mentorg.com documentation a mouse-click away back-annotation file is written with this (137.202.128.4). ◆ change, so that I1101S$37$5 in the MBA Autologic II version A.x requires Patch file does not match up with the true 244, located in the directory: I1101S%5 in the schematic. The problem may be fixed by modify- ANNOUNCEMENT ing the mbapp.nawk script, which processes the MBA file for use in PLD_DVE_BA, to change the $37$’s back /pub/patches/release_A/ XC8100 FPGA Product Family is Discontinued 36 to %’s. For more information, send E-mail autologic2 to [email protected] with send 618 in iting the strong market succcess of the subject line. Once this modification withis the filenames: C SRAM and FLASH technologies, Xilinx this difficult technology,” stated Xilinx CEO made, Timsim8 should run smoothly. README_P244 Wim Roelandts. (patch information) announced on Aug. 31, 1996, that it will discontinue the XC8100 “But, compared to SRAM development, INSTALL_P244 TM (installation instructions) family of one- there are very few people working in sg_p244.sss.tar.Z time programmable antifuse FPGA devices. antifuse. As a result, antifuse will lag be- (SunOS 4.x) The XC8100 family, first introduced last hind SRAM, entail dispro- sg_p244.ss5.tar.Z autumn, was just entering production. portionately large develop- (Solaris 2.x) No layoffs or reductions in R&D spend- ment costs, and be sg_p244.hpu.tar.Z ing are associated with this decision. Xilinx relegated to limited mar- ❝ to (HP-UX) employees involved with antifuse develop- kets. For these reasons we compared ment are taking on new duties in other believe further investmentSRAM development, there are areas of the company. Resources and in antifuse product devel- Autologic II version B.x requires Patch very few people working in 320, located in the directory: research and development spending are opment are too large to be /pub/patches/release_B/ being redirected to focus more effectively justified.” antifuse. As a result, antifuse autologic2 on SRAM-based FPGAs, CPLDs and new A number of options are opportunities more closely aligned with available to supportwill current lag behind SRAM, entail those products, such as LogiCore modules. XC8100 users, includingdisproportionately large with the filenames: “The XC8100 team successfully developed assistance in moving de- README_P320 a number of patented, industry-first innova- signs to other pin-compat-development costs, and be (patch information) tions in antifuse architecture, design, pro- ible Xilinx devices, software INSTALL_P320 relegated to limited markets. (installation instructions) gramming and processes — accomplishments upgrades to support other sg_p320.sss.tar.Z no one else in the entire semiconductor programmable logic products and refunds (SunOS 4.x) industry has been able to achieve so far with for XACTstep ❞ sg_p320.ss5.tar.Z (Solaris 2.x) sg_p320.hpu.tar.Z (HP-UX) TM 8000 software.◆ XC7300 CPLDs & XABEL-CPLD: The Industry’s After running Fncsim -o Synopsys he combination of ultra-low-cost signaling levels and 100% PCI compliance Q(use original schematic) on a 44-pin XC7300 CPLDs and easy-to-use provide support for the newest CPUs and design that contains X-BLOX How can I prevent FPGA XABEL-CPLD development software pro- high-performance memories. components, I see no-connect Compiler from writing my vides users withT the best value in program- 44-pin CPLDs also have proven ex- symbols on certain pins in the Qtiming constraints into the mable logic. Three XC7300 family members tremely adept at fixing “ broken” ASICs. simulation schematic. What’s .sxnf file? are now available in 44-pin PLCC, PQFP or ASIC users are discovering that 44-pin happening? VQFP packages — the XC7336, XC7336Q CPLD solutions can be used to safeguard and XC7354 devices. or repair ASIC functionality. Sometimes During its optimization process, These no-connects will appear in theSynopsys’ FPGA Compiler attempts to Xilinx 44-pin XC7300 CPLDs provide a fixed-function ASICs can be rendered simulation schematic any place where two greater range of performance and signifi- “unusable” by specification changes, pro- meet the timing constraints issued by you; pin vertices are laying on top of each and subsequently writes out the timing cantly lower costs than PALs and GALs. In cess variations that disrupt system timing other. In the original schematic, the pins fact, the logic from several PAL /GAL de- or design errors. Planning ahead by reserv- constraints into the netlist (.sxnf) file for would be connected by a zero-length net.the Xilinx tools to use. You may want to vices can be integrated into a single ing board space for a small form factor, 44- In the simulation schematic, however, the XC7300 CPLD at a lower device cost than pin CPLD can provide ASIC designers with issue these constraints to the Xilinx tools 12 coincident pins will not be connected in a separate constraints file, where you the replaced PALs/GALs (and sometimes at “system insurance.” The CPLD can be used (hence, the no-connect symbol). a component cost equivalent to a single to implement control circuitry or correct have the ablility to be more specific about The best fix for this problem is to goparticular paths that you want to constrain. high-speed PAL). The XC7300 CPLDs also sensitive timing paths. In this way, the back to the original schematic and move can replace TTL bus drivers, further reduc- flexibility to fix unwanted surprises is built- To do this, issue the following any coincident vertices apart, so that thecommand just prior to writing out the ing component count and cost. Advanced in to the design. net between them may be seen. system features such as 3.3V or 5V I/O .sxnf file:

xnfout_constraints_per_ endpoint = 0

Push-Button Software Gets the Job Done

OF 1996

○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○○ % Improvement $33.00 $18.00 $12.00 2H97 30% 25% 31% 28% 25% $8.00 $4.50 R 11 AUGUST 1996 New Product earn about the newest Xilinx products and services through our extensive library of product literature. The most recent pieces are listed below. To order or to obtain a com- Literatureplete list of all available literature, please contact your local Xilinx sales◆ representative.

TITLE DESCRIPTION NUMBER XC7372 XC73108 XC73144 XC9536 XC95108 XC95216 PINS TYPE CODE XC4005L XC4010L XC4013L XC5202 XC5204 XC5206 XC5210 XC5215 XC7236A XC7272A XC7318 XC7336 XC7336Q XC7354

1996 Programmable Logic Data Book Technical Data 0010303 PLASTIC LCC PC44 ◆ ◆◆◆◆ ◆ L 1996 Programmable Logic Data Book on CD-ROMTechnical Data 500360 PLASTIC QFP PQ44 ◆◆◆ ◆◆ Product Overview Brochure Features & Benefits 0010130-05 44 PLASTIC VQFP VQ44 ◆ ◆◆◆ Software Selector Guide Features & Benefits 0010304 CERAMIC LCC WC44 10 FPGA Brochure Features & Benefits 0010305 48 PLASTIC DIP PD48 ◆◆◆ 64 PLASTIC VQFP VQ64 ◆◆◆ PLASTIC LCC PC68 68 UPCOMING EVENTS CERAMIC LCC ◆◆WC68 ◆◆◆◆ ◆ ◆◆ ◆ CERAMIC PGA PG68 ◆◆◆ PLASTIC LCC PC84 ◆ Look for Xilinx technical papers and/or product exhibits at these upcoming industry fo- rums. For further information about any of these conferences, please contact Kathleen 84 CERAMIC LCC WC84 ◆◆◆ ◆◆ ◆ Pizzo (Tel: 408-879-5377 FAX: 408-879-4676).◆ CERAMIC PGA PG84 ◆ CERAMIC QFP CQ100 ◆◆◆ PLASTIC PQFP PQ100 EuroDAC & EuroVHDLDSP World/ICSPAT Electronica Sept. 16-20 Oct. 8-10 Nov. 12-15 100 PLASTIC TQFP TQ100 Geneva, Switzerland Boston, MA Munich, Germany PLASTIC VQFP VQ100 ◆◆◆◆ International WorkshopSilicon Design Photonics East TOP BRZ. CQFP CB100 on Field ProgrammableConference Nov. 18-22 120 CERAMIC PGA PG120 ◆ Logic and ApplicationsOct. 9-10 Boston, Massachusetts ◆◆ 132 PLASTIC PGA PP132 Sept. 23-25 Birmingham, ◆◆◆◆ ◆◆ ◆◆ Darmstadt, Germany United Kingdom BIAS & DSP Italy CERAMIC PGA PG132 Nov. 26-29 PLASTIC TQFP TQ144 144 PCI Europe WESCON Milan, Italy CERAMIC PGA PG144 Oct. 1-2 Oct. 22-24 Paris, France Anaheim, California DSP UK 156 CERAMIC PGA PG156◆◆◆ Dec. 3-4 160 PLASTIC PQFP PQ160 DSP Germany DSP France London, United Kingdom CERAMIC QFP CQ164 ◆ Please note that the XC8100 family Oct. 1-2 Oct. 22-24 164 has been discontinued. TOP BRZ. CQFP CB164 Munich, Germany Paris, France ◆◆◆ ◆◆ PLASTIC PGA PP175 See page 13. 175 39 CERAMIC PGA PG175 ◆◆ 176 PLASTIC TQFP TQ176 ◆ 184 CERAMIC PGA PG184◆◆◆ ◆◆ 191 CERAMIC PGA PG191 196 TOP BRZ. CQFP CB196◆◆ FINANCIAL RESULTS PLASTIC PQFP PQ208 208 METAL MQFP MQ208 ◆ ◆ Quarterly Sales revenues rose to $150.2 million in growth. The bright spot was the North HI-PERF QFP HQ208 ◆ the first fiscal quarter of 1977 (ending June American distribution channel, which 223 CERAMIC PGA PG223 ◆ Revenue30, 1996), a 19% increase over the same grew 10% over the prior quarter.” 225 PLASTIC BGA BG225 quarter one year ago and a 0.3% increase The XC5000 FPGA family continued WINDOWED BGAWB225 Topsfrom the immediately preceding quarter. its torrid growth rate, with sales up 30% 228 TOP BRZ. CQFP CB228 “The June quarter was a difficult quarter over the previous quarter. Recently an- $150M PLASTIC PQFP PQ240 for the semiconductor industry,” noted nounced price cuts (see page 11) should 240 Xilinx Chief Executive Officer Willem even further expand the market for this METAL MQFP MQ240 Roelandts. “Although Xilinx was not cost-optimized FPGA family. HI-PERF QFP HQ240 immune to this widespread slowdown, we Xilinx stock is traded on the NASDAQ 299 CERAMIC PGA PG299 did experience minor sequential revenue exchange under stock symbol XLNX. 304 HI-PERF. QFP HQ304 352 PLASTIC BGA BG352 ◆ 411 CERAMIC PGA PG411 432 PLASTIC BGA BG432 ◆ = Product currently shipping or planned 499 CERAMIC PGA PG499 ❖ = New since last issue of XCELL 596 PLASTIC BGA BG596 (none appear in this issue) What’s New on WebLINXTM Xilinx Home Page • www.xilinx.com

/ WebLINX was recently named ◆ Product Spotlights an Infoworld HotSite! Here are a few of Examine a showcase of our latest prod- OTES 9 EATURES Includes 502/550/380 & Foundry PC, Sun, HP kits now available PC, Customer w/v6.0 will receive v6.0.1 update Customer w/v6.0 will receive v6.0.1 update Includes PROSeries 6.1 Includes PROSeries 6.1 Incl PROSeries 6.1/PROsynth 5.02X Includes support for XC4000E and XC9500 Includes support for XC4000E and XC9500 Includes support for XC4000E and XC9500 Includes support for XC4000E and XC9500 Initiator and target; Req signed lic agreement Support for SDT+, VST+ v1.2 New version w/XC9500; First ship 4/29/96 version New Includes PRO Series 6.1 Includes PRO Series 6.1 with v5.2.1 and v6.0.1 N F the reasons why: ucts, currently featuring the XC4000EX and XC9500 device families and the ◆ TM Foundation Series software, with its 5.20 Includes DS-401 v5.2 5.20 Includes XC5200 X-BLOX Support 5.20 5.20 6.10 5.20 ELEASE

ERSION SmartSearch Agents Released REVIOUS 5.2/6.05.2/6.0 Now available on HP7 5.2/6.0 Includes 502/550/380 5.2/6.0 request only PC update by 5.2/6.0 R V P Come visit the industry-wide search en- easy-to-use, low-cost VHDL synthesis gine made specifically for topics involv- solution. AST PDT OMP ing programmable logic. You can create L 7/967/96 7/96 6.0 7/967/967/96 6.0 6.0 7/967/96 6.0 7/96 6.0 7/967/96 6.0 6.0 7/96 6.0 7/96 6.0 7/967/967/96 6.0 7/96 6.0 6.0 8/96 6.0 1.0 7/967/96 6.0 7/96 7/96 7/96 7/96 7/96 6.0 7/96 7/96 7/96 6.0 C your own agents to notify you by e-mail as material you want becomes available◆ On-Line Net Seminars in any of multiple sites on the web. In cooperation with Marshall Industries, 9.01 Xilinx holds live seminars on the

ERSION Check out this on-line company and V product overview covering topics such Recordedas seminars on the XC5200 and Xilinx corporate and product strategies,XC9500 device families also are avail- URRENT 6.2 4.1. 7.007.00 7.00 7.001.101.10 1.10 na na 1.10 1.10 na na 1.10 na na Target only; Req signed lic agreement 6.007.00 6.0.1 7.00 7.00 na na 2.00 2.00 2.00 na na 6.016.11 5.2.1 5.2.1 PC1 SN2 HP7 U 6.0.16.0.16.0.1 5.2.1 5.2.1 5.2.1 5.2.1 5.2.1 5.2.1 6.0.1 6.0.1 6.0.1 6.0.1 6.0.1 6.0.1 6.0.1 6.0.16.0.1 5.2.16.0.1 6.0.1 5.2.1 6.0.1 6.0.1 6.0.1 6.0.1 6.0.1 6.0.1 6.0.1 C device selection, XACTstep able to review at your convenience. TM software ◆ solutions, quality assurance and Xilinx technical support services.

Two basic classes are available from Xilinx, a schematic-based and a synthe- aries aries aries aries aries sis-based class. SUPPORT

Actually, both classes focus more on explaining and demonstrating the basic overall design methodologies for using concepts behind HDL-based design by

SILICON Xilinx devices, rather than the specific

XILINX RELEASED SOFTWARE STATUS-AUGUST 1996 STATUS-AUGUST RELEASED SOFTWARE XILINX examining many of the specific language RODUCT UNCTION Entry,Simulation,Lib, Optimizer Module Generator & Optimizer P F Core Implementation Entry/Simulation/Core Core + Interface Models & XNF Translator front-end tools. (The tutorials shipped with constructs that should be used when de- the development systems provide the XXXXX XXXXX signing with these tools. specific tool training for the new user.) All designers can benefit from taking The schematic-based class has traditionally XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX DS-OR-BAS-PC1 XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX XXXXXX one of these classes. Even designers al- 2K 3K 4K 5K 7K 9K utilized ViewLogic tools in the examples ready familiar with Xilinx technology can and labs. However, with the introduction learn some new methods to reduce design ESCRIPTION RODUCT of XACTstep version 6.0.1, the class has P D XC7K Support Support XC7K, XC9500 XC7K, XC9500 Support 8.4=A.4PROcapturePROsim Interface and Libraries Interface and Libr Interface and Libr time and increase device performance. been updated to use the Foundation Remember, either class (and even customized classes) can be presented right at your own facility. Please contact your local TM Sales office or our training registrar with ATEGORY RODUCT Development System and its front-end your needs. The latest schedule of classes Foundation Series Foundation Series LogiCore-PCI SlaveLogiCore-PCI Master X X Viewlogic/S Viewlogic/S Viewlogic/S Viewllogic/S 3rd Party Alliance 3rd Party Alliance Foundation Series Foundation Series Mentor OrCAD Synopsys Synopsys Viewlogic Viewlogic ViewlogicXABEL XBLOX Cadence Mentor Libr and Interface Evaluation CORE XEPLD XABEL-CPLD XACT-CPLD Mentor OrCADSynopsysViewlogic Viewlogic Libr and Interface Interface and Libr P C

:software for in-warranty users by request only, U= Update by request only, N=New Product, E= Engineering tools from Aldec. and contact information is always available EY E Verilog 2K,3K,4K,7K Libraries U 3rd Party Alliance

U OrCAD U Viewlogic The synthesis-based class uses the on WebLINX, our World Wide Web site K

KEY PR = Pre-release requiring in-warranty status or Product Marketing apporval PR = Pre-release requiring in-warranty status or XILINX PACKAGES XILINX

XILINX INDIVIDUAL PRODUCTS INDIVIDUAL XILINX Synopsys tools. The course goes beyond (www.xilinx.com).◆ Aug-96 XC17256L XC17128L V1.31A

Xilinx Helps Fund New Seiko-Epson Foundry XC17256D

Xilinx has announced its funding ofour competitive position and allow us to up to $300 million for the construction ofdesign a products with ever higher densities XC17128D Aug-96 new semiconductor manufacturing facility.and faster performance, “ stated Xilinx XC1765L The facility will be built and operated byChief Executive Officer Willem Roelandts.

Seiko-Epson Corp. in Sakata, Japan (about“Just as important, it will help us meet 3Q96 200 miles north of Tokyo). Xilinx will growing customer demand worldwide for 6.462.25 6.46 2.25 6.46 2.25 XC1718L V2.7V2.7 V2.7 V2.7 V3.10 V3.10 V5.61 V5.61

make incremental advance payments overour products into the next century.” 6.5.10 6.5.10 6.5.10 6.5.10 V2.4U V2.4U V1.31A the next two and one-half years to help This investment agreement further XC1765D 8 finance construction of the facility. In strengthens the close relationship between 3Q963Q96 3Q96 3Q96 3Q96 3Q963Q963Q96 3Q96 3Q96 3Q96 V1.16 V1.16 V1.16 V1.16 V1.24 6.5.10 6.5.10 6.5.10 6.5.10 Aug-96Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 return, Xilinx will receive a specified num-Xilinx and Seiko-Epson; Seiko-Epson has V2.26HV2.26H V2.26H V2.26H V2.26H V2.26H ber of wafers from the new line throughbeen a supplier to Xilinx for more than a XC1718D XC1736D the year 2002. decade. Xilinx also will maintain its exist- SPROM.310 SPROM.310 SPROM.310 SPROM.310 The new operation will manufacture ing8" foundry partnerships with Yamaha, wafers using advanced 0.35 to 0.25 micronTaiwan Semiconductor Manufacturing CMOS technology. In time, these advancedCompany (TSMC), United Microelectronics IQ-180 IQ-280 Uniwriter 40 processes will enable the development ofCorporation (UMC) and IC Works. As MODEL ALLPRO-88 ALLPRO-88XR ALLPRO-96 CHIPMASTER 2000 CHIPMASTER 6000 MODEL 200 SYSTEM 2000 programmable logic devices with capacitiesreported in XCell #20, Xilinx owns a 25% FLEX-700 SuperPRO II/PHW-112HW-130 2.4B 5.00 2.4B 2.01 5.00 2.4B 2.01 5.00 2.4B 2.01 1.00 XPRO-1 PIN-MASTER 48ROM 5000 B ROM 3000 U Aug-96ROM9000 Aug-96 Aug-96 Chipmaster 5000 Optima Multisyte Sprint Plus48 Eclipse Quasar T-10 UDP T-10 ULC POWER-100EXPRO-60/80TURPRO-1 Aug-96 Aug-96MULTI-APRO TUP-300TUP-400SuperPRO SuperPRO II Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 2.4B Aug-96 Aug-96 Aug-96 2.4B Aug-96 Aug-96 2.4B 2.4B reaching 500,000 gates. Production at theequity stake in a new foundry being con- TURPRO-1 F/X TURPRO-1 T/X APRO facility is expected to begin in early 1998.structed by UMC in Taiwan and scheduled “We’re confident that our continuing to come on-line in the first half of 1997. partnership with Seiko-Epson will enhance

◆ XC17256L RED SQUARE MQP ELECTRONICS NEEDHAM’S ELECTRONICS EMP20 MANUFACTURER GRAPHICSLINK COMPUTER CLK-3100 LOGICAL DEVICES ALLPRO-40 XC17128L XILINX MICRO PROSS SMSSTAG SUNRISE SUNSHINE Expert SYSTEM GENERAL TRIBAL MICROSYSTEMS XELTEK XC17256D New Data Book Now Available XC17128D

Both CD-ROM and printed versionsfiles) of and its installer are included on the XC1765L the new “Xilinx Programmable Logic DataCD-ROM. The main table of contents, 41 Book” are now available. The material inchapter tables of contents and the index all the new data book also is available oninclude hypertext links to immediately XC1718L 3.7Q 3.7Q

WebLINX jump to the appropriate pages in the book. V1.40 V1.40 V1.40 V1.40 Aug-96Aug-96Aug-96Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 TM , the Xilinx World At 900 pages, the data book includes XC1765D

Wide Web site data sheets for the XC7300, XC9500, V2.0 V2.0 V1.1E V1.1E3Q96 V1.1E 3Q96 3Q96 V3.17 V3.17 V3.17 V3.17 Aug-96Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 Aug-96 (www.xilinx.com), in the XC3000A/L, XC3100A/L, XC4000E, 10.84B10.84B10.84B10.84B10.84B10.84B10.84B10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B 10.84B V3.17V3.17V3.17V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 V3.17 form of individual prod- XC4000EX/XL, XC5200, XC6200, and V2.4U V2.4U V2.4U uct specifications. XC1700D device families. Product specifi- XC1718D XC1736D The CD-ROM, a first cations for the older XC2000, XC3000, with this edition, works XC3100, and XC4000/A/H/D/L families are with PCs, Sun worksta- not included, but are still available on XPGM CP-1128 EP-1140 BP-1200 V3.15 V3.15 V3.15 MODEL 2900 3900 AutoSite ChipLab Aug-96 Aug-96 Aug-96 Aug-96 PC-UPROG tions, and HP worksta- WebLINX. The military/high-reliability and tions. Detailed tables of HardWire LEAPER-10 LP U4 V2.0 V2.0 ALLMAX/ALLMAX+ MEGAMAX 3000-145 5000-145 6000 APS All-03A All-07 Micromaster 1000/E Speedmaster 1000/E Speedmaster LV BP-2100135H-FT/U MTK-1000 MTK-2000 MTK-4000 V3.15 V3.15 V3.15 2700 contents and the ability to search for LABTOOL-48PILOT-U24 PILOT-U28 PILOT-U32 PILOT-U40 Aug-96PILOT-U84 PILOT-142 PILOT-143 Aug-96PILOT-144 Aug-96PILOT-145 Aug-96 keywords makes the CD-ROM a valuable Micromaster LV LV40 Portable tool. The entire data book resides in a TM product lines are overviewed, 1996 PROMS-AUGUST SERIAL XC1700 XILINX FOR SUPPORT PROGRAMMER single “.pdf” file. The Acrobat™ Reader but detailed product specifications are still program (that allows users to view .pdf found in separate, dedicated documents. To obtain a copy, contact your local Xilinx sales representative. ◆ E E TOOLS DEUS EX MACHINA DATAMANDATA I/O DATAMAN-48 UniSite V1.30 V1.30 V1.30 B&C MICROSYSTEMS INC. Proteus-UP40 BP MICROSYSTEMS MANUFACTURER ADVANTECH WHITE=changed since last issue; 1736A, 1765 and 17128 columns eliminated since last issue LEAP ELECTRONICS ICE TECHNOLOGY LTD ELAN DIGITAL SYSTEMS HI-LO SYSTEMS RESEARCH BYTEK ADVIN PROGRAMMER SUPPORT FOR XILINX XC7200 CPLDS —AUGUST 1996

Speedmaster LV V1.1 V1.1 LEAP ELECTRONICS LEAPER-10 V2.0 V2.0 Video Processing With XC7300 CPLDs LP U4 V2.0 V2.0 LOGICAL DEVICES ALLPRO-88 ALLPRO-88XR BICOM, Inc., (Monroe, CT) is a provider of hard- ALLPROF-96 6.4.26 6.4.26 ware and software “building blocks” for developing a Chipmaster 2000 V2.4U V2.4U Chipmaster 6000 V1.31A V1.31A wide range of voice processing applications. BICOM’s products are used in the develop- passed two boards rather than one. XPRO-1 ment of systems for voice mail, interactive The design was entered and implemented on a PC MICROPROSS ROM9000 3Q96 3Q96 voice response, audiotex, dictation and call using OrCAD schematic entry tools. The com- MQP ELECTRONICS SYSTEM 2000 Aug-96 Aug-96 center management. plexity of the design (which included a mix of PIN-MASTER 48 Aug-96 Aug-96 The recent design of their new Gemini analog and digital technologies) and tight devel- series of high-density computer telephony opment schedules dictated the use of program- 42 NEEDHAM’S ELECTRONICS EMP20 V3.10 V3.10 SMS Expert 3Q96 3Q96 platforms required a high-performance CPLD to integrate mable devices with predictable performance and Optima 3Q96 3Q96 a variety of logic functions. With cost and ease-of-use good pin-locking capabilities. The XC7336 CPLD Multisyte 3Q96 3Q96 considerations in mind, the Xilinx fulfilled both these needs. Pinouts were pre- XC7300 assigned and maintained throughout multiple design STAG Eclipse 6.4.26 6.4.26 iterations. This allowed the designers to concentrate on SUNRISE ELECTRONICS T-10 UDP Aug-96 Aug-96 the more difficult architectural aspects of the design. T-10 ULC Aug-96 Aug-96 TM CPLD family was chosen. As first-time Xilinx users, BICOM engineers were SUNSHINE ELECTRONICS POWER-100 Aug-96 Aug-96 The voice processing board impressed with the level of technical support EXPRO-60/80 Aug-96 Aug-96 contains 14 XC7336 devices. provided by the Xilinx team. SYSTEM GENERAL TURPRO-1/FX Aug-96 Aug-96 The XC7336-5 CPLDs are used In summary, by MULTI-APRO Aug-96 Aug-96 to hold a variety of logic functions, in- using the TRIBAL MICROSYSTEMS TUP-300 V3.09 V3.09 TUP-400 V3.09 V3.09 cluding address decoders, state machines, I/O func- XC7300 CPLD tions and glue logic, with XC7336-15 CPLDs for the com- family, BICOM FLEX-700 V3.09 V3.09 plicated timing associated with engineers were XELTEK SUPERPRO SUPERPRO II 2.4B 2.4B the telecommunications channel. able to meet their If BICOM had used traditional performance needs, reduce design complexity and cost, SUPERPRO II/P 2.4B 2.4B PALs for these logic functions, and save valuable board space as well. XILINX HW-130 1.14 1.04 the design would have encom- WHITE=changed since last issue ◆ Note:The XC7236 and XC7272 columns have been eliminated CUSTOMER SUCCESS STORIES PROGRAMMER SUPPORT FOR XILINX XC7300 CPLDS-AUGUST 1996

WHITE=changed since last issue RS6000 HP7 compliant with Texas Instrument to attract the attention of the CAEContinued tool from the Modules (TIM) specifications and are vendors. For many of these vendors,previous pagethis UN ✓✓ ✓✓

PLATFORMS supported by a library of common DSP conference was their first chance to talk functions. MiroTech has signed an OEM with the early adopters of reconfigurable ✓✓✓ ✓ ✓ ✓ ✓✓✓✓ PC S agreement with a major manufacturer of computing technology; it is certainly not DSP boards. inconceivable that some cooperative prod- NI IB uct development efforts will eventually ✓✓✓ ✓✓✓✓✓ ✓✓✓ ✓✓✓ ✓✓ ✓✓✓ ✓✓✓✓✓ ✓✓ ✓ ✓✓✓✓ ✓ ✓✓✓✓ ✓ ✓✓✓✓ ✓✓✓✓✓✓ ✓ ✓ ✓✓✓ ✓ ✓✓✓ ✓ ✓✓✓✓ ✓✓✓ ✓✓✓ ✓✓✓ ✓✓✓ L The remaining companies at the confer- result from this meeting. ence previewed products in development. K 5 9 ✓✓ ✓ ✓✓ ✓✓✓✓ K 7k 7k 7k 7k 7k 7k 7k 7k 7k 7k 7k 7k 7k 7k 7k 9k 9k 7k 7k 7k 7k enVia Inc. (Menlo Park, CA) is developing 7k,9k 7k,9k consumer telecommunications equipment that uses reconfigurable FPGAs to address 5200 7

XACT6 XACT6 7k XACT6 7k XACT6 7k the growing problem of incompatible / XC CPLD U K K

K CAD Technologies (Sunnyvale, CA) and In summary, reconfigurable computing consulting firm Memec Design Services result from this meeting.

ESIGN technology is continuing to ‘come of age,’ Xilinx Tool Kit XNF2MTV Xilinx I/F Kit interface XNF XD-1 Included Xilinx Design Kit included Xilinx Front End Xilinx Synthesis Lib. Call Xilinx Call Xilinx Call Xilinx Call Xilinx Call Xilinx Call Xilinx Call Xilinx Call OrCAD Call Xilinx Call Xilinx Call Xilinx Call Xilinx Xilinx Kit LCA-PP Xilinx Mapper Xilinx Design Kit Call Xilinx Call Xilinx Call Xilinx EDIF Interface Xilinx Mapper SYN-LCA D Included End Xilinx Front Call Xilinx Call Xilinx (Garden Valley, CA) also attended, and with several companies already garnering❞ are applying RC technology in some new revenue from a wide variety of RC-based application areas (but it’s too early to products, penetration of RC technology reveal them). into large, well-known electronic equip- Another encouraging sign was the ment manufacturers, and the attention presence of representatives from several of of leading design tool vendors. I’m the CAE companies in the Xilinx Alliance already looking forward to next Program. The enormous potential of year’s conference. reconfigurable computing is beginning UNCTION Timing Analysis SimulationSchematic Entry to VHDL translator XNF Included Schematic Entry/Sim Synthesis Synthesis Synthesis Schematic Entry Simulation Simulation Schematic Entry Schematic Entry Synthesis Synthesis, SimulationSchem/Sim/Synth Fitter XEPLD Synthesis Simulation, Timing Analysis Call Xilinx Schematic Entry Synthesis Synthesis Simulation Graphical Design Entry/Simulation/Debug Schematic Entry, Synthesis & Simulation Schematic Entry, Synthesis F & Simulation & HDL Editor Schematic Entry Synthesis Synthesis Synthesis 44 SimulationSchematic Entry Topdown FPGA Synthesis Front End Xilinx

◆ 2.11 Simulation 5.31 5.02 ERSION 9504 1.05.02 Entry/Simulation Schematic V 4.4j (PC) Simulation 4.6a (WS)

Sharp-eyed readers may notice a slight change to the format of XCell in ALLIANCE-EDA COMPANIES & PRODUCTS-AUGUST 1996-1 OF 2 OF 1996-1 & PRODUCTS-AUGUST COMPANIES ALLIANCE-EDA AME

N this issue. The tables listing component availability, Xilinx software status, Alliance ROFESSIONALS

P partner information, and device programmer status have been moved from the “General Information” section to the last few pages of the newsletter. As a few RODUCT SHIZUE V-System/VHDL Silos IIIVanguard V-BAK 95.100 1.1 Voyager LM1200Modeler Hardware Xilinx Logic Module DesignBook 2.0 Design Entry Active-CAD 2.0 ASIC NavigatorX-Syn Entry Schematic Synplify 2.6a QSimThedaLOG/iC2 Simulation 4.0 4.2 Design ArchitectQuickSim IISimulate (Win)VST 386+ (DOS) B.x Capture (Win)SDT 386+ (DOS)PLD 386+ (DOS) B.x ABEL 6.10 1.2Synario 1.2 7.0 Simulation 2.0 Simulation FPGA ExpressProSynthesis ProSim 6.2 2.2 ProCapturePowerView 1.0 Synthesis 6.1 6.1 6.0 Schematic Entry Schem/Sim/Synth/Timing AnalLOG/iC Classic Call Xilinx 4.2 P ComposerQuickHDL 4.4 Schematic Entry B.x FPGA CompilerVSSDesign Compiler 3.4b 3.4b 3.4b Simulation Synplify-Lite 2.6a VerilogConceptFPGA Designer Synergy 2.4 2.1 2.3 FPGA Synthesis readers have suggested, this will make the tables easier to find as well as providing XILINX XILINX for better continuity for those who read the whole journal front-to-back. We are always interested in reader feedback. This issue includes a short reader survey on page 47. We would greatly appreciate if you would take a few minutes to fill out this questionnaire and mail or FAX it back to us. Alternatively, you can send

AME your comments directly to me via E-mail at [email protected]. We’re looking N forward to hearing from you.

OMPANY

Model Technology Summit Design Corp. Visual HDLTopDown Design Solutions 3.0 Protel TechnologyQuad Design TechnologySimuCad MotiveSophia Sys & Tech Schematic Advanced 3.1 Server Schematic Entry/Client 4.3 Xilinx Interface IK Technology Co.IKOS Systems INCASES Engineering GmbH I (Synopsis Division) Capilano Computing Design WorksEscalade Exemplar Logic 3.1 Galileo 3.2 Synthesis/Timing Analysis Simulation C Aldec Compass Design Automation Mentor GraphicsOrCAD AutologicSynario Design Automation B.x Viewlogic WorkView Office 7.1.2/7.2 ISDATA Logic Modeling Corp.Model Smart Models Simulation In Smart Model Lib. Synopsys Synplicity, Inc. Cadence ◆

RUBY DIAMOND THE FAWCETT

from Time Logic (Incline K /3 ✓✓✓ ✓ ✓✓✓ ✓✓ ✓ ✓ ✓ ✓✓ ✓✓✓✓ ✓✓ ✓✓ ✓✓✓✓ ✓✓✓✓ ✓✓✓ ✓✓ ✓ ✓✓ ✓✓✓ ✓✓✓ ✓✓✓✓ ✓ ✓✓✓✓✓✓ ✓ ✓✓✓✓ ✓✓ ✓ ✓✓✓✓ ✓✓ ✓ ✓✓✓✓ ✓✓ ✓ ✓✓✓✓ 4 computing is beginning to maceutical companies and medical ✓ K 3k,4k 3k,4k 3k,4k 3k,4k 3k,4k 3k,4k 3k,4k 3k,4k 3k,4k Village, NV), and the X-CIMresearch facilities, where it outperforms 2 attract the attention of the line of DSP acceleration multi-million-dollar supercomputers. modules from MiroTech CAE tool vendors. Microsystems (Saint Laurent,• MiroTech Microsystems is addressing Proven Xilinx compatibility

❞ Quebec, Canada). the FPGA-based DSP market. Its DSP and These partners have a high degree of compatibility acceleration modules are fully

• Available soon in retail IT K

music equipment stores, Ruby: have repeatedly shown themselves to be significant contribu- tors to our users’ development solutions. Emerald:

Digital Wings is a 128-track ESIGN XNFGEN Xilinx Library Interface XNF Axess 2.Yes Xilinx Kit Xilinx Kit Xilinx Design Module Xilinx I/F Kit XNF Interface XNF Xilinx Kit XILINX Tool Kit XILINX Tool Included Included AALCA interface Xilinx FPGA Design Kit Xilinx Kit audio authoring system that operates in D Kit Xilinx FPGA Design Kit Xilinx FPGA Design Kit Xilinx FPGA Design Kit Xilinx FPGA Design Kit Xilinx FPGA Design Xilinx FPGA Design Kit the Windows environment on a PC (see XCell #20, page 42). Metalithic Systems

GUEST EDITORIAL

The XC9500 ISPEN and ISPEX instruc- UNCTION Rapid Prototyping Design Capture Synthesis/Simulation LASAR model generationTiming Specification and Analysis Included Worst Case Simulation Testability Analysis Test Vector GenerationLogic Analysis Top-Down Design SystemSynthesis Kit Xilinx Simulation Included 4k 7k Schematic Simulation Gate-level Sim HDL, Synthesis, SimulationASIC to FPGA Netlist Mapping Included Schematic Entry Synthesis Testability Analysis Design Management Synthesis Synthesis F D. The RUN-TEST/IDLE state is the Simulation Design Entry Synthesis 45 tions provide a framework for protecting “action” state in which programming the user’s system during ISP operations. or erase latency times are spent. This type of functionality is absolutely This is exactly the way XC9500 parts critical for developing a truly workable software for these products. 14.x 1.0c 2.60 Generation Automatic Test interface AALCA 2.60 14.0 12.2 12.0 function. ERSION

ISP-based system — Xilinx has it now. V step C. The interchange of information A final report will be made to the 1149.1 should be included as part of the working group at the International Test Conference in October. At that time, it will ALLIANCE-EDA COMPANIES & PRODUCTS-AUGUST 1996-2 OF 2 OF 1996-2 & PRODUCTS-AUGUST COMPANIES ALLIANCE-EDA be decided whether to pursue this as a AME separate standard within the 1149 frame- N work or as an application of the 1149.1 standard. RODUCT Paradigm RP TransPROTsutsuji 1.2 Synthesis PROVERD PARTHENONPLDesigner-XLLasar 2.3 3.3 Synthesis 6 System ExplorerASIC ExplorerXILLASTimingDesigner 2.1 2.3 System Emulation Logic Compressor 3.0 ASIC EmulationFS-ATG 4.1 CKTSIM Synthesis optimization Axess 2.3 3.0 3.0 4K One-Hot State Machine Lib.Paradigm XP Graphic Design for One-Hot State Machines QuickBenchSmartViewer 1.0FS-SIM Visual Test Bench Generator Included 3.0 VulcanVerBest Design Capture 4.5Peak FPGA Plus Simulation Gatran 2.2 ATGEN 3.3 P Veribest VHDL 14.0 AsynSoftwireSharpeye 3.3 3.3 Multi-FPGA Partitioning Included D M MVeriBest Synthesis Synovation 14.x Veribest VerilogVeriBest SimulatorPLDSyn 14.0 14.0 Simulation Either way, Xilinx has already equipped XILINX the new XC9500 family with the industry’s

❝ NC Either way, Xilinx has best JTAG/ISP capabilities and is spearhead- I already equipped the new XC9500 family with ing the next generation of programming and testing standards. UTOMATION

the industry’s best JTAG/ISP capabilities and is AME A spearheading the next generation of N These partners have strong strategic relationships with Xilinx and have ESIGN Computer programming and testing standards. D

OMPANY

❞ EDA Zycad Tokyo Electron LimitedTrans EDA Limited ViewCADZuken 1.2 FLDL to XNF translator Fujitsu LSI Harmonix Corporation MINC Teradyne The Rockland Group Integrated Network Analysis Epsilon Design Systems ALPS LSI Technologies, Inc.ALPS LSI Technologies, Edway Design SystemsAptix Corporation Aptix Corporation Aster Ingenierie S.A. Chronology Corporation Synthesis/Simlulation Flynn Systems Probe 3.0 Accolade Design Automation C V CINA- Veribest ACEO Technology, Inc. Acugen Software, Inc.

EMERALD ◆ RUBY Alliance Program Categories: Diamond: a direct impact on our releases. Typically, Xilinx is directly involved in the development and testing of the interface to XACT 46 iwoi onDb (508) 480-0881 John Dube Loren Lacy (916) 622-7935 (408) 496-4515 Inquiries about the Xilinx Alliance Program can be e-mailed to [email protected]. Zycad Shige Ohtani Rocky Awalt Kathie O’Toole Zuken Visual Software Solutions, Inc. Viewlogic Veribest Richard Jones VEDA DESIGN AUTOMATION INC Trans EDA Limited TopDown Design Solutions Ed (508) 897-0028 Tokyo Electron Limited Luise Markham Marketing Department The Rockland Group Teradyne Synplicity, Inc. Synopsys Frank Meunier Synario Design Automation Summit Design Corporation Sophia Sys & Tech SimuCad Quad Design Technology, Inc. Protel Technology +49-89-839910 (503) 531-2412 OrCAD Model Technology Minelec Christian Kerscher MINC McCollow Marnie Mentor Graphics Logical Devices Logic Modeling Corp. (Synopsis Division) ITS (408) 474-5002 (206) 869-4227 x116 (604) 522-6200 ISDATA INCASES Engineering GmbH IKOS Systems (408) 428-6209 IK Technology Co. Murray Marcia Harmonix Corporation Chris Dewhurst MikeMcClure Fujitsu LSI Flynn Systems David Rinehart Lotz Christopher 656-2189 (510) Henry Verheyen Exemplar Logic (603) 881-8821 Escalade Epsilon Design Systems, Inc. Compass Design Automation CINA-Computer Integrated Network Analysis Hudson Nancy Chronology Corporation Capilano Computing Ray Wei Cadence Aster Ingenierie S.A. Aptix Corporation Alta Group ALPS LSI Technologies, Inc. Aldec Acugen Software, Inc. ACEO Technology, Inc. Accolade Design Automation C OMPANY N AME XILINX ALLIANCE-EDA CONTACTS-AUGUST 1996 ieHni (201) 989-2900 (305) 423-8448 Mike Hannig Makato Ikeda Andy Bloom (617) 422-3753 James Douglas Art Pisani (408) 232-4764 Mike Jew Alisa Yaffa 988-8250 (805) Lynn Fiance Jacquelin Taylor 671-9500 (503) Tom Tilbon Britta Sullivan (303) 279-6868 x209 Mike Jingozian Greg Seltzer Kevin Bush +49-72-1751087 Sam Picken Mot David +81-3-3839-0606 Ralph Remme Brad Roberts (603) 598-4444 Tsutomu Someya (408) 654-1651 Shigeaki Hakusui Masato Tsuru Matt Van Wagner Shubha Shukla Rod Dudzinski Cuong Do (408) 944-7016 Brad Ashmore 441489571562 Ann Heilmann 470-2686 (800) Baruch Deutsch David Blagden Dave Pellerin C ONTACT Sinclair N AME +81-4-594-27787 (303) 581-2330 [email protected] +44-703-255118 (603) 888-8811 +81-3-334-08198 (415) 961-4962 (415) 694-4289 (206) 867-6257 (503) 643-9281 (510) 487-9700 (408) 243-8143 (503) 526-5465 +32-02-4603175 (719) 590-1155 (503) 685-1298 (408) 366-8509 (617) 935-8335 +81-4-4812-8043 (510) 337-3741 (408) 934-1536 (415) 940-1723 +33-99537171 (408) 523-4137 (702) 456-1222 x12 P HONE N UMBER [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] E- MAIL A DDRESS A. The IDCODE and USERCODE registers are a vital part of any ISP device following areas: meaningful. General consensus seems to be forming in the one another for the development of a standard approach to be diagnostics. The vendor approaches to ISP were close enough as diverse emulation technologies and remote field test was great. Immediate applications could be envisioned in fields and HP. GenRad and Teradyne; ISP end-users such as Cisco Systems sultants; automatic test equipment manufacturers such as HP, such as Asset Intertech, Corelis, Intellitech and APG Test Con- Lattice, AMD, Cypress and IBM; third-party tool manufacturers The attendees included PLD manufacturers such as Xilinx, Altera, Hewlett Packard’s Manufacturing Test Division in Loveland, CO. from about 20 companies. This first ‘study group’ meeting was held on April 19 at purview, with Xilinx taking the lead in this effort. group chose to take a active role in bringing an ISP extension 1149.1 under its XC4000 series FPGAs optionally can be programmed through the TAP). The working (For example, XC9500 family CPLDs are always programmed through the TAP, and development is becoming a de facto standard among most PLD manufacturers. that the use of 4-pin 1149.1 test access port (TAP) as platform for ISP programming algorithm re-work. development costs escalate as new devices come on-line, requiring extensive variety of ISP parts available. In addition, their own test and diagnostic software party applications solutions that address the system-level issues for wide manufacturing flows and enable remote system updating. that are already soldered on a system board to facilitate prototyping, streamline GUEST EDITORIAL I tem would be otherwise unobtainable. instructions makes ISP impractical since the revision level and contents of a sys- Indeed, not supporting these part, program content and version identification The XC9500 CPLD architecture already includes these optional 1149.1 functions. will probably be made mandatory. There was broad agreement that the value of standardization Xilinx and Hewlett Packard organized a meeting of more than 30 participants At the last IEEE 1149.1 (JTAG) working group meeting, it was recognized As ISP proliferates, end-users are strained by the difficulty of finding third Xilinx T n-system programming (ISP) allows users to program and re-program parts Standardization Effort By NEIL G. JACOBSON akes the Lead in ISP ◆

Manager, JTAG Research & Development Continued on the next page

of finding third party applications users are strained by the difficulty solutions that addresss the system- level issues for the wide variety ❝ As ISP of ISP parts available

. ❞ R 3 2 property of their respective owners. Inc. All other trademarks are the Company” is a service mark of Xilinx, and “The Programmable Logic Series, and products, HardWire, Foundation trademarks; all XC-designated Xilinx logo and XACT are registered customers of Xilinx, Inc. the XCELL is published quarterly for All rights reserved. ©1996 Xilinx Inc. E-Mail: FAX: Phone: San Jose, CA 95124 2100 Logic Drive Xilinx, Inc. Editor: comments and submissions to: Please direct all inquiries, XCELL 408-879-4676 408-879-5097 Bradly Fawcett [email protected] XACT step are trademarks; R

(see

that

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