Direct Hardware Generation from High-Level Programming Language

Budapest University of Technology and Economics Department of Control Engineering and Information Technology

DIRECT HARDWARE GENERATION FROM HIGH-LEVEL PROGRAMMING LANGUAGE

Ph.D. thesis Csák, Bence

Consultant: Prof. Dr. Arató, Péter Full member of Hungarian Academy of Sciences

Budapest 2009

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1. INTRODUCTION The ever increasing speed and complexity demand of control applications is driving developers to work out newer and newer solutions for ages. In the course of this arrived mankind to the point where after purely mechanical components, electromechanical, electrical and later electronic components are used in the more and more complex control and computing machines. For the sake of flexibility of control systems even in the times of purely mechanical systems, program control has been created, which then spread over to electromechanical and later electronic systems. Development of programming has accelerated truly in the times of electronic computers. Today programs are written at an abstraction level from which no single step is enough to get to the level, where the first programs were written. This high level ensures that extremely big software systems can operate even safety critical systems without malfunction. The unquenchable desire for even higher computation power - despite of the development of software engineering - forces that certain tasks are solved by purpose built hardware. In case of a given task the desired performance is assured on a cost-effective way by composing the system of application specific hardware and CPU based software. Optimal partition of software and hardware parts is aided by the methodology of hardware-software co-design. Here, system specification is given on a standard symbolic language, from which a given partitioning procedure derives hardware and software components. This symbolic language is usually C, as the sphere of users is rather extensive, it is applicable to describe digital systems and it provides an “executable specification”, so the specification itself is testable. This thesis introduces a methodology, which provides components and building rules for the hardware-software mapping of digital systems. The Department of Control Engineering and Information Technology of the Budapest University of Technology and Economics is researching for years in the field of hardware- software co-design and hardware mapping of computation-intensive tasks. This thesis belongs to this environment, however emphasis is put onto hardware mapping of high- level language defined, general (calculation and control-intensive) tasks and provides a novel, extremely scalable microprocessor architecture for software mapping. Based on the course of the thesis, literature in connection with C-based design and sub- RISC processors have to be regarded. 2. RESEARCH GOALS The main goals of the research were: 1) Workout of a direct C-HW mapping methodology, which – compared to existing methodologies – supports more general applications and is less restrictive. Enables the systematic translation of a C coded algorithm into RTL described hardware so that the developer does not need to posess complex hardware knowledge and still he can optimise on the speed-economy scale the resulting hardware. 2) Enhancement of the methodology by 1) so that parallel function is supported even with the permission of competition cases and with the resolution of those.

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3) Enhancement of the methodology by 1) and 2) so that pipelining is enabled. Construction and sectioning of the pipeline is solved on a way that it does not need complex apparatus and enables extremes in sectioning and extremes in timely behaviour. 4) Enhancement of the methodology by 1), 2) and 3) – as hardware mapping methodology – by a microprocessor architecture so that system components to be mapped into software can have a widely scalable, application oriented microprocessor, which can also be programmed on high-level languages.

By reaching the research goals an electronic system – consisting of hardware and software components - can be created, which provides a high degree of freedom – especially in the system-on-chip category – to partitioning procedures.

The methodology of this thesis fits very well the demand today to realise greater and greater processing performance on a chip.

3. NEW RESULTS Thesis 1: I have worked out a new model and direct systematic design procedure, which maps a high-level language (C) program to a hardware structure.

This methodology is able to map C codes with slight limitations, using a parser being not part of this thesis, into hardware structures. The output of the procedure is a block scheme, or VHDL code supporting a wider range of FPGA or ASIC technologies. The resulting synchronous hardware uses one single-phase clock signal. The C-HW mapping is systematic, no expert database is needed. An expression or statement can be of any complexity. Execution of those need one or more clock signals, which amount is known in compile time. Variables are multi assignment variables. Simple variables and non-array variables can be accessed concurrently at any depth. Use of pointers is allowed, as well as even dynamic datatypes. Function type variables are applicable. Hardware modules, representing functions can be “called” from multiple points with no theoretical limit, but these can be used also as hardware macros. Parameter of a function can also be another function. Recursive function call – with some limitation – is enabled. The methodology could use stack memories, but such has not been worked out yet. At the current workout brake statement can only be used in conjunction with the switch- case statement, while continue statement is not supported yet, however the basis methodology is able to embed these features as well. This thesis has been published in [SP1, SP5, SP6, SP7, SP8, SP10, SP11]

Thesis 2: I have worked out a new methodology, which enables parallel operation admitting competition cases with a run-time resolution so that the paralleled sections have a very fine – even memory access level - granularity and their deadlock and stagnation free function is granted.

This methodology distinguishes itself from today’s similar solutions that it enables paralleling at a very high granularity and it allows and then resolves competitions for

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resources. Competition resolution is done by prioritisation, but this – thank to a “competition closing” solution – does not lead to stagnation or deadlock even if a high priority section would initiate consecutive accesses. This methodology is evenly applicable to allow reading an array – in competition - for multiple clients, or to mutually exclude any number of blocks in parallel functioning clients (like block, process, task, application). Communication among parallel functioning parts can be solved by commonly accessible variables. This thesis has been published in [SP2, SP9]

Thesis 3: I have worked out a new methodology that enables pipelining in C language defined hardware.

The methodology distinguishes itself from known procedures that the architecture of the pipeline is scalable at a high granularity (number of stages, their size, their boundaries), unbalanced pipeline structure is allowed, data dependent or stage-wise different execution time is allowed and following a pipeline jam of any duration the pipeline resumes without error. Further advantage is that any variable (by type or scope) can be used (for read and write) within the pipeline. This thesis has been published in [SP2]

Thesis 4: I have worked out such an IP, which like RISC processors, but their principles taken ad absurdum, realises stored program function having one single kind of instruction on a way that it can be programmed on high-level language and it is extremly scalable.

The IP worked out (intellectual property – parametrisable, scalable, integrative, reusable functional unit defined by its description) can be used as the microprocessor of the software-realised partition of the functions of a hardware-software co-design, even in multiprocessor environment. The IP can even be programmed on a high-level language, as it can use a stack memory (for data storage and subroutine administration), which memory is freely placed and sized within the main memory, serving code and data storage. Thank to its basis principle it can be scaled extremely, so it is applicable from substituting combinatorial networks upto running high-level programs (e.g. C/C++). Its simple, low area structure qualifies it for mass usage on one single chip, which supports well multiprocessor and multiprocessor plus purpose built hardware applications. The solution proposed by this thesis is a microprocessor architecture having one single instruction. This is the final end of the development path marked by CISC and – later – RISC processors, a SISC (single instruction set computer). The single instruction is the move instruction, which – with the help of functional registers provided by the architecture – enables the operational diversity usual at known microprocessors. In this architecture not operations achieve data movements, but data movements achieve operations. This thesis has been published in [SP3, SP4]

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4. REFERENCES Literature used during the workout of the dissertation

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[154] A. Church, "An unsolvable problem of elementary number theory", American Journal of Mathematics v. 58, pp. 345–363., 1936.06.30 [155] A. Church, "A note on the Entscheidungsproblem", Journal of Symbolic Logic v. 1, n. 1, & v. 3, n. 3., 1936.06.30 [156] S. Kleene, "Introduction to Metamathematics", North-Holland, ISBN-0-7204-2103-9, 1952.06.30

[157] P. Arató, T. Kandár, B. Csák, "Optimizing Algorithms for System Level Synthesis", INES2002 IEEE, Selected Publications of INES 2002 Conference, pp. 373-384. ISBN 3-935798-25-3, 2003.11.15 [158] P. Arató, B. Csák, "Pipeline Mode in C-based Direct Hardware Implementation", Periodica Polytechnica, elfogadva, megjelenésre vár, 2009.07.15 [159] B. Csák, "Egyutasítású Mikroprocesszor Architektúra", Szabadalmi Közlöny, P00 03913, 2002.05.15 [160] B. Csák, "HU 224 576, Mikroprocesszor Architektúra", Magyar Szabadalmi Közlöny, 2005.11.28 [161] P. Arató, B. Csák, T. Kandár, Z. Mohr, "Some Components Of A New Methodology Of System-Level Synthesis", INES2002 IEEE, The 6th IEEE INES2002, Hotel Adriatic, Opatija, Croatia, 2002.05.26 [162] P. Arató, B. Csák, "Hardware Software Co-Design Based On Standard C-Language Source Code", ICCC03 IEEE, Siófok, Hungary, 2003.08.29 [163] P. Arató, B. Csák, "Programming Language Based Definition of Application Oriented Hardware", WISP03 IEEE, Budapest, Hungary, 2003.09.04

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[164] P. Arató, B. Csák, "Hardware Definition Based on Standard C-language Source Code", FDL03 ECSI, Frankfurt, Germany, 2003.09.23 [165] P. Arató, B. Csák, "Solutions for Competition Cases in C-Language Defined Application Specific Hardware", ICCC04 IEEE, Vienna, Austria, 2004.08.30 [166] B. Csák, T. Kandár, Z. Mohr, "Új Módszerek A Rendszerszintű Szintézisben", microCAD 2002, Miskolc, Hungary, 2002.03.07 [167] P. Arató, B. Csák, "Programming Language Based Definition of Application Oriented Hardware", Proceedings of IEEE WISP03 (ISBN: 0-7803-7864-4), Budapest, Hungary, 2003.09.04 5. OWN PUBLICATIONS Article in edited book [SP1] Péter Arató, Tibor Kandár, Bence Csák, „Optimizing Algorithms for System Level Synthesis”, Intelligent Systems at the Service of Mankind, Selected Publications of INES 2002 Conference, Editors: Wilfried Elmenreich, J. Tenreiro Machado, Imre J. Rudas, UBooks Volume I, November, 2003. pp. 373-384. ISBN 3-935798-25-3

Journal article in foreign-language issued in Hungary [SP2] Péter Arató, Bence Csák, „PIPELINE MODE IN C-BASED DIRECT HARDWARE IMPLEMENTATION”, Periodica Polytechnica, elfogadva, megjelenés 2009 folyamán

Patent application issued in Hungary [SP3] Csák Bence, „Egyutasítású Mikroprocesszor Architektúra”, Szabadalmi Közlöny, P00 03913, 2002 Május

Patent granted in Hungary [SP4] Csák Bence, „Mikroprocesszor Architektúra”, Szabadalmi Közlöny, HU224 576, 2005.11.28

Conference presentation in foreign-language published in the conference’s proceedings [SP5] Dr. Péter Arató, Bence Csák, Tibor Kandár, Zoltán Mohr, „Some Components Of A New Methodology Of System-Level Synthesis”, INES2002, The 6th IEEE International Conference On Intelligent Engineering Systems, Hotel Adriatic, Opatija, Croatia, May 26-28, 2002.

[SP6] Dr. Péter Arató, Bence Csák, „Hardware Software Co-Design Based On Standard C- Language Source Code”, ICCC03, IEEE International Conference on Computational Cybernetics, Siófok, Hungary, August 29-31, 2003.

[SP7] Dr. Péter Arató, Bence Csák, „Programming Language Based Definition of Application Oriented Hardware”, WISP03, 2003 IEEE International Symposium on Intelligent Signal Processing, Hotel Gellért, Budapest, Hungary, September 4-6, 2003., ISBN: 0-7803-7864-4

[SP8] Dr. Péter Arató, Bence Csák, „Hardware Definition Based on Standard C-language Source Code”, FDL03, 2003 ECSI Forum on Specification & Design Languages, University of Frankfurt, Germany, September 23-26, 2003.

[SP9] Dr. Péter Arató, Bence Csák, „Solutions for Competition Cases in C-Language Defined Application Specific Hardware”, ICCC04, 2004 IEEE International Conference on Computational Cybernetics, Vienna University of Technology, Austria, 30 August - 1 September, 2004

[SP11] Péter Arató, Bence Csák: Programming Language Based Definition of Application Oriented Hardware, Hardware-Software Partitioning in Embedded System Design, Proceedings of IEEE International Symposium on Intelligent Signal Processing (ISBN: 0-7803-7864-4), Budapest, Hungary, 4-6. Sep. 2003

Conference presentation in hungarian [SP10] Csák Bence, Kandár Tibor, Mohr Zoltán, Új Módszerek A Rendszerszintű Szintézisben, microCAD’ 2002 Nemzetközi Tudományos Konferencia, Miskolc, 2002. március 7-8.

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6. PUBLICATIONS ON OTHER FIELDS International patents or patent applications

[IP1] DISK BRAKE COMPRISING ELECTRIC MOTOR-DRIVEN ADJUSTING DEVICES AND METHOD FOR BRAKING USING THE PARKING BRAKE Inventor: BAUMGARTNER JOHANN (DE); GERUM EDUARD (DE); (+9) Applicant: KNORR BREMSE SYSTEME (DE) EC: F16D65/14P8F; F16D65/14B6B2; (+2) IPC: F16D65/18; F16D65/18 Publication info: EP1893882 - 2008-03-05

[IP2] Clamp device Inventor: CSAK BENCE (HU); HERGES MICHAEL (DE); (+1) Applicant: KNORR BREMSE SYSTEME (DE) EC: F16D65/14B6B; F16D65/14C; (+5) IPC: F16D63/00; F16D63/00 Publication info: US2007251773 - 2007-11-01

[IP3] Parking brake Inventor: KIENER WOLFGANG (DE); LANGE STEPHAN (DE); (+9) Applicant: KNORR BREMSE SYSTEME (DE) EC: F16D49/00; B60T1/00B; (+3) IPC: F16D55/00; F16D55/00 Publication info: US2007246309 - 2007-10-25

[IP4] Braking system for vehicles, in particular utility vehicles, comprising at least two separate electronic braking control circuits Inventor: GERUM EDUARD (DE); BROCH WALTER (DE); (+2) Applicant: KNORR BREMSE SYSTEME (DE) EC: B60T13/66 IPC: B60T13/00; B60T13/66; B60T13/00 (+1) Publication info: US2007170774 - 2007-07-26

[IP5] Function or wear monitoring device for components of utility vehicle, has sensors on spring- mounted axle for measuring oscillations in one or more directions Inventor: CSAK BENCE (HU) Applicant: KNORR BREMSE SYSTEME (DE) EC: G01M13/02M; G01M17/04 IPC: B60R16/02; G01M13/02; G01M17/04 (+5) Publication info: DE102004025154 - 2005-12-15

[IP6] Temperature sensing device for rotating vehicle components. Inventor: CSAK BENCE (HU) Applicant: KNORR BREMSE SYSTEME (DE) EC: F16D66/02B2B2 IPC: F16D66/02; F16D66/00; F16D66/00 (+2) Publication info: EP1564431 - 2005-08-17

[IP7] Trailer and semi-trailer braking system Inventor: CSAK BENCE (HU); HEILMANN HARRO (DE); (+3) Applicant: KNORR BREMSE SYSTEME (DE) EC: B60T13/68B; B60T17/02 IPC: B60T13/00; B60T13/68; B60T17/02 (+6) Publication info: US2005179314 - 2005-08-18

[IP8] Trailer and semitrailer brake valve with integrated control for the air spring Inventor: CSAK BENCE (HU); HEILMANN HARRO (DE); (+3) Applicant: DAIMLERCHRYSLER (DE) EC: B60G7/00A; B60G9/00; (+5) IPC: B60G7/00; B60G9/00; B60G11/30 (+10) Publication info: US2005162004 - 2005-07-28

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[IP9] TRANSPORT TRIGGERED MICROPROCESSOR ARCHITECTURE Inventor: CSAK BENCE (HU) Applicant: CSAK BENCE (HU) EC: G06F9/38T IPC: G06F9/38; G06F9/38; (IPC1-7): G06F9/38 Publication info: WO03083648 - 2003-10-09

[IP10] ONE COMMAND MICROPROCESSOR ARCHITECTURE Inventor: CSAK BENCE (HU) Applicant: CSAK BENCE (HU) EC: IPC: G06F9/30; G06F9/30; (IPC1-7): G06F9/30 Publication info: HU0003913 - 2002-05-29

[IP11] METHOD OF DETERMINATION WORKING CAPACITY OF A WORKING PERSON Inventor: PALOTAS LASZLO (HU); KOVACS MIHALY (HU); (+13) Applicant: HONVEDELMI MINISZTERIUM HADITE (HU) EC: IPC: A61B5/00; A61B5/16; A61B5/22 (+5)

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