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Direct Hardware Generation from High-Level Programming Language

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Direct Hardware Generation from High-Level Programming Language Budapest University of Technology and Economics Department of Control Engineering and Information Technology DIRECT HARDWARE GENERATION FROM HIGH-LEVEL PROGRAMMING LANGUAGE Ph.D. thesis Csák, Bence Consultant: Prof. Dr. Arató, Péter Full member of Hungarian Academy of Sciences Budapest 2009 Tezisfuzet_EN.doc 1/12 1. INTRODUCTION The ever increasing speed and complexity demand of control applications is driving developers to work out newer and newer solutions for ages. In the course of this arrived mankind to the point where after purely mechanical components, electromechanical, electrical and later electronic components are used in the more and more complex control and computing machines. For the sake of flexibility of control systems even in the times of purely mechanical systems, program control has been created, which then spread over to electromechanical and later electronic systems. Development of programming has accelerated truly in the times of electronic computers. Today programs are written at an abstraction level from which no single step is enough to get to the level, where the first programs were written. This high level ensures that extremely big software systems can operate even safety critical systems without malfunction. The unquenchable desire for even higher computation power - despite of the development of software engineering - forces that certain tasks are solved by purpose built hardware. In case of a given task the desired performance is assured on a cost-effective way by composing the system of application specific hardware and CPU based software. Optimal partition of software and hardware parts is aided by the methodology of hardware-software co-design. Here, system specification is given on a standard symbolic language, from which a given partitioning procedure derives hardware and software components. This symbolic language is usually C, as the sphere of users is rather extensive, it is applicable to describe digital systems and it provides an “executable specification”, so the specification itself is testable. This thesis introduces a methodology, which provides components and building rules for the hardware-software mapping of digital systems. The Department of Control Engineering and Information Technology of the Budapest University of Technology and Economics is researching for years in the field of hardware- software co-design and hardware mapping of computation-intensive tasks. This thesis belongs to this environment, however emphasis is put onto hardware mapping of high- level language defined, general (calculation and control-intensive) tasks and provides a novel, extremely scalable microprocessor architecture for software mapping. Based on the course of the thesis, literature in connection with C-based design and sub- RISC processors have to be regarded. 2. RESEARCH GOALS The main goals of the research were: 1) Workout of a direct C-HW mapping methodology, which – compared to existing methodologies – supports more general applications and is less restrictive. Enables the systematic translation of a C coded algorithm into RTL described hardware so that the developer does not need to posess complex hardware knowledge and still he can optimise on the speed-economy scale the resulting hardware. 2) Enhancement of the methodology by 1) so that parallel function is supported even with the permission of competition cases and with the resolution of those. Tezisfuzet_EN.doc 2/12 3) Enhancement of the methodology by 1) and 2) so that pipelining is enabled. Construction and sectioning of the pipeline is solved on a way that it does not need complex apparatus and enables extremes in sectioning and extremes in timely behaviour. 4) Enhancement of the methodology by 1), 2) and 3) – as hardware mapping methodology – by a microprocessor architecture so that system components to be mapped into software can have a widely scalable, application oriented microprocessor, which can also be programmed on high-level languages. By reaching the research goals an electronic system – consisting of hardware and software components - can be created, which provides a high degree of freedom – especially in the system-on-chip category – to partitioning procedures. The methodology of this thesis fits very well the demand today to realise greater and greater processing performance on a chip. 3. NEW RESULTS Thesis 1: I have worked out a new model and direct systematic design procedure, which maps a high-level language (C) program to a hardware structure. This methodology is able to map C codes with slight limitations, using a parser being not part of this thesis, into hardware structures. The output of the procedure is a block scheme, or VHDL code supporting a wider range of FPGA or ASIC technologies. The resulting synchronous hardware uses one single-phase clock signal. The C-HW mapping is systematic, no expert database is needed. An expression or statement can be of any complexity. Execution of those need one or more clock signals, which amount is known in compile time. Variables are multi assignment variables. Simple variables and non-array variables can be accessed concurrently at any depth. Use of pointers is allowed, as well as even dynamic datatypes. Function type variables are applicable. Hardware modules, representing functions can be “called” from multiple points with no theoretical limit, but these can be used also as hardware macros. Parameter of a function can also be another function. Recursive function call – with some limitation – is enabled. The methodology could use stack memories, but such has not been worked out yet. At the current workout brake statement can only be used in conjunction with the switch- case statement, while continue statement is not supported yet, however the basis methodology is able to embed these features as well. This thesis has been published in [SP1, SP5, SP6, SP7, SP8, SP10, SP11] Thesis 2: I have worked out a new methodology, which enables parallel operation admitting competition cases with a run-time resolution so that the paralleled sections have a very fine – even memory access level - granularity and their deadlock and stagnation free function is granted. This methodology distinguishes itself from today’s similar solutions that it enables paralleling at a very high granularity and it allows and then resolves competitions for Tezisfuzet_EN.doc 3/12 resources. Competition resolution is done by prioritisation, but this – thank to a “competition closing” solution – does not lead to stagnation or deadlock even if a high priority section would initiate consecutive accesses. This methodology is evenly applicable to allow reading an array – in competition - for multiple clients, or to mutually exclude any number of blocks in parallel functioning clients (like block, process, task, application). Communication among parallel functioning parts can be solved by commonly accessible variables. This thesis has been published in [SP2, SP9] Thesis 3: I have worked out a new methodology that enables pipelining in C language defined hardware. The methodology distinguishes itself from known procedures that the architecture of the pipeline is scalable at a high granularity (number of stages, their size, their boundaries), unbalanced pipeline structure is allowed, data dependent or stage-wise different execution time is allowed and following a pipeline jam of any duration the pipeline resumes without error. Further advantage is that any variable (by type or scope) can be used (for read and write) within the pipeline. This thesis has been published in [SP2] Thesis 4: I have worked out such an IP, which like RISC processors, but their principles taken ad absurdum, realises stored program function having one single kind of instruction on a way that it can be programmed on high-level language and it is extremly scalable. The IP worked out (intellectual property – parametrisable, scalable, integrative, reusable functional unit defined by its description) can be used as the microprocessor of the software-realised partition of the functions of a hardware-software co-design, even in multi- processor environment. The IP can even be programmed on a high-level language, as it can use a stack memory (for data storage and subroutine administration), which memory is freely placed and sized within the main memory, serving code and data storage. Thank to its basis principle it can be scaled extremely, so it is applicable from substituting combinatorial networks upto running high-level programs (e.g. C/C++). Its simple, low area structure qualifies it for mass usage on one single chip, which supports well multiprocessor and multiprocessor plus purpose built hardware applications. The solution proposed by this thesis is a microprocessor architecture having one single instruction. This is the final end of the development path marked by CISC and – later – RISC processors, a SISC (single instruction set computer). The single instruction is the move instruction, which – with the help of functional registers provided by the architecture – enables the operational diversity usual at known microprocessors. In this architecture not operations achieve data movements, but data movements achieve operations. This thesis has been published in [SP3, SP4] Tezisfuzet_EN.doc 4/12 4. REFERENCES Literature used during the workout of the dissertation [1] R. Dömer, A. Gerstlauer, D. Gajski, "SpecC Language Reference Manual V2.0", 2002.12.12 [2] Andreas Gerstlauer, "The SpecC Methodology", University of California, Irvine, 2001 [3]
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