International Journal of Industrial Electronics and Electrical Engineering, ISSN(p): 2347-6982, ISSN(e): 2349-204X Volume-6, Issue-3, Mar.-2018, http://ijieee.org.in REALIZATION OF ALL LOGIC GATES WITH NAND GATE USING OPTISPICE

1SONALI DASH, 2ABHIJEET SINGH, 3ANKIT MISHRA, 4DHEERAJ ANAND

1,2,3,4Department of Electronics and Telecommunication Engineering, Bharati Vidyapeeth (Deemed To Be) University, College of Engineering, Pune, Maharashtra

Abstract - This study implements NAND gate as universal gate to realize other gates (XOR, OR, AND, NOT) using Hierarchical model in OptiSpice Software.

Keywords - Logical gate, Universal gate, Hierarchical model, Sub-circuits

I. INTRODUCTION multiplexers, ALUs(Arithmetic Logic Units). They may use memory or can be memory-less. Currently Logic gates are the fundamental block of any digital logic gates are also being realized using Field Effect circuit. They are used to implement any Boolean Transistors(FETs), in general, and Metal Oxide function. They have one or more binary input and Semiconductor Field Effect Transistor(MOSFETs), in produce a single output. It represents a value using a particular. binary low(0) or binary high(1). Charles Sanders Peirce can be regarded as the father of The output of a gate can be used to drive the input of Universal gates as he was the one who first realised any other gate. But, there is a limit to it, which is their implementation (during 1880)[3]. called ‘fan-out’ limit. Hence, output of any gate can drive only finite number of gates. Initially, relays were used to realize logic gates which later got replaced by vacuum tubes. Later, transistors Similarly, there is also a component of delay in the replaced vaccum tubes to implement logic gates. Now, circuits. In cascasded circuits, it is equal to the sum of programmable logic gates are also available which can individual circuits. This leads to delay in high speed be programmed using FPGA(Field Programmable circuits which employ multiple gates. Also, if there are Gate Array).The advantage of programmable logic multiple inputs in the circuit, it can lead to more delay. gates is that a large number of gates can be integrated Universal gates are used to implement any of the other into a single package. Logic gates can also be gate type [1]. They do not need any other gate to simulated using softwares such as OptiSpice. implement the circuit. There are two universal gates. NAND and NOR. NAND gate is the complement of Semi-conductor logic gates are used widely as they output of an AND gate whereas NOR gate is the also act as high voltage amplifier, hence, limiting the output of the complement of a NOR gate. The losses in propagation. universal gates are economical and their fabrication is also easier to implement than other gates, Currently. Nano-technology is also being used to implement logic gates. Active research is going on in The NAND gate exhibits the property of functional the field of molecular logic gates. completeness [2].It can be used to get the truth table of any other gate, i.e. ,implementation of any gate and it’s III. THEORY relative truth table can be achieved. A logic gate is an elementary building block of a It is also called Sheffer stroke. It yields true if any digital circuit. Most logic gates have 2 inputs and one condition is false, and false if all conditions are true. output. At any given moment, each terminal is in one The term ‘alternate denial’ is also used to represent a among the 2 binary conditions low (0) or high NAND gate. (1), delineated by totally different voltage levels. The logic state of a terminal can, and usually will, II. LITERATURE SURVEY change often, because the circuit processes data. In most logic gates, the low state is close to zero volts (0 The logic gates are the physical implementation V), whereas the high state is close to 5 volts positive Binary logic. Traditionally, they are being (+5 V). There are seven basic logic gates: AND, OR, implemented using diodes or transistors as their XOR, NOT, NAND, NOR, and XNOR. primary device which act as electronic switch. All mathematical operations and algorithms can be The and gate is so named because, if zero is implemented using Boolean logic and hence logic named "false" and one is named "true," the gate gates. The logic gates may include multiplexers, de- acts within the same manner as the logical "and"

Realization of all Logic Gates with NAND Gate using OptiSpice

9 International Journal of Industrial Electronics and Electrical Engineering, ISSN(p): 2347-6982, ISSN(e): 2349-204X Volume-6, Issue-3, Mar.-2018, http://ijieee.org.in operator. The subsequent illustration and table show A logical inverter, also called as NOT gate to the circuit image and logic combinations for an AND differentiate it from other types of electronic inverter gate. (In the image, the input terminals are at left and devices, has only one input. It reverses the logic state. the output terminal is at right.) The output is “true” when each inputs are "true." Otherwise, the output is "false."

Inverter or NOT gate

Input Output AND gate 1 0

Input 1 Input 2 Output 0 1

0 0 0 The NAND gate operates as an AND gate followed by 0 1 0 a NOT gate. It acts in the manner of the logical 1 0 0 operation "and" followed by negation. The output is "false" if both inputs are "true." Otherwise, the output 1 1 1 is "true."

The OR gate gets its name from the very fact that it behaves like the fashion of the logical inclusive "or". The output is "true" if either or each of the input is "true". If each input is "false," then the output NAND gate is "false." Input 1 Input 2 Output 0 0 1 0 1 1 OR gate 1 0 1

1 1 0 Input 1 Input 2 Output

0 0 0 CMOS (complementary metal-oxide semiconductor) is 0 1 1 the semiconductor technology employed in the 1 0 1 transistors that are manufactured into most of today’s computer microchips. 1 1 1 Semiconductors are manufactured from Si and Ge, The XOR (exclusive- OR) gate acts within the same materials that "sort of" conduct manner as the logical "either/or". The output is "true" electricity, however not enthusiastically. Areas of if either, but not each, of the inputs are "true". The these materials that are "doped" by adding impurities output is "false" if each input is "false" or become complete conductors of if each input are "true". A different way of viewing either additional electrons with a negative charge (N- this circuit is to watch that the output is one if the type transistors) or of positive charge carriers (P-type inputs are different, however zero if the transistors). In CMOS technology, each sort inputs are identical. of transistors are employed in a complementary way to form a current gate that forms an efficient means of electrical management. CMOS transistors use nearly no power when not needed because the current direction changes faster, however, the XOR gate transistors become hot. This characteristic tends to limit the speed at which microprocessors can operate. Input 1 Input 2 Output 0 0 0 IV. RESULTS AND ANALYSIS

0 1 1 NAND is used as Universal gate to form all the gates 1 0 1 using Hierarchy in OptiSpice . While NAND itself is 1 1 0 simulated using CMOS as follows:

Realization of all Logic Gates with NAND Gate using OptiSpice

10 International Journal of Industrial Electronics and Electrical Engineering, ISSN(p): 2347-6982, ISSN(e): 2349-204X Volume-6, Issue-3, Mar.-2018, http://ijieee.org.in After launching the Waveform Viewer, we get the following output waveform:

NAND implementation using CMOS OUTPUT for XOR

The two V input values are given as follows: pulse Similarly, AND gate is taken as Parent of the heirarchy Two Pulse Voltages are given as inputsas well as a DC which is followed by sub-circuits : bias is provied with 15V.The values of Pulse Voltages are as follows: Vpulse 1 is given with initial volage of 0.0 V with Pulse value of 5V.Time delay is of 5ns. Pulse width is of 4ns and period is of 8ns. Vpulse 2 has initial value of 0.0V and Pulse voltage of 5V with 0 time delay. Pulse width is of 2ns and period is of 4ns.

XOR implementation as parent cicuit of heirarchy:

Parent circuit of AND

While sub-cicuit of AND gate is formed by NAND in the second level of heirarchy:

XOR parent cicuit

Furthermore, Sub-cicuit of XOR from NAND is formed:

Output waverform after running simulation of NAND:

Realization of all Logic Gates with NAND Gate using OptiSpice

11 International Journal of Industrial Electronics and Electrical Engineering, ISSN(p): 2347-6982, ISSN(e): 2349-204X Volume-6, Issue-3, Mar.-2018, http://ijieee.org.in

NAND output

Now, NOT gate is taken as parent cicuit of heirarchy. NOT gate has an important role in optical circuits as it is used as switch. Now, OR gate is taken as parent of the heirarchy which is to be implemented using sub-circuits:

Parent circuit of OR

Parent circuit of NOT In the sub-circuit layer,OR is implemented using universal NAND gate: NAND gate is used in the sub-circuit to form a NOT gate.

Finally ,Output waveform is noted down: Output waveform of OR gate is noted down:

Realization of all Logic Gates with NAND Gate using OptiSpice

12 International Journal of Industrial Electronics and Electrical Engineering, ISSN(p): 2347-6982, ISSN(e): 2349-204X Volume-6, Issue-3, Mar.-2018, http://ijieee.org.in CONCLUSION

By implementing Heirarchical logic to form all logic gates in OptiSpice, we encounter NOT gate formed through universal NAND gate.This NOT gate is to be further implemented as SWITCH in Optical Laser circuits.

REFERENCES

[1] J. Franke, J. Zeitler, and T. Reitberger, “A novel engineering process for spatial opto-mechatronic applications,” CIRP Annals-Manufacturing Technology, 2016. [2] M. Heins et al., “Design Flow Automation for Silicon Photonics: Challenges, Collaboration, and Standardization,” in Silicon Photonics III, Springer, 2016, pp. 99–156. OR output [3] M. Vladescu and P. Schiopu, “Advanced educational program in optoelectronics for undergraduates and graduates in electronics,” in Advanced Topics in Optoelectronics, Microelectronics, and Nanotechnologies 2014, 2015, p. 92580B–92580B.

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Realization of all Logic Gates with NAND Gate using OptiSpice

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