Real-Time Operating System (RTOS)
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AMD Athlon™ Processor X86 Code Optimization Guide
AMD AthlonTM Processor x86 Code Optimization Guide © 2000 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other applica- tion in which the failure of AMD’s product could create a situation where per- sonal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD logo, AMD Athlon, K6, 3DNow!, and combinations thereof, AMD-751, K86, and Super7 are trademarks, and AMD-K6 is a registered trademark of Advanced Micro Devices, Inc. Microsoft, Windows, and Windows NT are registered trademarks of Microsoft Corporation. -
Last Time Today Response Time Vs. RM Computing Response Time More Second-Priority Task I Response Time
Last Time Today Priority-based scheduling Response time analysis Static priorities Blocking terms Dynamic priorities Priority inversion Schedulable utilization And solutions Rate monotonic rule: Keep utilization below 69% Release jitter Other extensions Response Time vs. RM Computing Response Time Rate monotonic result WC response time of highest priority task R Tells us that a broad class of embedded systems meet their 1 time constraints: R1 = C 1 • Scheduled using fixed priorities with RM or DM priority Hopefully obvious assignment • Total utilization not above 69% WC response time of second-priority task R 2 However, doesn’t give very good feedback about what is Case 1: R 2 ≤ T1 going on with a specific system • R2 = C 2 + C 1 Response time analysis R T T Tells us for each task, what is the longest time between R1 2 1 2 when it is released and when it finishes Then these can be compared with deadlines 1 1 Gives insight into how close the system is to meeting / not 2 meeting its deadline Is more precise (rejects fewer systems) More Second-Priority Task i Response Time Case 2: T 1 < R 2 ≤ 2T 1 General case: R = C + 2C Ri 2 2 1 Ri = Ci + ∑ Cj j ∀j∈hp (i) T R1 T1 R2 2T 1 T2 1 1 1 hp(i) is the set of tasks with priority higher than I 2 2 Only higher-priority tasks can delay a task Case 3: 2T 1 < R 2 ≤ 3T 1 Problem with using this equation in practice? R2 = C 2 + 3C 1 General case of the second-priority task: R2 = C 2 + ceiling ( R 2 / T 1 ) C 1 1 Computing Response Times Response Time Example Rewrite -
Preemption-Based Avoidance of Priority Inversion for Java
Preemption-Based Avoidance of Priority Inversion for Java Adam Welc Antony L. Hosking Suresh Jagannathan [email protected] [email protected] [email protected] Department of Computer Sciences Purdue University West Lafayette, IN 47906 Abstract their actions via mutual exclusion locks. The resulting programming model is reasonably simple, Priority inversion occurs in concurrent programs when but unfortunately unwieldy for large-scale applications. A low-priority threads hold shared resources needed by some significant problem with using low-level, lock-based syn- high-priority thread, causing them to block indefinitely. chronization primitives is priority inversion. We propose a Shared resources are usually guarded by low-level syn- new solution for priority inversion that exploits close coop- chronization primitives such as mutual-exclusion locks, eration between the compiler and the run-time system. Our semaphores, or monitors. There are two existing solu- approach is applicable to any language that offers the fol- tions to priority inversion. The first, establishing high- lowing mechanisms: level scheduling invariants over synchronization primitives to eliminate priority inversion a priori, is difficult in practice • Multithreading: concurrent threads of control execut- and undecidable in general. Alternatively, run-time avoid- ing over objects in a shared address space. ance mechanisms such as priority inheritance still force • Synchronized sections: lexically-delimited blocks high-priority threads to wait until desired resources are re- of code, guarded by dynamically-scoped monitors. leased. Threads synchronize on a given monitor, acquiring it We describe a novel compiler and run-time solution to on entry to the block and releasing it on exit. -
Real-Time Operating Systems (RTOS)
Real-Time Operating Systems (RTOS) 101 Real-Time System Characteristics RTOS Architecture Rate Monotonic • A real-time system is a computer system which is required by its specification to adhere to: Scheduling (RMS) – functional requirements (behavior) • A priority is assigned based on the inverse of its pe- – temporal requirements (timing constraints, deadlines) riod • Specific deterministic timing (temporal ) requirements – Shorter execution periods = higher priority – “Deterministic" timing means that RTOS services consume only – Longer execution periods = lower priority known and expected amounts of time. • Common way to assign fixed priorities • Small size (footprint) – If there is a fixed-priority schedule that meets all dead- lines, then RMS will produce a feasible schedule Types of Real-Time Systems • Simple to understand and implement • A generic real-time system requires that results be produced RTOS Task Services • P1 is assigned a higher priority than P2. within a specified deadline period. • An embedded system is a computing device that is part of a • Scheduling and Dispatching larger system. • Inter-task Communication • A safety-critical system is a real-time system with catastro- phic results in case of failure. • Memory System Management • A hard real-time system guarantees that real-time tasks be Earliest Deadline First (EDF) • Input / Output System Management completed within their required deadlines. Failure to meet a single deadline may lead to a critical catastrophic system • Scheduling Time Management & Timers failure such as physical damage or loss of life. • Priorities are assigned according to deadlines: • Error Management • A firm real-time system tolerates a low occurrence of missing – the earlier the deadline, the higher the priority a deadline. -
A PROGRAMMABLE COMPUTER INTERFACE for CAMAC F by Robert W
NASA TECHNICAL NOTE NASA TN D-7148 A PROGRAMMABLE COMPUTER INTERFACE FOR CAMAC f by Robert W. Bercaw, Theodore E. Fessler, \ and Jeffrey M. Arnold Lewis Research Center Cleveland, Ohio 44135 NATIONAL AERONAUTICS AND SPACE ADMINISTRATION • WASHINGTON, D. C. • MARCH 1973 1. Report No. 2. Government Accession No. 3. Recipient's Catalog No. NASA TN D-7148 4. Title and Subtitle 5. Report Date March 1973 A PROGRAMMABLE COMPUTER INTERFACE FOR CAMAC 6. Performing Organization Code 7. Author(s) 8. Performing Organization Report No. Robert W. Bercaw, Theodore E. Fessler, and Jeffrey M. Arnold E-6957 10. Work Unit No. 9. Performing Organization Name and Address 503-10 Lewis Research Center 11. Contract or Grant No. National Aeronautics and Space Administration Cleveland, Ohio 44135 13. Type of Report and Period Covered 12. Sponsoring Agency Name and Address Technical Note National Aeronautics and Space Administration 14. Sponsoring Agency Code Washington, B.C. 20546 15. Supplementary Notes 16. Abstract An interface has been developed for CAMAC instrumentation systems that implements data transfers controlled either by the computer CPU or by an autonomous (data-channel) processor in the interface unit. The data channel processor executes programs stored in the computer memory. These programs consist of standard CAMAC module commands plus special control characters and commands for the processor itself. The interface was built for the PDP-15 computer, which has an 18-bit word structure, but both 18- and 24-bit data transfers can be made. A software system has been written that exploits the many features of the processor. 17. Key Words (Suggested by Author(s)) 18. -
Application Note Saving Data During a Power Failure Using the Dataflash® E-Series Family
Saving Data During a Power Failure Using the DataFlash® E-Series Family Application Note Saving Data During a Power Failure Using the DataFlash® E-Series Family Abstract This application note is intended to provide readers with information on how to save critical data to the Flash memory of DataFlash E-Series devices in the event of a power failure. The power failure is simulated by removing power to the devices. This document does not discuss how the power failure is detected, how the microcontroller may respond to the failure, or how the power rail is controlled for both the DataFlash device and the microcontroller. Product Highlights • Single 3V Read/Write Operation (1.65V - 3.6V Supply Range) • SPI Mode 0 and Mode 3 Compatible • Fast Read Access Times: 85 MHz Maximum Clock Frequency • Individual Hardware and Software Sector Protection • Security: 128-byte Register • JEDEC Standard Manufacturer and Device ID Read • Endurance: 100,000 Program/Erase Cycles per Page Minimum • Data Retention: 20 Years • Packaging Options: SOIC, DFN, WLCSP, Die/Wafer • Green (Pb/Halide-free) Packaging Options Application Note 114 11-Dec-2020 AN114 1 of 13 © 2020 Dialog Semiconductor Saving Data During a Power Failure Using the DataFlash® E-Series Family Revision History Revision Date Description A0 11-Dec-2020 Initial Release Application Note 114 11-Dec-2020 AN114 2 of 13 © 2020 Dialog Semiconductor Saving Data During a Power Failure Using the DataFlash® E-Series Family 1 Introduction The DataFlash E-series family of Flash memory devices are often used in applications such as server configuration, data logging, event counters and failure/error/status loggers. -
14-/12-Bit, 250MSPS, Ultralow-Power ADC with Analog Buffers Check for Samples: ADS41B29, ADS41B49
ADS41B29 ADS41B49 www.ti.com SBAS486E – NOVEMBER 2009–REVISED JULY 2012 14-/12-Bit, 250MSPS, Ultralow-Power ADC with Analog Buffers Check for Samples: ADS41B29, ADS41B49 1FEATURES DESCRIPTION The ADS41B29/B49 are members of the ultralow- 23• ADS41B49: 14-Bit, 250MSPS ADS41B29: 12-Bit, 250MSPS power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. • Integrated High-Impedance These devices use innovative design techniques to Analog Input Buffer: achieve high dynamic performance, while consuming – Input Capacitance: 2pF extremely low power. The analog input pins have – 200MHz Input Resistance: 3kΩ buffers, with benefits of constant performance and input impedance across a wide frequency range. The • Maximum Sample Rate: 250MSPS devices are well-suited for multi-carrier, wide • Ultralow Power: bandwidth communications applications such as PA – 1.8V Analog Power: 180mW linearization. – 3.3V Buffer Power: 96mW The ADS41B49/29 have features such as digital gain – I/O Power: 135mW (DDR LVDS) and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input • High Dynamic Performance: ranges, especially at high input frequencies. The – SNR: 69dBFS at 170MHz integrated dc offset correction loop can be used to – SFDR: 82.5dBc at 170MHz estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at • Output Interface: scaled-down power with no loss in performance. – Double Data Rate (DDR) LVDS with Programmable Swing and Strength: The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel – Standard Swing: 350mV CMOS digital output interfaces. The low data rate of – Low Swing: 200mV the DDR LVDS interface (maximum 500MBPS) – Default Strength: 100Ω Termination makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. -
Parallelization Hardware Architecture Type to Enter Text
Parallelization Hardware architecture Type to enter text Delft University of Technology Challenge the future Contents • Introduction • Classification of systems • Topology • Clusters and Grid • Fun Hardware 2 hybrid parallel vector superscalar scalar 3 Why Parallel Computing Primary reasons: • Save time • Solve larger problems • Provide concurrency (do multiple things at the same time) Classification of HPC hardware • Architecture • Memory organization 5 1st Classification: Architecture • There are several different methods used to classify computers • No single taxonomy fits all designs • Flynn's taxonomy uses the relationship of program instructions to program data • SISD - Single Instruction, Single Data Stream • SIMD - Single Instruction, Multiple Data Stream • MISD - Multiple Instruction, Single Data Stream • MIMD - Multiple Instruction, Multiple Data Stream 6 Flynn’s Taxonomy • SISD: single instruction and single data stream: uniprocessor • SIMD: vector architectures: lower flexibility • MISD: no commercial multiprocessor: imagine data going through a pipeline of execution engines • MIMD: most multiprocessors today: easy to construct with off-the-shelf computers, most flexibility 7 SISD • One instruction stream • One data stream • One instruction issued on each clock cycle • One instruction executed on single element(s) of data (scalar) at a time • Traditional ‘von Neumann’ architecture (remember from introduction) 8 SIMD • Also von Neumann architectures but more powerful instructions • Each instruction may operate on more than one data element • Usually intermediate host executes program logic and broadcasts instructions to other processors • Synchronous (lockstep) • Rating how fast these machines can issue instructions is not a good measure of their performance • Two major types: • Vector SIMD • Parallel SIMD 9 Vector SIMD • Single instruction results in multiple operands being updated • Scalar processing operates on single data elements. -
Guaranteeing Real-Time Performance Using Rate Monotonic Analysis
Carnegie Mellon University Software Engineering Institute Guaranteeing Real-Time Performance Using Rate Monotonic Analysis Embedded Systems Conference September 20-23, 1994 Presented by Ray Obenza Software Engineering Institute Carnegie Mellon University Pittsburgh PA 15213 Sponsored by the U.S. Department of Defense Carnegie Mellon University Software Engineering Institute Rate Monotonic Analysis Introduction Periodic tasks Extending basic theory Synchronization and priority inversion Aperiodic servers Case study: BSY-1 Trainer 1 Introduction Carnegie Mellon University Software Engineering Institute Purpose of Tutorial Introduce rate monotonic analysis Explain how to perform the analysis Give some examples of usage Convince you it is useful 2 Introduction Carnegie Mellon University Software Engineering Institute Tutorial Format Lecture Group exercises Case study Questions welcome anytime 3 Introduction Carnegie Mellon University Software Engineering Institute RMARTS Project Originally called Real-Time Scheduling in Ada Project (RTSIA). • focused on rate monotonic scheduling theory • recognized strength of theory was in analysis Rate Monotonic Analysis for Real-Time Systems (RMARTS) • focused on analysis supported by (RMS) theory • analysis of designs regardless of language or scheduling approach used Project focused initially on uniprocessor systems. Work continues in distributed processing systems. 4 Introduction Carnegie Mellon University Software Engineering Institute Real-Time Systems Timing requirements • meeting deadlines Periodic -
RTOS Northern Real Time Applications (NRTA)
By N.J. Keeling, Director of Marketing, RTOS Northern Real Time Applications (NRTA). Missed it! - How Priority Inversion messes up real-time performance and how the Priority Ceiling Protocol puts it right. In hard real-time systems it is important that everything runs on-time, every time. To do this efficiently it is necessary to make sure urgent things are done before less urgent things. When code is developed using a real-time operating system (RTOS) that offers pre-emptive scheduling, each task can be allocat- ed a level of priority. The best way to set the priority of each task is according to the urgency of the task: the most urgent task gets the highest priority (this ordering scheme is known as Deadline Monotonic). PRE-EMPTIVE MULTI-TASKING there is a requirement for data to be shared between ulti-tasking through use of an RTOS sched- the various tasks in the application. Clearly this is a typ- uler enables the processor to be shared ical situation: imagine an I/O data stream that is imple- M between a number of tasks in an applica- mented with two tasks. The first (called H) is a high pri- tion. In most priority schemes the scheduler is pre- ority task and drives communications hardware. It emptive: a task of a higher priority will 'break in' on the takes data from a buffer and places it onto a network. execution of lower priority tasks and take over the The task needs to run and finish by a short deadline, processor until it finishes or is pre-empted in its turn by which is why it has a high priority. -
Multitasking and Real-Time Scheduling
Multitasking and Real-time Scheduling EE8205: Embedded Computer Systems http://www.ee.ryerson.ca/~courses/ee8205/ Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University Overview • RTX - Preemptive Scheduling • Real-time Scheduling Techniques . Fixed-Priority and Earliest Deadline First Scheduling • Utilization and Response-time Analysis • Priority Inversion • Sporadic and Aperiodic Process Scheduling Chapter 6 of the Text by Wolf, Chapter 13 of Text by Burns and Wellings and Keil-RTX documents © G. Khan Embedded Computer Systems–EE8205: Real-time Scheduling Page: 1 Priority-driven Scheduling Rules: • each process has a fixed priority (1 lowest); • highest-priority ready process gets CPU; • process continues until done. Processes • P1: priority 3, execution time 10 • P2: priority 2, execution time 30 • P3: priority 1, execution time 20 P3 ready t=18 P2 ready t=0 P1 ready t=15 P2 P1 P2 P3 time 0 10 20 30 40 50 60 © G. Khan Embedded Computer Systems–EE8205: Real-time Scheduling Page: 2 RTX Scheduling Options RTX allows us to build an application with three different kernel- scheduling options: • Pre-Emptive scheduling Each task has a different priority and will run until it is pre- empted or has reached a blocking OS call. • Round-Robin scheduling Each task has the same priority and will run for a fixed period, or time slice, or until has reached a blocking OS call. • Co-operative multi-tasking Each task has the same priority and the Round-Robin is disabled. Each task will run until it reached a blocking OS call or uses the os_tsk_pass() call. -
The 8255A Is Generally Seen As 8-Bit Bidirectional Data Buffer, Which Is
PROGRAMMABLE PERIPHERAL INTERFACE 8255 The 8255A is generally seen as 8-bit bidirectional data buffer, which is specially designed to transfer the data with the execution of input output instructions requested by the CPU. It has the ability to use with almost any microprocessor. It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured with their different functional characteristics, each possessing unique features to upgrade the flexibility of 8255. Ports of 8255A 8255A consists of three ports, i.e., PORT A, PORT B, and PORT C. Port A contains one 8-bit output latch/buffer and one 8-bit input buffer possessing both pull- up and pull-down devices present in Port A. Port B is similar to PORT A. Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7- PC4) with the help of control word. These three ports are further classified into two groups, i.e. Group A includes PORT A and upper PORT C. Group B includes PORT B and lower PORT C. These two groups can be programmed in three different modes, i.e. the first mode is named as mode 0, the second mode is named as Mode 1 and the third mode is named as Mode 2. Data Bus Buffer : It is a tri-state 8-bit bidirectional data buffer, which helps in interfacing the microprocessor to the system data bus. Data is transmitted or received by the buffer with the input output instructions given by the CPU.