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Introducing Vivado ML Introducing Vivado® ML Editions Nick Ni, Director of Marketing, Software & AI Solutions © Copyright 2021 Xilinx EDA Challenges Today 92B transistors Lack of QoR Breakthrough 1 35B transistors Typically in 1-3% gain range 19B transistors 7B transistors Design Sizes - 38% CAGR Capacity + Routability 2 Compile and iteration time rising 2011 2014 2016 2019 28nm 20nm 16nm 7nm 2 © Copyright 2021 Xilinx Machine Learning is All About Data EDA = decades of data + massive design reuse Training Inference class APPLICATIONS Classification Object Detection Segmentation Speech Recognition Anomaly Detection Now… EDA 3 © Copyright 2021 Xilinx 1 Machine Learning: Next Big Leap for QoR Tipping point: EDA engineers “know-how” heuristics to data-driven ML models EDA Task ML AIG/MIG optimizer DNN selection Breakthrough in QoR gain: 1% → 10%+ Classify optimal flow CNN Generate optimal flow GCN, RL Placement decisions GCN, RL Evaluate potential paths SVM, NN Faster design iteration for a QoR target Routing congestion CNN, GAN, ML, MARS Predict wirelength LDA, KNN Table Source: Guyue Huang, et al. 2021. Machine Learning for Electronic Design Automation: A Survey. arXiv:2102.03357 Photo credit: Rohit Sharma, Machine Intelligence in Design Automation CNN = Convolutional Neural Network, RL = Reinforcement Learning, KNN = K-Nearest-Neighbor, GAN = Generative Adversarial Network, SVM = Support Vector Machine, GCN = Graph Convolutional Networks, DNN = Deep Neural Network, MARS = Multivariate Adaptive Regression Splines, LDA = Linear Discriminant Analysis 4 © Copyright 2021 Xilinx Examples of publications for ML on EDA 2 Breaking Ever-Growing Design into Modules Modular designing for system-level reuse Hierarchical compile of reconfigurable modules Only load the modules you need in milliseconds while system is online 5 © Copyright 2021 Xilinx Introducing ML-based Design Optimization 10% average QoR gain Hierarchical compile of reconfigurable modules 5x average compile time reduction 6 © Copyright 2021 Xilinx Example: ML-Based Automatic Timing Closure Intelligent Design Runs (IDR) ML-based congestion estimation ML-based strategy prediction Predicts router behavior and avoids creating congestion Pick top strategies from 60+ custom strategies based on 100,000+ set of training data ML-based delay estimation Better delay predictions for complex routing © Copyright 2021 Xilinx 7 © Copyright 2021 Xilinx Design Iteration 5x Reduction on Difficult Designs Without IDR Typical iteration: 25 With IDR User iteration: 1 Save Time and Compute Resources 8 © Copyright 2021 Xilinx Average 10%, Up to 50% QoR improvement 700 600 Up to 50% gain 500 400 Average 10% gain 300 200 100 0 Default Fmax Intelligent Design Run Fmax Major breakthrough QoR gain for higher performance 9 © Copyright 2021 Xilinx 2 Hierarchical Module-Based Compilation Define Reconfigurable Modules (RM) Only compile and close timing what’s in the RM Hierarchical Compilation Linear speedup with parallel tasks Secure Handoff Does not contain rest of design, only workspace Most of the design is trimmed away 10 ©© Copyright Copyright 20212021 XilinxXilinx 2 Compile Time Reduction with Abstract Shell 7:12:00 6:00:00 4:48:00 Average 5x compile 3:36:00 time reduction Run Time 2:24:00 Lower better 1:12:00 0:00:00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 51 53 54 55 56 57 58 Test Case Full Shell Abstract Shell 5x more design runs every day 11 © Copyright 2021 Xilinx 2 Extending Module Design into End-to-End Flow Block Design Containers Team-based Graphical IP Design Flow with modules Dynamic Function eXchange Swap different hardware design in milliseconds while system is online Team-based productivity boost 12 ©© Copyright Copyright 20212021 XilinxXilinx Customer Success Stories Intelligent Design Runs Block Design Containers Abstract Shell ‘Intelligent Design Runs is a game- ‘Block Design Containers allowed ‘Using DFX and Abstract Shell has changer by offering a push-button us to reuse portions of our IPI enabled us to keep our IP protected method for aggressively improving design much more efficiently than and at the same time allows our timing results. IDR generates QoR previous versions of Vivado. This customers to create their own suggestions that bring maximum led to faster design times and less dynamic IP. DFX is especially impact, resulting in expert quality chance for manual design entry valuable for mission-critical results and a reduction in user mistakes.’ operations by permitting function analysis, especially for tough to swapping while the device remains close designs.’ operational.’ 13 © Copyright 2021 Xilinx Vivado ML Editions AVAILABLE NOW AVAILABLE NOW Standard Edition Enterprise Edition Free NL: $2,995 Limited device support FL: $3,595 Supports all Xilinx Devices 14 © Copyright 2021 Xilinx Vivado ML: State-of-The-Art EDA with ML algorithms ML-based design optimization 1 10% average QoR gain Hierarchical compile of reconfigurable modules 2 5X average compile time reduction 15 © Copyright 2021 Xilinx Design Smarter https://www.xilinx.com/products/design-tools/vivado.html Link to video Whitepapers 16 © Copyright 2021 Xilinx Thank You © Copyright 2021 Xilinx.
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