Getting Started with V-System

VHDL, Verilog, and Mixed-HDL Simulation for Workstations and PCs

Model Technology V-System/VHDL, V-System/PLUS, and V-System/VLOG are produced by Model Technology Incorporated. Unauthorized copying, duplication, or other reproduction is prohibited without the written consent of Model Technology. The information in this manual is subject to change without notice and does not represent a commitment on the part of Model Technology. The program described in this manual is furnished under a license agreement and may not be used or copied except in accordance with the terms of the agreement. The online documentation provided with this product may be printed by the end- user. The number or copies that may be printed is limited to the number of licenses purchased. V-System is a trademark of Model Technology Incorporated. PostScript is a registered trademark of Adobe Systems Incorporated. UNIX is a registered trademark of AT&T in the USA and other countries. FLEXlm is a trademark of Globetrotter Software, Inc. IBM, AT, and PC are registered trademarks, AIX and RISC System/6000 are trademarks of International Business Machines Corporation. Windows is a trademark, Microsoft and MS-DOS are registered trademarks of Microsoft Corporation. OSF/Motif is a trademark of the Open Software Foundation, Inc. in the USA and other countries. SPARC is a registered trademark and SPARCstation is a trademark of SPARC International, Inc. Sun Microsystems is a registered trademark, and Sun, SunOS and OpenWindows are trademarks of Sun Microsystems, Inc. All other trademarks and registered trademarks are the properties of their respective holders. Copyright (c) 1990-1997, Model Technology Incorporated. All rights reserved. Confidential. Online documentation may be printed by licensed customers of Model Technology Incorporated for internal business purposes only. Software Version: V-System 4.6 for workstations and PCs Published: June 1997 Model Technology Incorporated 8905 SW Nimbus Avenue, Suite 150 Beaverton OR 97008-7100 USA phone: 503-641-1340 fax: 503-526-5410 email: [email protected], [email protected] home page: http://www.model.com $50 US

2 Software License Agreement

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Model Technology Software License

1. LICENSE. MTI grants to you the nontransferable, nonexclusive right to use the copy of the enclosed software program (the “SOFTWARE”) on the computer hardware server equipment, identified in writing by you by make, model and workstation or host identification number and the equipment served, in machine-readable form only , as allowed by the authorization code provided to you by MTI or its agents. All authorized systems must be used within the country for which the systems were sold. Workstation licenses must be located at a single site, i.e. within a one-kilometer radius (and identified in writing to MTI). PC products licensed by a hardware security key may be relocated within the country for which sold. 2. COPYRIGHT. The SOFTWARE is owned by MTI (or its licensors) and is protected by United States copyright laws and international treaty provisions. Therefore you must treat the SOFTWARE like any other copyrighted material, except that you may either (a) make one copy of the SOFTWARE solely for backup or archival purposes, or (b) transfer the SOFTWARE to a single hard disk provided you keep the original solely for backup or archival purposes. You may not copy the written materials accompanying the SOFTWARE. 3. USE OF SOFTWARE. The SOFTWARE is licensed to you for internal use only. You shall not conduct benchmarks or other evaluations of the SOFTWARE without the advance written consent of an authorized representative of MTI. You shall not sub-license, assign or otherwise transfer the license granted or the rights under it without the prior written consent of MTI or its applicable licensor. You shall keep the SOFTWARE in a restricted and secured area and shall grant access only to authorized persons. You shall not make software available in any form to any person other than your employees whose job performance requires access and who are specified in writing to MTI. MTI may enter your business premises during normal business hours to inspect the SOFTWARE, subject to your normal security. 4. PERMISSION TO COPY LICENSED SOFTWARE. You may copy the SOFTWARE only as reasonably necessary to support an authorized use. Except as permitted by Section 2, you may not make copies, in whole or in part, of the SOFTWARE or other material provided by MTI without

3 the prior written consent of MTI. For such permitted copies, you will include all notices and legends embedded in the SOFTWARE and affixed to its medium and container as received from MTI. All copies of the SOFTWARE, whether provided by MTI or made by you, shall remain the property of MTI or its licensors. You will maintain a record of the number and location of all copies of the SOFTWARE made, including copes that have been merged with other software, and will make those records available to MTI or its applicable licensor upon request. 5. TRADE SECRET. The source code of the SOFTWARE is trade secret or confidential information of MTI or its licensors. You shall take appropriate action to protect the confidentiality of the SOFTWARE and to ensure that any user permitted access to the SOFTWARE does not provide it to others. You shall take appropriate action to protect the confidentiality of the source code of the SOFTWARE. You shall not reverse-assemble, reverse-compile or otherwise reverse- engineer the SOFTWARE in whole or in part. The provisions of this section shall survive the termination of this Agreement. 6. TITLE. Title to the SOFTWARE licensed to you or copies thereof are retained by MTI or third parties from whom MTI has obtained a licensing right. 7. OTHER RESTRICTIONS. You may not rent or lease the SOFTWARE. You shall not mortgage, pledge or encumber the SOFTWARE in any way. You shall ensure that all support service is performed by MTI or its designated agents. You shall notify MTI of any loss of the SOFTWARE. 8. TERMINATION. MTI may terminate this Agreement, or any license granted under it, in the event of breach or default by you. In the event of such termination, all applicable SOFTWARE shall be returned to MTI or destroyed. 9. EXPORT. You agree not to allow the MTI SOFTWARE to be sent or used in any other country except in compliance with this license and applicable U.S. laws and regulations. If you need advice on export laws and regulations, you should contact the U.S. Department of Commerce, Export Division, Washington, DC 20230, USA for clarification.

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4 CUSTOMER REMEDIES. MTI’s entire liability and your exclusive remedy shall be, at MTI’s option, either (a) return of the price paid or (b) repair or replacement of the SOFTWARE that does not meet MTI’s Limited Warranty and which is returned to MTI. This Limited Warranty is void if failure of the SOFTWARE has resulted from accident, abuse or misapplication. Any replacement SOFTWARE will be warranted for the remainder of the original warranty period or 30 days, whichever is longer. NO OTHER WARRANTIES. MTI disclaims all other warranties, either express or implied, including but not limited to implied warranties of merchantability and fitness for a particular purpose, with respect to the SOFTWARE and the accompanying written materials. This limited warranty gives you specific legal rights. You may have others, which vary from state to state. NO LIABILITY FOR CONSEQUENTIAL DAMAGES. In no event shall MTI or its suppliers be liable for any damages whatsoever (including, without limitation, damages for loss of business profits, business interruption, loss of business information, or other pecuniary loss) arising out of the use of or inability to use these MTI products, even if MTI has been advised of the possibility of such damages. Because some states do not allow the exclusion or limitation of liability for consequential or incidental damages, the above limitation may not apply to you.

Important Notice

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5 Table of Contents

Software License Agreement ...... 3 Model Technology Software License ...... 3 Limited Warranty ...... 4 Important Notice ...... 5

1 - Introduction

Standards supported ...... 9 Assumptions ...... 9 Software versions ...... 10 Sections in this guide ...... 10 Conventions ...... 10 HDL and HDL item ...... 11 Where to find our documentation ...... 11 Comments ...... 12

2 - V-System Installation for Workstations

System requirements ...... 13 Installation procedure ...... 13 Installed directories and files...... 17 Platform specific directories...... 20

3 - V-System Installation for PCs

System requirements ...... 21 Current Customers ...... 21 Installation procedure ...... 21 Getting an Authorization Code ...... 23

4 - The V-System Graphic Interface

Tree windows ...... 27 Transcript or Main window ...... 28 Startup dialog box for workstations ...... 29 Simulate a Design dialog box for PCs ...... 30 Structure window ...... 31

6 - Table of Contents Getting Started with V-System Source window ...... 32 Process window ...... 33 Signals window ...... 34 Dataflow window ...... 35 Variables window ...... 36 List window ...... 37 Wave window ...... 38 Running command-line and batch-mode simulations ...... 40 Command-line mode ...... 40 Batch mode ...... 40

5 - Using V-System for Workstations

Lesson 1: Basic VHDL simulation ...... 44 Lesson 2: Basic Verilog simulation ...... 52 Lesson 3: Mixed VHDL/Verilog simulation ...... 63 Lesson 4: Debugging a VHDL design ...... 68 Lesson 5: Running a batch-mode simulation ...... 77 Lesson 6: Executing commands at startup ...... 79 Practice 1: Searching in tree windows ...... 81 Practice 2: Wave window shortcuts ...... 83 Continuing with V-System for workstations ...... 84

6 - Using V-System for PCs

V-System application window ...... 86 V-System menu bar ...... 88 V-System tool bar ...... 91 Tutorial setup ...... 92 Lesson 1: Basic VHDL simulation ...... 93 Lesson 2: Basic Verilog simulation ...... 106 Lesson 3: Mixed VHDL/Verilog simulation ...... 122 Lesson 4: Debugging a VHDL design ...... 129 Practice: Using the keyboard, mouse and menus ...... 141 V-System PC keyboard shortcuts ...... 142 Wave window mouse actions ...... 143 Wave window menus ...... 145 Continuing with V-System for PCs ...... 146

Getting Started with V-System Table of Contents - 7 A - Resources

Books ...... 147 Organizations ...... 148 Corporations & Consultants ...... 149 Online resources ...... 152

B - Technical Support

8 - Table of Contents Getting Started with V-System 1 - Introduction

The purpose of this guide is to introduce Model Technology’s V-System simulation software and its graphical user interface for PCs and workstations: V-System/VHDL (for VHDL only), V-System/VLOG (for Verilog only), and V-System/PLUS (for mixed VHDL and Verilog). Engineers that must simulate mixed VHDL/Verilog designs will be able to complete their work within one simulator environment because of V-System/PLUS’ single-kernel simulation. Although the text covers both VHDL and Verilog, you will find it a useful reference even if your design work is limited to a single HDL.

Standards supported

V-System VHDL supports both the IEEE 1076-1987 and 1076-1993 VHDL standards. Any design developed with V-System will be compatible with any other VHDL system that is compliant with either IEEE Standard 1076-1987 or 1076-1993. V-System Verilog is based on the IEEE 1364 Verilog Hardware Description Language Reference Manual. The Open Verilog International Verilog LRM version 2.0 is also applicable to a large extent. The PLI is supported on PCs and workstations, while VCD support is available for workstation users. In addition, all products support SDF 1.0, 2.0, and 2.1 and (with the exception of V-System/ VLOG) Vital 2.2b, and Vital ’95.

Assumptions

We assume that you are familiar with the use of your operating system. If you are using a PC and are not familiar with Microsoft Windows, we recommend that you work through the tutorials provided with MS Windows before using V-System. If you are using V-System on a workstation, we also assume that you are familiar with the graphical interface on your workstation: either OpenWindows or OSF/Motif on SPARCstations and OSF/Motif on IBM and Hewlett-Packard workstations. In addition, we assume that you have a working knowledge of VHDL and Verilog. Although V-System is an excellent tool to use while learning HDL concepts and practices, this booklet is not written to support that goal. If you need more information about HDLs, visit the Model Technology home page at http://www.model.com. You can also contact your local Model Technology distributor for information about training classes.

Getting Started with V-System Introduction - 9 Software versions

This document was written to support V-System 4.6 for PCs and workstations. If the software you are using is a later release, check the README file (on the CD-ROM, or disk #1 for PCs) that accompanied the software. Any supplemental information will be there.

Sections in this guide

In addition to this introduction, you will find the following major sections in this guide: 2 - V-System Installation for Workstations on page 13 3 - V-System Installation for PCs on page 21 4 - The V-System Graphic Interface on page 25 5 - Using V-System for Workstations on page 43 6 - Using V-System for PCs on page 85 A - Resources on page 147 B - Technical Support on page 181

Conventions

Text conventions used in this manual include:

italic text provides emphasis and sets off file and path names

bold text indicates commands, command options, and menu choices, as well as package and library logical names monospaced type is used for program and command examples Conventions underlined text indicates a cross-reference used as a hyperlink in the online versions of this documentation – the hyperlinks are blue in online documents The right angle (>) is used to connect menu choices when traversing menus as in: File > Save

10 - Introduction Getting Started with V-System HDL and HDL item

“HDL” refers to either VHDL or Verilog when a specific language reference is not needed. Depending on the context, “HDL item” can refer to any of the following: • VHDL block statement, component instantiation, constant, generate statement, generic, package, signal, or variable • Verilog function, module instantiation, named fork, named begin, net, task, or register variable

Where to find our documentation

Model Technology’s documentation is available in the following formats and locations:

DOCUMENT FORMAT HOW TO GET IT

Getting Started paper shipped with product; additional copies at $50 each (for customers (installation & with current maintenance) tutorial) Getting Started PDF online find “tutorial.pdf” in “/modeltech/docs” (workstation products); look on CD-ROM for “docs” folder (PC products) Getting Started HTML view from home page: www.model.com Workstation User’s paper shipped with product; additional copies at $50 each (for customers Manual with current maintenance) Workstation User’s PDF online find “ws_man.pdf” in “/modeltech/docs” Manual (workstation products only) PC User’s Manual paper shipped with product; additional copies at $50 each (for customers with current maintenance) PC User’s Manual PDF online look on CD-ROM for “docs” folder (PC products) Tcl syntax reference ASCII find “tcl_syn” in “/modeltech/docs” (workstation products only)

Getting Started with V-System Introduction - 11 DOCUMENT FORMAT HOW TO GET IT

various tech notes ASCII find the “technotes” directory in “/modeltech/docs” (workstation products only) Verilog tech notes ASCII find the “verilog” directory “/modeltech/docs” (workstation products); look on CD-ROM for “docs” folder (PC products)

Comments

Comments and questions about this manual and V-System software are welcome. Call, write, or fax or email: Model Technology Incorporated 8905 SW Nimbus Avenue, Suite 150 Beaverton OR 97008-7100 USA phone: 503-641-1340 fax: 503-526-5410

email: [email protected]

home page: http://www.model.com

12 - Introduction Getting Started with V-System 2 - V-System Installation for Workstations

System requirements

SPARCstation IBM RISC/6000 HP 700

Operating system & SunOS 4.1 & AIX 3.2.5 & OSF/Motif HP-UX 9.01 & HP VUE 3.0 interface OpenWindows 3.0 1.2 or OSF/Motif 1.2

Solaris 2.4 & OSF/ Motif 1.2 or OpenWindows 3.0

Memory 32 Mb minimum Storage hard disk with at least 35 Mb spare capacity Installation media 1/4” tape, QIC 24 format, CD-ROM 4 mm DAT, CD-ROM

Installation procedure

Note: Please refer to the installation instructions packaged with your product for the latest information; they may supercede the installation instructions here. Also please be sure to read the readme file included with V-System after you finish your installation. Before you begin a new V-System Workstation installation, make sure you have a V-System Authorization Certificate with the license.dat file; you need the file to run V-System. If you don’t have the certificate or the license file, you can get one by email ([email protected]) or fax from Model Technology.

Getting Started with V-System V-System Installation for Workstations - 13 Be sure to include your workstation’s identification in your fax or email:

Syntax Platform

hostid SPARC /etc/lanscan HP 700

uname -m RISC/6000

The commands used to install V-System are case-sensitive, so they must be entered exactly as shown in the following steps. (Note that neither the prompt nor the at the end of a line is shown in the examples.)

Step 1. V-System can be installed in any directory. These instructions assume that you are installing it in the /usr directory. You can change to the desired installation directory by entering one of the following commands: cd /usr

or cd

Step 2. For CD-ROM installation, extract the file for your platform (plus base.tar and manuals.tar) with this syntax (we assume that the is mounted): tar xf //WORKSTATION/install/ For tape installation, extract the files using the tape install command for your platform.

Platform Tape install commands

All platforms base.tar (extract for all platforms)

Sun OS-4/Solaris 1.x sun4.tar tar xf /dev/rst0

Sun OS-5/Solaris 2.x sunos5.tar tar xf /dev/rmt/0

14 - V-System Installation for Workstations Getting Started with V-System Platform Tape install commands

HP hp700.tar tar xf /dev/rmt/0m IBM rs6000.tar tar xf /dev/

All platforms manuals.tar ( manuals in pdf format)

This creates a top-level directory named modeltech.

Step 3. Add the pathname of the V-System executable directory to your search path: /usr/modeltech/sun4 /usr/modeltech/sunos5 /usr/modeltech/hp700 /usr/modeltech/rs6000

Step 4. Enter or edit the license.dat file in the modeltech directory. Typically the file looks like this: SERVER hostname nnnnnnnn 1650 DAEMON modeltech ./modeltech ./options FEATURE vsim modeltech 4.000 dd-mmm-yr n 123456789abcdef12345 "name" FEATURE vcom modeltech 4.000 dd-mmm-yr n 123456789abcdef12345 "name"

Note: To enable starting the license daemon from any directory, change the DAEMON line to use full path. For example: DAEMON modeltech /usr/modeltech/hp700/modeltech/usr/modeltech/hp700/options

Step 5. For HP installation using HP-UX version 9.x only: either the device /dev/lan0 must be writable by the userID that starts the server, or the lmgrd daemon and the lmhostid utility must be made “setuid root”. The commands to do this are: chmod a+w /dev/lan0

or chown root lmgrd lmhostid chmod u+s lmgrd lmhostid

Getting Started with V-System V-System Installation for Workstations - 15 Step 6. Start the license manager daemon by entering the following commands: cd /usr/modeltech/ START_SERVER

where can be sun4, sunos5, hp700, rs6000. If your system runs other applications that use Globetrotter Software’s FLEXlm, a complete user’s manual for FLEXlm is available at Globetrotter Software’s home page: http://www.globetrotter.com/manual.htm

Step 7. You may delete the executables you don’t want; for example: cd /usr/modeltech/ rm -rf hp700

16 - V-System Installation for Workstations Getting Started with V-System Installed directories and files

18 - V-System Installation for Workstations Getting Started with V-System | |-numeric sources for rebuilding accelerated IEEE arithmetic | | | packages | | |-mti_numeric_std.vhd | | |-mti_numeric_bit.vhd || | |-std/ | | |-standard.vhd sources for rebuilding std library | | |-textio.vhd sources for package TEXTIO || | |-synopsys/ sources for rebuilding accelerated arithmetic | | | packages | | |-mti_std_logic_arith.vhd | | |-mti_std_logic_misc.vhd | | |-mti_std_logic_signed.vhd | | |-mti_std_logic_unsigned.vhd | | |-std_logic_textio.vhd || | |-verilog/ source for rebuilding Verilog library | | |-vltypes.vhd || | |-vital2.2b/ sources for rebuilding the VITAL 2.2b library | | |-README | | |-prmtvs_b.vhd | | |-prmtvs_p.vhd | | |-timing_b.vhd | | |-timing_p.vhd || | |-vital95/ sources for rebuilding the VITAL 95 library | | |-README | | |-prmtvs_b.vhd | | |-prmtvs_p.vhd | | |-timing_b.vhd | | |-timing_p.vhd |-vital2.2b/ VITAL version 2.2b library | |-_info | |-vital_primitives/ | |-vital_timing/

Getting Started with V-System V-System Installation for Workstations - 19 Platform specific directories

20 - V-System Installation for Workstations Getting Started with V-System 3 - V-System Installation for PCs

System requirements V-System requires: • a 386/486/Pentium PC • 16 Mb (megabytes) of memory, 32Mb with Windows 95 and NT • Microsoft Windows Version 3.1 (in enhanced mode), Windows 95, Windows NT (not supplied) • a hard disk drive with more than 10 Mb spare capacity • a 3-1/2" disk drive or CD-ROM drive

Current Customers If you are already using V-System PC version 4.4 or older, you should install this in a different directory than the older version. You will also need to recompile all your libraries before running any simulations. You don't need to touch the std, ieee, vital2.2b, and verilog libraries shipped with this release.

How to protect your investment Keep your investment in V-System safe by protecting your hardware security key. It is an absolutely essential part of your system since the software will not run without it. And while Model Technology will replace a defective key, lost or stolen keys will not be replaced. One way you can protect your investment is by insuring it. While most insurance companies won’t insure software, they will insure hardware, so insure the key for the full V-System value.

Getting Started with V-System V-System Installation for PCs - 21 Installation procedure

If you are installing V-System from floppies, the installation program will prompt you for the correct disks. Not all disks and files are necessary for all installations. Please do not copy files without using the install program. For Windows 3.1, version 4.6 requires Win32S 1.30; the installation program detects and installs the required version of Win32s if needed. For NT users, version 4.6 requires NT 3.51, 4.0 or later, and new hardware security key drivers; the installation program will install the new driver. Windows 95 installations require only the V-System software.

Step 1. CD-ROM Place the V-System media in the correct drive (disk or CD-ROM drive). From within Windows, choose Run from the File menu in the Program Manager (or Start and Run under Windows 95 Windows NT). Then type “D:\vsystem\disk1\setup” in the Command Line box. (Substitute your drive letter if it is not D.)

Step 1. 3-1/2” Floppy Place V-System disk #1 in your drive. From within Windows, choose Run from the File menu in the Program Manager (or Start and Run under Windows 95 or Windows NT). Then type “A:\setup” in the Command Line box. (Substitute your drive letter if it is not A.)

Step 2. After a short pause, the first of a series of V-System installation dialog boxes is displayed. Follow the instructions and answer the questions in the dialog boxes to complete the installation procedure.

Step 3. Install the security key on the parallel printer port. If you have a printer or another device attached to the same port, attach that device to the security key. It will not interfere with normal operations.

Note for Windows 95 and Windows NT users

There are command-line versions of vcom, vdel, vdir, vlib, vmap, and vsim located in the installation directory.

Getting Started with V-System V-System Installation for PCs - 22 From the command line you can compile or simulate without invoking the V-System graphic interface as in the following two examples. vcom -nodebug example.vhd

or: vsim -lib design my_asic structure

You can also use the vsystem -do command to call the main application with graphic interface and tell it to simulate a circuit, for example: vsystem -do "vsim -t fs testbench; run 100; exit -f"

Or execute the commands in a .do file. The command below calls run_test.do macro file. vsystem -do "do run_test.do"

Getting an Authorization Code

V-System version 4.6 requires a new hardware security key with an authorization code. The code determines whether VHDL, Verilog, or mixed-HDL support is turned on. All codes are based on the product type you purchased, the key ID, and your maintenance expiration date. In most cases your key will be delivered already programmed with your permanent code. If it is not, send email to [email protected], with your key number and return email address.

Note: If you purchased from a Model Technology OEM partner, follow the instructions in your package to contact them. If you receive a new programmable key to replace an existing Model Technology PC key, your new key is delivered ready to run all options of the new software for 30 days from when you first invoke V-System. You can get a permanent code for the product you purchased by returning your old key in the provided postpaid envelope along with your new key’s serial number and your email address. We will send you a permanent code via email.

23 - V-System Installation for PCs Getting Started with V-System Entering your permanent authorization code Make this menu selection when you start V-System: Help>About V-System>Authorization. (If your authorization has expired V-System will prompt you with a dialog box.) Key in your new code and click Apply; the authorization information changes to reflect the current type of authorization and the new maintenance end date. Click Ok to complete the authorization. When it is permanently programmed, your key will run all products of the correct type with build dates before your maintenance end date. When your maintenance expires you can still run any product built up until that date. When you renew your maintenance, you will receive a new authorization code that will extend the date. Updates to V-System PC will be made available via the postal system, ftp, and our website at http://www.model.com. Information about changes to the PC software will be posted on our website as they occur. We hope you find this distribution system of electronic updates and key- authorized software efficient and easy to use.

Getting Started with V-System V-System Installation for PCs - 24 4 - The V-System Graphic Interface

The PC and workstation versions of V-System share a similar graphic user interface (GUI). There are, however, some implementation differences to consider. • For workstations All tools are invoked separately from the UNIX command line. • For PCs V-System can be installed as an integrated application that runs in a single window; all tools, including library management tools like VMAP or VDEL, are invoked from the same window. (This is the only option if you are running V-System under Windows 3.11.) Discussions about our PC products consequently refer to a single program named “V-System”, while discussions about our workstation products refer to separate tools such as VCOM, VLOG (the VHDL and Verilog compilers), or VSIM (the simulator). Running V-System without the graphic interface See Running command-line and batch-mode simulations on page 40 for information on running V-System without the graphic interface. Also, see Lesson 5: Running a batch-mode simulation on page 77 for batch mode information specific to workstations.

Getting Started with V-System The V-System Graphic Interface - 25 V-System windows

Once the simulator is running, you have the same windows available to run the simulator and debug your design; these are: • Transcript or Main window (Transcript window on PCs and Main on workstations) • Structure window to show the elements of the design you are simulating • Source window to show your VHDL and/or Verilog code • Signals window to show the values of VHDL signals and Verilog nets and register variables • Variables window to show the values of VHDL constants, generics, and variables and Verilog register variables • Process window to display processes scheduled to execute • Dataflow window to trace signals and nets through processes • List window to show your simulation results • Wave window to display your results graphically

26 - The V-System Graphic Interface Getting Started with V-System Tree windows

Tree windows

In many windows, V-System provides hierarchical views of your design data. The Structure window (shown) displays the hierarchy of instantiations. The Signals, Variables, and Wave windows allow composite data types such as arrays and records to be expanded to see their sub- elements. VHDL items are indicated with a box and Verilog items are indicated with a circle.

Viewing the hierarchy Whenever you see a tree view, you can use the mouse to collapse or expand the hierarchy. Select the symbols as shown below.

SYMBOL DESCRIPTION

[+] Indicates that you can expand this item to view the structural elements it contains. plus box/circle Do this by clicking the box/circle containing the plus sign. [–] Indicates that the hierarchy has been expanded. You can hide the names of minus box/circle structural elements in the region by clicking on the box or circle containing the minus sign. [] Indicates that the item contains no lower-level structural elements. empty box/circle

Getting Started with V-System The V-System Graphic Interface - 27 Transcript or Main window

Transcript or Main window

The Transcript (or Main VSIM window on workstations) is the first V-System window you’ll see in the application window when you are using V-System. It is the main V-System control window.

In the Windows environment, the transcript window is typically used to: • type in commands to compile, simulate, and manipulate libraries • look at the text output of commands, error messages, and VHDL assertion statements On workstations, the VSIM window is used to control the simulator, not the other V-System tools. The Motif version is shown below.

28 - The V-System Graphic Interface Getting Started with V-System Startup dialog box for workstations

Startup dialog box for workstations

When you first invoke VSIM on a workstation you will see the Startup dialog box (shown below in the Motif version).

The VSIM Startup dialog box allows you to select the library and the top-level design unit to simulate. You can also select the simulation resolution. After you select the Load button the dialog box closes and the Main window remains. You can then call any (or all) of eight VSIM windows from the Main window, as you’ll see in the lessons later. If you select Cancel you will return to Main window command line.

Getting Started with V-System The V-System Graphic Interface - 29 Simulate a Design dialog box for PCs

Simulate a Design dialog box for PCs

When you first invoke VSIM on a PC you will see the Simulate a Design dialog box below.

This dialog box has four tabs to select simulation options: • The first, labeled Design, allows you to select a library and top-level design unit to simulate. • The second tab, labeled VHDL, allows setting of several VHDL-specific options. • The Verilog tab supports Verilog-specific options including control of time and hazard checking as well as user-defined simulator arguments. • The fourth tab configures SDF (Standard Delay Format) functions.

30 - The V-System Graphic Interface Getting Started with V-System Structure window

Structure window

The Structure window provides a hierarchical view of your design. A level of hierarchy is created by each of the following HDL items: • For VHDL component instantiation, generate statement, block statement, and package • For Verilog design elements, model instances, named blocks, tasks, and functions VHDL design elements are indicated by squares and Verilog elements are indicated by circles. The OSF/Motif version of the Structure window is shown below.

As previously mentioned in Tree windows on page 27, you can click on the boxes or circles to view different levels of the design hierarchy.

Getting Started with V-System The V-System Graphic Interface - 31 Source window

Source window

You can view your VHDL and Verilog source code in the Source window. The current line is highlighted and breakpoints are indicated by a dot next to the line number. Breakpoints may be set or removed by double-clicking any executable line within the PC Source window. In the workstation Source window, click near the line number to set the breakpoint; for multi-line statements select the last line.

32 - The V-System Graphic Interface Getting Started with V-System Process window

Process window

The Process window displays the VHDL and Verilog processes that are scheduled to run during the current simulation. You can view either all the processes in the region selected with the Structure window, or all those that are scheduled to run during the current simulation cycle. The Process window has two modes, Active and In Region. On workstations the mode can be selected from a tool bar within the Process window. On PCs the mode selection is made from the menu bar using the Options>Processes>View... menu sequence. When Active is selected, the window displays a list of the processes that are scheduled to execute in this simulation cycle. When In Region is selected, the window lists all processes in the region currently selected in the Structure window. The Windows 95 version is shown below with Active selected.

Getting Started with V-System The V-System Graphic Interface - 33 Signals window

Signals window

The Signals window shows the names and current values of the signals in the current region as selected by the Structure window. If you are using V-System/PLUS, Verilog nets and registers will also be shown. Items are viewed in the order declared in your code. The current region is the portion of your design that you have selected in the Structure window. The OpenWindows and Motif versions are shown.

As in other tree windows, collapsed records and arrays are indicated by the plus boxes. Click on one to expand that level. When no lower levels exist, the box is empty. A minus box indicates an expanded item.

34 - The V-System Graphic Interface Getting Started with V-System Dataflow window

Dataflow window

The Dataflow window allows you to trace VHDL signals and Verilog nets and registers through your design.

For VHDL, the Dataflow window shows either: • a signal in the center of the window with all the processes that drive the signal on the left, and all the processes that read the signal on the right side of the window, or • a process with all the signals read by the process shown as inputs on the left of the window, and all the signals driven by the process on the right side of the window. For Verilog, the Dataflow window shows either: • a net in the center of the window with all the processes that drive the net on the left, and all the processes triggered by the net on the right, or • a process with all the nets that trigger the process show as inputs on the left of the window, and all the nets driven by the process on the right.

Getting Started with V-System The V-System Graphic Interface - 35 Variables window

Variables window

The VSIM Variable window displays a list of VHDL generics, constants, and variables, and Verilog registers from the process currently selected in the Process window.

Again, collapsed records and arrays are indicated by the plus boxes. Click on one to expand that level. When no lower levels exist, the box is empty. A minus box indicates an expanded item. If you are using V-System/PLUS, Verilog registers will also be displayed in this window.

36 - The V-System Graphic Interface Getting Started with V-System List window

List window

The List window displays the results of your simulation run in table form. Using the List window menu you can: • save the listing or the configuration settings • edit which signals are displayed and how they are displayed • define triggering, window update, and signal options • set the list defaults

If you are using V-System/PLUS, Verilog nets and registers will also be displayed in this window.

Getting Started with V-System The V-System Graphic Interface - 37 Wave window

Wave window

The Wave window, like the List window, displays the results of your simulation run — though the Wave window shows the VHDL signals (along with Verilog nets and registers if you are using V-System/PLUS) in waveforms rather than in a table. The window has two parts: • the left pane lists the signals by name and shows their value at the cursor position • the right pane shows the signal values graphically against simulation time

In addition to displaying the waveforms and values, you can use the Wave window to: • select an HDL item or position a cursor using the mouse • edit, cut, and paste the items within the name/value pane • control what’s shown in the waveform display with the Zoom menu • add and remove cursors and specify cursor snap distance

38 - The V-System Graphic Interface Getting Started with V-System Wave window

• specify signal format options including height, radix, and color • write a PostScript file of the waveforms • save the window configuration Zooming in the Wave window • For workstations Use the middle mouse button in the right windowpane (the waveform display). Position the mouse cursor to the left side of the desired zoom interval, press the middle mouse button, and while continuing to press, drag to the right and then releaes at the right side of the desired zoom interval. You can also zoom using the ZOOM menu. • For PCs Use the right mouse button in the right windowpane. Click and drag (rubberband) to zoom the display - the time expands to match the mouse movements. Shortcuts for using the Wave window can be found on page 141 for PCs and on page 83 for workstations.

Getting Started with V-System The V-System Graphic Interface - 39 Running command-line and batch-mode simulations

Running command-line and batch-mode simulations

The typical method of running V-System is interactive: you push buttons and/or pull down menus in a series of windows in the graphic interface. Another option is to run V-System from a command line. If you are using V-System on a workstation or running it on a PC under Windows 95 or NT you can use either the command line, and batch modes to invoke VSIM.

Command-line mode

This an operational mode that has only an interactive command line; no interactive windows are opened. • For workstations Invoke VSIM with the -c option as the first argument. • For PCs Invoke VSIM (vsim.exe) from the DOS prompt in Windows 95 or Windows NT. The resulting transcript file is created in such a way that the transcript can be re-executed without change if you desire. Everything except the explicit commands you enter will begin with a leading comment character (#).

Batch mode

Batch mode is an operational mode where no user interaction with the simulation is required; there is neither an interactive command line nor interactive windows. • For workstations VSIM can be invoked in this mode by redirecting standard input using the UNIX “here- document” technique. Batch mode does not require the -c option. For example: vsim ent arch <

Here is another example of batch mode, this time using a file as input:

40 - The V-System Graphic Interface Getting Started with V-System Running command-line and batch-mode simulations vsim counter < yourfile

From a user's point of view, command-line mode can look like batch mode if you use the vsim -do option to execute a macro that does a quit -f before returning, or if the startup.do macro does a quit -f before returning. But technically, that mode of operation is still command-line mode because stdin is still operating from the terminal. • For PCs VSIM is run from a Windows 95 or NT DOS prompt and standard input and output are re-directed to and from files. This works great for regression testing. For example: C:\vsystem> vsim ent arch outfile

where infile contains: force reset 0 force clk 0, 0 1 50 -rep 100 run 10000

See the V-System User’s Manual for information on which V-System commands may be run from the command line or DOS prompt.

Getting Started with V-System The V-System Graphic Interface - 41 42 - The V-System Graphic Interface Getting Started with V-System 5 - Using V-System for Workstations

The purpose of this section is to help you become familiar with Model Technology’s V-System workstation simulators: • V-System/VHDL for VHDL only, • V-System/VLOG for Verilog only and • V-System/PLUS for mixed VHDL and Verilog simulation. We assume that you are familiar with the graphical interface on your workstation: either OpenWindows or OSF/Motif on SPARCstations and OSF/Motif on IBM and Hewlett-Packard workstations. We also assume that you have a working knowledge of HDL design. Although V-System is an excellent tool to use while learning HDL concepts and practices, this guide is not written to support that goal. Throughout this guide we have used illustrations from either Motif and OpenWindows. Though the windows may differ in details, the window functions within V-System are identical. The exercises presented in this section apply to both simulators with two exceptions; Lesson 2 is a Verilog simulation for V-System/PLUS or V-System/VLOG, and Lesson 3 is a mixed VHDL/ Verilog exercise for V-System/PLUS. Additional details for VHDL, Verilog, and mixed VHDL/ Verilog simulation can be found in the V-System/PLUS Workstation User’s Manual. Divisions in this section include: • Lesson 1: Basic VHDL simulation on page 44 • Lesson 2: Basic Verilog simulation on page 52 • Lesson 3: Mixed VHDL/Verilog simulation on page 63 • Lesson 4: Debugging a VHDL design on page 68 • Lesson 5: Running a batch-mode simulation on page 77 • Lesson 6: Executing commands at startup on page 79 • Practice 1: Searching in tree windows on page 81 • Practice 2: Wave window shortcuts on page 83

Getting Started with V-System Using V-System for Workstations - 43 Lesson 1: Basic VHDL simulation

Lesson 1: Basic VHDL simulation

The goals for the first lesson are: • create a library • compile a VHDL file • start the simulator • understand the basic VSIM windows, mouse, and menu conventions • run VSIM using the run command • list some signals • use the waveform display • force the value of a signal • single-step through a simulation run • set a breakpoint • use the Wave window To begin, follow the steps below. (Note that neither the prompt nor the Return that ends a command line is shown in the examples.)

Step 1. Create a new directory and go there by entering the UNIX shell commands: mkdir cd

Step 2. Copy the VHDL files from the //modeltech/examples directory into the current directory by entering the command (note the period specifying the current directory): cp //modeltech/examples/*.vhd .

44 - Using V-System for Workstations Getting Started with V-System Lesson 1: Basic VHDL simulation

Step 3. Before you compile any HDL code, you need a design library to hold the compilation results. To create a new design library, enter the following: vlib work

This creates a subdirectory named work. This subdirectory contains a special file named _info. Do not create these using UNIX shell commands—always use the vlib command.

Step 4. Compile the file counter.vhd by entering the command: vcom counter.vhd

Step 5. Start the simulator by entering the command: vsim

The VSIM Startup window comes up, as shown below.

Getting Started with V-System Using V-System for Workstations - 45 Lesson 1: Basic VHDL simulation

The VSIM Startup window allows you to select the library and the top-level design unit to simulate. You can also select the resolution limit for this simulation. By default, the following will appear in the VSIM Startup window for this simulation run: • Simulator resolution: ns • Library: work • Entity, Configuration, or Module: counter • Architecture: only Note that OpenWindows illustrations are used in the lessons; V-System window functions are identical regardless of the interface.

Step 6. Click Load to accept these settings.

Step 7. Bring up all the VSIM windows by entering the following line at the VSIM prompt: VSIM> view *

Step 8. To list the top-level signals, move the pointer to the VSIM Signals window, then to the List menu button. Click List (MENU mouse button in OpenWindows) and select Signals in region from the dialog box.

46 - Using V-System for Workstations Getting Started with V-System Lesson 1: Basic VHDL simulation

Step 9. To add top-level signals to the Wave window, move the pointer to the Wave menu button. Click Wave (MENU mouse button in OpenWindows) and select Signals in region from the dialog box.

Step 10. Apply stimulus to the clock input by moving the pointer to the main VSIM window and entering the following command at the VSIM prompt, as shown in the illustration below: VSIM> force clk 1 50, 0 100 -repeat 100

Getting Started with V-System Using V-System for Workstations - 47 Lesson 1: Basic VHDL simulation

The force command is interpreted by VSIM to mean: • force clk to the value 1 at 50 ns after the current time • then to 0 at 100 ns after the current time • repeat this cycle every 100 ns You will see the effects of this force command as soon as you tell the simulator to run.

Step 11. Now you will exercise different Run functions. They are found under the Run menu button (OpenWindows) or Run in the Motif menu bar.

Step 12. Select Run 100 ns. This causes the simulation to run and then stop after 100 ns.

Step 13. Select Run Time'High. This causes the simulator to run forever. To stop the run, go on to the next step.

Step 14. Click Break. The arrow points to the next HDL statement to be executed. Next, you will set a breakpoint in the function on line 18.

Step 15. Move the pointer to the VSIM Source window. Using the vertical scroll bar, scroll until line 18 is visible. Click at or near line number 18 to set the breakpoint. You should see a dot next to the line number where the breakpoint is set. This breakpoint can be toggled on and off by clicking it.

48 - Using V-System for Workstations Getting Started with V-System Lesson 1: Basic VHDL simulation

Step 16. Select Continue in the Run menu in the main VSIM window to resume the run that you interrupted. VSIM will hit the breakpoint, as shown by an arrow in the VSIM Source window and by a message in the main VSIM window. Also note that the parameters and variables within the function are displayed in the VSIM Variables window.

Step 17. Click Step to single-step through the simulation. Notice that the values change in the VSIM Variables window. You can keep clicking Step if you wish.

Getting Started with V-System Using V-System for Workstations - 49 Lesson 1: Basic VHDL simulation

Now let’s take a look at the simulation in the Wave window. In the Wave window, you can use cursors to: • probe for values: signal values update whenever you move the cursor • find the time that a signal changes by clicking on the signal. The cursor will snap to the edge • measure time intervals

Step 18. Experiment with using the cursors, scrolling, and zooming (see page 83 for Wave window shortcuts).

50 - Using V-System for Workstations Getting Started with V-System Lesson 1: Basic VHDL simulation

Step 19. When you’re done experimenting, quit the simulator by entering the command: VSIM> quit -force

This command exits VSIM without saving data. Your window positions will be saved in the vsystem.ini file and the windows will close.

Getting Started with V-System Using V-System for Workstations - 51 Lesson 2: Basic Verilog simulation

Lesson 2: Basic Verilog simulation

You must be using V-System/PLUS or V-System/VLOG Workstation for this lesson. The goals for this lesson are: • compile a Verilog design • examine the hierarchy of the design • list signals in the design • change list attributes • set a breakpoint • add and remove cursors in the waveform display If you’ve completed the previous lesson, Basic VHDL simulation, you’ll notice how the V-System simulation processs for VHDL and Verilog is virtually the same.

Step 1. Create a new directory and go there by entering the UNIX shell commands: mkdir cd

Step 2. Copy the Verilog files from the //modeltech/examples directory into the current directory by entering the command (note the period specifying the current directory): cp //modeltech/examples/*.v .

Before you can compile a Verilog design, you need to create a library to store the compilation results. If you are only familiar with interpreted Verilog simulators such as Cadence Verilog XL this will be a new idea for you. Because V-System is a compiled Verilog, it requires a target design library for the compilation. V-System can compile both VHDL and Verilog code into the same library if desired.

52 - Using V-System for Workstations Getting Started with V-System Lesson 2: Basic Verilog simulation

Step 3. To create a new design library, enter the following: vlib work

This creates a subdirectory named work. This subdirectory contains a special file named _info. Do not create these using UNIX shell commands—always use the vlib command. Next, you need to compile the Verilog design. The example design we'll be using consists of two Verilog source files, each containing a unique module. The file counter.v contains a module called counter which implements a simple 8-bit binary up-counter. The other file, tcounter.v, is a testbench module (test_counter ) used to verify counter. Under simulation you will see that these two files are configured hierarchically with a single instance (instance name dut) of module counter instantiated by the testbench. You'll get a chance to look at the structure of this code later. For now, you need to compile both files into the work design library.

Step 4. Compile the Verilog files by entering the command: vlog counter.v tcounter.v

Note that the order in which you compile the two Verilog modules is not important. This may again seem strange to Verilog XL users who understand the possible problems of interface checking between design units, or compiler directive inheritance. V-System defers such checks until the design is loaded by VSIM (the VHDL simulator). So it doesn't matter here if you choose to compile counter.v before or after tcounter.v.

Step 5. Start the simulator by entering the command: vsim

Getting Started with V-System Using V-System for Workstations - 53 Lesson 2: Basic Verilog simulation

The VSIM Startup window comes up, as shown below.

The VSIM Startup window allows you to select the library and the top-level design unit to simulate. You can also select the resolution limit for this simulation. By default, the following will appear in the VSIM Startup window for this simulation run: • Simulator resolution: ns • Library: work • Entity, Configuration, or Module: Module counter • Architecture: (none) Note that OpenWindows widgets are used within the Motif windows manager for this lesson; V-System window functions are identical regardless of the interface.

Step 6. Select Module test_counter and click Load to accept these settings and activate the main VSIM window.

54 - Using V-System for Workstations Getting Started with V-System Lesson 2: Basic Verilog simulation

Step 7. Bring up the VSIM Signals, List and Wave windows by entering the following line at the VSIM prompt within the main VSIM window: VSIM> view signals list wave

Step 9. Remaining in the VSIM Signals window, add top-level signals to the Wave window: Click the Wave menu button (MENU mouse button in OpenWindows) and select Signals in region from the dialog box; the Wave menu pin-up is shown below.

Getting Started with V-System Using V-System for Workstations - 55 Lesson 2: Basic Verilog simulation

Step 10. Now let’s open the VSIM Structure and Source windows. Enter the following command at the VSIM prompt: VSIM> view structure source

Step 11. Rearrange the windows to give yourself a clear view of all open windows (VSIM, Signals, List, Wave, Structure and Source), then click inside the Structure window.

Notice how this window describes the hierarchical structure of the design. In the illustration the Structure window shows three hierarchical levels: test_counter, counter and the function called increment. (If test_counter is not displayed you simulated counter instead of test_counter.) You can navigate within the hierarchy by clicking on a line within the window.

Step 12. Click on FUNCTION increment and notice how other VSIM windows are automatically updated as appropriate. Specifically, the Source window displays the Verilog code at the hierarchical level you selected in the Structure window. Using the Structure window in this way is analogous to scoping commands in interpreted Verilogs. For now, make sure the test_counter module is showing in the Source window by clicking on the top line in the Structure window.

56 - Using V-System for Workstations Getting Started with V-System Lesson 2: Basic Verilog simulation

Step 13. Now you will exercise different Run functions. They are found in the main VSIM window under the Run menu button (OpenWindows) or Run in the Motif menu bar. (You may need to expand the window to view all of the buttons.)

Step 14. Select Run >100 ns. This causes the simulation to run and then stop after 100 ns (the default simulation length). Instead of clicking the RUN button you could also type the run command. To try it now, type: run 500

Now the simulation has run for a total of 600ns (the default 100ns plus the 500 you just asked for). A status bar reflects this information at the bottom of the main VSIM window.

Step 15. The last command you typed (run 500) caused the simulation to advance for 500ns. You can also advance simulation to a specific time. Type: run @ 3000

This advances the simulation to time 3000ns. Note that the simulation actually ran for 2400ns (3000 - 600).

Step 16. Now select Run >Time'High. This causes the simulator to run forever. To stop the run, go on to the next step.

Getting Started with V-System Using V-System for Workstations - 57 Lesson 2: Basic Verilog simulation

Step 17. Click Break. The arrow points to the next HDL statement to be executed.

You window won’t look exactly like the illustration because your simulation very likely stopped at a different point. Next we'll take a brief look at some interactive debug features of the V-System environment. To start with, let's see what we can do about the way the List window presents it's data.

Step 18. From the List window menu bar click on the Signals button. Select a display radix of Decimal for the signal count. Click Apply. This causes the List window output to change; the count signal is now listed in decimal rather than the default binary.

58 - Using V-System for Workstations Getting Started with V-System Lesson 2: Basic Verilog simulation

Step 19. Let’s set a breakpoint at line 30 (which contains a call to the Verilog function increment). To do this, simply move the cursor to the Source window and scroll the window to display line 30. Click at or near line number 30 to set a breakpoint.

Getting Started with V-System Using V-System for Workstations - 59 Lesson 2: Basic Verilog simulation

You will see a dot appear next to the line number. This indicates that a breakpoint has been set for that line. Clicking line 30 once more would remove the breakpoint but don’t do that now.

Step 20. Select Run from the VSIM menu bar to resume execution of the simulation. When the simulation hits the breakpoint, it stops running, highlights the Source window and issues a message in the Transcript window.

Step 21. Typically when a breakpoint is reached you will be interested in one or more signal values. There are a few ways to determine this. You can: • look at the values shown in the Signals window, or • examine the current value of the signal count by typing: examine count

As a result of your command the count is output to the VSIM window.

Step 22. Let’s move through the Verilog source functions with V-System’s Step and Step Over commands. Click Step Over on the toolbar.

This causes the simulator to step over the function call on line 30. The Step button on the toolbar would have single-stepped the simulator, including each line of the increment function.

60 - Using V-System for Workstations Getting Started with V-System Lesson 2: Basic Verilog simulation

Step 23. Experiment by yourself for a while; setting and clearing breakpoints as well as Step’ing and Step Over’ing function calls until you feel comfortable with the operation of these commands.

Step 24. Now let’s get a Wave window view of the simulation; activate the Wave window. When the Wave window is first drawn, there is one cursor in it at time zero. Clicking anywhere in the waveform display brings that cursor to the mouse location. Up to ten cursors can be present at the same time. Cursors are displayed with a time box showing the precise simulation time at the bottom. When you have more than one cursor, each time box appears in a separate track at the bottom of the display.

Step 25. Try adding or removing cursors with the Cursor > New Cursor | Delete Cursor command. When you add a cursor, it is drawn in the middle of the display. Once you have more than one cursor, VSIM adds a delta measurement showing the time difference between the two cursor positions. The selected cursor is drawn as a solid line; all other cursors are drawn with dotted lines.

Getting Started with V-System Using V-System for Workstations - 61 Lesson 2: Basic Verilog simulation

Step 26. Click in the waveform display. Notice how the cursor closest to the mouse position is selected and then moved to the mouse position. Another way to position multiple cursors is to use the mouse in the time box tracks at the bottom of the display. Clicking anywhere in a track selects that cursor and brings it to the mouse position. The cursors are designed to snap to the closest wave edge to the left on the waveform that the mouse pointer is positioned over. You can position a cursor without snapping by dragging in the area below the waveforms.

Step 27. Experiment with using the cursors, scrolling, and zooming (see page 83 for Wave window shortcuts).

Step 28. When you’re done experimenting, quit the simulator by entering the command: VSIM> quit -force

62 - Using V-System for Workstations Getting Started with V-System Lesson 3: Mixed VHDL/Verilog simulation

Lesson 3: Mixed VHDL/Verilog simulation

You must be using V-System/PLUS Workstation for this lesson. Thanks to V-System’s single kernel simulator, the VHDL simulation procedures you learned in the previous lesson apply directly to mixed VHDL/Verilog simulation. The goals for this lesson are: • compile multiple VHDL and Verilog files • simulate a mixed VHDL and Verilog design • list VHDL signals and Verilog nets and registers • view the design in the Structure window • view the HDL source code in the Source window

Step 1. First, return to the directory you created in Lesson 1. cd

Next copy the VHDL and Verilog files to the directory (note the period specifying the current directory): cp //modeltech/examples/mixedHDL/*.vhd . cp //modeltech/examples/mixedHDL/*.v .

Step 2. A group of Verilog files can be compiled in any order. Note, however, in a mixed VHDL/ Verilog design the Verilog files must be compiled before the VHDL files. Compile the Verilog files with this command: vlog cache.v memory.v proc.v

Step 3. Depending on the design, the compile order of VHDL files can be very specific. In the case of this lesson, the file top.vhd must be compiled last. Compile the VHDL files with this command: vcom util.vhd set.vhd top.vhd

Getting Started with V-System Using V-System for Workstations - 63 Lesson 3: Mixed VHDL/Verilog simulation

Step 4. Invoke vsim with the name of the top level design: vsim top

Step 5. At the VSIM prompt type: VSIM> view *

Step 6. This time you will use the VSIM command line to add all of the HDL items in the region to the List and Wave windows: VSIM> list * VSIM> wave *

Step 7. The Structure window is hierarchical. Notice the mixture of VHDL and Verilog in the design. VHDL levels are indicated by a square “prefix” in the Structure window, while Verilog levels are indicated by a circle “prefix.” Try expanding (+) and contracting (–) the structure layers. You’ll find Verilog modules have been instantiated by VHDL architectures and VHDL by Verilog.

64 - Using V-System for Workstations Getting Started with V-System Lesson 3: Mixed VHDL/Verilog simulation

Let’s take another look at the design.

Step 8. Click on the Verilog module, c: cache. The source code for the Verilog module is now shown in the Source window.

Step 9. Scroll down to line #25. (You might try searching as alternative to scrolling, see page 81 for more information.) Note the declaration of cache_set; this is a VHDL entity instantiated within the Verilog file cache.v.

Getting Started with V-System Using V-System for Workstations - 65 Lesson 3: Mixed VHDL/Verilog simulation

Step 10. Click on the line "s0:cache_set(only)" in the Structure window.

The Source window now shows the VHDL code for the cache_set entity.

66 - Using V-System for Workstations Getting Started with V-System Lesson 3: Mixed VHDL/Verilog simulation

Before you quit, try experimenting with some of the commands you’ve learned from Lesson 1. Note that in this design, “clk” is already driven, so you won’t need to use the force command.

Step 11. When you’re ready to quit simulating, enter the command: VSIM> quit -force

Getting Started with V-System Using V-System for Workstations - 67 Lesson 4: Debugging a VHDL design

Lesson 4: Debugging a VHDL design

The goals for this lesson are: • show an example of a VHDL testbench — a VHDL architecture that instantiates the VHDL design units to be tested, provides simulation stimuli, and checks the results • map a logical library name to an actual library • change the default run length • recognize assertion messages in the command window • change the assertion break level • restart the simulation run using the restart command • examine composite types displayed in the VSIM Variables window • change the value of a variable • use a strobe to trigger lines in the VSIM List window • change the radix of signals displayed in the VSIM List window The example in this lesson uses a package which you will put into a different library.

Step 1. To create the new library, enter the following command at the shell prompt: vlib library_2

Step 2. Compile the package by entering the next command at the shell prompt: vcom -work library_2 stdlogic.vhd

Step 3. The other VHDL files expect the stdlogic package to be in a library having the logical name IEEE. To set this up, you can edit the [Library] section of the vsystem.ini file, or you can create a logical library name with the vmap command: vmap ieee library_2

68 - Using V-System for Workstations Getting Started with V-System Lesson 4: Debugging a VHDL design

vmap modifies the vsystem.ini file for you.

Step 4. Compile the other files by entering the following sequence of commands: vcom gates.vhd vcom adder.vhd vcom testadder.vhd

The command could also list all the files on one line: vcom gates.vhd adder.vhd testadder.vhd

Step 5. Start the simulator by entering the following command at the shell prompt: vsim

The VSIM Startup window is displayed, as shown below.

Getting Started with V-System Using V-System for Workstations - 69 Lesson 4: Debugging a VHDL design

Step 6. Perform the following steps in this window: • Make sure that the simulator resolution is ns. • Look in the Entity or Configuration scroll box and select the design unit named test_adder_structural. This design unit is a configuration, so no architectures are displayed in the architecture scroll box at the bottom of the window. • Click Load to accept the settings.

Step 7. To open all the VSIM windows, enter the following command in the main VSIM window at the VSIM prompt: VSIM> view *

V-System will open all the windows in the positions you left them in at the end of the last exercise if no one has run the simulator since then.

Step 8. To list the top-level signals, enter the command: VSIM> list /*

Step 9. To add top-level signals to the Wave window, enter the command: VSIM> wave /*

Step 10. To change the length of the default simulation run in the VSIM main window, click the button marked Prop. This stands for “properties.” (In Motif, it’s the Options command.)

Step 11. This brings up the VSIM Properties window. Move the pointer to the Default Run field and enter 1000. Do not change the other settings.

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Step 12. Click Apply (OK in Motif) to accept the new settings.

Step 13. Next, you will run the simulator. In the main VSIM window, select Run and then click 1000 ns.

A message in the main VSIM window will notify you that there was an assertion error. # ** Error: Sum is 00000111. Expected 00001000

Getting Started with V-System Using V-System for Workstations - 71 Lesson 4: Debugging a VHDL design

Let's find out what's wrong. Perform the following steps to track down the assertion message:

Step 14. In the main VSIM window, click the Prop button (Options in the Motif menu bar).

Step 15. Change the selection for Break on Assertion to Error and click Apply. This will cause the simulator to stop at the HDL statement after the assertion is displayed.

Step 16. To restart the simulation, in the main VSIM window, select File and then click Restart design. Then press Restart on the VSIM Restart dialog box.

Step 17. Next, in the main VSIM window, select Run and then click 1000 ns.

Step 18. Notice that the arrow in the VSIM Source window is pointing to the statement after the assertion.

Step 19. If you turn to the VSIM Variables window now, you can see that i = 6, so the simulation

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stopped in the sixth iteration of the test pattern’s loop. (Resize the Variables window to see everything.)

Step 20. Expand the variable named test_patterns by clicking the [+].

Step 21. Also expand the sixth record in the array, that is, test_patterns(6), by clicking the [+]. The VSIM Variables window should look like the one below:

The assertion shows that the signal sum does not equal the sum field in test_patterns(6). Note that the sum of the inputs a, b, and cin should be equal to the output sum. But there is an error in the test vectors. To correct this error, you need to restart the simulation and modify the initial value of the test vectors.

Step 22. In the main VSIM window, type: VSIM> restart -f

The -f option causes VSIM to restart without popping up the confirmation dialog.

Getting Started with V-System Using V-System for Workstations - 73 Lesson 4: Debugging a VHDL design

Step 23. In the VSIM Variables window, expand test_pattern(6) again. Then highlight the sum record by clicking on the variable name (not the box before the name) and then click the Change menu button.

Step 24. Select the last four bits in the value field 1000 by dragging the pointer across them. Then replace them with 0111. (Note that this is a temporary edit, you must use your text editor to permanently change the source code.)

Step 25. Collapse the Variables window if necessary and click Change.

Step 26. Select Run and 1000 ns. At this point, the simulation will run without any errors. # ** Note: Test completed with no errors. # Time: 1 us Iteration: 0 Instance: /

Next you will learn how to change the triggering for the VSIM List window.

74 - Using V-System for Workstations Getting Started with V-System Lesson 4: Debugging a VHDL design

By default, a new line is displayed in the VSIM List window for each time unit at which a listed signal changes. The following steps will change this so that values are only listed every 100 ns.

Step 27. In the VSIM List window, select Triggers (OpenWindows) or Properties and then Triggers (Motif). Perform the following steps in the resulting Triggers dialog box : • Deselect Trigger on: Signals to disable triggering on signals. • Select Trigger on: Strobe to enable the strobe. • Enter 100 in the Strobe period field. • Enter 70 in the First strobe at field. • Click the appropriate button to tell the simulator you accept the settings.

Step 28. Your next action will be to change the radix for a, b, and sum to decimal. In OpenWindows, go to the VSIM List window and select Signals. This will open the List Signals dialog box. Select the signal you want in this box. In Motif, use the List window buttons Properties and then Signals. This brings up the List Signals dialog box. Select the signal name by clicking on the name at the top of the List window.

Getting Started with V-System Using V-System for Workstations - 75 Lesson 4: Debugging a VHDL design

Make these selections in the List Signals dialog box: • Select signal a, then click Decimal , then click Apply. • Select signal b, then click Decimal, then Apply. • Select signal sum, then click Decimal, then Apply.

This brings you to the end of this lesson, but feel free to experiment further with the menu system. When you are ready to end the simulation session, quit VSIM without saving data by entering the following command in the main VSIM window: VSIM> quit -force

76 - Using V-System for Workstations Getting Started with V-System Lesson 5: Running a batch-mode simulation

Lesson 5: Running a batch-mode simulation

The goals for the fifth lesson are: • run a batch-mode simulation • execute a macro file • view a saved simulation

Step 1. For this lesson, you will use a macro file that provides stimulus for the counter. For your convenience, a macro file has been provided with the V-System/Workstation program. You need to copy this macro file from the installation directory by entering the command: cp //modeltech/examples/stim.do .

Step 2. Create a batch file using an editor; name it yourfile. With the editor, put the following on separate lines in the file: list -decimal * do stim.do write list counter.lst

Step 3. To run the batch-mode simulation, enter one the following command: vsim -wav saved.wav counter < yourfile

This is what you just did in Step 3: • invoked the VSIM simulator on a design unit called counter that was provided with your software • you used the -wav switch to instruct the simulator to save the simulation results in a log file named saved.wav • used the contents of yourfile to specify that values are to be listed in decimal, to execute a stimulus file called stim.do, and to write the results to a file named counter.lst, the default for a design named counter

Getting Started with V-System Using V-System for Workstations - 77 Lesson 5: Running a batch-mode simulation

Step 4. Since you saved the simulation results in saved.wav, you can view the simulation results by starting up VSIM with its –view switch: vsim -view saved.wav

Step 5. Open these windows with the VIEW button or the equivalent command: VSIM> view structure signals list wave

Note: You cannot open the Process or Variables windows. You are looking at a saved simulation, not examining one interactively; the logfile saved in saved.wav was used to reconstruct the current windows.

Step 6. Now that you have the windows open, put the signals in them: VSIM> wave * VSIM> list *

Step 7. Use the available VSIM windows to experiment with the saved simulation results and quit when you are ready: VSIM> quit

If you want to read more about the batch and command line modes, see the V-System/PLUS Workstation User’s Manual.

78 - Using V-System for Workstations Getting Started with V-System Lesson 6: Executing commands at startup

Lesson 6: Executing commands at startup

The goals for the sixth and final lesson are: • specify the design unit to be simulated on the command line • edit the vsystem.ini file • execute commands at startup

Step 1. For this lesson, you will use a macro file that provides startup information. For convenience, a startup file has been provided with the V-System program. You need to copy this macro file from the installation directory by entering the command (note the period specifying the current directory): cp //modeltech/examples/startup.do .

Step 2. Next, you will edit the system initialization file in the current directory to specify a command that is to be executed after the design is loaded. To do this, open the vsystem.ini file using a text editor and add the following line in the [vsim] section of the file: Startup = do startup.do

Step 3. Take a look at the macro file. It uses the predefined variable $entity to do different things at startup for different designs.

Step 4. Start the simulator and specify the top-level design unit to be simulated by entering the following command at the shell prompt: vsim counter

Notice that the simulator loads the design unit without displaying the VSIM Startup window. This is handy if you are simulating the same design unit over and over. Also notice that all the windows are open. This is because the view * command is included in the macro that you executed at startup.

Getting Started with V-System Using V-System for Workstations - 79 Lesson 6: Executing commands at startup

Step 5. If you plan to continue with the following practice sessions, keep V-System running. If you would like to quit the simulator, enter the following command at the prompt in the main VSIM window: VSIM> quit -force

To read more about the vsystem.ini file and batch/command line modes, see the V-System/ PLUS Workstation User’s Manual.

80 - Using V-System for Workstations Getting Started with V-System Practice 1: Searching in tree windows

Practice 1: Searching in tree windows

The find and next commands search vertically for names within tree windows. You can try these commands during simulation in the Process, Signals, Structure, Variables and Wave windows. If you don’t have a simulation running you can start one from the previous lessons. Syntax .Process Find [-Field ] [-Quiet] [-Reverse] .Process Next

.SIgnals Find [-Field ] [-Quiet] [-Reverse] .SIgnals Next

.STructure Find [-Field ] [-Quiet] [-Reverse] .STructure Next

.Variables Find [-Field ] [-Quiet] [-Reverse] .Variables Next

.Wave Next [-Field ] [-Quiet] [-Reverse] .Wave Next

The name search is initiated from the currently selected HDL item. If no items are selected, the search starts at the top. The search results in the matched item being selected; the window is scrolled if required in order to make the item visible. When searching in the Structure window, the search will examine unexpanded nodes and treat them as expanded. If a match is found within a collapsed node, the collapsed node will be selected. But this node is not the matched node; it is a parent of the match. In order to see the actual match, you will need to expand the node and do a .structure next. If you do a .structure next without expanding the node, the search will select the parent again; so to get beyond that point you will need to take some action: either expand the node or select a sibling of the parent. Arguments

–Field Changes the field searched in the item. The field number ranges from 1 to 3 for all windows except the structure window where it ranges from 1 to 2. The field number defaults to 1 for all

Getting Started with V-System Using V-System for Workstations - 81 Practice 1: Searching in tree windows

windows except the process window, which defaults to 3. By changing the field, you can search for entity (arch) in the Structure window, instead of instance labels; in other windows you can search for signal or variable values instead of names; in the Process window you can search for status or process labels instead of full paths. Optional.

–Quiet Suppresses “no match” messages. Optional.

–Reverse Causes the search to go backwards. (Note that using -reverse might be slow in trees with 1000 or more elements.) Optional.

The search pattern can be an arbitrary string or wildcard pattern (see below). Required. Examples The examples below show two commands. The first searches the Wave window for any signal name beginning with “bus”. The second command searches the Structure window for a design unit named my_comp using arch(only); the –field argument specifies that the entity(architecture) field, not the instance name field, is to be searched. .wave find bus* .st f -f 2 my_comp(only)

82 - Using V-System for Workstations Getting Started with V-System Practice 2: Wave window shortcuts

Practice 2: Wave window shortcuts

Using the following keys with the mouse cursor within the Wave window will cause the indicated actions. Give them a try with your current simulation. If you don’t have a simulation running you can start one from the previous lessons.

Note: Under OpenWindows the mouse cursor must be over the scroll bar for the scrolling shotcuts to work. V-System for workstations keyboard shortcuts

KEY ACTION

i I or + zoom in o O or - zoom out f or F zoom full l or L zoom last r or R zoom range scroll waveform display up scroll waveform display down scroll waveform display left scroll waveform display right searches forward (right) to the next transition on the selected signal searches backward (left) to the previous transition on the selected signal

Zooming with the mouse Use the middle mouse button in the right windowpane (the waveform display). Position the mouse cursor to the left side of the desired zoom interval, press the middle mouse button, and while continuing to press, drag to the right and then releaes at the right side of the desired zoom interval. You can also zoom using the ZOOM menu.

Getting Started with V-System Using V-System for Workstations - 83 Continuing with V-System for workstations

Continuing with V-System for workstations

More information on V-System commands, functions and techniques for use can be found in the following locations: • V-System/PLUS Workstation User’s Manual an Adobe Acrobat (.pdf ) version of our user’s manual is available in the /modeltech/docs directory after installation • Tips and Techniques appendix of the user’s manual • technote text files installed with V-System located in the /modeltech/docs directory

84 - Using V-System for Workstations Getting Started with V-System 6 - Using V-System for PCs

The purpose of this section is to help you become familiar with how to use V-System for PC’s to generate and debug your designs. We assume that you are familiar with the use of the Microsoft Windows operating system. If this is not the case, we recommend that you work through the tutorials provided with Microsoft Windows before using V-System. Please note that this section is designed to help you use V-System/VHDL PC and V-System/ PLUS PC; it is not a VHDL or Verilog tutorial. Work through the lessons to learn how to use the V-System within the PC environment. You must be using V-System/PLUS PC to work Lessons 2 and Lesson 3, which involve Verilog and mixed VHDL/Verilog simulations.

Divisions in this section include: • V-System application window on page 86 • V-System menu bar on page 88 • V-System tool bar on page 91 • Tutorial setup on page 92 • Lesson 1: Basic VHDL simulation on page 93 • Lesson 2: Basic Verilog simulation on page 106 • Lesson 3: Mixed VHDL/Verilog simulation on page 122 • Lesson 4: Debugging a VHDL design on page 129 • Practice: Using the keyboard, mouse and menus on page 141

Getting Started with V-System Using V-System for PCs - 85 V-System application window

V-System application window

The V-System application window and Transcript window are pictured below as they appear when V-System is first started. Note that typical window parts are used in V-System. The control-menu icon, title bar, minimize, maximize and close buttons appear across the top. A menu bar appears immediately under those items. Scroll bars are available when necessary at the right side and bottom of the window.

A tool bar (under the menu bar) and a status bar (at the bottom of the application window) are added by V-System. The status bar gives you information about the data in the active V-System window. The tool bar gives you access to most common V-System functions no matter which V-System window is active. Choices under the Window >menu bar option let you turn on and off the tool bar and the status bar.

86 - Using V-System for PCs Getting Started with V-System V-System application window

In addition to the Transcript window, the V-System application window also accommodates eight other windows for use during your design compilation, simulation, and debugging. They are the Dataflow, List, Signals, Source, Structure, Process, Variables, and Wave windows. A portion of each window is shown below.

Getting Started with V-System Using V-System for PCs - 87 V-System menu bar

V-System menu bar

The menu bar at the top of the application window lets you access all the V-System commands and features. The menus are listed below with brief descriptions of the command’s use.

File Directory... change working directories Execute Macro... run a macro Compile VHDL... compile VHDL source Compile Verilog... compile Verilog source ------Simulate... start a simulation Restart... restart a simulation End Simulation... end a simulation and stay in V-System ------Select Source File select the code shown in Source window ------Exit V-System exit V-System

View All open all VSIM windows ------Source open and/or view the Source window Structure open and/or view the Structure window Variables open and/or view the Variables window Signals open and/or view the Signals window List open and/or view the List window Process open and/or view the Process window Wave open and/or view the Wave window Dataflow open and/or view the Dataflow window

Library New... create a new HDL design library Contents... view the contents of a library Mapping... map a library to a new name

88 - Using V-System for PCs Getting Started with V-System V-System menu bar

Project New... create a new vsystem.ini project file Change... change to another project file ------ former vsystem.ini file name of current vsystem.ini file

Run Run run simulation for one default run length Run Forever run simulation until you stop it Step single-step the simulator Step Over execute without single-stepping through a subprogram Cont continue the simulation Break stop the simulation

Signals View... select which signal types to view Add to Wave > Selected Signal add specified signal to Wave window Signals in Region add all signals in region to Wave window Signals in Design add all signals in the design to the Wave window Add to List > Selected Signal add specified signal to List window Signals in Region add all signals in region to List window Signals in Design add all signals in the design to the List window Add to log file > Selected Signal add specified signal to log file Signals in Region add all signals in region to log file Signals in Design add all signals in the design to log file ------Force Signal change value of selected signal

Options Compile Options > VHDL select VHDL compiler options Verilog select Verilog compiler options Simulation Options... select simulation and Source display options Edit Breakpoints... modify or delete source code breakpoints Macro Options > Echo Commands echo macro commands in transcript window Hide Commands do not echo commands

Getting Started with V-System Using V-System for PCs - 89 V-System menu bar

Processes > View Active Processes view only processes active in current delta View Processes in Region view all processes in current region

Window Cascade cascade windows Tile Horizontal tile windows horizontally Tile Vertical tile windows vertically Arrange Icons arrange icons at bottom of application window Restore All restore all icons to windows ------Colors change colors of window features Fonts change font settings in windows Settings store window settings ------Tool Bar toggle tool bar Status Bar toggle status bar ------1 Transcript switch to, or show if hidden 2 Source switch to, or show if hidden 3 List switch to, or show if hidden 4 Structure switch to, or show if hidden 5 Process switch to, or show if hidden 6 Variables switch to, or show if hidden 7 Signals switch to, or show if hidden 8 Wave switch to, or show if hidden 9 Dataflow switch to, or show if hidden

Help Index open the V-System help index Using Help open the Windows help introduction ------About V-System display V-System application information

90 - Using V-System for PCs Getting Started with V-System V-System tool bar

V-System tool bar

In addition to the functions accessed through the menu bar, you can use the V-System tool bar for several frequently-used commands:

BUTTON MENU EQUIVALENT

VCOM File > Compile VHDL…. VLOG File > Compile Verilog…. VSIM File > Simulate…. RUN Run > Run …. CONT Run > Cont…. STEP Run > Step…. OVER Run > Step Over….

Grayed-out tool bar buttons (like RUN and CONT or STEP and OVER above) indicate commands that are not currently available. You’ll use the tool bar buttons for the lessons later in this section.

Getting Started with V-System Using V-System for PCs - 91 Tutorial setup

Tutorial setup

Before we turn you loose with V-System, let’s set up your application windows and save their settings so that if you are interrupted and restart, you will find the windows like you left them. In this setup you will learn how to: • start the application • save your window settings

Step 1. Start by invoking V-System: Double-click the V-System icon. The V-System application window will come up with the Transcript window showing. Maximize the V-System application window to fill your screen.

Step 2. If you cannot see the tool bar or the status bar, use the Window > Tool Bar and Window > Status Bar menu sequences to make them visible.

Step 3. Use the Window > Settings menu sequence and check all of the boxes indicated in the Save Settings dialog box shown below. Now whenever you exit V-System, your window settings will be saved.

Click OK. You can now exit, or continue on to Lesson 1.

Note: In the exercises, just type what’s shown in this guide and then use the or key to complete the line.

92 - Using V-System for PCs Getting Started with V-System Lesson 1: Basic VHDL simulation

Lesson 1: Basic VHDL simulation

The goals for the first lesson are: • create a library • create a new project file • compile a VHDL file • start the simulator • use the RUN command • list some signals • use the waveform display • force the value of a signal • single-step through a simulation run • set a breakpoint • save the listing from the List window to a file • quit the simulator

Step 1. For this exercise you need to change directories to locate the tutorial files. To do this, pull down the File menu and select Directory. This brings up the Change Directory To: dialog box. You can navigate among the directories and view their contents in the files scroll box. The directory your looking for, \examples, is located within the directory that contains vsystem.exe, the V-System executable.

Step 2. Double-click on the examples entry in the directories list box to move within the \examples directory. Click OK.

Getting Started with V-System Using V-System for PCs - 93 Lesson 1: Basic VHDL simulation

If you click Cancel, the dialog box is closed and you remain in the same working directory as before. You must click the OK button to actually change to a different directory. Using the File > Directory menu command is the same as entering the change directory (cd) command at the V-System prompt in the Transcript window. In fact, the following command is echoed in the Transcript window: cd C:\vsystem\examples

Step 3. Before you can compile a VHDL source file, you need to create a design library to hold the compilation results. Pull down the Library menu and select New…. This brings up a dialog box that prompts you to enter the name of the new VHDL library.

Enter the name work and click Create. The command is echoed in the Transcript window: vlib work

94 - Using V-System for PCs Getting Started with V-System Lesson 1: Basic VHDL simulation

This creates a VHDL library named work under the current directory. Even though this command creates a DOS directory called work, it is important to realize that it is more than just a directory. You must use only the Library > New option or a vlib V-System command to create a new V-System library. Do not use the DOS mkdir command or Microsoft Windows to create the directory!

Note: If this tutorial has already been run on your system, a message will report that the work subdirectory already exists in the current directory. You can ignore the message and proceed.

Step 4. Now you need to create a new project file in your current working directory. This project file will remember things about your environment (such as window sizes and positions, etc.), so that next time you work in this directory, V-System will automatically reload your environment for you. To create a new project, select Project > New. Type in vsystem.ini, which is the name V-System expects to find when you come back to this project later.

Note: A project file will already exist if someone has done this exercise before. Again, V-System will just give you a message that you can safely ignore.

Step 5. Pull down the Project menu again and notice that the file /examples/vsystem.ini is checked, indicating that V-System is using that project file. If you wanted, you could change back to the original project file by simply selecting it from the menu, which would move the check mark to it —but don’t do that.

Step 6. Next, compile the VHDL source file named counter.vhd. To do this, pull down the File menu and select Compile VHDL….

Getting Started with V-System Using V-System for PCs - 95 Lesson 1: Basic VHDL simulation

This brings up the Compile VHDL Source dialog box. For now, click Done.

Step 7. Press the VCOM button on the tool bar. The same dialog box appears. Now select the VHDL source file for the counter, which is named counter.vhd, and then click Compile. When you click Compile, the V-System VHDL compiler is invoked and generates the messages shown below unless it encounters errors.

During compilation, the V-System prompt is not displayed. You will know that the compiler is finished when the V-System prompt returns to the Transcript window command line.

Step 8. After the VHDL source file is compiled, close the dialog box by selecting Done, and then you can start the simulator by pulling down the File menu and selecting Simulate.

96 - Using V-System for PCs Getting Started with V-System Lesson 1: Basic VHDL simulation

This brings up the Simulate a Design dialog box, where you select the library and the top-level design unit to simulate. You can also select the simulation time resolution. But select Cancel for now.

See Simulate a Design dialog box for PCs on page 30 for more detail about the Simulate a Design dialog box.

Step 9. Click on the VSIM button in the tool bar. This time select the entity named counter to be simulated. When you select the entity name, the names of any associated architectures are displayed in the scrollbox at the bottom of the dialog. The counter only has one architecture, which is named only. Click OK to accept the settings. The remaining V-System windows are now available for viewing within the original application window.

Step 10. Use the View>All menu sequence to open all of the V-System windows. If you are the first person to use this tutorial, the windows will cascade. The windows may be in some other arrangement if the tutorial has already been used. For now, select Window > Tile Vertically. The order of the windows might be different on your screen, but you should be able to see all nine as in the illustration.

Getting Started with V-System Using V-System for PCs - 97 Lesson 1: Basic VHDL simulation

Note that the Transcript window has echoed “view *” for your window command.

Step 11. At this point, let’s put signals in both the List and the Wave windows. Type: list *

and then: wave *

Notice that no matter which window is active, when you type while running V-System on a PC, you are automatically entering information on the Transcript window command line. The commands you typed made signals appear in the List and Wave windows. If you desired to, you could list or view only specified signals by entering the signal names after the command instead of the asterisk. (When you do that, separate the names with spaces.)

98 - Using V-System for PCs Getting Started with V-System Lesson 1: Basic VHDL simulation

Step 12. An alternative would be to use the menu bar. If you use the Signals menu, you will see several options.

Step 13. Before we go on, let’s customize the window positions and sizes. Select Window > Tile Vertically. Make the Transcript, Source, and Structure windows about equal size across the top tier. Then put the Process, Signals, Dataflow, and Variables windows in the second row. Now if you make the List and Wave windows twice as big, you will be using the entire screen again — probably something like the illustration.

Getting Started with V-System Using V-System for PCs - 99 Lesson 1: Basic VHDL simulation

Step 14. Use the Window > Settings menu sequence to be sure all your changes will be saved. Make sure these boxes are checked: Sizes, Colors, Fonts and Save sizes on exit.

Step 15. Now let’s apply some stimulus to the clock input of our circuit. Type: force clk 1 50, 0 100 -repeat 100

This force command means: • Force clk to the value “1” at 50 ns (nanoseconds) after the current time, • then to “0” 100 ns from now, and • repeat this cycle every 100 ns.

Step 16. Select RUN on the tool bar. This causes the simulation run for the default simulation length, which is 100 ns. (The default simulation run length can be modified with Options > Simulation Options… from the menu bar.) Other ways of entering a run command include typing it in the Transcript window, or selecting an option from the Run menu: Run, Run Forever, Step, Step Over, Cont or Break. See V-System menu bar on page 88 for more information about run options.

Step 17. Next type: run 500

100 - Using V-System for PCs Getting Started with V-System Lesson 1: Basic VHDL simulation

Now that you have run the simulation for 600 nanoseconds, look at the status bar at the bottom of the V-System application window. It should look something like this illustration.

Step 18. If your status bar is different, it is because the status bar changes with the active window. Click in another V-System window and examine the status bar again.

Step 19. Let’s get back to running the simulator. You can run the simulator for a long time by entering a large number of time units. You can also make the simulator run to a specific time with a command like this: run @

Use the run command with @ to run to time 5000: run @5000

Step 20. To see the effect of the Break feature, you are now going to start a long simulation run and then click the BREAK button while it is running to stop the simulator. On the menu bar, select Run > Run Forever. (The run -a command produces the same effect.)

Step 21. To stop the simulator while it is running, click the BREAK button. This updates the Source window; an arrow will be pointing to the next VHDL statement to be executed.

Getting Started with V-System Using V-System for PCs - 101 Lesson 1: Basic VHDL simulation

Note: Your window won’t look like the illustration above. Your simulation will probably stop at a different point.

Step 22. If your Source window is hard to read because the standard tabs are too big for the window size, change the tabs with the Options > Simulation Options menu sequence. Select the Misc tab in the Simulation Options dialog box, then change the Tab Width to 2 characters, leaving the other options unchanged. Click OK, then Yes, to save your changes.

Step 23. Next, set a breakpoint on line 35, which has a call to the VHDL function named "increment".

102 - Using V-System for PCs Getting Started with V-System Lesson 1: Basic VHDL simulation

To do this, move the pointer to the Source window and find line 35. Use the vertical scroll bar if necessary. Double-click on line 35 to set the breakpoint. You will see a dot next to the line number when the breakpoint is set. A breakpoint can be toggled on and off by double-clicking on the line.

Step 24. Select CONT (continue) on the tool bar to resume the run that you interrupted. When the simulator hits the breakpoint, it is indicated by highlighting in the Source window and by a message in the Transcript window.

Step 25. Examine the current value of the signal count by entering the command: examine count

You can also see this information in the Signals window.

Step 26. You can find out what kind of variable or signal count is by using the V-System command describe. To see this, enter: describe count

Getting Started with V-System Using V-System for PCs - 103 Lesson 1: Basic VHDL simulation

The system should report (in the Transcript window) that count is an 8-bit array of an enumerated type:

Step 27. Click OVER (for Step Over) in the tool bar to step over this instruction. If you had clicked STEP instead, the simulation would have entered the increment function called in line 35.

Step 28. Re-examine the value of count and notice that its value has not changed. Even though the signal count has been assigned a new value, the counter has not yet been incremented, because a signal assignment does not take effect until after any propagation delay that is specified using an after clause in its VHDL signal assignment statement.

Step 29. Again, select CONT to resume the run.

Step 30. On your own, go ahead and try setting and deleting breakpoints at different points in the counter source file, and using the STEP and OVER buttons until you feel comfortable with these commands.

Step 31. When you are ready, you can record the simulation values by writing the contents of the V-System List window to a file (this is optional; this could be a huge file). To do this, enter the following command in the Transcript window: write list counter.lst

104 - Using V-System for PCs Getting Started with V-System Lesson 1: Basic VHDL simulation

Alternately you can activate the List window (by clicking anywhere in it) and then choose File > Save Listing…. The listing will resemble the illustration below. ns delta count clk reset 0 +0 00000000 0 0 50 +0 00000000 1 0 55 +0 00000001 1 0 100 +0 00000001 0 0 150 +0 00000001 1 0 155 +0 00000010 1 0 . . . 62555 +0 01110010 1 0 62600 +0 01110010 0 0 62650 +0 01110010 1 0 62655 +0 00000000 1 0 62700 +0 00000000 0 0 62750 +0 00000000 1 0

Step 32. Now quit the simulator. You can type exit or you can choose File > Exit V-System with the Transcript window active. V-System then returns a dialog box.

At this point you can confirm the action with the Yes button. If you want to skip the dialog box, enter the command: exit -force

Getting Started with V-System Using V-System for PCs - 105 Lesson 2: Basic Verilog simulation

Lesson 2: Basic Verilog simulation

The goals for this lesson are: • compile a Verilog design • examine the hierarchy of the design • list signals in the design • change list attributes • set a breakpoint If you’ve completed the previous lesson, Basic VHDL simulation, you’ll notice how the V-System simulation processs for VHDL and Verilog is virtually the same.

Step 1. First, you need to change directory to the folder where the tutorial files are located. To do this, pull down the File menu and select Directory. This brings up the Change Directory To: dialog box with which you can browse the file system of your PC and choose directories via the directories list scrollbox.

Notice the dialog box may not default to the directory where V-System is installed. You may need to browse to locate the V-System install directory and the tutorial files. The tutorial folder is called examples and should be in the same directory as vsystem.exe, the V-System executable.

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Step 2. Move inside the examples folder by double-clicking the examples entry in the directories list box. Click OK If you click Cancel, the dialog box is closed and you remain in the working directory you were in before. You must click OK to actually change to a new directory. Using the File > Directory menu command is the same as entering the change directory (cd) command at the V-System prompt in the Transcript window. In fact, notice how your change directory dialog box actions were echoed in the Transcript window e.g.: cd C:\vsystem\examples

Step 3. Pull down the Library menu and select New... This brings up a dialog box where you can enter the name of your new library. Before you can compile a Verilog design, you need to create a library to store the compilation results. If you are only familiar with interpreted Verilog simulators such as Cadence Verilog XL this will be a new idea for you. Because V-System is a compiled Verilog, it requires a target design library for the compilation. V-System can compile both VHDL and Verilog code into the same library if desired.

Enter the name work and click Create. Notice how the command is echoed in the Transcript window: vlib work

This creates a design library named work in the current working directory. Even though this appears to be a DOS directory, it is in fact much more. You must use only the Library > New... option (or a vlib V-System command) to create a new V-System library. Do not use the DOS mkdir (or an equivalent Microsoft Windows operation) to create a design library directory!

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Note: If this tutorial has already been run on your system, or you’ve just completed Lesson 1, a message will report that the work subdirectory already exists in the current directory. You may safely ignore this message and proceed.

Step 4. To create a new project file, select Project > New. Type in vsystem.ini. which is the name V- System expects to find when you return to this project later.

Next you need to create a new project file in your current working directory. This project file will be used by V-System to remember your environment settings (such as window sizes and positions, etc.) so the next time you work from this directory V-System can reload the environment for you. A project file may already exist in the current directory if someone has previously run this tutorial. Again, V-System may give you a warning message to that effect, which you can safely ignore.

Step 5. Pull down the Project menu again and notice that the file examples/vsystem.ini is checked, indicating it is currently in use by V-System. If you wanted, you could change back to the previous project file by simply selecting it from the menu. This would move the check mark - but don't do that now.

Next, you need to compile the Verilog design.

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The example design we'll be using consists of two Verilog source files, each containing a unique module. The file counter.v contains a module called counter which implements a simple 8-bit binary up-counter. The other file (tcounter.v) is a testbench module (test_counter) used to verify counter. Under simulation you will see that these two files are configured hierarchically with a single instance (instance name dut) of module counter instantiated by the testbench. You'll get a chance to look at the structure of this code later. For now, you need to compile both files into your design library work and there are two ways to do this, from the menu bar or from the tool bar.

Step 6. Pull down the File menu and select Compile Verilog. This brings up the Compile Verilog Source dialog box. Notice this dialog box lists all files in the current directory with a .v suffix which is a useful convention for naming Verilog source files. You could select a file here and click Compile but don't do that just yet. Instead click Done.

Step 7. Click the VLOG menu button. The same Compile Verilog Source dialog box appears. Now select a Verilog source file and click compile. Notice that the order in which you compile the two Verilog modules is not important. This may again seem strange to Verilog XL users who understand the possible problems of interface checking between design units, or compiler directive inheritance. V-

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System defers such checks until the design is loaded by VSIM (the HDL simulator). So it doesn't matter here if you choose to compile counter.v before or after tcounter.v. Notice in the compile dialog box a selector box called Compile More. If this is selected, the dialog box remains active after you click Compile so you can compile more than one source file. When you click Compile, VLOG (the Verilog compiler) is invoked and should generate output messages similar to these:

During compilation, the V-System prompt is not displayed. When the compiler finishes the prompt returns. When all files have been compiled, click Done. Now that the design files have been compiled, you are ready to simulate. Before you move on however, it is interesting to pull down the Library > Contents menu. This shows the a list of the current contents of the active library (work in this case). You should see the two modules of this design counter and test_counter. One option available to you here is to delete one or more of the design modules from the library but don't do that now. Instead click Done.

Step 8. Now let’s start the simulation. You can either pull down the File menu and select Simulate... -or- click the menu button called VSIM.

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Either action brings up the Simulate a Design dialog box. This dialog box has four tabs to select simulation options: Design, VHDL, Verilog, and SDF. At this point, you can accept the defaults in each case. Click the Design tab, make sure work is the targeted library and select the top-most module in the design test_counter. If you choose to simulate only the counter module you will have a very short and uneventful simulation run since test_counter contains the clock generator and other stimulus necessary for counter to run. See Simulate a Design dialog box for PCs on page 30 more information on the Simulate a Design dialog box.

Step 9. Click OK to invoke the simulator. The remaining V-System windows are now available for viewing within the original application window. Use the View>All menu sequence to open all of the V-System windows. If you are the first person to use this tutorial, the windows will cascade. The windows may be in some other arrangement if the tutorial has already been used. In any case, pull down Window > Tile Vertically. This should arrange the nine windows somewhat like the following illustration.

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The order of the windows may be different on your machine but you should see all nine. See The V-System Graphic Interface on page 25 for a detailed description of each window. Although you have invoked the simulator, and runtime checking of the code has occurred, the simulation is halted at time zero waiting for your command.

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Step 10. Click inside the Structure window.

Notice how this window describes the hierarchical structure of the design. In the illustration the Structure window shows three hierarchical levels: test_counter, counter and the function called increment. You can navigate within the hierarchy by clicking on a line within the window.

Step 11. Click on FUNCTION increment and notice how other VSIM windows are automatically updated as appropriate. Specifically, the Source window displays the Verilog code at whichever hierarchical level you selected in the Structure window. Using the Structure window in this way is analogous to scoping commands in interpreted Verilogs. For now, make sure the test_counter module is showing in the Source window by clicking on the top line in the Structure window.

Step 12. Before we run the simulation, let's put some signals in the List and Wave windows. You can do this either by typing a command, or using the pull down menus. Let's do one of each. First, type: wave *

This causes the Wave window to display the signals clk, rst and count. The * is a wildcard and here it means all signals at the current hierarchical level. (Typing wave -r * would have displayed all signals throughout the design hierarchy.) In a moment, when you run the simulation you will see the Wave window update with signal values.

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Step 13. Secondly, pull down Signals > Add to List > Signals in Design. This causes the List window to display the signals clk, rst and count as well as the current simulation time. (The same effect could be achieved by typing list -r * .) If you desired, you could invoke these commands to display individual signals by specifying the signal names instead of the * wildcard or by selecting Signals > Add to List > Selected Signals from the pulldown menus. Notice that whenever you type a command in V-System it appears in the Transcript window. This is true regardless of which window you have currently active.

Step 14. At this point why not take a moment to customize your window positions and sizes. Try to dedicate the most screen-space to the Transcript, Wave, Source and List windows.

Note: As you become familiar with the V-System environment you will find yourself using some windows more than others. You can easily make more room for yourself in the application window by minimizing some of the V-System windows you don’t currently need.

Step 15. When you are happy with your work, pull down Window > Settings to be sure your changes will be saved into the vsystem.ini file. Make your selections as in this illustration.

Step 16. Click RUN on the toolbar.

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This causes the simulation to run for the default simulation length, 100ns. (The default simulation run length can be changed with Options > Simulation Options... from the menu bar.) Instead of clicking the RUN button you could also type the run command. To try it now, type: run 500

Now the simulation has run for a total of 600ns (the default 100ns plus the 500 you just asked for). See the status bar at the bottom of the V-System window. It should show something like this illustration.

If your status bar is different it is because the status bar changes depending upon the active V- System window. Try selecting a different window and look at the status bar again.

Step 17. The last command you typed (run 500) caused the simulation to advance for 500ns. You can also advance simulation to a specific time. Type: run @ 3000

This advances the simulation to time 3000ns. Note that the simulation actually ran for 2400ns (3000 - 600). Also note that the Transcript window echos the results specified in the test_counter module; the time echoed is not intended to match the time shown on the V-System status bar.

Step 18. If you wish, you can also use the run command to simply run, with no predetermined stop time. Pull down Run > Run Forever from the menu.

Step 19. You may stop the simulator while it is running by a simple click. Do so now by clicking the BREAK button on the toolbar.

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This halts the simulation and updates the Source window which now features a > (greater-than sign) next to the line of source code about to be executed. See the illustration.

Your windows won't look exactly like the illustration because your simulation very likely stopped at a different point. Also, we are showing only two windows in this illustration. Next we'll take a brief look at some interactive debug features of the V-System environment. To start with, let's see what we can do about the way the List window presents its data.

Step 20. In the List window select the signal named count. From the List window menu bar, pull down Options > Signal Options... and select a display radix of Decimal. Click DONE. This causes the List window output to change; the count signal is now listed in decimal rather than the default binary.

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Step 21. V-System includes an extensive breakpoint feature. Make sure the second line (dut:counter) in the Structure window is selected, then set a breakpoint at line 30 in the Source window. To set the breakpoint, simply move the cursor to the Source window and scroll the window to display line 30, and double-click on line 30. You will see a dot appear next to the line number. This indicates that a breakpoint has been set for that line. Double-clicking line 30 once more would remove the breakpoint but don’t do that now.

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Step 22. Select CONT from the toolbar to resume execution of the simulation. When the simulation hits the breakpoint, it stops running, highlights the Source window and issues a message in the Transcript window.

Step 23. Typically when a breakpoint is reached you will be interested in one or more signal values. There are a few ways to determine this. You can: • look at the values shown in the Signals window, or • examine the current value of the signal count by typing: examine count

Perhaps more usefully, you can ask V-System to automatically issue the examine command when the breakpoint is reached.

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Step 24. Pull down Options > Edit Breakpoints from the main menu bar. This brings up the Breakpoints dialog box. This dialog box should look like the illustration.

Notice that the breakpoint we entered is displayed. Highlight the breakpoint for line 30 by clicking on it. Now click the Modify button in this dialog box. The Command field becomes active and you can type into it: examine count

This command will be executed every time the breakpoint on line 30 is reached. Click Done, answer Yes to the new dialog box that asks you to confirm your action and click Done once more to close the Breakpoints dialog box.

Step 25. Select CONT from the toolbar one more. When the breakpoint on line 30 is triggered, the simulator stops running as before but now you can see output from the automatic examine count command in the Transcript window.

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Step 26. Click OVER on the toolbar. This causes the simulator to step over the function call on line 30. The STEP button on the toolbar would have single-stepped the simulator, including each line of the increment function.

Step 27. Experiment by yourself for a while; setting and clearing breakpoints as well as STEP’ing and OVER’ing function calls until you feel comfortable with the operation of these commands.

Step 28. When you are ready, you can save the output of the VSIM List window if you like, by entering the following command: write list counter.lst

Note: This could be a large file, so this step is optional... You could, of course, accomplish the same task by using the pulldown menus File > Save Listing...

Step 29. You have now completed Lesson 2. You can quit the simulator by typing exit or by choosing the File > Exit V-System menu bar sequence.

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You will be asked to confirm your decision to exit simulation by clicking the Yes button in a dialog box. Alternatively, if you want to skip the confirmation dialog box type: exit -force

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Lesson 3: Mixed VHDL/Verilog simulation

You must be using V-System/PLUS PC for this lesson. Thanks to V-System’s single kernel simulator, the VHDL and Verilog simulation procedures you learned in the previous lessons apply directly to mixed VHDL/Verilog simulation. The goals for this lesson are: • compile multiple VHDL and Verilog files • simulate a mixed VHDL and Verilog design • list VHDL signals and Verilog nets and registers • view the design in the Structure window • view the HDL source code in the Source window

Step 1. Restart V-System. Using the File>Directory menu sequence, and the Change Directory To: dialog box, move to the \example\mixedHDL directory (within the install directory). In the Transcript window, V-System echos the cd command.

Step 2. Before you can compile an HDL source file, you need to create a new work library. Type this command in the Transcript window (or use the Library>New menu sequence): vlib work

Note: If this tutorial has already been run on your system, a message will report that the work subdirectory already exists in the current directory. You can ignore the message and proceed.

Step 3. Now you need to create a new project file in your current working directory. Select Project > New and type in vsystem.ini.

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Note: A project file will already exist if someone has done this exercise before. Again, V-System will just give you a message that you can safely ignore.

Step 4. Now you can compile the Verilog files using the File>Compile_Verilog... menu sequence. V-System displays the Compile Verilog Source dialog box:

Compile cache.v, memory.v and proc.v in any order you choose. Note that a group of Verilog files can be compiled in any order. In a mixed VHDL/Verilog design, however, the Verilog files must be compiled before the VHDL files.

Step 5. Depending on the design, the compile order of VHDL files can be very specific. In the case of this lesson, the file top.vhd must be compiled last. Compile the VHDL files from the Transcript window command line with this command: vcom util.vhd set.vhd top.vhd

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Step 6. Begin simulation from the VSIM button on the tool bar. Invoke vsim with the name of the top level design from the Simulate a Design dialog box:

Step 7. From the menu bar select the Window>Restore All option. Arrange the windows so the List, Wave, Source and Structure windows are within view.

Step 8. This time you will use the VSIM command line to add all of the HDL items in the region to the List and Wave windows: list * wave *

Step 9. The Structure window is hierarchical. Notice the mixture of VHDL and Verilog in the design. VHDL levels are indicated by a square “prefix” in the Structure window, while Verilog levels are indicated by a circle “prefix.” Try expanding (+) and contracting (–) the structure layers. You’ll find Verilog modules have been instantiated by VHDL architectures and VHDL by Verilog.

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Let’s take another look at the design.

Step 10. Click on the Verilog module, c: cache. The source code for the Verilog module is now shown in the Source window. Scroll down to line #25. Note the declaration of cache_set; this is a VHDL entity instantiated within the Verilog file cache.v.

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Step 11. Click on the line "s0:cache_set(only)" in the Structure window.

The Source window now shows the VHDL code for the cache_set entity.

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Step 12. Try experimenting with some of the toolbar commands you’ve used in previous lessons: RUN, BREAK, CONT, STEP and OVER. Note that in this design, “clk” is already driven, so you won’t need to use the force command.

Step 13. Now let’s get a Wave window view of the simulation; activate the Wave window. When the Wave window is first drawn, there is one cursor in it at time zero. Clicking anywhere in the waveform display brings that cursor to the mouse location. Up to ten cursors can be present at the same time. Cursors are displayed with a time box showing the precise simulation time at the bottom. When you have more than one cursor, each time box appears in a separate track at the bottom of the display.

Step 14. Try adding or removing cursors with the Cursor > Add | Remove command.

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When you add a cursor, it is drawn in the middle of the display. Once you have more than one cursor, VSIM adds a delta measurement showing the time difference between the two cursor positions. The selected cursor is drawn as a solid line; all other cursors are drawn with dotted lines.

Step 15. Click in the waveform display. Notice how the cursor closest to the mouse position is selected and then moved to the mouse position. Another way to position multiple cursors is to use the mouse in the time box tracks at the bottom of the display. Clicking anywhere in a track selects that cursor and brings it to the mouse position. The cursors are designed to snap to the closest wave edge to the left on the waveform that the mouse pointer is positioned over. You can position a cursor without snapping by dragging in the area below the waveforms.

Step 16. Experiment with using the cursors, scrolling, and zooming (see Wave window mouse actions on page 143 for Wave window shortcuts).

Step 17. When you’re done experimenting, quit the simulator by entering the command: quit -f

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Lesson 4: Debugging a VHDL design

The goals for this lesson are: • use a VHDL testbench (a testbench is a VHDL architecture that instantiates the VHDL design units to be tested, provides simulation stimuli, and checks the results) • map a logical library name to an actual library • change the default run length • recognize assertion messages in the command window • change the assertion break level • restart the simulation run using the restart command • change the value of a variable • use a strobe to trigger lines in the V-System List window • list signals in different radixes in the List window

Step 1. Restart V-System if necessary, then change to the tutorial file directory by pulling down the File menu and selecting Directory. This brings up the Change Directory To: dialog box. Double-click the subdirectory examples and click OK.

Step 2. To create the new library, pull down the Library menu and select New. This brings up a dialog box asking you the name of library you want to create.

Step 3. Enter the name lib2 and click Create. This creates a new library directory under the current working directory. In the V-System window, you will see the following command echoed: vlib lib2

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Note: If this tutorial has already been run on your system, a message will report that the lib2 subdirectory already exists in the current directory. You can ignore the message and proceed.

Step 4. The next step is to set your work library to be the lib2 library you just created. In the last tutorial, you created a work library called work, but now you will “map” the work library to lib2. The old work library is still there, but it will not be referenced by V-System if a logical mapping for work exists.

Step 5. Now pull down the Library menu and select Mapping…. A dialog box like the one shown below will appear.

Step 6. Now click on the New button. This brings up another dialog box where you can type in the desired mapping. In this case, type in work for the library name and lib2 for the directory name. This tells V-System that whenever it sees a reference to the work library, use the lib2 library instead. Click on OK to accept the new library mapping.

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Step 7. None of the changes you've made to the library mapping take effect until you click on OK in the Library Mapping dialog box. This way you can add, edit, and delete mappings as much as you like and then discard the changes by clicking Cancel. Go ahead and click OK now.

Step 8. Next, compile the design units for this tutorial: • gates.vhd • adder.vhd • testadd.vhd You can do this four different ways. One, by selecting Compile VHDL... from the File menu and compiling the source files one-by-one using the Compile VHDL Source dialog box. Two, you could access the same dialog box with the VCOM button on the tool bar. Three, you can enter the following sequence of commands at the V-System prompt: vcom gates.vhd vcom adder.vhd vcom testadd.vhd

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And four, you could compile multiple files using a single vcom command, as in the following example: vcom gates.vhd adder.vhd testadd.vhd

Let’s use the tool bar and the Compile VHDL Source dialogue box. Press the VCOM button on the tool bar.

Step 9. Once you have the Compile VHDL Source dialog box on the screen, note the Compile More check box.

When Compile More is checked, the dialog box stays open until you click on Done. If the box is unchecked, each time you compile, the dialog box is closed. This is handy on smaller screens because then you can see the compiler messages in the Transcript window. Now compile the source files. Note that the order you do this is important because testadd.vhd uses adder.vhd and adder.vhd in turn uses gates.vhd, so compile them in this order: • gates.vhd • adder.vhd • testadd.vhd When you’re finished, click Done.

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Step 10. You can confirm that these design units have been compiled into the library by pulling down the Library menu and selecting Contents…. This brings up a dialog box that displays the names of all the design units in the library.

Step 11. Scroll through the list of configurations and entities to see what has been compiled into the work library. Choose an entity and click on it, and all of its architectures will be shown in the lower list box. When you are done, click Done to close the window.

Step 12. Now start the simulator by pulling down the File menu and selecting Simulate… (or use the VSIM tool bar button). However you choose to invoke the simulator, the Simulate a Design dialog box is displayed.

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Step 13. Select the Design tab and perform the following steps: • make sure that the simulator resolution is ns • look in the design unit scrollbox and select the configuration named test_adder_structural (because this design unit is a configuration, no architectures are displayed in the architecture scrollbox at the bottom of the dialog) • click OK to accept the settings Now open the other eight V-System windows with the View>All menu sequence. The windows will appear in the sizes and positions in which we left them in the previous lesson. We’ll first use the Source and Structure windows to examine the design.

Step 14. Double-click in the title bar of the Structure window to maximize it. V-System automatically generates this view from your VHDL code. Click on the minus sign in the box for testbench(adder8) at the top level. Now you can explore the design by collapsing and expanding the levels of hierarchy shown in the window. A level of hierarchy is created by each component instantiation, generate statement, block statement, and package.

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The plus sign means other levels exist below it. The minus sign is used on fully-expanded items. An empty box has no lower levels.

Step 15. When you finish exploring, return the Structure window to its original size by clicking on the Restore button (the one in the upper right – with arrows pointing up and down in Windows 3.x, or the box with small overlapping windows in Windows 95).

Step 16. Now click on a name (as opposed to a box) in the Structure window. Note that as you click on parts of the design in the Structure window, both the Source and Signals windows change to show the correct source file contents and the signals in it.

Step 17. Select testbench(adder8) in the Structure window by clicking on the name before going on.

Step 18. Put signals in the List and Wave windows by typing: list * wave *

Step 19. Change the default simulation run length; choose Options > Simulation Options….

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On the VSIM tab, change the Default Run Length to 1000. Do not change the other settings for now. Click OK, then Yes, to accept the new settings.

Step 20. Next, you will run the simulator. Click RUN on the V-System tool bar. A message in the Transcript window will notify you that there was an assertion error. Let's find out what's wrong. Perform the following steps to track down what caused the assertion message.

Step 21. Select Options > Simulation Options….

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Step 22. Under the Assertions tab, change the selection for Break on Assertion to Error and click OK, then Yes. This will cause the simulator to stop at the VHDL statement after the assertion is displayed.

Step 23. To restart the simulation, pull down the File menu and select Restart….

For now, leave all the options as they are and select OK.

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Step 24. Next, click RUN on the tool bar. Notice that the arrow in the Source window is pointing to the statement after the assertion.

Step 25. The assertion occurred because the signal sum does not equal vector.sum, which is derived from the sum field in test_patterns. The sum of the inputs a, b, and cin should be equal to the output sum. The error is in the test vectors.

Step 26. To correct this error, you need to restart the simulation and modify the initial value of the test vectors. But before you restart, determine which element of the test_patterns array needs to be modified. From the assertion error message, you can see that the expected pattern was wrong: 0101 plus 0001 plus 1 (the carry) should be 0111, not 1000.

Step 27. Now look at the test_patterns array with the Variables window. Use the plus boxes to expand the elements and find the element that has the sum field value of 00001000. It is the sixth line in the list, so you can refer to that element as test_patterns(6), and the sum field of that can be referred to as test_patterns(6).sum.

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Step 28. Select Restart… from the File menu. Restart… resets the values to those that were set when you first entered the simulator. Click OK.

Step 29. Now we can change the value of the sum record; type: change test_patterns(6).sum 00000111

Note that this is a temporary edit, you must use your text editor to permanently change the source code.

Step 30. Select RUN on the tool bar. At this point, the simulation will run without any errors.

Step 31. Your next action will be to add a, b, and sum to the List window and specify that their values are to be displayed using the decimal radix. To do this, enter the following command: list -decimal a b sum

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Now you should have a List window with contents like the illustration.

Note that since you used the list -decimal command, the a, b, and sum signals appear twice in the List window, once in binary and then again in decimal format.

Step 32. This brings you to the end of this lesson. Feel free to experiment further with the menu system if you wish. (You may also want keep this simulation running for the following keyboard and mouse practice session.) When you are ready to end the simulation session, quit V-System without saving data by selecting Exit V-System from the File menu. You can also do this by typing the following command (the same as exit -force) : exit -f

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Practice: Using the keyboard, mouse and menus

This practice session will introduce some of the keyboard shortcuts, mouse actions and V-System window menus that are available during simulation. You’ll need to have a simulation running to try the commands. If you aren’t currently running a simulation, you can restart one from a previous lesson. The Wave window is featured because a majority of the shortcuts can be used within it. We encourage you to try the shortcuts in other windows as well. One thing to keep in mind as you use the keyboard commands in other windows: scrolling works only in windows that currently display scroll bars.

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V-System PC keyboard shortcuts

KEY ACTION

scroll up one screen scroll down one screen scroll left one screen

scroll right one screen move to beginning of window move to end of window scroll up one line scroll down one line scroll left one column scroll right one column full zoom zoom in zoom out last zoom run simulation continue simulation single-step single-step over function call C break (interrupt simulation run or macro execution) cancels a dialog box

V-System menu bar commands are also accessible with Windows commands.

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Wave window mouse actions

You can perform different actions with the mouse depending on whether you are in the signal name/value panel (left windowpane) or in the waveform display panel (right windowpane).

In the right windowpane:

ACTION USE DO

select an item left button click on the item’s waveform - the nearest cursor (if any) is repositioned (delete cursors with Cursor > Remove from the Wave window menu) move a cursor left button click on waveform in desired location - the nearest cursor is repositioned (add cursors with Cursor > Add from the Wave window menu) zoom the display right button click and drag (rubberband) to zoom the display - the time expands to match the mouse movements

Getting Started with V-System Using V-System for PCs - 143 Practice: Using the keyboard, mouse and menus

In the left windowpane:

ACTION USE DO

select an item left button click on any item name extend selection click on any item above or below the current selection left button add to selection click on any unselected item left button

subtract from selection click on any selected item left button move item left button drag selected item to new position in the list expand item levels left button click on a plus box collapse item levels left button click on a minus box call up Wave window menus right button click anywhere in the left windowpane

To resize the windowpanes: Using the left mouse buttom, click and drag on the bar separating the windowpanes.

144 - Using V-System for PCs Getting Started with V-System Practice: Using the keyboard, mouse and menus

Wave window menus

The Wave window also has its own menu bar; the Wave window menu bar commands are listed below.

File Write PostScript file write out the window contents as a file Save Configuration... save the current Wave window formats to a do file

Edit Cut delete a signal and place it on the clipboard Copy copy a signal to the clipboard Paste paste signal now on clipboard ------Delete All delete every signal in the Wave window

Zoom Full show all time steps in the simulation In 2X show more detail and less simulation time Out 2X show less detail and more simulation time Last revert to last Wave window zoom setting Range... specify the exact simulation time to display

Cursor Add add cursor to the window Remove remove a cursor from the window

Options Waveform Options... specify the signal’s height and snap range Signal Options... specify the color, format or radix of a signal

This collection of keyboard, mouse and menu commands should give you plenty of options for trying out V-System’s graphical interface. When you’re through practicing, end the simulation with one of the options you’ve learned in a previous lesson.

Getting Started with V-System Using V-System for PCs - 145 Continuing with V-System for PCs

Continuing with V-System for PCs

More information on V-System commands, functions and techniques for use can be found in the following locations: • the V-System/VHDL PC User’s Manual • the Tips and Techniques appendix of the V-System user’s manual

146 - Using V-System for PCs Getting Started with V-System A - Resources

Books

Applications of VHDL to Circuit Design Randolph E. Harr and Alec G. Stanculescu, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts 02061, USA. 1991.

Chip-Level Modeling with VHDL James R. Armstrong, Prentice Hall, Englewood Cliffs, New Jersey 07632, USA. 1988.

The Designer’s Guide to VHDL Peter J. Ashenden, Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San Francisco, California 94104-3205, USA. 1995. (ISBN: 1-55860-270-4)

A Guide to VHDL Syntax Jayaram Bhasker, Prentice Hall, Englewood Cliffs, New Jersey 07632, USA. 1995.

IEEE Standard VHDL Language Reference Manual ANSI/IEEE Std 1076-1993. Published by The Institute of Electrical and Electronics Engineers, Inc., 345 East 47th Street, New York, New York 10017-2394, USA. ISBN:1-55937-376-8, June 1994. To purchase the standard, write IEEE Customer Service, Hoes Lane, Tiscataway NJ 08855-1331, or phone 800-678-4333 (908-562-5420 from outside the U.S.), 908-981-9667 fax.

Practical Programming in Tcl and Tk Brent Welch, Prentice Hall, Englewood Cliffs, New Jersey 07632, USA. 1995.

Tcl and the Tk Toolkit John K. Ousterhout, published by Addison-Wesley Publishing Company, Inc. (ISBN 0-201- 63337-X).

Verilog Language Reference Manual 2.0 Open Verilog International, 15466 Los Gatos Blvd, Suite 109-071, Los Gatos CA 95032 Phone: (408) 353-8899 , fax: (408) 353-8869 , email: [email protected], Contact: Lynn Horobin

Getting Started with V-System Resources - 147 VHDL, 2nd Edition Douglas L. Perry, McGraw-Hill, Inc., Professional Publishing Group, 11 West 19th Street, New York, New York 10011, USA. 1993.

VHDL: Analysis and Modeling of Digital Systems Zainalabedin Navabi, Northeastern University, McGraw-Hill Publishing Company, College Division, 1221 Avenue of the Americas, New York, New York, 10020, USA. 1993.

VHDL Coding Styles and Methodologies Ben Cohen, Kluwer Academic Publishers, Boston, Massachusetts, USA. 1995. (ISBN: 0-7923- 9598-0)

VHDL: Hardware Description and Design Roger Lipsett, Carl Schaefer, & Cary Ussery, Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts 02061, USA. 1989.

VHDL Primer Jayaram Bhasker, Prentice Hall, Englewood Cliffs, New Jersey 07632, USA. 1992.

Organizations

IEEE The Institute of Electrical and Electronics Engineers, Inc., 345 East 47th Street, New York, New York 10017-2394, USA. Fax:212-705-7453. The IEEE P1364 workgroup is in the process of standardizing the Verilog hardware description language. Upon approval by IEEE V-System/PLUS will adopt the approved Verilog standard.

Open Verilog International 15466 Los Gatos Blvd, Suite 109-071, Los Gatos CA 95032 Phone: (408) 353-8899 , fax: (408) 353-8869 , email: [email protected], Contact: Lynn Horobin The SDF mapping rules described in the Model Development Specification are based on version 2.1 of OVI's Standard Delay Format Specification. This document is available from Open Verilog International.

148 - Resources Getting Started with V-System VHDL International 407 Chester Street, Menlo Park, CA 94025-3718, USA. Phone: 800-554-2550 or 415-329- 0578, fax: 415-324-3150. A consortium of VHDL tool vendors and users that exists to promote the usage and standardization of VHDL. For information about VHDL International membership and mailings, contact Conference Management Services.

VHDL International Users’ Forum 407 Chester Street, Menlo Park, CA 94025-3718, USA. Phone: 800-554-2550 or 415-329- 0578, fax: 415-324-3150. The users’ group within VHDL International. This group currently holds meetings twice a year in the spring and fall, which are attended by several hundred delegates. For information about VIUF meetings, membership, newsletters, and bulletin board services, contact Conference Management Services.

Corporations & Consultants

Automata Publishing Company 1072 South Saratoga-Sunnyvale Road, BLDG A107, San Jose CA 95129 USA. Phone: 800-8- VIPER1 or 408-255-0705, fax 408-253-7916, email: [email protected]. PCI VHDL simulation models. Contact: Mona Singh.

CAST Computer Aided Software Technologies, Inc. 24 White Birch Drive, Pomona NY 10970 USA. Phone: 914-354-4945, Fax: 914-354-0325; email: [email protected], Web: http://www.cast-inc.com, VHDL services including model development, FPGA and ASIC design kits, training, simulation consulting. Contact: Newton Abdalla.

Comit Systems Inc. 1250 Oakmead Parkway, Suite 210, Sunnyvale CA 94088 USA. Phone: 408-988-2988; fax: 408-988-2133; email: [email protected]. FPGA design, VHDL modeling for embedded systems and related areas. Contact: Balachandran Sreekandath.

Daemon Modeling 834 SW Westwood Drive, Portland OR 97201 USA. Phone: 503-977-0554, email: [email protected]. Model development with emphasis on processor models. Contact: Daemon Anastas.

Getting Started with V-System Resources - 149 DP Consulting 9015 NE 139th Street, Kirkland WA 98034 USA. Phone: 206-821-9124. Model development. Contact: Richard Pado.

EDA Solutions Pty. Ltd. Level 3, South Tower, 1-5 Railway Street Chatswood NSW 2067, Australia. Phone: 011 61 2 9413-4611, fax: 011 61 2 9413-4622, email: [email protected]. Provides VHDL training, consulting services, and VHDL model development. Contact: Alain Legrand.

EEC Consultants, Inc. 3243 Springwood Drive, Clearwater FL 34621 USA. Phone: 813-786-2929. VHDL models. Contact: Kent Ulrich.

Hardi Electronics AB Box 966, S220 09 Lund, Sweden. Phone: (46) 11-77-90; fax: (46) 13-15-99. Provides VHDL training, consulting services, and product distribution. Contact: Lars-Eric Lundgren.

LEDA SA 35 Avenue du Granier, 38240 Meylan, France. Phone: (33) 76-41-92-43. fax: (33) 76-41-92- 44. Provides VHDL training, consulting services, and product distribution. Contact: Francis Sourbier.

Logic Modeling 19500 NW Gibbs Drive, Beaverton OR 97006 USA. Phone: 503-690-6900, fax: 503-690- 6906. Provides modeling libraries.

Paolo Tabacco Via Dei Berio 91, Rome Italy (00155). Phone: 39-6-22595-306; fax: 39-6-2280739; email: [email protected]. Designs for boards and ASICs using V-System and Exemplar CORE in aerospace and commercials applications. Contact: Paolo Tabacco.

Papillon Research Corporation 52 Domino Drive, Concord MA 01742 USA. Phone: 508-371-9115; fax: 508-371-9175; email: [email protected]; internet: http://www.papillonres.com/~papillon. Full product design including ASIC, FPGA, synthesis and modeling, analog, EMI and mechanical engineering. Contact: Dave Matthews.

150 - Resources Getting Started with V-System Proxy Modeling 1580 Washington Blvd., Fremont CA 94539 USA. Phone: 510-440-VHDL. Provides modeling and consulting. Contact Keith G. Irwin or Pam G. Rissmann.

Saros Technology Limited St. Michaels House, 94 High Street, Wallingford, Oxon OX10 OBW, United Kingdom. Phone: 011-44-1491-837787, fax: 011-44-1491-837477, email: [email protected], internet: http://www.saros.co.uk. Providers of V-System support in the UK. Developers of the VHDL editor, Turbo Writer. Contact: Carey Sayer

Seva Technologies Inc. 200 Brown Road, Suite 103, Fremont, CA 94539 USA. Phone: 510-249-9085, fax: 510-249-9082, email: [email protected]. VHDL training, consulting services. Contact: Larry Saunders.

System Simulation Solutions 1100 NW Compton Drive, Beaverton, OR 97006, USA. Phone: 503-690-1200. VHDL modeling services. Contact: James B. Morris.

Topdown Design Solutions 71 Spit Brook Road, Suite 301, Nashua, NH 03060, USA. Phone: 603-888-8811, fax: 603-888-7694, email: [email protected]. The manufacturers of the VHDL SelfStart_Kit, an inexpensive, hands-on, self-paced tutorial system designed to be used with V-System/VHDL PC. VHDL training courses and consulting services are also available. Contact: Art Pisani.

TransGate Technologies 19310 Oak Street, Aloha OR 97007-4422 USA. Phone: 503-591-1232, email: [email protected]. Model development with emphasis on communications and application- specific memories, ASIC/PLD design. Contact: Phillip Tomson.

VAutomation Inc. 20 Trafalgar Square, Suite 443, Nashua, NH 03063 USA. Phone: 603-882-2282; fax: 603-882- 1587; email: [email protected]; internet: http://www.vautomation.com Sythesizable HDL models. Contact: Eric Ryherd.

Getting Started with V-System Resources - 151 VHDL Technology Group 100 Broadhead Road, Suite 140, Bethlehem, PA 18017 USA. Phone: 610-882-3130, fax: 610-882-3133, email: [email protected]. VHDL training and consulting services. Contact: William D. Billowitch.

Widman Associates 70 Crestmont Drive, Oakland, CA 94619 USA. Phone: 510-482-3564, fax 510-482-5339. Contact: Bob Widman.

Online resources email: [email protected] newsnet news groups: sci.electronics.cad comp.arch.fpga comp.lang.verilog comp.lang.vhdl comp.lsi comp.lsi.testing home pages: http://www.model.com http://www.vhdl.org/vhdl_intl http://www.e2w3.com http://www.translogiccorp.com http://www.translogic.nl

152 - Resources Getting Started with V-System B - Technical Support

Getting the latest version information If you want the latest version information from Model Technology, get on our email news alias. Send email to [email protected]. Make the subject read "Subscribe to MTI_News". Put your email address in the body of the message. Then whenever there are updates, bugfixes, or product enhancements, you’ll be among the first to know.

Getting help The best thing is to email us a test case. Our email address is [email protected]. The next best thing is to copy/print the following form, fill it out, and fax it to us at 503-526-5410.

Getting Started with V-System Technical Support - 153 Model Technology Fax Support Form Your name: Your company: Your phone number: Your FAX number: Your email address: Description of the problem (please include the exact wording of any error messages):

V-System Version: (Use the Help About dialog box with Windows; type vcom for workstations.) PC hardware security key serial number: Host ID of licence server for workstations:

154 - Technical Support Getting Started with V-System Index

Default simulation run length on a PC 135 A describe V-System command on PCs 103 Application window on PCs 86 Design library, creating Assertion error on workstations 71 on PCs 94 Authorization code 23 on workstations 45, 53 Design structure hierarchical view in the Structure window 27 B of a mixed VHDL/Verilog design 64 of a Verilog design 56 Break command on PCs 101 Breakpoints continuing simulation after, on workstations 49 E setting on PCs 102 setting on workstations 48 Errors breaking on assertion on workstations 72 C finding in VHDL design on PCs 138 Change directory on workstations 72 for PCs 93 viewing in Source window Compile on PCs 138 confirming compiled design units on PCs 133 on workstations 72 on PCs 95 examine V-System command packages on workstations 68 on PCs 103 several design units on PCs 131 the order of Verilog modules on workstations 53 Verilog on PCs 109 H Verilog on workstations 52 Configurations HDL items defined 11 selecting for simulation on workstations 70 Hierarchical design structure Continue (CONT) tool bar button on PCs 103 of a mixed VHDL/Verilog design 64 of a Verilog design 56 Hierarchical view in tree windows 27 D

Dataflow window 35 I Debugging a VHDL design on PCs 129 Initialization file, see Project file on workstations 68

Getting Started with V-System Index - 155 Installing V-System PC keyboard shortcuts 142 on workstations 13 Process window 33 workstation modes 33 Project file K new on PCs 95, 122 Keyboard shortcuts on PCs 142 Keyboard shortcuts on workstations 83 Q

quit VSIM command L on workstations 51, 62, 128 Quitting the simulator Library on PCs 105 IEEE on workstations 68 Library creation and mapping on workstations 68 R Library, creating on PCs 94 Records List window 37 displaying values of on workstations 73 change display radix on PCs 116 Run change display radix on workstations 58 PC menu bar commands 100 save listing on PCs 105 workstation menu bar commands 57 run VSIM command M on workstations 48, 57

Macros S example of on workstations 77 Main VSIM window 28 Saving V-System window settings on PCs 92 Mapping the work library Searching on PCs 130 in tree windows on workstations 81 Mouse actions in PC Wave window 143 Signals applying stimulus to on workstations 47 in Dataflow window 35 O in the List and Wave windows on PCs 135 OVER tool bar button on workstations 70 on PCs 104 listing in region on workstations 46 specifying radix of on workstations 75 P triggering listings for on workstations 74 viewing in current region 34 Packages Signals window 34 stdlogic on workstations 68

156 - Index Getting Started with V-System Simulation Tutorial setup for PCs 92 batch-mode on workstations 77 changing default run length on a PC 135 error correction on PCs 138 V executing commands at startup on workstations 79 in batch mode 40 Variables in command-line mode 40 change value of sum record on PCs 139 mixed VHDL/Verilog on PCs 122 Variables window 36 mixed VHDL/Verilog on workstations 63 Verilog on PCs 96 interface checking between design units 53 restart -f option on workstations 73 viewing design in PC Structure and Source windows restart on a PC 137 124 saving results in log file on workstations 77 viewing design in workstation Structure and Source single-stepping on workstations 49 windows 64 starting on workstations 69 Verilog simulation Verilog on PCs 110 on PCs 106 Verilog on workstations 52 on workstations 52 VHDL on PCs 93 VHDL simulation VHDL on workstations 44 on PCs 93 Source window 32 on workstations 44 Startup window on workstations 29 View signals in current region 34 Status bar on PCs 101 Viewing simulation results in the List window 37 Step VSIM workstation window 28 V-System menu bar on PCs 88 workstation menu bar command 60 Step Over workstation menu bar command 60 W Step over, see OVER Stimulus, apply to design on PC 100 Wave window 38 Structure window 31 cursors on workstation 61, 127 System requirements menus on PCs 145 for PCs 21 mouse actions on PCs 143 for workstations 13 Windows changing positions and sizes on PCs 99 T viewing all on workstations 70 Work library mapping Transcript window 28 on PCs 130 Tree windows on workstations 68 hierarchical view in 27 searching in on workstations 81 Triggering changing in workstation List window 75

Getting Started with V-System Index - 157 Z

Zoom in Wave window on PCs 145 workstation shortcuts 83

158 - Index Getting Started with V-System