Efficient Utilization of SIMD Extensions
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Elementary Functions: Towards Automatically Generated, Efficient
Elementary functions : towards automatically generated, efficient, and vectorizable implementations Hugues De Lassus Saint-Genies To cite this version: Hugues De Lassus Saint-Genies. Elementary functions : towards automatically generated, efficient, and vectorizable implementations. Other [cs.OH]. Université de Perpignan, 2018. English. NNT : 2018PERP0010. tel-01841424 HAL Id: tel-01841424 https://tel.archives-ouvertes.fr/tel-01841424 Submitted on 17 Jul 2018 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Délivré par l’Université de Perpignan Via Domitia Préparée au sein de l’école doctorale 305 – Énergie et Environnement Et de l’unité de recherche DALI – LIRMM – CNRS UMR 5506 Spécialité: Informatique Présentée par Hugues de Lassus Saint-Geniès [email protected] Elementary functions: towards automatically generated, efficient, and vectorizable implementations Version soumise aux rapporteurs. Jury composé de : M. Florent de Dinechin Pr. INSA Lyon Rapporteur Mme Fabienne Jézéquel MC, HDR UParis 2 Rapporteur M. Marc Daumas Pr. UPVD Examinateur M. Lionel Lacassagne Pr. UParis 6 Examinateur M. Daniel Menard Pr. INSA Rennes Examinateur M. Éric Petit Ph.D. Intel Examinateur M. David Defour MC, HDR UPVD Directeur M. Guillaume Revy MC UPVD Codirecteur À la mémoire de ma grand-mère Françoise Lapergue et de Jos Perrot, marin-pêcheur bigouden. -
(LINUX) Computer in Three Parts
Science on a (LINUX) computer in three parts Introductory short couse, Part II Thorsten Becker University of Southern California, Los Angeles September 2007 The first part dealt with ● UNIX: what and why ● File system, Window managers ● Shell environment ● Editing files ● Command line tools ● Scripts and GUIs ● Virtualization Contents part II ● Typesetting ● Programming – common languages – philosophy – compiling, debugging, make, version control – C and F77 interfacing – libraries and packages ● Number crunching ● Visualization tools Programming: Traditional languages in the natural sciences ● Fortran: higher level, good for math – F77: legacy, don't use (but know how to read) – F90/F95: nice vector features, finally implements C capabilities (structures, memory allocation) ● C: low level (e.g. pointers), better structured – very close to UNIX philosophy – structures offer nice way of modular programming, see Wikipedia on C ● I recommend F95, and use C happily myself Programming: Some Languages that haven't completely made it to scientific computing ● C++: object oriented programming model – reusable objects with methods and such – can be partly realized by modular programming in C ● Java: what's good for commercial projects (or smart, or elegant) doesn't have to be good for scientific computing ● Concern about portability as well as general access Programming: Compromises ● Python – Object oriented – Interpreted – Interfaces easily with F90/C – Numerous scientific packages Programming: Other interpreted, high- abstraction languages -
Vectorization Optimization
Vectorization Optimization Klaus-Dieter Oertel Intel IAGS HLRN User Workshop, 3-6 Nov 2020 Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Changing Hardware Impacts Software More Cores → More Threads → Wider Vectors Intel® Xeon® Processor Intel® Xeon Phi™ processor 5100 5500 5600 E5-2600 E5-2600 E5-2600 Platinum 64-bit E5-2600 Knights Landing series series series V2 V3 V4 8180 Core(s) 1 2 4 6 8 12 18 22 28 72 Threads 2 2 8 12 16 24 36 44 56 288 SIMD Width 128 128 128 128 256 256 256 256 512 512 High performance software must be both ▪ Parallel (multi-thread, multi-process) ▪ Vectorized *Product specification for launched and shipped products available on ark.intel.com. Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. 2 *Other names and brands may be claimed as the property of others. Vectorize & Thread or Performance Dies Threaded + Vectorized can be much faster than either one alone Vectorized & Threaded “Automatic” Vectorization Not Enough Explicit pragmas and optimization often required The Difference Is Growing With Each New 130x Generation of Threaded Hardware Vectorized Serial 2010 2012 2013 2014 2016 2017 Intel® Xeon™ Intel® Xeon™ Intel® Xeon™ Intel® Xeon™ Intel® Xeon™ Intel® Xeon® Platinum Processor Processor Processor Processor Processor Processor X5680 E5-2600 E5-2600 v2 E5-2600 v3 E5-2600 v4 81xx formerly codenamed formerly codenamed formerly codenamed formerly codenamed formerly codenamed formerly codenamed Westmere Sandy Bridge Ivy Bridge Haswell Broadwell Skylake Server Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. -
Some Notes on BLAS, SIMD, MIC and GPGPU (For Octave and Matlab)
Some Notes on BLAS, SIMD, MIC and GPGPU (for Octave and Matlab) Christian Himpe ([email protected]) WWU Münster Institute for Computational and Applied Mathematics Software-Tools für die Numerische Mathematik 15.10.2014 About1 BLAS & LAPACK Affinity SIMD Automatic Offloading 1 Get your Buzzword-Bingo ready! BLAS & LAPACK BLAS (Basic Linear Algebra System) Level 1: vector-vector operations (dot-product, vector norms, generalized vector addition) Level 2: matrix-vector operations (generalized matrix-vector multiplication) Level 3: matrix-matrix operations (generalized matrix-matrix multiplication) LAPACK (Linear Algebra Package) Matrix Factorizations: LU, QR, Cholesky, Schur Least-Squares: LLS, LSE, GLM Eigenproblems: SEP, NEP, SVD Default (un-optimized) netlib reference implementation. Used by Octave, Matlab, SciPy/NumPy (Python), Julia, R. MKL Intel’s implementation of BLAS and LAPACK. MKL (Math Kernel Library) can offload computations to XeonPhi can use OpenMP provides additionally FFT, libm and 1D-interpolation Current Version: 11.0.5 (automatic offloading to Phis) Costs (we have it, and Matlab ships with it, too) Go to: https://software.intel.com/en-us/intel-mkl ACML AMD doesn’t want to be left out. ACML (AMD Core Math Libraries) Can use OpenCL for automatic offloading to GPUs Special version to exploit FMA(4) instructions Choice of compiled binaries (GFortran, Intel Fortran, Open64, PGI) Current Version: 6 (automatic offloading to GPUs) Free (but not open source) Go to: http://developer.amd.com/tools-and-sdks/ cpu-development/amd-core-math-library-acml OpenBLAS Open Source, the third kind. OpenBLAS Fork of GotoBLAS Good performance for dense operations (close to the MKL) Can use OpenMP and is compiled for specific architecture Current Version: 0.2.11 Open source (!) Go to: http://github.com/xianyi/OpenBLAS FlexiBLAS So many BLAS implementations, so little time.. -
Vegen: a Vectorizer Generator for SIMD and Beyond
VeGen: A Vectorizer Generator for SIMD and Beyond Yishen Chen Charith Mendis Michael Carbin Saman Amarasinghe MIT CSAIL UIUC MIT CSAIL MIT CSAIL USA USA USA USA [email protected] [email protected] [email protected] [email protected] ABSTRACT Vector instructions are ubiquitous in modern processors. Traditional A1 A2 A3 A4 A1 A2 A3 A4 compiler auto-vectorization techniques have focused on targeting single instruction multiple data (SIMD) instructions. However, these B1 B2 B3 B4 B1 B2 B3 B4 auto-vectorization techniques are not sufficiently powerful to model non-SIMD vector instructions, which can accelerate applications A1+B1 A2+B2 A3+B3 A4+B4 A1+B1 A2-B2 A3+B3 A4-B4 in domains such as image processing, digital signal processing, and (a) vaddpd (b) vaddsubpd machine learning. To target non-SIMD instruction, compiler devel- opers have resorted to complicated, ad hoc peephole optimizations, expending significant development time while still coming up short. A1 A2 A3 A4 A1 A2 A3 A4 A5 A6 A7 A8 As vector instruction sets continue to rapidly evolve, compilers can- B1 B2 B3 B4 B5 B6 B7 B8 not keep up with these new hardware capabilities. B1 B2 B3 B4 In this paper, we introduce Lane Level Parallelism (LLP), which A1*B1+ A3*B3+ A5*B5+ A7*B8+ captures the model of parallelism implemented by both SIMD and A1+A2 B1+B2 A3+A4 B3+B4 A2*B2 A4*B4 A6*B6 A7*B8 non-SIMD vector instructions. We present VeGen, a vectorizer gen- (c) vhaddpd (d) vpmaddwd erator that automatically generates a vectorization pass to uncover target-architecture-specific LLP in programs while using only in- Figure 1: Examples of SIMD and non-SIMD instruction in struction semantics as input. -
Run-Time Adaptation to Heterogeneous Processing Units for Real-Time Stereo Vision
Run-time Adaptation to Heterogeneous Processing Units for Real-time Stereo Vision Benjamin Ranft Oliver Denninger FZI Research Center for Information Technology FZI Research Center for Information Technology Karlsruhe, Germany Karlsruhe, Germany [email protected] [email protected] Abstract—Todays systems from smartphones to workstations task are becoming increasingly parallel and heterogeneous: Pro- data cessing units not only consist of more and more identical element cores – furthermore, systems commonly contain either a discrete general-purpose GPU alongside with their CPU or even integrate both on a single chip. To benefit from this trend, software should utilize all available resources and adapt to varying configurations, including different CPU and GPU performance or competing processes. This paper investigates parallelization and adaptation strate- gies using dense stereo vision as an example application – a basis e. g. for advanced driver assistance systems, but also robotics or gesture recognition. At this, task-driven as well as data element- and data flow-driven parallelization approaches data are feasible. To achieve real-time performance, we first utilize flow data element-parallelism individually on each processing unit. Figure 1. Parallelization approaches offered by our application On this basis, we develop and implement further strategies for heterogeneous systems and automatic adaptation to the units (GPUs) often outperform multi-core CPUs with single hardware available at run-time. Each approach is described instruction, multiple data (SIMD) capabilities w. r. t. frame concerning i. a. the propagation of data to processors and its rates and energy efficiency [4], [5], although there are relation to established methods. An experimental evaluation with multiple test systems and usage scenarious reveals advan- exceptions [6]. -
Exploiting Automatic Vectorization to Employ SPMD on SIMD Registers
Exploiting automatic vectorization to employ SPMD on SIMD registers Stefan Sprenger Steffen Zeuch Ulf Leser Department of Computer Science Intelligent Analytics for Massive Data Department of Computer Science Humboldt-Universitat¨ zu Berlin German Research Center for Artificial Intelligence Humboldt-Universitat¨ zu Berlin Berlin, Germany Berlin, Germany Berlin, Germany [email protected] [email protected] [email protected] Abstract—Over the last years, vectorized instructions have multi-threading with SIMD instructions1. For these reasons, been successfully applied to accelerate database algorithms. How- vectorization is essential for the performance of database ever, these instructions are typically only available as intrinsics systems on modern CPU architectures. and specialized for a particular hardware architecture or CPU model. As a result, today’s database systems require a manual tai- Although modern compilers, like GCC [2], provide auto loring of database algorithms to the underlying CPU architecture vectorization [1], typically the generated code is not as to fully utilize all vectorization capabilities. In practice, this leads efficient as manually-written intrinsics code. Due to the strict to hard-to-maintain code, which cannot be deployed on arbitrary dependencies of SIMD instructions on the underlying hardware, hardware platforms. In this paper, we utilize ispc as a novel automatically transforming general scalar code into high- compiler that employs the Single Program Multiple Data (SPMD) execution model, which is usually found on GPUs, on the SIMD performing SIMD programs remains a (yet) unsolved challenge. lanes of modern CPUs. ispc enables database developers to exploit To this end, all techniques for auto vectorization have focused vectorization without requiring low-level details or hardware- on enhancing conventional C/C++ programs with SIMD instruc- specific knowledge. -
Parallel Programming Models for Dense Linear Algebra on Heterogeneous Systems
DOI: 10.14529/jsfi150405 Parallel Programming Models for Dense Linear Algebra on Heterogeneous Systems M. Abalenkovs1, A. Abdelfattah2, J. Dongarra 1,2,3, M. Gates2, A. Haidar2, J. Kurzak2, P. Luszczek2, S. Tomov2, I. Yamazaki2, A. YarKhan2 c The Authors 2015. This paper is published with open access at SuperFri.org We present a review of the current best practices in parallel programming models for dense linear algebra (DLA) on heterogeneous architectures. We consider multicore CPUs, stand alone manycore coprocessors, GPUs, and combinations of these. Of interest is the evolution of the programming models for DLA libraries – in particular, the evolution from the popular LAPACK and ScaLAPACK libraries to their modernized counterparts PLASMA (for multicore CPUs) and MAGMA (for heterogeneous architectures), as well as other programming models and libraries. Besides providing insights into the programming techniques of the libraries considered, we outline our view of the current strengths and weaknesses of their programming models – especially in regards to hardware trends and ease of programming high-performance numerical software that current applications need – in order to motivate work and future directions for the next generation of parallel programming models for high-performance linear algebra libraries on heterogeneous systems. Keywords: Programming models, runtime, HPC, GPU, multicore, dense linear algebra. Introduction Parallelism in today’s computer architectures is pervasive – not only in systems from large supercomputers to laptops, but also in small portable devices like smart phones and watches. Along with parallelism, the level of heterogeneity in modern computing systems is also gradually increasing. Multicore CPUs are often combined with discrete high-performance accelerators like graphics processing units (GPUs) and coprocessors like Intel’s Xeon Phi, but are also included as integrated parts with system-on-chip (SoC) platforms, as in the AMD Fusion family of ap- plication processing units (APUs) or the NVIDIA Tegra mobile family of devices. -
A Compiler Target Model for Line Associative Registers
University of Kentucky UKnowledge Theses and Dissertations--Electrical and Computer Engineering Electrical and Computer Engineering 2019 A Compiler Target Model for Line Associative Registers Paul S. Eberhart University of Kentucky, [email protected] Digital Object Identifier: https://doi.org/10.13023/etd.2019.141 Right click to open a feedback form in a new tab to let us know how this document benefits ou.y Recommended Citation Eberhart, Paul S., "A Compiler Target Model for Line Associative Registers" (2019). Theses and Dissertations--Electrical and Computer Engineering. 138. https://uknowledge.uky.edu/ece_etds/138 This Master's Thesis is brought to you for free and open access by the Electrical and Computer Engineering at UKnowledge. It has been accepted for inclusion in Theses and Dissertations--Electrical and Computer Engineering by an authorized administrator of UKnowledge. For more information, please contact [email protected]. STUDENT AGREEMENT: I represent that my thesis or dissertation and abstract are my original work. Proper attribution has been given to all outside sources. I understand that I am solely responsible for obtaining any needed copyright permissions. I have obtained needed written permission statement(s) from the owner(s) of each third-party copyrighted matter to be included in my work, allowing electronic distribution (if such use is not permitted by the fair use doctrine) which will be submitted to UKnowledge as Additional File. I hereby grant to The University of Kentucky and its agents the irrevocable, non-exclusive, and royalty-free license to archive and make accessible my work in whole or in part in all forms of media, now or hereafter known. -
Using Arm Scalable Vector Extension to Optimize OPEN MPI
Using Arm Scalable Vector Extension to Optimize OPEN MPI Dong Zhong1,2, Pavel Shamis4, Qinglei Cao1,2, George Bosilca1,2, Shinji Sumimoto3, Kenichi Miura3, and Jack Dongarra1,2 1Innovative Computing Laboratory, The University of Tennessee, US 2fdzhong, [email protected], fbosilca, [email protected] 3Fujitsu Ltd, fsumimoto.shinji, [email protected] 4Arm, [email protected] Abstract— As the scale of high-performance computing (HPC) with extension instruction sets. systems continues to grow, increasing levels of parallelism must SVE is a vector extension for AArch64 execution mode be implored to achieve optimal performance. Recently, the for the A64 instruction set of the Armv8 architecture [4], [5]. processors support wide vector extensions, vectorization becomes much more important to exploit the potential peak performance Unlike other SIMD architectures, SVE does not define the size of target architecture. Novel processor architectures, such as of the vector registers, instead it provides a range of different the Armv8-A architecture, introduce Scalable Vector Extension values which permit vector code to adapt automatically to the (SVE) - an optional separate architectural extension with a new current vector length at runtime with the feature of Vector set of A64 instruction encodings, which enables even greater Length Agnostic (VLA) programming [6], [7]. Vector length parallelisms. In this paper, we analyze the usage and performance of the constrains in the range from a minimum of 128 bits up to a SVE instructions in Arm SVE vector Instruction Set Architec- maximum of 2048 bits in increments of 128 bits. ture (ISA); and utilize those instructions to improve the memcpy SVE not only takes advantage of using long vectors but also and various local reduction operations. -
AMD Core Math Library (ACML)
AMD Core Math Library (ACML) Version 4.2.0 Copyright c 2003-2008 Advanced Micro Devices, Inc., Numerical Algorithms Group Ltd. AMD, the AMD Arrow logo, AMD Opteron, AMD Athlon and combinations thereof are trademarks of Advanced Micro Devices, Inc. i Short Contents 1 Introduction................................... 1 2 General Information ............................. 2 3 BLAS: Basic Linear Algebra Subprograms ............. 19 4 LAPACK: Package of Linear Algebra Subroutines ........ 20 5 Fast Fourier Transforms (FFTs) .................... 24 6 Random Number Generators....................... 75 7 ACML MV: Fast Math and Fast Vector Math Library .... 163 8 References .................................. 229 Subject Index ................................... 230 Routine Index ................................... 233 ii Table of Contents 1 Introduction ............................... 1 2 General Information ....................... 2 2.1 Determining the best ACML version for your system ........... 2 2.2 Accessing the Library (Linux) ................................ 4 2.2.1 Accessing the Library under Linux using GNU gfortran/gcc ......................................................... 4 2.2.2 Accessing the Library under Linux using PGI compilers pgf77/pgf90/pgcc ......................................... 5 2.2.3 Accessing the Library under Linux using PathScale compilers pathf90/pathcc ........................................... 6 2.2.4 Accessing the Library under Linux using the NAGWare f95 compiler................................................. -
Introduction on Vectorization
C E R N o p e n l a b - Intel MIC / Xeon Phi training Intel® Xeon Phi™ Product Family Code Optimization Hans Pabst, April 11th 2013 Software and Services Group Intel Corporation Agenda • Introduction to Vectorization • Ways to write vector code • Automatic loop vectorization • Array notation • Elemental functions • Other optimizations • Summary 2 Copyright© 2012, Intel Corporation. All rights reserved. 4/12/2013 *Other brands and names are the property of their respective owners. Parallelism Parallelism / perf. dimensions Single Instruction Multiple Data • Across mult. applications • Perf. gain simply because • Across mult. processes an instruction performs more works • Across mult. threads • Data parallel • Across mult. instructions • SIMD (“Vector” is usually used as a synonym) 3 Copyright© 2012, Intel Corporation. All rights reserved. 4/12/2013 *Other brands and names are the property of their respective owners. History of SIMD ISA extensions Intel® Pentium® processor (1993) MMX™ (1997) Intel® Streaming SIMD Extensions (Intel® SSE in 1999 to Intel® SSE4.2 in 2008) Intel® Advanced Vector Extensions (Intel® AVX in 2011 and Intel® AVX2 in 2013) Intel Many Integrated Core Architecture (Intel® MIC Architecture in 2013) * Illustrated with the number of 32-bit data elements that are processed by one “packed” instruction. 4 Copyright© 2012, Intel Corporation. All rights reserved. 4/12/2013 *Other brands and names are the property of their respective owners. Vectors (SIMD) float *restrict A; • SSE: 4 elements at a time float *B, *C; addps xmm1, xmm2 • AVX: 8 elements at a time for (i=0; i<n; ++i) { vaddps ymm1, ymm2, ymm3 A[i] = B[i] + C[i]; • MIC: 16 elements at a time } vaddps zmm1, zmm2, zmm3 Scalar code computes the above b1 with one-element at a time.