EEEB273 – Electronics Analysis & Design II

Learning Outcome (4) Able to: • Analyze and design a basic two- MOSFET current-source circuit with additional MOSFET devices in the reference portion of MOSFET the circuit to obtain a given bias current. • Analyze and design more sophisticated Current MOSFET current-source circuits, such as the circuit, Wilson circuit, and wide-swing cascode circuit. Sources • Analyze the output resistance of the various MOSFET current-source circuits and design a MOSFET current- source circuit to obtain a specified output resistance. 1 2 Reference: Neamen, Chapter 10

4.0) FET Biasing 4.1) Basic Two-Transistor MOSFET Current Source

• Field-effect transistor (FET) ICs are biased with 4.1.0) The Circuit current sources in the same way as bipolar circuits.

Problem-Solving Technique • Analyze the reference side of the circuit to determine gate-to-source . Using these gate-to-source voltages, determine the bias current in terms of the Figure 10.2: Basic reference current. two-transistor BJT • To find the output resistance, place a test at the current source. output node and analyze the small-signal equivalent circuit. Keep in mind that the reference current is constant, which Fig 10.16: Basic two- may make some of the gate voltages constant or at ac transistor N-MOSFET ground. 3 current source 4

4.1) Basic Two-Transistor MOSFET Current Source (Cont) 4.1) Basic Two-Transistor MOSFET Current Source (Cont)

4.1.1) Current Relationship 4.1.1) Current Relationship (Cont)  2 • M1 is always • When = 0: IREF = Kn1(VGS −VTN1 ) (10.40) biased in saturation I region because the Therefore: REF (10.41) VGS = VTN1 + drain and gate Kn1 terminals of • M2 is always be biased in saturation region. Thus enhancement-mode 2 Load current is: I = K V −V (10.42) M1 are connected. O n2 ( GS TN 2 ) 2 Fig 10.16: Basic two- » ÿ I REF transistor N-MOSFET I = K … +V −V Ÿ (10.43) ‰ O n2 K TN1 TN 2 current source. 5 n1 ⁄ 6

Lecturer: Dr Jamaludin Bin Omar 4-1 EEEB273 – Electronics Analysis & Design II

4.1) Basic Two-Transistor MOSFET Current Source (Cont) 4.1) Basic Two-Transistor MOSFET Current Source (Cont)

4.1.1) Current Relationship (Cont) 4.1.1) Current Relationship (Cont)

• If M1 and M2 are identical , then • The relationship between IO and IREF changes V = V if the width-to-length ratios, or aspect ratios, of TN1 TN 2 the 2 transistors change. and • If the transistors are matched except for the Kn1 = Kn2 aspect ratios, then Thus, I = I (10.44) O REF (W / L) I = 2 I (10.45) • Since there is NO GATE CURRENT in O (W / L) REF , the induced load current is identical to 1 the reference current, provided the two • This provides designers versatility in their transistors are matched. circuit designs. 7 8

4.1) Basic Two-Transistor MOSFET Current Source (Cont) 4.1) Basic Two-Transistor MOSFET Current Source (Cont)

4.1.2) Output Resistance, ro 4.1.2) Output Resistance, ro (Cont)

• Stability of IO as a function of VDS is an important • Since transistors in the are consideration in many applications. processed on the same IC, all physical

• Taking into account the finite output resistance parameters, such as VTN, µn, Cox, and , are of both transistors, i.e.  ≠ 0: essentially identical for both devices. • Therefore, taking ratio of I to I will 2 O REF IO = Kn2 (VGS −VTN 2 ) (1+ λ2VDS 2 ) (10.46(a)) produce

IO (W / L)2 (1+ λVDS 2 ) and = ⋅ (10.47) 2 (10.46(b)) I REF (W / L)1 (1+ λVDS1 ) I REF = Kn1(VGS −VTN1 ) (1+ λ1VDS1 )

which is a function of aspect ratios, , and . 9 VDS 10

4.1) Basic Two-Transistor MOSFET Current Source (Cont) 4.1) Basic Two-Transistor MOSFET Current Source (Cont)

4.1.2) Output Resistance, ro (Cont) 4.1.2) Output Resistance, ro (Cont) • The stability of can be described in terms IO Ï As with BJT current-sources of the output resistance.

• For a given IREF, VDS1 = VGS1 = constant. circuits, MOSFET current   • Normally, VDS1 = VGS1 << 1, and if (W/L)2 = sources require a large , then the change in bias current with (W/L)1 output resistance for respect to a change in VDS2 is excellent stability. 1 dI 1 ≡ O ≅ λI = O (10.48) RO dVDS 2 rO2

where rO2 is the output resistance of M2 11 12

Lecturer: Dr Jamaludin Bin Omar 4-2 EEEB273 – Electronics Analysis & Design II

4.1) Basic Two-Transistor MOSFET Current Source (Cont) 4.1) Basic Two-Transistor MOSFET Current Source (Cont)

4.1.3) Reference Current, IREF 4.1.3) Reference Current, IREF (Cont)

• In BJT circuits, the IREF is generally established by the bias voltages and a .

• Since MOSFETs can be configured to act like a

resistor, the IREF in MOSFET current mirrors is usually established by using

Fig 10.16: Basic two- additional transistors, e.g. M3. transistor N-MOSFET 13 Fig 10.17: MOSFET current source. 14 current source Fig 10.17: MOSFET current source.

4.1) Basic Two-Transistor MOSFET Current Source (Cont) 4.1) Basic Two-Transistor MOSFET Current Source (Cont)

4.1.3) Reference Current, IREF (Cont) 4.1.3) Reference Current, IREF (Cont)

• Use current mirror in Figure 10.17 • From the circuit, can be seen: • Transistors M1 and M3 are in series. + − Assuming  = 0: VGS1 +VGS3 = V −V 2 2 IREF = Kn1(VGS1 −VTN1 ) = Kn3(VGS3 −VTN 3 ) • Therefore, ≈ ’ (W / L)3 ∆ (W / L)3 ÷ • Assuming VTN, µn, and Cox are identical in all 1− ∆ W / L ÷ transistors, thus: (W / L)1 + − « ( )1 ◊ VGS1 = ⋅(V −V )+ ⋅VTN = VGS 2 W / L ≈ ’ ( )3 ∆ (W / L)3 ÷ ≈ ’ 1+ ∆1+ ÷ (W / L)3 ∆ (W / L)3 ÷ (W / L) W / L V = ⋅V + 1− ⋅V 1 « ( )1 ◊ GS1 (W / L) GS3 ∆ (W / L) ÷ TN 1 « 1 ◊ 15 16

4.1) Basic Two-Transistor MOSFET Current Source (Cont) 4.1) Basic Two-Transistor MOSFET Current Source (Cont)

4.1.3) Reference Current, IREF (Cont) 4.1.3) Reference Current, IREF (Cont)

• Finally, the load current, for  = 0, is given by Design Example 10.8

≈W ’ ≈ 1 ’ 2 I = ∆ ÷ ∆ µ C ÷(V −V ) Objective: Design a MOSFET current source to O n ox GS 2 TN meet a set of specifications. « L ◊2 « 2 ◊ ' Specifications: The circuit to be designed has the k ≈W ’ 2 I = n ⋅∆ ÷ (V −V ) (10.53) configuration shown in Figure 10.17. O 2 « L ◊ GS 2 TN The bias voltages are V + = +2.5 V, V -- = 0 V. 2 ’ Transistors are available with parameters k n = 100 2  • Since the designer has control over the µA /V , VTN = 0.4 V, and = 0. width-to-length ratios of the transistors, Design the circuit such that IREF = 100 µA, IO = 60 there is a considerable flexibility in the design µA, and VDS2(sat) = 0.4 V. of MOSFET current sources. 17 18

Lecturer: Dr Jamaludin Bin Omar 4-3 EEEB273 – Electronics Analysis & Design II

4.1) Basic Two-Transistor MOSFET Current Source (Cont) 4.1) Basic Two-Transistor MOSFET Current Source (Cont)

4.1.3) Reference Current, IREF (Cont) 4.1.3) Reference Current, IREF (Cont)

Design Example 10.8 (Cont) Design Example 10.8 (Cont)

Solution: With VDS2(sat) = 0.4 = VGS2 – 0.4, The reference current is given by then V = 0.4 + 0.4 = 0.8 V = V ' GS2 GS1 k ≈W ’ 2 I = n ⋅∆ ÷ (V −V ) REF « ◊ GS1 TN ≈W ’ I 2 L 1 Therefore, ∆ ÷ = O ' ≈W ’ I « L ◊2 kn 2 Since V = V Ï ∆ ÷ REF V −V GS1 GS2 = ' ( GS 2 TN ) « ◊ k 2 2 L 1 n (VGS2 −VTN ) ≈W ’ 60 2 ∴∆ ÷ = = 7.5 ≈W ’ 100 100 2 ∆ ÷ « L ◊2 ∴ = = 12.5 (0.8 − 0.4) « L ◊ 100 2 2 1 (0.8 − 0.4) 19 2 20

4.1) Basic Two-Transistor MOSFET Current Source (Cont) 4.1) Basic Two-Transistor MOSFET Current Source (Cont)

4.1.3) Reference Current, IREF (Cont) 4.1.4) Using N-MOSFET and P-MOSFET

Design Example 10.8 (Cont)

The value of VGS3 is + -- VGS3 = (V – V ) – VGS1 = 2.5 – 0.8 = 1.7 V

2 Since IREF = Kn3 (VGS3 – VTN) , therefore

≈W ’ I REF ∆ ÷ = ' « L ◊ k 2 3 n (V −V ) 2 GS3 TN ≈W ’ 100 ∴∆ ÷ = = 1.18 « L ◊ 100 2 3 (1.7 − 0.4) 2 21 Figure 10.17 Figure P10.52 22

4.2) Multi-MOSFET Current-Source Circuits 4.2.1) Cascode Current Mirror

• Among multi-MOSFET current- • As in Figure 10.18, source circuits are: with increased output

resistance RO ß Cascode Current Mirror • IREF is established ß Wilson Current Mirror using another transistor. ß Wide-Swing Current Mirror • When all transistors are matched:

Fig 10.18: MOSFET IO = IREF 23 cascode current mirror. 24

Lecturer: Dr Jamaludin Bin Omar 4-4 EEEB273 – Electronics Analysis & Design II

4.2.1) Cascode Current Mirror (Cont) 4.2.1) Cascode Current Mirror (Cont)

• To determine output resistance at the drain of

M4, use the small-signal equivalent circuit.

• IREF constant ‰ gate voltages to M1 and M3, and hence M2 and M4, are constant ÏEquivalent to an ac . • Therefore, the ac equivalent circuit for calculating the output resistance is shown in Figure 10.19(a). The small signal equivalent circuit is given in Figure 10.19(b).

• The small-signal resistance looking Fig 10.19: Equivalent circuits of the MOSFET into the drain of M2 is rO2. 25 cascode current mirror for determining RO 26

4.2.1) Cascode Current Mirror (Cont) 4.2.1) Cascode Current Mirror (Cont)

V − (−V ) • From Figure 10.19(b), summing currents at output I = I + I Ω I = g V + x gs4 node yields x 1 2 x m gs4 V − (−V ) ro4 x gs4 I x = gmVgs4 + ro4 Also Vgs4 = −I xro2

ro2 Vx Therefore I x + I x + gmro2 I x = ro4 ro4

Vx 0 −Vgs4 − I xro2 = 0 Finally R = = r + r (1+ g r ) (10.57) O I o4 o2 m o4 Ω x Vgs4 = −I xro2 27 28

4.2.1) Cascode Current Mirror (Cont) 4.2.1) Cascode Current Mirror (Cont) Ω Example 10.9 • Normally gmro4 >> 1 gmro4ro2 >> ro4 Thus R ≅ g r r Objective: Compare the output resistance of the O m o4 o2 cascode MOSFET current mirror (CMCM) to that of the two-transistor MOSFET current mirror (2TMCM). • This implies that the output resistance of this cascode configuration is much larger than that of the basic two-transistor current source. Consider the 2TMCM in Figure 10.17 and the CMCM in Figure 10.18.

Ï Since dIO is proportional to 1/RO, the Assume that IREF = IO = 100 µA in both circuits, load current in the cascode circuit is more -1  = 0.01 V for all transistors, and gm = 0.5 mA/V. stable against variations in output voltage. 29 30

Lecturer: Dr Jamaludin Bin Omar 4-5 EEEB273 – Electronics Analysis & Design II

4.2.1) Cascode Current Mirror (Cont) 4.2.2) Wilson Current Mirror

Example 10.9 (Cont)

Solution: The output resistance of 2TMCM is, from Equation (10.48),

rO = 1/( IREF) = 1/[(0.01)(100µ)] = 1 M

For the CMCM circuit,

rO2 = rO4 = 1/( IO) = 1/[(0.01)(100µ)] = 1 M

Therefore, RO of the CMCM circuit is, from Equation (10.57), R = r + r (1 + g r ) O O4 O2 m O4 Fig 10.20: (a) MOSFET Wilson current mirror, = 1M + (1M)[1 + (0.5m)(1M)] = 502 M 31 (b) Modified MOSFET Wilson CM. 32

4.2.2) Wilson Current Mirror (Cont) 4.2.2) Wilson Current Mirror (Cont)

• Fig 10.20(a) is MOSFET Wilson current mirror. • In modified MOSFET Wilson current mirror:

Ï Add transistor M4 • Note: VDS1 = VGS2 + VGS3 • For a constant IREF, VDS of M1, M2 and M4 are VDS2 = VGS2 held constant ÏV of M and M are equal (V = V ) Ï VDS1 ≠ VDS2 DS 1 2 DS1 DS2 • Primary advantage of both Wilson current • Since:  ≠ 0 mirrors: INCREASE in output resistance RO, Ï is slightly different from IO / IREF Ï i.e. further stabilizes the load current IO. the aspect ratios • Output resistance of Wilson current mirror: • This problem is solved in the modified Wilson current mirror, shown in Figure 10.20(b). R ≅ g r r 33 O m o3 o2 34

4.2.3) Wide-Swing Current Mirror 4.2.3) Wide-Swing Current Mirror (Cont)

4.2.3.1) Minimum output voltage swing, VO(min) a) Simple two-transistor CM

• The minimum output voltage for the simple two-transistor current mirror is − VO (min) = V +VDS 2 (sat)

• If VGS = 0.75V and VTN = 0.50V _ then VO(min) is only 0.25V above V i.e. VDS2(sat) = VGS - VTN = 0.25V. Fig 10.21: A wide-swing MOSFET cascode current mirror. 35 36

Lecturer: Dr Jamaludin Bin Omar 4-6 EEEB273 – Electronics Analysis & Design II

4.2.3) Wide-Swing Current Mirror (Cont) 4.2.3) Wide-Swing Current Mirror (Cont)

4.2.3.1) Minimum output voltage swing, VO(min) 4.2.3.1) Minimum output voltage swing, VO(min)

b) MOSFET cascode CM b) MOSFET cascode CM (Cont)

• The gate voltage of M4 is • Assuming matched transistors, − V =V =V ≡V VG4 = V +VGS1 +VGS3 GS1 GS2 GS 4 GS • Then

• The minimum VD4 is then − VD4 (min) = V + (VGS +VDS4 (sat)) VD4 (min) = VS 4 +VDS4 (sat)

• If VGS = 0.75V and VTN = 0.50V VD4 (min) = VG4 −VGS4 +VDS4 (sat) _ then VD4(min) = 1.0V above V 37 38

4.2.3) Wide-Swing Current Mirror (Cont) 4.2.3) Wide-Swing Current Mirror (Cont)

4.2.3.1) Minimum output voltage swing, VO(min) 4.2.3.2) VO(min) of Wide-swing cascode CM

b) MOSFET cascode CM (Cont) • WSCCM does not limit output voltage swing like cascode circuit.

• Increase in VO(min) means reduced • WSCCM maintains high RO. maximum output voltage swing of the • All transistors are identical load circuit, which is critical in low- except for the different width-to- power applications. length ratios (as shown in Figure

Ï Although RO of cascode is higher, 10.21). output swing is smaller. • M3 and M4 together act like a Figure 10.21: WSCCM single connected-transistor *** Wide-swing cascode current- to create V . mirror produces increased Ro and G3 • With M4, VDS3 is matched to VDS2. increased output voltage swing. 39 40

4.2.3) Wide-Swing Current Mirror (Cont) 4.2.3) Wide-Swing Current Mirror (Cont)

4.2.3.2) VO(min) of Wide-swing cascode CM (Cont) 4.2.3.2) VO(min) of Wide-swing cascode CM (Cont)

• Since M5 is ¼ the size of M1 ~ M4 • The minimum VO at the drain of M1 is and since all drain currents are equal, then VD1(min) = VG1 −VGS1 +VDS1(sat) V (min) = V −V +V −V + (V −V ) (VGS5 −VTN ) = 2(VGSi −VTN ) D1 [( GS5 TN ) TN ] GS1 GS1 TN

where VGSi corresponds to gate-to- or source voltage of M1 ~ M4 VD1(min) = VGS5 −VTN = 2(VGSi −VTN ) = 2VDSi (sat) Figure 10.21: WSCCM • The voltage at the gate of M1 is • If VGSi = 0.75V and VTN = 0.50V, VG1 =VGS5 = (VGS5 −VTN ) +VTN then VD1(min) = 0.50V, Ï ½ of cascode circuit. 41 42

Lecturer: Dr Jamaludin Bin Omar 4-7 EEEB273 – Electronics Analysis & Design II

4.2.3) Wide-Swing Current Mirror (Cont) 4.3) Bias-Independent Current-Source

4.2.3.3) Summary of VO(min) • Previous current sources:

ß IREF is dependent on supply voltages. • For VGSi = 0.75V and VTN = 0.50V: ß So, IO depends on supply voltages, _ 2TMCM Ï VO(min) = 0.25V above V which is undesirable in most cases.

_ CMCM Ï VO(min) = 1.00V above V • Circuit design in which the load current is essentially independent of the bias is WSCCM Ï (min) = 0.50V above _ VO V shown in Figure 10.22, with width-to- length ratios given.

43 44

4.3) Bias-Independent Current-Source (Cont) 4.3) Bias-Independent Current-Source (Cont)

• Since PMOS devices are matched, ID1 = ID2 ' k ≈W ’ 2 For M1: n I D1 = ∆ ÷ (VGS1 −VTN ) 2 « L ◊1 ' kn ≈W ’ 2 For M2: I D2 = ∆ ÷ (VGS 2 −VTN ) 2 « L ◊2

KVL for M1, VGS 2 = VGS1 − I D2 R M2 and R ‰ ≈ ’ 1 ∆ (W / L)1 ÷ Solving for R: R = ∆1− ÷ kn1I D1 « (W / L)2 ◊ 45 46 Figure 10.22: Bias-independent MOSFET current mirror.

4.3) Bias-Independent Current-Source (Cont) 4.4) MOSFET Active Load Circuit

• Value of R establishes ID1 = ID2 • M1 and M2 form a • ID1 and ID2 then establishes VGS1 and VSG3 PMOS active load • VGS1 and VSG3, in turn, can be applied to M5 circuit. and M6 to establish load currents IO1 and IO2 • M2 is the active load device for driver • ID1 and ID2 are independent of supply voltages + _ transistor M . V and V as long as M2 and M3 are biased in 0 the saturation region. • Consider the voltage • As the difference, V+ - V_ , increases, the transfer function of VO values of V and V increase but the Figure 10.33: Simple versus VI for this circuit. DS2 SD3 MOSFET with . currents remain essentially constant active load, showing 47 currents and voltages. 48

Lecturer: Dr Jamaludin Bin Omar 4-8 EEEB273 – Electronics Analysis & Design II

4.4.1) DC Analysis: MOSFET Active Load Circuit 4.4.1) DC Analysis: MOSFET Active Load Circuit (Cont) • Establish Q-point in · As input changes the region where M0 between VIH and VIL and M2 are biased in  the Q-point moves the saturation region up and down load mode. curve producing a change in output  Only small range of voltage. input voltage is · When VI = VI2  M0 available. is driven into non- saturation region. · Q-point corresponds Fig 10.35: Driver transistor · When V = V  Q Fig 10.34: Voltage transfer I I1 2 to VI = VI Q characteristics and load is driven into non- characteristics of MOSFET curve for MOSFET circuit circuit with active load. saturation region. 49 with active load. 50

4.1) Basic Two-Transistor MOSFET Current Source

Larger circuits

Fig 10.16: Basic two-transistor NMOS MOSFET

51 current source. 52

4.1) Basic Two-Transistor MOSFET Current Source (Cont) 4.2.1) Cascode Current Mirror

4.1.3) Reference Current, IREF

Fig 10.17: Fig 10.18: MOSFET MOSFET cascode current source. 53 current mirror. 54

Lecturer: Dr Jamaludin Bin Omar 4-9 EEEB273 ± Electronics Analysis & Design II

4.2.1) Cascode Current Mirror (Cont) 4.2.2) Wilson Current Mirror

Fig 10.20: (a) MOSFET Wilson CS, (b) Modified Fig 10.19: Equivalent circuits of the MOSFET MOSFET Wilson CS. cascode current mirror for determining RO 55 56

4.2.3) Wide-Swing Current Mirror

Fig 10.21: A wide-swing MOSFET cascode current mirror. 57

Lecturer: Dr Jamaludin Bin Omar 4-10