An Optimal Digital Filtering Technique for Incremental Delta-Sigma Adcs Using Passive Integrators

electronics

Article An Optimal Digital Filtering Technique for Incremental Delta-Sigma ADCs Using Passive Integrators

Hyunmin Park, Hyungil Chae and Jintae Kim *

Electrical and Electronics Engineering Department, Konkuk University, Seoul 05029, Korea; [email protected] (H.P.); [email protected] (H.C.) * Correspondence: [email protected]

Abstract: This paper presents an optimal digital filtering technique to enhance the resolution of incremental delta-sigma modulators (incremental DSMs, IDSMs) using a low-power passive integrator. We first describe a link between a passive integrator and its impact on the output of the IDSM. We then show that the optimal digital filter design can be cast as a convex optimization problem, which can be efficiently solved. As a test vehicle of the proposed technique, we use a behavioral 2nd-order IDSM model that captures critical non-idealities of the integrator, such as gain compression and output saturation. The effectiveness of the presented technique is verified using extensive simulations. The result shows that the presented filtering technique improves signal-to-noise and distortion ratio (SNDR) by 15 dB–20 dB, achieving SNDR over 90 dB when the oversampling ratio (OSR) = 256, and this corresponds to best-in-class performance when compared to previously published DSM designs using passive integrators.

Keywords: analog-to-digital converter; delta-sigma modulator; extended ranging; passive integrator; digital calibration; optimal ﬁltering

Citation: Park, H.; Chae, H.; Kim, J. An Optimal Digital Filtering 1. Introduction Technique for Incremental High-resolution and low-bandwidth analog-to-digital converters (ADC) are essential Delta-Sigma ADCs Using Passive building blocks in various sensor and IoT applications. Traditionally, delta-sigma ADCs Integrators. Electronics 2021, 10, 213. have been the dominant architecture for designing such ADCs since it can aggressively https://doi.org/10.3390/electronics reduce the quantization noise for a sufficiently high oversampling ratio. However, the 10020213 delta-sigma modulator (DSM) requires an integrator to realize the noise-shaping, thereby necessitating a power-hungry operational amplifier (op-amp) in the design. Since the power Received: 8 December 2020 efficiency of op-amps does not directly improve with finer process nodes, such a design Accepted: 14 January 2021 Published: 18 January 2021 requirement remains a challenge when one wants to design a low-power, high-resolution ADCs in highly scaled technologies.

Publisher’s Note: MDPI stays neutral To address this challenge, there have been quite a few works that explored alternative with regard to jurisdictional claims in design approaches that aim to achieve quantization noise shaping without op-amps. For published maps and institutional affil- instance, [1] uses an open-loop integrator based on a dynamic amplifier in a DSM to realize iations. 3rd-order noise shaping. While using a dynamic amplifier may lead to lower power, it is vulnerable to process and temperature variation. As a more aggressive approach, one can use passive DSMs by removing amplifiers in the design [2–5]. Such implementations, however, suffer from the lack of a gain element. For example, the fully passive second-order DSM in [3] is constrained by the noise performance of the quantizer because the signal at Copyright: © 2021 by the authors. µ Licensee MDPI, Basel, Switzerland. the input of the quantizer is only 100 Vrms. The authors in [4] compare a fully passive and This article is an open access article a conventional DSM designed in the same process, revealing that the fully passive DSM distributed under the terms and exhibits 10 dB less SNDR than the conventional one. To overcome this challenge, hybrid conditions of the Creative Commons approaches that mix both active and passive integrators have been explored [6–11]. The Attribution (CC BY) license (https:// continuous-time (CT) DSM in [6] uses a two-pole active integrator structure, thereby using creativecommons.org/licenses/by/ only two amplifiers for a 4th-order CTDSM. The 5th-order CTDSM in [7] uses a power- 4.0/). hungry op-amp only for the first integrator, while the rest of the four stages are passive

Electronics 2021, 10, 213. https://doi.org/10.3390/electronics10020213 https://www.mdpi.com/journal/electronics Electronics 2021, 10, 213 2 of 14

and gm-C integrators. The downside, however, is that leakage in the passive integrators degrades overall noise performance, leading to a measured SNDR of only 63.4 dB. Similarly, in [8], the third-order discrete-time DSM uses a single op-amp to realize gm-C integrator and two other poles are implemented as passive integrators, ending up with a dynamic range of only 54 dB. The 2-1 multi-stage noise shaping (MASH) CTDSM in [10], which is also a hybrid topology with a passive RC-integrator and a low-gain amplifier, achieves a slightly higher SNDR of 72 dB thanks to the digital cancellation logic that takes care of variations in open-loop gain and passive element values. The work in [11] is the most recent article that thoroughly studies the design tradeoffs of active-passive hybrid structure for designing DSMs, achieving 88 dB of SNDR with OSR of 260 from their discrete-time third-order DSM. High SNDR, however, is mainly attributed to their new third-order structure utilizing local feedbacks that realize zeros in the noise transfer function (NTF) of the DSM, and finding several design parameters is not straightforward. For instance, authors in [11] reported that seven interdependent gain parameters had to be found by recursive behavioral simulations. Our foregoing reviews on prior publications share common design approaches aiming to overcome limitations of using low-power passive integrators—First, they rely upon some gain elements to get over the noise penalty of using passive integrators. Second, to overcome the integrator leakage inherent in passive integrators, compensation techniques such as digital cancellation logic [10] or optimized NTF zero in analog circuits [11] are used. The challenge in these cases is the lack of straightforward methods for finding the design parameters for the compensation, which is the motivation of this work. This paper presents an optimal digital filtering technique that can enhance the linearity of a DSM utilizing hybrid passive-active integrators. We present a straightforward method for finding design parameters of the optimal digital filter without uncertainty. A test vehicle of the proposed filtering technique is a 2nd-order incremental DSM (IDSM) having an extended-range (ER) function [12,13] to further enhance the resolution. The main reason for choosing this architecture is the simplicity of the topology that does not suffer from instability as well as the potential to achieving high SNDR beyond 90 dB. Our method is based on two recognitions that (1) the optimal digital decimation filter structure for IDSMs using leaky integrators must be redefined for the best possible SNR, and (2) the residual signal at the output of the last leaky integrator in a DSM can be combined with a filtered DSM output to further enhance the resolution of ADC. Conceptually, (2) has been demonstrated in DSMs using a conventional active integrator based on high-gain op-amps [12,13]. Our contribution, however, is showing that such an extended range method can still be applied to the DSMs using leaky integrators if a proper digital filtering technique is applied. Table1 compares the main distinctions between our work and prior works utilizing hybrid active-passive integrators.

Table 1. Comparison with other analog-to-digital converters (ADCs) using passive integrators.

This Work [1][4][11] Structure of ADC 2nd DT + ER NS-SAR 2nd DT DSM 3rd DT DSM Structure of integrator P-H H A-A and P-P P-H-H Incremental? Yes No No No Optimal digital ﬁlter? Yes No No No P: passive, A: active-Resistor-Capacitor (RC), H: hybrid (passive + gain), DT: discrete time.

Section2 reviews the fundamentals of incremental DSMs using leaky integrators and the theoretical foundation of the optimal digital filtering method. Section3, which is the main contribution of this work, describes a straightforward procedure for finding tap weights of the optimal digital filter. Section4 discusses design concerns when implementing DSMs using leaky integrators with a focus on integrator output swing and gain nonlinearity Electronics 2021, 10, x FOR PEER REVIEW 3 of 14

Table 1. Comparison with other analog-to-digital converters (ADCs) using passive integrators.

This Work [1] [4] [11] Electronics 2021, 10, 213 Structure of ADC 2nd DT + ER NS-SAR 2nd DT DSM 3rd DT DSM3 of 14 Structure of integrator P-H H A-A and P-P P-H-H Incremental? Yes No No No issue.Optimal Section digital5 presents filter? numerical experiments Yes based No on ADCNo models designed No using a P:behavioral passive, A: simulator.active-Resistor-Capacitor Section6 concludes (RC), H: the hybrid paper. (passive + gain), DT: discrete time.

2.2. IDSM IDSM Model Model Using Using Leaky Leaky Integrators Integrators FigureFigure 1 illustratesillustrates aa block block diagram diagram of of a second-ordera second-order IDSM. IDSM. The The DSM DSM is a feedforwardis a feedfor- wardtopology topology where where a residual a residual quantization quantization error is e generatedrror is generated at the output at the of output the last of integrator. the last integrator.Therefore, re-quantizingTherefore, re-quantizing the residual the error residual by an extraerror quantizerby an extra (ADC quantizerres in Figure (ADC1)res and in Figurecombining 1) and the combining post-ﬁltered the output post-filtered from the DSMoutput and from the outputthe DSM from and ADC theres outputwith proper from ADCweightsres with can proper future enhanceweights can the resolution.future enhance the resolution.

b1 a1/a2 = 0.72/0.64 v b 2 b1/b2 = 1/1.72

M-1 Fs M-2 a1 a2 w y Dout,dsm + + + 2 VIN - z-1 z-1 … F /M Decimation RST RST s Fs Dout,ER Filter + DAC VREF·y ADCres k

FigureFigure 1. 1. AA block block diagram diagram of of the the conventional conventional 2 2nd-ordernd-order discrete discrete time time (DT) (DT) incremental incremental delta-sigma delta-sigma modulatormodulator (IDSM) (IDSM) with with extended extended range. range.

ForFor decimating DSMDSM output, output, a digitala digital finite-impulse-response finite-impulse-response (FIR) (FIR) CoI (cascade-of-CoI (cascade-of-integrator)integrator) filter is filter a popular is a popular choice, choice, which iswhich proven is proven to be effective to be effective in maximizing in maximiz- SNR ingwhen SNR the when integrators the integrators are ideal are [13 ideal]. However, [13]. However, when there when is athere leakage is a leakage in the integrators, in the integrators,such a CoI such filter a yieldsCoI filter suboptimal yields suboptimal results. To results. further To investigate further investigate the impact the of leakageimpact of in leakagethe integrator, in the letintegrator, us first consider let us first an ideal consider discrete-time an ideal integrator discrete-time whose integrator output is whose simply outputa sum ofis simply previous a sum input of and previous stored input value, and i.e., stored value, i.e.,

y[n[]]==x[n[−1− 1]]++y[n[−1− 1] ] (1)(1) which leads to the z-domain transfer function which leads to the z-domain transfer function 1 − , = z 1 = 1 (2) H = 1−= −1 (2) I,ideal 1 − z−1 z − 1 When there is a leakage in the integrators, the previous sample value y[n-1] is not entirelyWhen transferred there is ato leakage the current in the sample integrators, value they[n previous]. To accommodate sample value thisy [leakagen − 1] is and not possibleentirely signal transferred gain in to the currentpassive-active sample hybrid value yintegrator,[n]. To accommodate the expression this for leakage the ideal and integratorpossible signal in Equation gain in (1) the needs passive-active to be modified hybrid as: integrator, the expression for the ideal integrator in Equation (1) needs to be modiﬁed as: [] =⋅[−1] +⋅[−1] (3) where β < 1 accounts for they leakleakage[n] = αof· thex[n −integrator1] + β · y and[n − α1 ]is the forward signal gain.(3) Figure 2a shows a corresponding block diagram of the expression in Equation (3). Figure where β < 1 accounts for the leakage of the integrator and α is the forward signal gain. 2b illustrates one possible and potentially low-power, the implementation for such a Figure2a shows a corresponding block diagram of the expression in Equation (3). Figure2b leaky integrator, where the charge sharing between Cin and Cf realizes the passive inte- illustrates one possible and potentially low-power, the implementation for such a leaky gration, and the gain element of G compensates the signal loss. From the charge conser- integrator, where the charge sharing between Cin and Cf realizes the passive integration, and the gain element of G compensates the signal loss. From the charge conservation, one can easily show that the leakage and the forward gain terms in Equation (3) is determined as:

G · C G · Cf α = in , β = (4) Cin + Cf Cin + Cf Electronics 2021, 10, x FOR PEER REVIEW 4 of 14 Electronics 2021, 10, x FOR PEER REVIEW 4 of 14 vation, one can easily show that the leakage and the forward gain terms in Equation (3) is determinedvation, one canas: easily show that the leakage and the forward gain terms in Equation (3) is Electronics 2021, 10, 213 determined as: 4 of 14 ⋅ ⋅ = , = (4) ⋅ + ⋅ + = , = (4) + + andand α α= =1 1− −β holdsβ holds for for the the passive passive integrator.integrator. The Thez-domain z-domain transfer transfer function function of the of leaky the leaky integratorandintegrator α = 1 −is isβ then holds then given given for the by: passive integrator. The z-domain transfer function of the leaky integrator is then given by: −1 αz α HI,leaky,= = − = = (5) (5) , =1 − βz 1 =z − β (5) 1−1− −−

x[n]x[n] yyleakleak[[nn]] −1−1 S S2 α α + + ZZ S1 S1 Cin Cin 2 v[n] v[n] vinvin G G yyleakleak[[n]= C S2 S2 S1 S1f Cf αα·x·x[n−1]++ββ·y·y[n[n−1]−1] LeakyLeaky Cf β β β = Cf integrator Cβin+C =f integrator Cin+Cf (a)(a) (b) (b) FigureFigure 2. 2.(a()a A) Ablock block diagram diagram of of the the leaky leaky integrator integrator and and (b (b) )an an implementation implementation of of the the leaky leaky integrator with aa gaingain element.element. Figure 2. (a) A block diagram of the leaky integrator and (b) an implementation of the leaky integrator with a gain element. Figure 3 redraws the IDSM model, where a leaky integrator is used for the 1st stage. Figure3 redraws the IDSM model, where a leaky integrator is used for the 1st stage. West Figure 3 redraws the IDSMst model, where a leaky integrator is used for the 1 stage. Wehave have replaced replaced only only the 1stthe integrator 1 integrator with with a leaky a leaky integrator integrator because because the power the power dissipation dis- st Wesipationof have the 1st ofreplaced stagethe 1 integratorst stageonly integratorthe dominates 1 integrator dominates in atypical with in a a IDSMtypical leaky design. IDSMintegrator design. To compare because To compare the the optimal power the dis- sipationoptimalfilter expressions offilter the expressions 1st forstage anideal integrator for andan ideal a leaky dominates and integrator, a leaky in integrator, leta typical us first let considerIDSM us first design. an consider ideal To case an compare whereideal the optimalcasethere where is filter no there leakage, expressions is no i.e., leakage,β for= 1 an andi.e., ideal βα == 11. and It can αa = le 1. beaky It shown can integrator, be thatshown the letthat residual us the first residual signal consider wsignalafter an ideal casewM after cycleswhere M cycles ( Mtherebeing ( isM no thebeing leakage, oversampling the oversampling i.e., β ratio) = 1 and atratio) the α = at output 1. the It canoutput of thebe shownof second the second that integrator the integrator residual is given is signal wgiven afteras [12 asM]: [12]:cycles (M being the oversampling ratio) at the output of the second integrator is given(−1 as [12]:) [] = −M(M − 1) (1 ⋅ [−1] +2⋅[−2] +⋯+(−1) ⋅[1]) (6) w[M] = a1a2 vin − a1a2VREF(1 · y[M − 1] + 2 · y[M − 2] + ··· + (M − 1) · y[1]) (6) (−12 ) 2 [] = − (1 ⋅ [−1] +2⋅[−2] +⋯+(−1) ⋅[1]) (6) 2 a2 = 0.64 b1 v b2 b1/b2 = 0.5/1.72 a2 = 0.64 b1 Fs v G(1−β) a2b2 w b1y/b2 = 0.5/1.72Dout ,dsm + + + - VIN z−β z−1 … …… Fs G(1−β) + a2 w y Opt. Digital Dout ,dsm + Fs/M + Fs Dout, ER - RST RST Filter VIN z−β z−1 … ……+ DAC VREF·y F /M Opt. Digital RST RST s Fs Dout, ER ADCres k Filter + DAC V ·y Figure 3. A blockREF diagram of the 2nd-order DT IDSM architecture using a passive integrator and Figure 3. A block diagram of the 2nd-order DT IDSMADC architecturek using a passive integrator and optimal digital decimation filter. res optimal digital decimation filter. FigureIt 3.It is isA apparent apparentblock diagram from from Equation Equationof the 2nd (6)-order (6) that that DT the the IDSM residual residual architecture signal signal ww[ [MusingM]] is is a a linear linearpassive combination combination integrator and optimalofof vvinin and digitaland bitstream bitstream decimation yy[1],[1], filter.⋯···, y,[ yM[M − −1].1]. Therefore, Therefore, vin vcanin can be beoptimally optimally reconstructed reconstructed by bya propera proper digital-domain digital-domain decimation decimation filter. filter. The The op optimaltimal filter filter coefficients coefficients can can be be found found by by reformulatingreformulatingIt is apparent Equation Equation from (6)Equation (6) as: as: (6) that the residual signal w[M] is a linear combination of2 vin and bitstream2 y[1], ⋯, y[M − 1]. Therefore, vin can be optimally reconstructed by a = vin = ([] +(w[(1M] ⋅+ [a−11a2VREF] +2⋅(1 · y[m[−2− 1] +]2+⋯+· y[M −(−12] + ···) ⋅[1])),+ (M − 1 ) · y[1])), (7)(7) proper(−1 )digital-domaina1a2 M(M − 1) decimation filter. The optimal filter coefficients can be found by reformulating Equation (6) as: oror equivalently: equivalently: 2 = ([] +2· VREF(1 ⋅ [−1] +2⋅[−2] +⋯+(−1) ⋅[1])), (7) (−1) v = E + (1 · y[M − 1] + 2 · y[M − 2] + ··· + (M − 1) · y[1])), (8) in Q M(M − 1) or equivalently: where EQ = 2 · w[M]/(a1a2 M(M − 1)) is the quantization error. It follows from Equation (8) that the optimal decimation filter is a simple M-1 tap FIR filter with descending tap co-

Electronics 2021, 10, 213 5 of 14

efficients from M − 1 to 1. Moreover, since w[M] is linearly scaled quantization error of EQ, it immediately follows that combining the output of the decimation filter and digitized w[M] with proper scaling factor k will further enhance the resolution of the entire ADC conversion. Now, let us consider the case with β 6= 1 that corresponds to the passive and leaky integrator. Due to the incomplete integration, the reconstructed output using the conventional CoI FIR filter is not as effective in reducing quantization noise. A detailed derivation, which is assisted by a symbolic analysis tool, shows that the residual signal wleak[M] when using a passive integrator is expressed as:

M ! i M−j+1 ! ! k k−1 k k−1 wleak[M] = a2(1 − β) ∑ G β vin − a2(1 − β) ∑ ∑ G β y[j] . (9) k=1 j=1 k=1

Expressing vin using wleak leads to:

1 1 i M−j+1 k k−1 vin = ( − )· wleak[M] + A ∑j=1 ∑ = G β y[j] , a2 1 β A k 1 (10) M k k−1 A = ∑k=1 G β

or equivalently, 1 i M−j+1 v = E + Gk βk−1 y[j] . (11) in Q,leak A ∑j=1 ∑k=1 It follows from Equation (11) that even when passive integrators are used, we rec- ognize that (1) vin is still a weighted linear combination of y[1], ··· , y[M − 1] and (2) wleak[M] is a linearly scaled quantization error EQ,leak. The key difference, though, is that (1) the decimation filters should have different coefficients from the CoI filter and (2) the coefficient k when combining digitized wleak[M] and decimation filter output would be different from the case when β = 1. Therefore, once we figure out how to find these filter design parameters, effective quantization noise reduction can still be achieved for IDSMs using passive and leaky integrators.

3. Optimal Digital Decimation Filter Design The amount of leakage β of the integrator depends on actual circuit implementations, and it is often not easy to know β precisely in real designs. Therefore, this article presents a foreground calibration method that enables accurate estimation of the optimal filter coefficients. The calibration setup, along with the ADC structure consisting of an ADC core and a calibration filter logic, is illustrated in Figure4. The calibration logic is a linear M-tap FIR filter having filter coefficients h[m], m = 0, ··· , M − 1 in addition to the summer with a path gain of k for the ADCres. Since the weights of the FIR filter are fixed during the operation, they can be implemented as a combination of an adder, a register, and two multiplexers, as illustrated in Figure4. To find filter parameters, let us assume that we apply a sinewave having a signal frequency of fsig to the ADC with a sampling period TS and conversion length of L. Obtained digital output is then expressed as yi[m], m = 0, ··· , M − 1 and i = 1, ··· , L from the IDSM and Dout,res,i, i = 1, ··· , L from the ADCres for the extended range. Finding optimal digital filter coefficients can be formulated as a following convex optimization problem:

L 2 minimize ∑ err[i] i=1 subject to M−1 (12) err[i] = ∑ yi[m] · h[m] + k · Dout,res,i − vein,est[i] = m 0 vein,est[i] = Asin 2π fsigti + B cos 2π fsigti + C, ti = Ts, 2Ts, ··· , L · TS Electronics 2021, 10, x FOR PEER REVIEW 6 of 14

[] subject to (12) [] =[] ⋅ ℎ[] + ⋅ ,, −,[] Electronics 2021, 10, 213 6 of 14

,[] = 2 + cos2+, =,2,⋯,⋅

wherewhere the the optimization optimization variablesvariables are: are: (1)(1) thethe filter ﬁlter parameters parameters hh[[mm]] and andk ;k; (2)(2) thethe AA, ,BB, ,and and CC forfor estimatingestimating the the best-ﬁt best-fit sinewave. sinewave.

FigureFigure 4. 4. TheThe setup setup for ﬁndingfinding the the optimal optimal digital digital ﬁlter filter parameters. parameters.

InIn essence, essence, anan objective objective of of the the problem problem formulation formulation in Equation in Equation (12) is to (12) find theis to best find the bestfilter filter tap weightstap weightsh[m] ash[m well] as as well the as path the gain pathk for gain the k residue for the output residue such output a way such that a way error between the reconstructed best estimate and the actual input of length L is minimized that error between the reconstructed best estimate and the actual input of length L is in the least-squares sense. To numerically solve the Equation (12), this work uses CVX, minimizeda package forin the specifying least-squares and solving sense. convex To numerically problems [14 solve], where the the Equation problem (12), is solved this work usesvia CVX, an embedded a package interior-point for specifying method and solver. solving In convex addition, problems to test our [14], algorithm, where the we prob- lemcreated is solved a model via of an the embedded second order interior-point IDSM in Figure method3 using solver. CppSim In [ 15addition,], a time–domain to test our algorithm,behavioral we simulation created a package.model of For the experiments, second order we useIDSMG = in 2, Figure b1 = 0.5, 3 busing2 = 1.72 CppSim with an [15], a time–domainoversampling behavioral ratio of 256. simulation Figure5 illustrates package. the For obtained experiments, filter coefficients we use G for = 2, various b1 = 0.5, b2 = 1.72leakage with parameteran oversamplingβ values. ratio Interestingly, of 256. Figure when 5β illustrates= 0.999, which the obtained is the case filter when coefficients the forleakage various is veryleakage small, parameter the optimal β values. filter coefficient Interestingly, is symmetrically when β = shaped0.999, which around is the the case center tap weight. This contrasts with the CoI filter in an active-RC-based integrator. when the leakage is very small, the optimal filter coefficient is symmetrically shaped Such a difference stems from the fact that α and β are interdependent for the passive aroundintegrator. the center Specifically, tap weight.α = β = 1This h olds contrasts for an ideal with active-RC the CoI filter integrator in an in active-RC-based Equation (4), integrator.but when Suchβ gets a closedifference to 1, α stemsapproaches from 0 the in the fact case that of theα and passive β are integrator, interdependent leading to for the passivedifferent integrator. optimal filter Specifically, shape. In theory, α = β = the 1 h filter olds coefficients, for an ideal or theactive-RC impulse integrator response, can in Equa- tionanalytically (4), but when be chosen β gets depending close to on1, βα andapproaches path gain 0G inas the derived case inof Equationthe passive (11), integrator, but leadingFigure 5to shows different one interestingoptimal filter trend shape. that the In peak theory, value the of tapfilter weights coefficients, moves fromor the the impulse response,center to thecan end analytically of the impulse be responsechosen depending as β gets lower. on β and path gain G as derived in

Electronics 2021, 10, x FOR PEER REVIEW 7 of 14 Electronics 2021, 10, x FOR PEER REVIEW 7 of 14 Electronics 2021, 10, 213 7 of 14 Equation (11), but Figure 5 shows one interesting trend that the peak value of tap weightsEquation moves (11), from but Figurethe center 5 shows to the one end interesting of the impulse trend responsethat the peakas β getsvalue lower. of tap weights moves from the center to the end of the impulse response as β gets lower.

Figure 5. (a) Normalized optimal filter filter coefficient coefficient for various leakage values and ( b) corresponding magnitude and phase Figureresponse 5. (a) Normalized of the filter in optimal frequency-domain. filter coefficient for various leakage values and (b) corresponding magnitude and phase responseresponse of the of filter the filter in frequency-domain. in frequency-domain. To verify the actual performance enhancemen enhancementt of applying the optimal digital digital filter, filter, FigureTo verify 66 showsshows the simulatedsimulated actual performance SNDRsSNDRs ofof thethe enhancemen ADCADC inin FigureFiguret of3 3applyingwith with a a conventional conventional the optimal CoI CoI digital filter filter filter, Figureand the6 shows optimal simulated FIR filterfilter obtainedSNDRsobtained of fromfrom the theth ADCe proposedproposed in Figure algorithm.algorithm. 3 with Thea conventional simulatedsimulated SNDRSNDR CoI filter andranges the optimal fromfrom 5050 dB FIRdB and and filter 78 78 dB obtaineddB depending depending from on on theth thee leakage proposed leakage parameter parameter algorithm.β when β whenThe the conventional simulatedthe conven- SNDR rangestionalCoI filter from CoI is filter50 used. dB is In andused. contrast, 78 In dB contrast, with depending the with optimal theon optimal filterthe leakage presented filter parameterpresented in this work, in β thiswhen the work, SNDR the theconven- is tionalSNDRbeyond CoI is 90 beyondfilter dB for is 90 allused. dBβ values for In allcontrast, rangingβ values fromwith ranging 0.85the fromtooptimal 0.999, 0.85 demonstrating tofilter 0.999, presented demonstrating the effectivenessin this the work, ef- the SNDRfectivenessof the is proposed beyond of the algorithm.90 proposed dB for allalgorithm. β values ranging from 0.85 to 0.999, demonstrating the effectiveness of the proposed algorithm.

Figure 6. Comparison of signal-to-noise andand distortiondistortion ratioratio(SNDR) (SNDR) versus versus leakage leakage values values with with and withoutand without the optimalthe optimal digital digital ﬁlter. filter.

Table 2 highlights new contributions of this work in comparison to previously pub- Figure 6.Table Comparison2 highlights of signal-to-noise new contributions and distortion of this work ratio in (SNDR) comparison versus to leakage previously values pub- with lished digital filtering techniques for incremental ADCs. While they are all digitally andlished without digital the optimal filtering digital techniques filter. for incremental ADCs. While they are all digitally synthesizable and can be integrated on-chip with a core ADC, there are two different categories of filteringfiltering approaches, i.e., linearlinear andand nonlinearnonlinear filtering.filtering. In general, linear Table 2 highlights new contributions of this work in comparison to previously pub- filtering does not have the stability issue and can naturally benefit from the thermal noise lished digital filtering techniques for incremental ADCs. While they are all digitally synthesizable and can be integrated on-chip with a core ADC, there are two different

categories of filtering approaches, i.e., linear and nonlinear filtering. In general, linear

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averaging of the oversampled converters. On the other hand, in noise-free situations, a nonlinear and iterative filter can outperform the linear filter in terms of quantization error reduction. However, it is not immediately obvious that the nonlinear filter performs practically better due to the risk of instability from the iterative decoding, which may lead to thermal noise enhancement. For instance, in [16,17], the nonlinear iterative decoding filtering scheme was presented, but the performance under the influence of thermal noise was not verified. Reference [18] is an optimal linear filter approach, which is similar to this work but requires a customized algorithm to find filter coefficients. The optimal filtering technique in [19] is the most recent work, which combines the benefit of noise averaging of linear filtering and the nonlinear decoding at the cost of higher power dissipation and larger area than most linear filters such as Sinc and CoI filters. In contrast, the algorithm for finding optimal filter parameters is based on convex optimization, which already has a stable technology. Being able to easily design an optimal filter via existing solver technology such as CVX [14] is a clear advantage when compared to other methods. In addition, note that none of the previous works have shown whether it is possible to combine the extended range technique, which is to use an extra quantizer for the DSM, and the optimal filtering technique for the lossy integrator. Our additional contribution is that we showed that it is indeed possible to combine these two techniques to further enhance the SNDR.

Table 2. Comparison of various digital ﬁlter techniques for incremental delta-sigma modulator (IDSM).

This Work [16][17][18][19] Decimation filter Linear Nonlinear Nonlinear Linear Nonlinear structure Test vehicle ADC for 2nd-order IDSM with 2nd-order IDSM MASH11 IDSM 3rd-order IDSM 2nd-order IDSM algorithm verification extended range Verified for lossy and passive integrator in Yes No No No No DSM? Verified for extended Yes No No No No range? Filter parameters are Iterative decoding Achieved found via convex may incur random Requires a custom High complexity due only < 100 Sa/s due Comments optimization. noise enhancement algorithm to find to double iteration. to high filter design (global optimal (not verified in the filter coefficients. complexity guaranteed) paper)

4. Circuit-Level Design Considerations There are several design tradeoffs and considerations when one wants to apply the passive integrator in Figure2 to actual IDSM designs. The gain element G can easily be realized by any low-power open-loop amplifiers since G tends to be small (< 10) in practice, but the amplifier output may saturate. Therefore, the swing and the nonlinearity of the entire passive integrator are the paramount concern. The passive integrator, by nature, faces a tradeoff in choosing the ratio between the memory capacitor Cf and the sampling capacitor Cin. From the ADC and the amplifier design perspective, large β and therefore large Cf/Cin ratio are beneficial because the signal swing at the input of the amplifier is attenuated by this ratio, hence meeting the output swing and the linearity requirement in the following amplifier becomes easier. However, the required Cf can be unacceptably large because the Cin value must be chosen considering the kT/C noise limit of the entire conversion. To give a perspective, let us assume that the full input scale is 1Vpp,diff, and we target SNR of 90 dB with OSR = 256. A quick calculation reveals that Cin = 1 pF and Cf = 9 pF are required if we target β = 0.9. Therefore, the area penalty of realizing Cf quickly jeopardizes the benefit of using a low-power passive integrator. On the other hand, if β is too small, the amplifier followed by the passive integrator should handle large signal amplitude, making the nonlinearity of the amplifier more pronounced. Since the gain element in the passive integrator plays a critical role Electronics 2021, 10, x FOR PEER REVIEW 9 of 14

Therefore, the area penalty of realizing Cf quickly jeopardizes the benefit of using a low-power passive integrator. On the other hand, if β is too small, the amplifier followed by the passive integrator should handle large signal amplitude, making the nonlinearity of the amplifier more pronounced. Since the gain element in the passive integrator plays a critical role in attenuating the noise of the following integrator stages, one must consider the overall SNR budget of the ADC when choosing the gain value in the passive

Electronicsintegrator.2021, 10, 213 We found from exhaustive behavioral simulations that β = 0.8479 ofand 14 G = 2 [V/V] achieves a good compromise between the noise gain and the output signal amplitude. in attenuating the noise of the following integrator stages, one must consider the overall Figure 7 showsSNR the budget simulated of the ADC whenhistograms choosing the of gain the value output in the passiveamplitude integrator. in We the found integrator for both the first andfrom exhaustivethe second behavioral stage simulations by using that theβ = G 0.847 = 2 and andG = 2β [V/V]= 0.847. achieves The a goodhistograms indicate that the compromiseoutput swings between theare noise maintained gain and the outputwithin signal ±0.35 amplitude. V and ±0.3 V for the first Figure7 shows the simulated histograms of the output amplitude in the integrator for and the second integrator,both the first andrespectively, the second stage when by using a the±1G V= 2full-scale and β = 0.847. input The histograms sinusoid indicate is applied. Note that this levelthat of the signal output swingsswing are can maintained be easily within accommodated±0.35 V and ±0.3 V in for thetransistor-level first and the am- second integrator, respectively, when a ±1 V full-scale input sinusoid is applied. Note that plifier designs. this level of signal swing can be easily accommodated in transistor-level amplifier designs.

Figure 7.Figure The 7. simulatedThe simulated output output range range of (a )of the (a 1st) stagethe 1 integratorst stage andintegrator (b) the 2nd and stage integrator.(b) the 2nd stage integrator. We also evaluated the impact of the amplifier nonlinearity using behavioral sim- We also evaluatedulations. the Specifically, impact since of the most amplif differentialier amplifiersnonlinearity suffer fromusing compressive behavioral gain simula- nonlinearity versus input magnitude, we use the following gain model tions. Specifically, since most differential amplifiers suffer from compressive gain non- = · − · 2 linearity versus input magnitude, we use Vtheout followingG Vin γ V in (13) gain model in the amplifier block within our ADC model used in the behavioral simulations. Note that V is the input magnitude and γ is a parameter that represents the degree of compressive in nonlinearity, i.e., larger γ would =⋅ lead to higher −⋅ compressive nonlinearity. Figure8a shows (13) the gain versus Vin for several γ values and corresponding worst-case gain error. By using in the amplifier blockthis amplifier within model, our we ADC evaluated model the SNDR used of in the the entire behavioral ADC over various simulations. values γ. Note Figure8b shows the simulated SNDR versus the worst-case gain error arising from the in that V is the inputamplifier magnitude nonlinearity. and The γ simulations is a parameter indicate that that the gainrepresents error must bethe smaller degree than of compressive nonlinearity,2% to achievei.e., larger 90 dB, andγ would up to 5% gainlead error to ishigher allowable compressive if we allow 5 dB nonlinearity. degradation. Fig- While the gain error smaller than 2% is certainly attainable in CMOS amplifier designs, one ure 8a shows the gain versus Vin for several γ values and corresponding worst-case gain still must be cautious about the risk of SNDR degradation from poor amplifier linearity error. By using thisperformance amplifier when model, attempting we to use evaluated passive integrators the SNDR in the DSM of designs. the entire ADC over various values γ. Figure 8b shows the simulated SNDR versus the worst-case gain error arising from the amplifier nonlinearity. The simulations indicate that the gain error must be smaller than 2% to achieve 90 dB, and up to 5% gain error is allowable if we allow 5 dB degradation. While the gain error smaller than 2% is certainly attainable in CMOS amplifier designs, one still must be cautious about the risk of SNDR degradation from poor amplifier linearity performance when attempting to use passive integrators in the DSM designs.

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Electronics 2021, 10, 213 10 of 14 Electronics 2021, 10, x FOR PEER REVIEW 10 of 14

γ γ γ γ

Figure 8. (a) Compressive gain nonlinearity and the worst-case gain error of the amplifier. (b)

Simulated SNDR vs. gain error from the nonlinearity. FigureFigure 8.8.( (aa)) CompressiveCompressive gain gain nonlinearity nonlinearity and and the the worst-case worst-case gain gain error error of of the the amplifier. amplifier. (b ()b Simu-) Simulated SNDR vs. gain error from the nonlinearity. 5. Numericallated SNDR vs. Experiments gain error from the nonlinearity. 5.5. NumericalForNumerical realistic ExperimentsExperiments and extensive numerical experiments, we designed a full switched-capacitorForFor realisticrealistic and second-orderand extensive extensive numerical IDSM, numerical as experiments, shown experiments, in Figure we designed 9we using designed a fullCppSim. switched- a fullThe pa- rametercapacitorswitched-capacitor values second-order used insecond-order our IDSM, ADC as shown modelIDSM, in areas Figure shown summarized9 using in Figure CppSim. in 9Table using The 3. parameterCppSim. For realistic The values pa-simulations,usedrameter the in ourmodel values ADC includesused model in areour kT summarized/ADCC noise model of intheare Table switched-capacitorsummarized3. For realistic in Table simulations, circuits 3. For realistic as the well model simula- as in-the am- plifiercludestions, input-referred thekT/ modelC noise includes of thethermal switched-capacitor kT/C noise. noise ofThe the noise circuitsswitched-capacitor density as well asand the circuits the amplifier nonlinearity as well input-referred as the parameter am- γ valuethermalplifier γ in input-referred noise.Table The 3 are noise thermalderived density noise. from and The thea transistor-level nonlinearitynoise density parameter and design the nonlinearityin value 65 nmin TableCMOS parameter3 are process. derivedvalue γ fromin Table a transistor-level 3 are derived design from ina 65transistor-level nm CMOS process. design The in 65 behavioral nm CMOS model process. also The behavioral model also includes random mismatches for the sampling capacitor Cin1 includesThe behavioral random model mismatches also includes for the sampling random mismatches capacitor Cin1 forand the the sampling integration capacitor capacitor Cin1 and the integration capacitor Cf1 as well as a random gain variation for the first stage Candf1 as the well integration as a random capacitor gain variationCf1 as well for as the a random first stage gain amplifier. variation The for mismatch the first stage and amplifier.variationamplifier. The parameters The mismatch mismatch are necessary andand variationvariation for the parametersparameters Monte-Carlo are are simulations,necessary necessary for which forthe theMonte-Carlo are Monte-Carlo used to simulations,verifysimulations, the robustness which which are are of theused used proposed toto verifyverify optimal thethe ro filteringrobustnessbustness technique of ofthe the proposed to proposed possible optimal process optimal filtering spread filtering techniqueandtechnique device to topossible mismatches possible process process in actual spreadspread chip and fabrication.and device device mismatches mismatches in actualin actual chip chip fabrication. fabrication.

Figure 9. Overall IDSM architecture using a leaky integrator for the 1st stage and optimal digital filter.

FigureFigure 9. Overall 9. Overall IDSM IDSMTable architecture architecture 3. ADC parameters using using a a leaky leaky for behavioral integratorintegrator simulations. for for the the 1st 1st stage stage and and optimal optimal digital digital ﬁlter. filter. Parameter Value Table 3. ADC parameters for behavioral simulations. ADC sampling frequency (Fs) 12 (MHz) OversamplingParameter ratio (OSR) 64, 128,Value 256 ADCCalibration sampling signal frequency frequency (F s) 0.3412F (MHz)s InputOversampling thermal noise ratio of (OSR)1st amp 11 (nV/ 64,√ 128,) 256 Calibration signal frequency 0.34Fs Input thermal noise of 1st amp 11 (nV/√)

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Table 3. ADC parameters for behavioral simulations. Electronics 2021, 10, x FOR PEER REVIEW Parameter Value 11 of 14 ADC sampling frequency (Fs) 12 (MHz) Oversampling ratio (OSR) 64, 128, 256

CalibrationInput signal thermal frequency noise of 2nd amp 0.34Fs 15 (nV/√) √ Input thermal noise of 1stG amp, 11 (nV/ Hz) 2 (V/V), 0.5 √ Input thermal noise of 2ndb amp1, b2 15 (nV/ Hz) 0.5, 1.72 of capacitorG, γ mismatch for C = 1 pF 2 (V/V), 0.5 0.03% b1, b2 of gain variation 0.5, 1.72 1% σ of capacitor mismatchResolution for C = 1of pF ADCres 0.03% 8-bit σ of gain variation 1%

Figures 10Resolution and 11 show of ADC ares few snapshots of nominal simulations8-bit with OSR = 256 and OSR = 64, respectively, with no mismatch or variation parameters. In this experiment, we appliedFigures fsig 10= 0.028and 11F sshow when a fewOSR snapshots = 256 and of nominalfsig = 0.084 simulationsFs when withOSR OSR= 64, = 256respectively, and as representativeOSR = 64, respectively, inputs. Figure with no 10a mismatch shows or variationthe frequency parameters. domain In this spectrum experiment, of weADC out- putsapplied for OSRfsig == 0.028256 Fwhens when using OSR =the 256 conventional and fsig = 0.084 CoIFs when filter OSR (shown = 64, respectively,in blue) and as the pro- representative inputs. Figure 10a shows the frequency domain spectrum of ADC outputs posed optimal filter (shown in red). Figure 10b graphs the optimal FIR filter coefficients for OSR = 256 when using the conventional CoI filter (shown in blue) and the proposed thatoptimal are used filter to (shownproduce in red).the frequency-domain Figure 10b graphs the spectrum. optimal FIRSimilarly, filter coefficients Figure 11 that shows the frequency-domainare used to produce spectrum the frequency-domain and the filter spectrum.coefficients Similarly, when OSR Figure = 64.11 showsIn both the cases, ap- plyingfrequency-domain the optimal filter spectrum enhances and the SNDR filter coefficientsby 15 dB–20 when dB, OSR verifying = 64. In the both effectiveness cases, of the applyingoptimal the digital optimal filtering filter enhances technique SNDR regardless by 15 dB–20 of dB, oversampling verifying the effectivenessratios. Comparing Figuresof the 10b optimal and digital 11b leads filtering us technique to an interesting regardless ofobservation oversampling that ratios. the Comparingoptimal FIR filter Figures 10b and 11b leads us to an interesting observation that the optimal FIR filter shape shape is quite different for both cases even though they use the same passive integrator is quite different for both cases even though they use the same passive integrator model. model.This differenceThis difference stems from stems the fact from that the the optimalfact that filter the expression optimal shown filter inexpression Equation (11) shown in Equationis indeed (11) a function is indeed of the a func oversamplingtion of the ratio oversamplingM, which reassures ratio that M, the which filter coefficientsreassures that the filtermust coefficients be individually must found be individually for different oversamplingfound for different ratio. oversampling ratio.

Figure Figure10. (a) 10. Simulated(a) Simulated output output spectrum spectrum withwith the the optimal optimal filter filter (red) and(red) the and cascade-of-integrator the cascade-of-integrator (CoI) filter (blue) (CoI) when filter (blue) when oversamplingoversampling ratioratio (OSR) (OSR) = 256;= 256; (b )(b normalized) normalized coefficients coefficients of the of filter, the andfilter, (c) and the magnitude (c) the magnitude and phase and response phase of response of the filter.the filter.

x 10−2 2 20 0 SNDR = 52.7dB 0 SNDR = 77.6dB 1.6 −20 −40 −40 1.2 −60 −80 −80 0.8 200 100 0.4 0 −120 −100 0 −200 00.20.30.40.50.1 0 102030405060 10−5 10−4 10−3 10−2 10−1 100 Normalized Frequency Tap Index Normalized Freq [π rad/sample] (a) (b) (c) Figure 11. (a) Simulated output spectrum with the optimal filter (red) and the CoI filter (blue) when OSR = 65, (b) normalized coefficients of the filter, and (c) the magnitude and phase response of the filter.

It is also worth pointing out that when OSR is fixed, the optimal filter coefficients are invariant to the signal frequency used for the calibration. To experimentally prove our claim, Figure 12 shows a simulated output spectrum for three different signal fre-

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Input thermal noise of 2nd amp 15 (nV/√) G, 2 (V/V), 0.5 b1, b2 0.5, 1.72 of capacitor mismatch for C = 1 pF 0.03% of gain variation 1% Resolution of ADCres 8-bit

Figures 10 and 11 show a few snapshots of nominal simulations with OSR = 256 and OSR = 64, respectively, with no mismatch or variation parameters. In this experiment, we applied fsig = 0.028Fs when OSR = 256 and fsig = 0.084Fs when OSR = 64, respectively, as representative inputs. Figure 10a shows the frequency domain spectrum of ADC outputs for OSR = 256 when using the conventional CoI filter (shown in blue) and the proposed optimal filter (shown in red). Figure 10b graphs the optimal FIR filter coefficients that are used to produce the frequency-domain spectrum. Similarly, Figure 11 shows the frequency-domain spectrum and the filter coefficients when OSR = 64. In both cases, applying the optimal filter enhances SNDR by 15 dB–20 dB, verifying the effectiveness of the optimal digital filtering technique regardless of oversampling ratios. Comparing Figures 10b and 11b leads us to an interesting observation that the optimal FIR filter shape is quite different for both cases even though they use the same passive integrator model. This difference stems from the fact that the optimal filter expression shown in Equation (11) is indeed a function of the oversampling ratio M, which reassures that the filter coefficients must be individually found for different oversampling ratio.

Figure 10. (a) Simulated output spectrum with the optimal filter (red) and the cascade-of-integrator (CoI) filter (blue) Electronics 2021, 10, 213 12 of 14 when oversampling ratio (OSR) = 256; (b) normalized coefficients of the filter, and (c) the magnitude and phase response of the filter.

x 10−2 2 20 0 SNDR = 52.7dB 0 SNDR = 77.6dB 1.6 −20 −40 −40 1.2 −60 −80 −80 0.8 200 100 0.4 0 −120 −100 0 −200 00.20.30.40.50.1 0 102030405060 10−5 10−4 10−3 10−2 10−1 100 Normalized Frequency Tap Index Normalized Freq [π rad/sample] (a) (b) (c) Figure Figure11. (a) 11. Simulated(a) Simulated output output spectrum spectrum withwith the the optimal optimal filter filter (red) and(red) the and CoI filterthe CoI (blue) filter when (blue) OSR = when 65, (b) normalizedOSR = 65, (b) nor- malizedcoefficients coefficients of the of filter,the filter, and (c and) the ( magnitudec) the magnitude and phase and response phase of response the filter. of the filter. Electronics 2021, 10, x FOR PEER REVIEW 12 of 14 It is also worth pointing out that when OSR is fixed, the optimal filter coefficients are It is also worth pointing out that when OSR is fixed, the optimal filter coefficients invariant to the signal frequency used for the calibration. To experimentally prove our are claim,invariant Figure to 12 the shows signal a simulated frequency output used spectrum for the forcalibration. three different To experimentally signal frequen- prove sig S S, S ourquenciescies claim, (fsig ( f=Figure 0.08 = 0.08FS ,12 0.23F shows, F0.23S, andF a 0.34and simulatedFS0.34) whileF ) usingoutpwhileut the using spectrum same the filter samefor coefficients three filter different foundcoefficients from signal found fre- fromfsig f=sig 0.084 = 0.084Fs. TheFs. resultThe result shows thatshows SNDR that is universallySNDR is enhanceduniversally above enhanced 90 dB, showing above 90 dB, showingthat the that invariance the invariance of the optimal of the filter optimal coefficient filter to coefficient the signal frequency. to the signal frequency.

Figure Figure12. Simulated 12. Simulated output output spectrum spectrum when when input signal signal frequencies frequencies are ( aare) fsig (a=) 0.08 fsig F=S 0.08;(b) FfsigS; =(b 0.23) fsigF S=, and0.23 (Fc)S,f sigand= 0.34 (c) FfSsig. = 0.34FS.

ForFor extensive extensive verification, verification, we we have have perf performedormed 100100 Monte-Carlo Monte-Carlo simulations simulations for for OSR OSR = 256 with the capacitor mismatch and gain variation parameters in Table3. The = 256histogram with the in capacitor Figure 13 displaysmismatch the and distributions gain variation of SNDRs parameters with the optimal in Table filtering 3. The histogram(shown in Figure in blue) 13 and displays the CoI the filtering distributions (shown in red).of SNDRs The mean with value the ofoptimal SNDR improvesfiltering (shown in blue)from 67and dB the to 90 CoI dB, filtering demonstrating (shown that in the red) presented. The mean algorithm value can of enhanceSNDR improves the SNDR from 67 dB ofto IDSM90 dB, using demonstrating a low-power that passive the integrator presented beyond algorithm 90 dB evencan enhance under the the presence SNDR of of IDSM usingvarious a low-power component passive mismatches integrator and amplifier beyond gain 90 uncertainty. dB even under the presence of various In addition, we have designed a full transistor-level proof-of-concept design of the component mismatches and amplifier gain uncertainty. proposed ADC in the 65 nm CMOS process, where the residual ADC in Figure9 is implemented as synchronous 8-bit SAR ADC. Figure 14a shows the simulated output spectrum of the ADC after the optimal filtering. The result clearly proves that almost 20 dB of SNDR enhancement is attainable after the calibration in a full circuit simulation. In addition, the obtained weights of the decimation filter in Figure 14b are similar to those already shown in Figure 10b, indicating that the behavioral simulation matches well with transistor-level simulation. For the interest of readers, we also report that the power and area of this residual ADC is only 3% and 15% of the total power and area, respectively. Therefore, having this residual ADC does not incur substantial power and area costs.

Figure 13. Histogram of the signal-to-noise and distortion ratio (SNDR) from 100 Monte-Carlo simulations.

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quencies (fsig = 0.08FS, 0.23FS, and 0.34FS) while using the same filter coefficients found from fsig = 0.084Fs. The result shows that SNDR is universally enhanced above 90 dB, showing that the invariance of the optimal filter coefficient to the signal frequency.

Figure 12. Simulated output spectrum when input signal frequencies are (a) fsig = 0.08FS; (b) fsig = 0.23FS, and (c) fsig = 0.34FS.

For extensive verification, we have performed 100 Monte-Carlo simulations for OSR = 256 with the capacitor mismatch and gain variation parameters in Table 3. The histogram in Figure 13 displays the distributions of SNDRs with the optimal filtering (shown in blue) and the CoI filtering (shown in red). The mean value of SNDR improves from 67 dB to 90 dB, demonstrating that the presented algorithm can enhance the SNDR of IDSM Electronics 2021, 10, 213 using a low-power passive integrator beyond 90 dB even under the presence13 of 14 of various component mismatches and amplifier gain uncertainty.

Electronics 2021, 10, x FOR PEER REVIEWFigureFigure 13. 13. HistogramHistogram of of the the signal-to-noise signal-to-noise and and distortion distortion ratio (SNDR) ratio (SNDR) from 100 from Monte-Carlo 10013 ofMonte-Carlo 14 simulations.simulations.

In addition, we have designed a full transistor-level proof-of-concept design of the proposed ADC in the 65 nm CMOS process, where the residual ADC in Figure 9 is implemented as synchronous 8-bit SAR ADC. Figure 14a shows the simulated output spectrum of the ADC after the optimal filtering. The result clearly proves that almost 20 dB of SNDR enhancement is attainable after the calibration in a full circuit simulation. In addition, the obtained weights of the decimation filter in Figure 14b are similar to those already shown in Figure 10b, indicating that the behavioral simulation matches well with transistor-level simulation. For the interest of readers, we also report that the power and area of this residual ADC is only 3% and 15% of the total power and area, respectively. Therefore, having this residual ADC does not incur substantial power and area costs.FigureFigure 14.14.( (aa)) SimulatedSimulated outputoutput spectrumspectrum fromfrom transistor-leveltransistor-level circuitcircuit simulationsimulation inin 6565 nmnm comple-com- mentaryplementary metal-oxide-semiconductor metal-oxide-semiconductor (CMOS) (CMOS) model model with with the the optimal optimal filter filter (red) (red) and and the the CoI CoI filter filter (blue) when OSR = 256, and (b) the normalized coefficients of the optimal filter. (blue) when OSR = 256, and (b) the normalized coefficients of the optimal filter.

6.6. ConclusionsConclusions This paper presented an optimal digital filtering technique that enhances the SNDR This paper presented an optimal digital filtering technique that enhances the SNDR ofof incrementalincremental DSMsDSMs basedbased onon leakyleaky integrators.integrators. TheThe mainmain focusfocus ofof thisthis workwork isis toto come come upup withwith anan algorithmalgorithm thatthat findsfinds optimal optimal digital digital filter filter parameters. parameters. TheThe algorithm,algorithm, basedbased onon convexconvex optimization,optimization, providesprovides aa straightforwardstraightforwardand andpredictable predictableway way of of designing designing an an optimaloptimal digitaldigital filter filter for for IDSMs IDSMs using using a passive a pass integratorive integrator and aand low-gain a low-gain amplifier. amplifier. Based onBased a behavioral on a behavioral ADC model ADC thatmodel captures that captures fine details fine of details transistor-level of transistor-level circuits suchcircuits as gainsuch nonlinearity as gain nonlinearity and thermal and noise,thermal comprehensive noise, comprehensive behavioral behavi simulationsoral simulations confirm thatcon- thefirm proposed that the algorithmproposed isalgorithm quite effective is quite in ef enhancingfective in SNDR enhancing of the SNDR entire of A/D the conversion entire A/D beyondconversion 90 dB beyond despite 90 usingdB despite a passive using integrator. a passive Theintegrator. technique The presentedtechnique inpresented this work in isthis highly work digital is highly in nature, digital and in thereforenature, and can therefore be a favorable can be approach a favorable when approach one wants when to designone wants high-resolution to design ultra-low-powerhigh-resolution ultra-low-power sensor ADCs in highlysensor scaled ADCs CMOS in highly technology scaled whereCMOS designing technology high-gain where designing op-amps arehigh-gain costly inop-amps terms of are power costly and in area.terms of power and area.

Author Contributions: Conceptualization, H.P. and J.K.; validation, H.P.; writing—original draft preparation, H.P.; writing—review and editing, H.C. and J.K.; supervision, J.K. funding acquisition, J.K. All authors have read and agreed to the published version of the manuscript. Funding: This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF), funded by the Ministry of Education (2020R1F1A1067414), by Ministry of Science and ICT(2020M3F3A2A01085756), the Samsung Future Interconnect Tech- nology (FIT), and the Industrial Innovation Technology Future Semiconductor Project (10080611) of the Ministry of Industry and Commerce. Data Availability Statement: The data presented in this study are available on request from the corresponding author. The data are not publicly available due to the format incompatibility. Acknowledgments: We acknowledge IDEC, KAIST for supporting the CAD tools. Conflicts of Interest: The authors declare no conflicts of interest.

References 1. Miyahara, M.; Matsuzawa, A. An 84 dB dynamic range 62.5–625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier. In Proceedings of the 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 30 April–3 May 2017; Institute of Electrical and Electronics Engineers (IEEE): New York, NY, USA, 2017; pp. 1–4. 2. Chen, F.; Leung, B. A 0.25-mW low-pass passive sigma-delta modulator with built-in mixer for a 10-MHz IF input. IEEE J. Solid-State Circuits 1997, 32, 774–782, doi:10.1109/4.585244. 3. Chen, F.; Ramaswamy, S.; Bakkaloglu, B. A 1.5V 1mA 80dB passive ΣΔ ADC in 0.13μm digital CMOS process. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 13 February 2003, pp. 1–2.

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Author Contributions: Conceptualization, H.P. and J.K.; validation, H.P.; writing—original draft preparation, H.P.; writing—review and editing, H.C. and J.K.; supervision, J.K. funding acquisition, J.K. All authors have read and agreed to the published version of the manuscript. Funding: This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF), funded by the Ministry of Education (2020R1F1A1067414), by Ministry of Science and ICT(2020M3F3A2A01085756), the Samsung Future Interconnect Technology (FIT), and the Industrial Innovation Technology Future Semiconductor Project (10080611) of the Ministry of Industry and Commerce. Data Availability Statement: The data presented in this study are available on request from the corresponding author. The data are not publicly available due to the format incompatibility. Acknowledgments: We acknowledge IDEC, KAIST for supporting the CAD tools. Conﬂicts of Interest: The authors declare no conﬂict of interest.

References 1. Miyahara, M.; Matsuzawa, A. An 84 dB dynamic range 62.5–625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier. In Proceedings of the 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 30 April–3 May 2017; Institute of Electrical and Electronics Engineers (IEEE): New York, NY, USA, 2017; pp. 1–4. 2. Chen, F.; Leung, B. A 0.25-mW low-pass passive sigma-delta modulator with built-in mixer for a 10-MHz IF input. IEEE J. Solid-State Circuits 1997, 32, 774–782. [CrossRef] 3. Chen, F.; Ramaswamy, S.; Bakkaloglu, B. A 1.5V 1mA 80dB passive Σ∆ ADC in 0.13 µm digital CMOS process. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 13 February 2003; pp. 1–2. 4. Yeknami, A.F.; Qazi, F.; Alvandpour, A. Low-Power DT ∆Σ modulators using SC passive filters in 65 nm CMOS. IEEE Trans. Circuits Syst. I Reg. Papers 2014, 61, 358–370. [CrossRef] 5. Qazi, F.; D ˛abrowski, J.J. Passive SC Sigma Delta Modulators Revisited: Analysis and Design Study. IEEE J. Emerg. Sel. Top. Circuits Syst. 2015, 5, 624–637. [CrossRef] 6. Das, A.; Hezar, R.; Byrd, R.; Gomez, G.; Haroun, B. A 4th-order 86 dB CT ∆Σ ADC with two amplifier in 90 nm CMOS. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 10 February 2005; pp. 496–498. 7. Song, T.; Cao, Z.; Yan, S. A 2.7-mW 2-MHz continuous-time Σ∆ modulator with a hybrid active–passive loop filter. IEEE J. Solid-State Circuits 2008, 43, 330–341. [CrossRef] 8. Yousry, R.; Hegazi, E.; Ragai, H.F. A third-order 9-bit 10-MHz CMOS ∆Σ modulator with one active stage. IEEE Trans. Circuits Syst. I Reg. Papers 2008, 55, 2469–2482. [CrossRef] 9. Yeknami, A.F.; Alvandpour, A. A 0.7-V 400-nW fourth-order active-passive ∆Σ modulator with one active stage. In Proceedings of the International Conference on Very Large Scale Integration, VLSI-SoC, Istanbul, Turkey, 7–9 October 2013; pp. 1–6. 10. Nowacki, B.; Paulino, N.; Goes, J. A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT ∆ΣM. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 31 January—4 February 2016; pp. 274–275. 11. Hussain, A.; Sin, S.; Chan, C.; Maloberti, F.; Martins, R.P. Active–passive ∆Σ modulator for high-resolution and low-power Applications. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2017, 25, 364–374. [CrossRef] 12. Agah, A.; Vleugels, K.; Griffin, P.B.; Ronaghi, M.; Plummer, J.D.; Wooley, B.A. A high-resolution low-power incremental Σ∆ ADC with extended range for biosensor arrays. IEEE J. Solid-State Circuits 2010, 45, 1099–1110. [CrossRef] 13. Zhang, Y.; Chen, C.-H.; He, T.; Temes, G.C. A 16 b Multi-Step Incremental Analog-to-Digital Converter with Single-Opamp Multi-Slope Extended Counting. IEEE J. Solid-State Circuits 2017, 52, 1066–1076. [CrossRef] 14. Grant, M.; Boyd, S.; Ye, Y. CVX: Matlab Software for Disciplined Convex Programming, Version 2.1. Available online: http: //cvxr.com/cvx (accessed on 21 August 2020). 15. CppSim System Simulator. Available online: http://cppsim.com (accessed on 25 July 2020). 16. Kavusi, S.; Kakavand, H.; Gamal, A. On incremental sigma-delta modulation with optimal filtering. IEEE Trans. Circuits Syst. I Regul. Pap. 2006, 53, 1004–1015. [CrossRef] 17. Maréchal, S.; Krummenacher, F.; Kayal, M. Optimal filtering of an incremental second-order MASH11 sigma-delta modulator. In Proceedings of the 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, Beirut, Lebanon, 11–14 December 2011; pp. 240–243. 18. Steensgaard, J.; Zhang, Z.; Yu, W.; Sarhegyi, A.; Lucchese, L.; Kim, D.-I.; Temes, G.C. Noise–Power Optimization of Incremental Data Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 2008, 55, 1289–1296. [CrossRef] 19. Wang, B.; Law, M.-K.; Ali, S.Q.; Bermak, A. Near-Optimal Decoding of Incremental Delta-Sigma ADC Output. IEEE Trans. Circuits Syst. I Regul. Pap. 2020, 67, 3670–3680. [CrossRef]