Experience With the i860®

John B. Casey Vice President Technology

Kenneth R. Aupperle President Hauppauge Computer Works, Inc. 91 Cabot Court Hauppauge, New York 11788 (516) 434-1600

Hauppauge Computer Works, Inc.

Agenda

Why Couple the i860 and the ®?

Hardware Requirements

Software Requirements

Customer Application Experience

Ideas for the Future

Summary

Hauppauge Computer Works, Inc. Why Couple the i860 and the i486? Minicomputer applications moving down May have used array processor with the minicomputer Continued to do so in the PC implementation Hardware too costly for broad market appeal PC-type busses create performance bottlenecks Need more integration for higher performance and lower cost PC applications moving up Developed an appetite for floating point Possibly used a math coprocessor Now running out of horsepower Need high-performance numerics

Hauppauge Computer Works, Inc.

Some Actual Applications in the Image Processing Area

Screening Pap Smears for Pre-cancerous Cells

Printed Circuit Board Inspection

Low-end CAT scan (Computerized Axial Tomography)

Hauppauge Computer Works, Inc. Some Actual Applications in non-Imaging Areas

Multi-axis robotic arm positioning system

Real-time quality control of hot-rolled steel

Neural-network processing of video data

Oil-field data analysis

General-purpose vector processing

: Hauppauge Computer Works, Inc.

Hardware Requirements

Viable Stand-Alone i486 Product Implies low-cost infrastructure to support 1860 Memory System Wide range of sizes, including LARGE Flexible sharing scheme Application Freedom Many configurations possible

Hauppauge Computer Works, Inc. Original Hauppauge 4860® Block Diagram

-- " 0 I , - ----r------

------...:---1

.. -.. ----. --.---__; Ｎ｟ｾ｟ｃＺＺＺＺ］］］Ｎｊ ----______l- ｾ｟

.. --- ·_---- .. ＭＭＭＭｉＭＭＭＭＺＭＭＭＮＮＮＮＮＮＮＬＮＭＭＭＭＭＭＭｾＭ ---- .. ------.. -,------.. --.. ＭＭＭＭﾷ｟ＮｔＭＭＭＭＭＭＭＭＭＺＭＭＭＭＭＭＭＺＭﾷＭＭＮＭ［ｾ｟ ＭＭＭＭｾＭＭＮＭＮ - ... ｾＭＭ

_. _. - - . j _h · • • ｾ l . __ m • __ ....- ---_.__ .._--_.------7 Hauppauge Computer Works, Inc.

Providing Low-cost Support for i486 and i860 Processors

Support i486 IIBurst Modell for Cache Fills 1-clock bursts Imply a 64-blt physical DRAM system, with 2-way Interleaving as seen by the 1486

• i860 Requires 64-bit DRAM system.

64-bit Slot for local-bus expansion Memory expansion, video card, supports "master-mode"

Standard I/O SUbsystem for Economy EISA Bus using commercial chip set Bus folding buffers already exist, due to support of 1486 bursts

Hauppauge Computer Works, Inc. 32/64-bit Bus Structure

Ｍ］］Ｍｾ Ｍ］］Ｍｾ 32-BIT HIGH III ｾｾｾ III EISA SIMM BANK I/O BANK 32 32 /

32 DO .. 31 DO,,63 i860

Hauppauge Computer Works, Inc.

Providing a Wide Range of Memory Sizes

64-bit bus would require a minimum of 8 traditional"x9" SIMMs Too much real estate, not enough range, only 3 sizes possible Use 1 - 4 pairs of 36-blt JEDEC-standard SIMM modules Allows from 2 to 64 Megabytes of DRAM on the MotherBoard

Providing for Flexible Sharing of Memory

Applications demand many options: Privacy, sharing, write protect, etc. ｕｾ･ a very fast SRAM for address decode, this allows for dynamic configuration

It Hauppauge Computer Works, Inc. Providing for Cache Coherency of Shared Data

Additional complication when sharing: 1486 snoops bus for cache coherency, 1860 does not Configure shared area as cached for 1486, not cached for i860

Memory Map Scheme as Seen by Software

Distinct attributes for each 32K of each processor's address space Read/Write --- Read Only Cacheable --- Not Cacheable Fast DRAM -- Slow DRAM DRAM Enabled - No DRAM (usually I/O system) Select SIMM Module Pair 0/1/2/3, Front/Back Allows flexibility In sharing, exclusion, cache strategy, etc.

Hauppauge Computer Works, Inc.

Mapping SRAM Diagram

Front -64M < ADDRESS < 64M and BO-ck of 8 486/860 / 3 SIMM Modules 8K X 8 ..SELECT-...... A15 .. 25 12 nS Decode \JRITE PROTECT SRAM DRAM SPEED A31 ENABLE CACHE Cache Enable DRAM and CAS Control Circuit

/2.. Hauppauge Computer Works, Inc. Application Freedom Complete Symmetry in Memory Access • 1486 and 1860 have common page table formats, no extra work needed here

The 1860 has no I/O Instructions • Dedicate an address range to I/O cycles, 1860 access to C2000000-C200FFFF

Both processors have local caches, both will signal "bus requestll when in HOLD, I/O system issues HRQ when DMA Is desired • One PLD acts as a programmable central arbiter

Either processor may need to handle Interrupts • Design 1860 Interrupt control PLD, I/O system hangs off one chain, software-Initiated cross-processor interrupts also Implemented

/,3 Hauppauge Computer Works, Inc.

Bus Arbitration PLD Diagram

Priority Select (Fror1 Configura.tion Register) 12 L 64-Bit jREQUEST----+ , HOLD} i486 SLOT1AcK ｾ ,L GRANT L EISA{HOLD ｾ , HOLD} I/O SLO\J ｈｏｓｔｾ BUS ,L GRANT ;860 i486 jREQUEST----+ ARBITER lACK ｾ PLD l HC\J HOLD i860{REQUEST ----+ ｾ ACK ｾ , CPU MISS PLOCK ｾ LOCK ｾ T CLOCK

1-1 Hauppauge Computer Works, Inc. Interrupt Control System Diagram

i860

ATTN ＭＭＭＭｾＭ TIMER 860 1860 1486 1..__-+---tI INTERRUPT PARITY INTERRUPT CONTROLLER ERROR CONTROLLER ｌＮＭ｟ＭＭｉＭＭＭｾ 64 - BI T SLOT ATTN 486

EISA I/O SYSTEM

Hauppauge Computer Works, Inc.

Software Requirements

i486 Systems using the i860 as an Applications Accelerator Program runs on 1860, uses 1486 for I/O processing May Involve Intel's APX860 kernel for portability, ease of use Program runs on 1486, uses 1860 for compute-intensive tasks Typically requires custom programming, IIRemote Procedure Calill model Stand-alone i860 Typically running UNIX860 Possible use of 1486 to run a liDOS Window·

If, Hauppauge Computer Works, Inc. APX860 System Configuration -host version currently available from Hauppauge, DOS-host version under development -- f USER ｾｏｆｔｗ ARE

486 UNIX PROCESS I 860 SBS-COMPLIANT ) : PROCESS ) ( - I - {ABI UNIX 386 )', SBS

(DEVICE-t--_...., APX I DRIVERS I I EISA 64-Bit I/O i860 FRAME SYSTEM BUFFER

/7 Hauppauge Computer Works, Inc.

UNIX860 System Configuration Under development, not yet commercially available - shown running with 54-bit Frame Buffer and )(Windows at Unlforum In January 1990 - - USER SOFTWARE I J I 8088 DOS I I 860 UNIX PROCESS I PROGRAMS I ( J ./ - T X1 DOS ABI / COMPATIBILITY / X WINDOWS SOFTWARE II

UNIX 860 I I EISA 64-Bit I/O FRAME MBA SYSTEM i860 BUFFER

Hauppauge Computer Works, Inc. Customer Application Experience Implemented with PC and Array Processor

VIDEO DEDICATED VIDEO SIGNAL NEURO- INPUT PROCESSOR COMPUTER APPLICATION

HI-RES MONITOR RAM INTERFACE CPU ARRAY CARD PROCESSOR

16-BIT ISA [PCI ATJ BUS

OPTICAL DISK LAN DISK INTERFACE RAM INTERFACE INTERFACE

/9 .

Customer Application Experience Implemented on Hauppauge 4860

VIDEO VIDEO SIGNAL INPUT PROCESSOR

24 MB RAM i860

INTERFACE CARD 64-BIT SYSTEM BUS

EISA BUS CONTROLLER

16/32-BIT EISA BUS

OPTICAL DISK LAN DISK INTERFACE INTERFACE INTERFACE

Hauppauge Computer Works, Inc. Ideas for Future Development

Alliant/lntel PAX-compatibility plug-in module Gives the 1860 something to talk to in the Weitek socket Implements single-CPU version of Concurrency Control

64-bit RAM card - probably 64/256 Megabyte

Master-mode MUltiprocessor plug-in card for 64-bit slot

';2.1 Hauppauge Computer Works, Inc.

Working with the i860 Summary

Highlights Areas of compatibility between 1486 and 1860, such as page tabl'!s, data formats, address range Attractive balance of Integer/floating point power

Lowlights 1860 signal timing Is not as tight as the 1486, resulting In less margin and harder design Chip bugs In early versions of 1860 (details are not for group discussion)

22. Hauppauge Computer Works, Inc.