Jetic Gū 2020 Fall Semester (S3) Overview

CSCI 150 18.11.20 12:00 Introduction to Digital and Computer System Design Lecture 5: Registers I

• Focus: Fundamentals of Complex Digital Circuit Design • Architecture: von Neumann • Textbook v4: Ch7 7.1 7.2; v5: Ch6 6.1 6.2 • Core Ideas:

1. What are Registers

2. Register Transferring Operations and Circuit P0 Review Sequential Circuits

• Synchronous Sequential Circuit Signals arrive at discrete instants of time, n Your Favourite m Inputs Combinational Outputs outputs at next time step Circuit • Has Clock

200 CHAPTER 4 / SEQUENTIAL CIRCUITS Asynchronous Sequential Circuit • Statet Statet + 1 Inputs Outputs Signals arrive at any instant of time, Combinational outputs when ready circuit StorageFlip-flops Unit Clock pulses

• May not have Clock Clock (a) Block diagram

(b) Timing diagram of clock pulses FIGURE 4-3 Review Synchronous Clocked Sequential Circuit

the clock pulses are applied with other signals that specify the required change in the storage elements. The outputs of storage elements can change their value only in the presence of clock pulses. Synchronous sequential circuits that use clock pulses as inputs for storage elements are called clocked sequential circuits. These are the types of circuits most frequently encountered in practice, since they operate correctly in spite of wide differences in circuit delays and are relatively easy to design. The storage elements used in the simplest form of clocked sequential circuits are called !ip- !ops. For simplicity, assume circuits with a single clock signal. A !ip- !op is a binary storage device capable of storing one bit of information and hav- ing timing characteristics to be de"ned in Section 4-9. The block diagram of a synchronous clocked sequential circuit is shown in Figure 4-3. The !ip- !ops receive their inputs from the combinational circuit and also from a clock signal with pulses that occur at "xed intervals of time, as shown in the timing diagram. The !ip- !ops can change state only in response to a clock pulse. For a synchronous operation, when a clock pulse is absent, the !ip- !op outputs cannot change even if the outputs of the combinational circuit driving their inputs change in value. Thus, the feedback loops shown in the "gure between the combinational logic and the ! ip- !ops are broken. As a result, a transition from one state to the other occurs only at "xed time intervals dictated by the clock pulses, giving synchronous operation. The sequential circuit outputs are shown as outputs of the combinational circuit. This is valid even when some sequential circuit outputs are actually the !ip- !op outputs. In this case, the combinational circuit part between the !ip- !op outputs and the sequential circuit outputs consists of connections only. A !ip- !op has one or two outputs, one for the normal value of the bit stored and an optional one for the complemented value of the bit stored. Binary information can enter a !ip- !op in a variety of ways, a fact that gives rise to different types of !ip- !ops. Our focus will be on the most prevalent type used today, the D !ip- !op. Other !ip- !op types, such as the JK and T !ip- !ops, are described in the online mate- rial available at the Companion Website. In preparation for studying !ip- !ops and their operation, necessary groundwork is presented in the next section on latches, from which the !ip- !ops are constructed.

M04_MANO0637_05_SE_C04.indd 200 23/01/15 1:54 PM P1 Registers

What are Registers? Deﬁnitions; Register Loading; Parallel Loading

Summary P1 Registers Computer

CPU

Control Unit 200 CHAPTER 4 / SEQUENTIAL CIRCUITS Input/Output Memory Inputs devices Outputs Combinational circuit Flip-flops Datapath Clock pulses

(a) Block diagramClock

(b) Timing diagram of clock pulses also called arithmetic unit, logical unit, etc. FIGURE 4-3 Synchronous Clocked Sequential Circuit

the clock pulses are applied with other signals that specify the required change in the storage elements. The outputs of storage elements can change their value only in the presence of clock pulses. Synchronous sequential circuits that use clock pulses as 1. Voninputs Neumann for storage Architecture elements are called clocked sequential circuits. These are the types Review of circuits most frequently encountered in practice, since they operate correctly in spite of wide differences in circuit delays and are relatively easy to design. The storage elements used in the simplest form of clocked sequential circuits are called !ip- !ops. For simplicity, assume circuits with a single clock signal. A !ip- !op is a binary storage device capable of storing one bit of information and hav- ing timing characteristics to be de"ned in Section 4-9. The block diagram of a synchronous clocked sequential circuit is shown in Figure 4-3. The !ip- !ops receive their inputs from the combinational circuit and also from a clock signal with pulses that occur at "xed intervals of time, as shown in the timing diagram. The !ip- !ops can change state only in response to a clock pulse. For a synchronous operation, when a clock pulse is absent, the !ip- !op outputs cannot change even if the outputs of the combinational circuit driving their inputs change in value. Thus, the feedback loops shown in the "gure between the combinational logic and the ! ip- !ops are broken. As a result, a transition from one state to the other occurs only at "xed time intervals dictated by the clock pulses, giving synchronous operation. The sequential circuit outputs are shown as outputs of the combinational circuit. This is valid even when some sequential circuit outputs are actually the !ip- !op outputs. In this case, the combinational circuit part between the !ip- !op outputs and the sequential circuit outputs consists of connections only. A !ip- !op has one or two outputs, one for the normal value of the bit stored and an optional one for the complemented value of the bit stored. Binary information can enter a !ip- !op in a variety of ways, a fact that gives rise to different types of !ip- !ops. Our focus will be on the most prevalent type used today, the D !ip- !op. Other !ip- !op types, such as the JK and T !ip- !ops, are described in the online mate- rial available at the Companion Website. In preparation for studying !ip- !ops and their operation, necessary groundwork is presented in the next section on latches, from which the !ip- !ops are constructed.

M04_MANO0637_05_SE_C04.indd 200 23/01/15 1:54 PM P1 Registers Computer A very rough example

Calculate 1+1: CPU M1: 1 (00000001) T1 CPU exe. X1: 1 (00010001) M2: 1 (00000001) T2 X2: 1 (00100001) Control M3: 2 (00000010) T3 X3: X1+X2 (01110110) Unit 200 CHAPTER 4 / SEQUENTIAL CIRCUITS Input/Output Memory Inputs devices Outputs Combinational circuit Flip-flops Datapath Clock pulses

(a) Block diagram Clock 1+1=2 T1 T2 T3 (b) Timing diagram of clock pulses also called arithmetic unit, logical unit, etc. FIGURE 4-3 Synchronous Clocked Sequential Circuit

the clock pulses are applied with other signals that specify the required change in the storage elements. The outputs of storage elements can change their value only in the presence of clock pulses. Synchronous sequential circuits that use clock pulses as 1. Voninputs Neumann for storage Architecture elements are called clocked sequential circuits. These are the types Review of circuits most frequently encountered in practice, since they operate correctly in spite of wide differences in circuit delays and are relatively easy to design. The storage elements used in the simplest form of clocked sequential circuits are called !ip- !ops. For simplicity, assume circuits with a single clock signal. A !ip- !op is a binary storage device capable of storing one bit of information and hav- ing timing characteristics to be de"ned in Section 4-9. The block diagram of a synchronous clocked sequential circuit is shown in Figure 4-3. The !ip- !ops receive their inputs from the combinational circuit and also from a clock signal with pulses that occur at "xed intervals of time, as shown in the timing diagram. The !ip- !ops can change state only in response to a clock pulse. For a synchronous operation, when a clock pulse is absent, the !ip- !op outputs cannot change even if the outputs of the combinational circuit driving their inputs change in value. Thus, the feedback loops shown in the "gure between the combinational logic and the ! ip- !ops are broken. As a result, a transition from one state to the other occurs only at "xed time intervals dictated by the clock pulses, giving synchronous operation. The sequential circuit outputs are shown as outputs of the combinational circuit. This is valid even when some sequential circuit outputs are actually the !ip- !op outputs. In this case, the combinational circuit part between the !ip- !op outputs and the sequential circuit outputs consists of connections only. A !ip- !op has one or two outputs, one for the normal value of the bit stored and an optional one for the complemented value of the bit stored. Binary information can enter a !ip- !op in a variety of ways, a fact that gives rise to different types of !ip- !ops. Our focus will be on the most prevalent type used today, the D !ip- !op. Other !ip- !op types, such as the JK and T !ip- !ops, are described in the online mate- rial available at the Companion Website. In preparation for studying !ip- !ops and their operation, necessary groundwork is presented in the next section on latches, from which the !ip- !ops are constructed.

M04_MANO0637_05_SE_C04.indd 200 23/01/15 1:54 PM P1 Registers von Neumann CPU

• Control Unit • Determine sequence of data-processing operations performed by the datapath

• Datapath

• Processing logic units: Adder, Subtractor, Shifter, Counter, etc.

• Registers: Storage of temporary information, basic components of the digital system

Concept 6-1 / Registers and Load Enable 325 P1 Registers Register D0 D Q0

Clock C

Clear R REG

D1 D Q1 Clear C • n-bit register: uses n ﬂip-ﬂops D0 Q0 R stores n bits of information D1 Q1 D2 Q2 D D Q 2 2 D3 Q3 C (b) Symbol R

Load C inputs (clock inputs Clock of flip-flops) D3 D Q3 (c) Load control input Concept C

(a) Logic diagram

Clock

Load

C inputs

(d) Timing diagram

FIGURE 6-1 4-Bit Register

Register with Parallel Load Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all !ip-!ops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM 6-1 / Registers and Load Enable 325 6-1 / Registers and Load Enable 325 P1 Registers Register D0 D Q0 D0 D Q0 Clock C

Clock C Clear R REG Clear R D1 D Q1 Clear REG C D0 Q0 D1 D Q1 R • -bit register: uses flip-flops D1 Q1 n n Clear D Q C 2 2 stores bits of information D D Q n D0 Q0 2 2 D3 Q3 R D Q C 1 1 (b) Symbol An array of flip-flops with R • D D2 Q2 Load C inputs (clock inputs D2 resetD Q2 D Q 3 3 Clock of flip-flops) D3 D Q3 C (c) Load control input (b) Symbol C R R

Load C inputs (clock inputs of flip-flops) (a) Logic diagram D D Q Clock 3 3 Concept (c) Load control input Clock C

R Load

C inputs (a) Logic diagram (d) Timing diagram

Clock FIGURE 6-1 4-Bit Register

Load Register with Parallel Load Most digital systems have a master clock generator that supplies a continuous train C inputs of clock pulses. The pulses are applied to all !ip-!ops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching (d) Timing diagram the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock FIGURE 6-1 pulses are to have an effect on the register. The clock pulses are prevented from 4-Bit Register reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in Register with Parallel Load Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all !ip-!ops and registers in the system. In effect, the master clock acts like a heart that supplies a constantM06_MANO0637_05_SE_C06.indd beat to all parts 325 of 21/01/15 9:49 AM the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM 6-1 / Registers and Load Enable 325 6-1 / Registers and Load Enable 325 P1 Registers Register D0 D Q0 D0 D Q0 Clock C

Clock C Clear R REG Clear R D1 D Q1 Clear REG C • n-bit register: uses n flip-flops D0 Q0 D1 D Q1 R stores bits of information D1 Q1 n Clear D Q C 2 2 D D Q D0 Q0 2 2 D3 Q3 • An arrayR of flip-flops with D Q C D 1 1 (b) Symbol reset R D2 Q2 Load C inputs (clock inputs D2 D Q2 D Q 3 3 Clock of flip-flops) Clear: set register to all s D3 D Q3 • C 0 (c) Load control input (b) Symbol C R R

Load C inputs (clock inputs of flip-flops) (a) Logic diagram D D Q Clock 3 3 Concept (c) Load control input Clock C

R Load

C inputs (a) Logic diagram (d) Timing diagram

Clock FIGURE 6-1 4-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM 6-1 / Registers and Load Enable 325 P1 Registers Register D0 D Q0

Clock C

• n-bit register: Clearuses n flip-flops R stores bits of information REG n Clock D1 D Q1 Clear An array of flip-flops with C • D D0 Q0 reset R D1 Q1

D2 Q2 Clear: set registerD to all s D Q • 2 0 2 D3 Q3 C • Loading: set register to D (b) Symbol 3:0 R Triggered by Load or Clock Load C inputs (clock inputs Clock of flip-flops) D3 D Q3 (c) Load control input Concept C

(a) Logic diagram

Clock

Load

C inputs

(d) Timing diagram

FIGURE 6-1 4-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM 6-1 / Registers and Load Enable 325

D0 D Q0

Clock C

R P1 Clear Registers Register Operations REG D1 D Q1 Clock 6-1 / RegistersClear and Load Enable 325 C D0 Q0 R D Q D0 D Q0 1 1

D2 Q2 Clock C D D Q • All registers are most likely wired2 to one Clock 2 D3 Q3 R Clear C (b)REG Symbol • Loading a register: assigning new values to Rall n-bits of a register D1 D Q1 Load Clear C inputs (clock inputs Clearing a register: change all -bits of a registerC to s Clock of flip-flops) • D3 n D Q03 D0 Q0 R (c) Load control input C D1 Q1

D2 Q2 R D D Q 2 2 D3 Q3 C (a) Logic diagram (b) SymbolConcept R Clock Load C inputs (clock inputs Clock of flip-flops) D3 D Q3 Load (c) Load control input C

C inputs R

(d) Timing diagram (a) Logic diagram FIGURE 6-1 Clock 4-Bit Register

Most digitalC inputssystems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all !ip-!ops and registers in the system. In effect, the master clock acts like (ad )heartTimin gthat diag ramsupplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents FIGURE of 6-1the register are to be left unchanged. Thus, a separate control signal is used4-Bit to control Register the clock cycles during which clock pulses are to have an effect on the register. The clock pulses are prevented from Registerreaching the with register Parallel when Load its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in Most digital systems have a master clock generator that supplies a continuous train of clock pulses. The pulses are applied to all !ip-!ops and registers in the system. In effect, the master clock acts like a heart that supplies a constant beat to all parts of the system. For the design in Figure 6-1(a), the clock can be prevented from reaching the clock input to the circuit if the contents of the register are to be left unchanged. Thus, a separate control signal is used to control the clock cycles during which clock M06_MANO0637_05_SE_C06.inddpulses are 325 to have an effect on the register. The clock pulses are prevented from 21/01/15 9:49 AM reaching the register when its content is not to be changed. This approach can be implemented with a load control input Load combined with the clock, as shown in

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM P1 What if we don’t want6-1 to / Registers and Load Enable 325 Registers change the value of a register? D0 D Q0

Clock C

• Clock: generates a constantClear train of pulsesR triggering the C of each registers En REG D D Q 1 1CLK Clock gating (Bad Idea) Clear • C D0 Q0 R • Adding an Enabler to each C of each register D1 Q1

D2 Q2 D D Q • Bad idea: leads to diﬀerent2 propagation delay 2 D3 Q3 between the CLK and the Input D C (b) Symbol R

Load C inputs (clock inputs Clock of flip-flops) D3 D Q3 Concept (c) Load control input C

(a) Logic diagram

Clock

Load

C inputs

(d) Timing diagram

FIGURE 6-1 4-Bit Register

M06_MANO0637_05_SE_C06.indd 325 21/01/15 9:49 AM 6-2 / Register Transfers 327

P1 What if we don’t want to Registers change the value of a register?

EN D Q • Clock: generates a constant train of pulses D triggeringD the C of each registers EN C C D Flip-flop with enable C 6-2 / Register Transfers 327 • Use D ﬂip-ﬂops with built-in Enabler (Correct!) (a) (b) • The CLK goes directly to C

D0 D Q0 Input combined with signal • D EN ENEN D Q Ensure same propagation delay design D D C EN Why can’t we use a regular enabler at ? C C D D Flip-flop with enable C

(a) (b) D1 D Q1 Concept EN C D0 D Q0 EN C

D2 D Q2 D EN 1 D Q1 C EN C

D3 D Q3 D2 D Q2 Load EN EN Clock C C

FIGURE 6-2 4-Bit Register with Parallel Load done simultaneously for all four bits during a single positive pulse transition. This method of transfer is traditionally preferred over clock gating, since it avoids clock skew and the potential for malfunctionsdone simultaneously of the circuit.for all four bits during a single positive pulse transition. This method of transfer is traditionally preferred over clock gating, since it avoids clock skew and the potential for malfunctions of the circuit. 6-2 REGISTER TRANSFERS 6-2 REGISTER TRANSFERS A digital system is a sequential circuit made up of interconnected !ip-!ops and gates. A digital system is a sequential circuit made up of interconnected !ip-!ops and gates. In Chapter 4, we learned that Insequential Chapter 4, circuitswe learned can that be sequential speci"ed circuits by means can be ofspeci state"ed by means of state tables. To specify a large digitaltables. system To specifywith state a large tables digital is system very withdif" statecult, tables if not is imposvery dif-"cult, if not impos- sible, because the number of statessible, becauseis prohibitively the number large. of states To is overcome prohibitively this large. dif To"culty, overcome this dif"culty, digital systems are designed usingdigital a systems modular, are designedhierarchical using aapproach. modular, hierarchical The system approach. is The system is partitioned into subsystems orpartitioned modules, into each subsystems of which or modules, performs each some of which functional performs some functional task. The modules are constructed hierarchically from functional blocks such as reg- task. The modules are constructedisters, hierarchically counters, decoders, from multiplexers, functional buses, blocks arithmetic such as elements, reg- !ip-!ops, and isters, counters, decoders, multiplexers,primitive gates. buses, The various arithmetic subsystems elements, communicate !ip-! withops, data and and control signals primitive gates. The various subsystemsto form a digital communicate system. with data and control signals to form a digital system. In most digital system designs, we partition the system into two types of modules: a datapath, which performs data-processing operations, and a control unit, In most digital system designs, we partition the system into two types of modules: a datapath, which performs data-processing operations, and a control unit,

M06_MANO0637_05_SE_C06.indd 327 21/01/15 9:49 AM

M06_MANO0637_05_SE_C06.indd 327 21/01/15 9:49 AM P1 Registers Registers

• What is a register? • Basic Functions of a single Register

• Loading: set values to input

• Clearing: set values to 0

• Enabling: preserving existing values

Review P2 Example

x86 Registers And how addition is performed on your Computer CPU

Summary P2 Common CPU Processor Example Architectures

• These are all von Neumann architecture designs • X86 architecture (Intel CPUs, AMD CPUs) • X86-64 architecture (64bit version of X86) • ARM (iPhone, iPad, most Android devices) • MIPS (Others, including instructional)

Concept P2 Example X86 CPU Registers Intel 8086 CPU REG AX These registers are located on the CPU chips (in Datapath) D • REG BXQ D REG CXQ 8 GPRs, D REG DXQ • 8 General-Purpose Registers (GPRs) 6 Seg Regs, D 1 Flag Reg, Q …… 1 Instruc. Reg • AX: Accumulator register. Used in arithmetic operations

• BX: Base register. Used as a pointer to data

• CX: Counter register. Used in shift/rotate instructions and loops.

• DX: Data register. Used in arithmetic operations and I/O operations. • ……

Concept P2 Example X86 Addition Assembly Hardware Language • 12 + 35

Uses AX, BX: Cleared to 0 REG AX • 002Fh000Ch D Q 0000h002Fh000Ch 1. Load AXAX withwith 1212 (000Ch) MOV AX, 000Ch REG BX 0023h D Q 0000h0023h 2. Load BXBX withwith 3535 (0023h) MOV BX, 0023h

Adder- ADD AX, BX 002Fh 3. Perform additionAdd with with Adder- Adder- Subtractor Subtractor, storeLoad resultresult into AXAX

Demo P2 Example Datapath and Control Unit

• Control Unit at each time step, provide • Operation Code e.g. mov (66b8, etc.), add (6601, etc.)

• Parameters e.g. ax, bx, 12, 35

• Datapath • Select Register for Input and Output (Multiplexer) • Feed input into Register or Functional Blocks (Adder-Subtractor)

Concept P2 Example Datapath and Control Unit Red: Address Control Unit Green: Mode (CU) 1. ALU connected to Reg for 1st input

Datapath 4 2. ALU connected to Reg for 2nd input Register Array (Reg) 6 REG AX 1 3. connected to to store result D ALU Reg REG BXQ D REG CXQ D Adder- 4. CU tells ALU which register to take as 1st input REG DXQ D Subtractor Q (ALU) …… 5 5. CU tells ALU which register to take as 2st input 2 6. CU tells ALU which operation to do 7 Dec 3 7. CU tells which Reg to store result in Using decoder and EN on each Register

Concept P3 Transferring

Summary P3 Transferring Register Operations

• Movement of data stored in registers and Processing performed on the data • Components • set of registers in the system • operations performed on the data • control that supervises the sequence of operations in the system

Concept P3 Transferring Microoperation

• Microoperation: An elementary operation performed on data stored in registers

• Single Register (Transfer Operations): load, clear, shift, count, etc.

• Multiple Registers: add, subtract, etc.

Concept P3 Transferring Register Transfer VHDL

Operator Example Operator Example

Assignment <= ax <= 12h Bitwise AND and ax and bx

Reg. Transfer <= ax <= bx Bitwise OR or ax or bx

Addition + ax + bx Bitwise NOT not not ax

Subtration - ax - bx Bitwise XOR xor ax xor bx

Shift Left sll ax sll 2 Vectors ax(3 down to 0) ax(3 down to 0)

ax(7 down to 4) Shift Right srl ax srl 2 Concatenate & &ax(3 down to 0)

Concept P3 Transferring Register Transfer VHDL

1) ax <= 12 2) bx <= 18 3) cx <= ax + bx 4) dx <= bx - ax

• What are the binary values after these operations? (Assuming 8bit registers) • Answer: ax: 0000 1100 bx: 0001 0010 cx: 0001 1110 dx: 0000 0110

Example P3 Transferring Register Transfer VHDL

1) ax <= 12 2) bx <= ax sll 2 3) cx <= ax sll 3 4) dx <= ax srl 1

• What are the binary values after these operations? (Assuming 8bit registers) • Answer: ax: 0000 1100 bx: 0011 0000 cx: 0110 0000 dx: 0000 0110

Example P3 Transferring Register Transfer VHDL

1) ax <= 12 2) bx <= 20 3) cx <= ax and bx 4) dx <= ax or bx

• What are the binary values after these operations? (Assuming 8bit registers) • Answer: ax: 0000 1100 bx: 0001 0100 cx: 0000 0100 dx: 0001 1100

Example P3 Transferring Register Transfer VHDL

1) ax <= 12 2) bx <= 20 3) cx <= not ax 4) dx <= ax xor bx

• What are the binary values after these operations? (Assuming 8bit registers) • Answer: ax: 0000 1100 bx: 0001 0100 cx: 1111 0011 dx: 0001 1000

Example P3 Transferring Register Transfer VHDL

1) ax <= 12 2) bx <= 20 3) cx <= ax(5 down to 2) 4) dx <= bx(7 down to 4) 5) bx <= ax(5 down to 2) & bx(7 down to 4)

• What are the binary values after these operations? (Assuming 8bit registers) • Answer: ax: 0000 1100 bx: 0001 0100 cx: 0000 0011 dx: 0000 0001 bx: 0011 0001

Exercise P3 Transferring Register Transfer VHDL

1) ax <= 8 2) bx <= 23 3) cx <= bx(7 down to 4) & a(3 down to 0) 4) dx <= ax(4 down to 1) sll 4

• What are the binary values after these operations? (Assuming 8bit registers) • Answer: ax: 0000 1000 bx: 0001 0111 cx: 0001 1000 dx: 0100 0000

Exercise P3 Transferring Register Transfer VHDL

1) ax <= 13 2) bx <= 27 3) cx <= bx srl 2 4) dx <= (ax and bx) xor (not cx)

• What are the binary values after these operations? (Assuming 8bit registers) • Answer: ax: 0000 1101 bx: 0001 1011 cx: 0000 0110 dx: 1111 0000

Exercise P3 Transferring Register Transfer VHDL

1) ax <= 2Eh 2) bx <= ax(7 down to 4) xor ax(3 down to 0) 3) cx <= (ax slr 2) or (ax sll 1) 4) dx <= bx and cx

• What are the binary values after these operations? (Assuming 8bit registers) • Answer: ax: 0010 1110 bx: 0000 1100 cx: (0000 1011) or (0101 1100): (0101 1111) dx: 0000 1100

Exercise P3 Transferring Register Transfer Operations

Operator Example Operator Example

Assignment <= ax <= 12h Bitwise AND and ax and bx

Reg. Transfer <= ax <= bx Bitwise OR or ax or bx

Addition + ax + bx Bitwise NOT not ax not bx

Subtration - ax - bx Bitwise XOR xor ax xor bx

Shift Left sll ax sll 2 Vectors ax(3 down to 0) ax(3 down to 0)

ax(7 down to 4) Shift Right srl ax srl 2 Concatenate & &ax(3 down to 0)

Review