Power Management in an Embedded Multiprocessor Cluster, Revision 1.00 Introduction

thin SoCs, designers must designers thin SoCs, nd particularly well nd themselves ncy scaling of SoC components. illustrated using MIPS using MIPS Technologies’ illustrated measure to achieve low-power low-power footprints is to achieve measure cal multiprocessor clusters le clusters multiprocessor cal quirements. A typical A quirements. enable power gating and voltage/freque enable power gating Revision 1.00 Revision March 15, 2009 March Matthias Knoth, Matthias systems shall be s of embedded multiprocessor MIPS Technologies, Inc. MIPS Technologies, Document Number:MD00664 poral application needs. application Symmetri poral es in design methodology es in design methodology Multiprocessor Cluster Multiprocessor Power Management in an Embedded in an Embedded Management Power MIPS32® 1004K™ Coherent Processing (CPS).. System Processing 1004K™ Coherent MIPS32® performance scaling based on tem based on performance scaling Recent advanc to this technique. technique management power this paper, In d applications. Implemented wi Implemented into high-end embedded applications. have migrated clusters microprocessor Coherent re operational fit to thermal budgets supply and power tight meet

supports style cache “MESI” r CPU, require special techniques to special techniques r CPU, require ess region. For embedded embedded systems, For ess region. localized access to cache lines due to due cache lines to localized access - e.g. due to a pending store operation, cation of L1 tags per CPU promotescation par- per of L1 tags ibutes. Competing access to a particular ibutes. ) consists of up to four microprocessor microprocessor four to up of Figure 1) consists order to facilitate snoop traffic betweenrout- cores, snoopfacilitate traffic order to alized I/Ocoherence unitout to stream data in and of memory coherence. This scheme introducesownership to CPUs. Designers can program cluster internal events as events program cluster internal to CPUs. Designers can lectable activity level, masked and distributed to cores in to cores and distributed masked level, lectable activity e implemented snoop protocol e implemented ughoutcluster the change. upon to use or intent ual processor environments and threads. ual processor environments localized instruction and data caches pe caches and data localized instruction ular cache line with intent to modify line with intent to modify ular cache , exclusive, shared or invalid. Dupli shared or invalid. , exclusive, ion,. The CM also of mem- manages to and data from movement higher levels their cache line on demand. Similarly, demand. on their cache line calized if permitted by ownership attr ownership by calized if permitted Figure Figure 1 (CPS) System Processing Coherent 1004K™ MIPS32® ing of requests, ordering, and serializat cache. such as the L2 ory hierarchy, enhanceprocessing throughput,a speci designers can employ To the coherent domain. A programmable interrupt controller manages interrupt external into distribution the CPS. The controller is capable of routing up to 256 interrupt sources The CPS employs a centralized coherence manager unit (CM) a centralized coherence manager in employs CPS The with se edge- or level-sensitive sources as as external well allel operation of execution pipelinesnoopand request processing.operationallel of execution (CPS, System Processing 1004K™ Coherent The MIPS Technologies virt independent two providing each cores, As a core acquires ownership of a partic ownership acquires core As a maintain consistency between localized and their common cache contents addr consistency maintain designers typicallyapplyschemes snoop-based to maintain of local cache lines,thro which are posted attributes Coherent microprocessor clusters, having having clusters, microprocessor Coherent line attributes to markas modified lines attributes line peer CPUs are notified and will update will and peer CPUs are notified lo load instructions can stay pending Th cache line must be orderedmaintain consistency. to 2 Power Management in an Embedded Multiprocessor Cluster, Revision 1.00 Introduction

vidual CPS compo- and processor state. and processor eactivation of individ- eactivation ng system processor states programmable power controllerprogrammable power CPUPower Management Modes ead yield qualifier to supportto ead yield qualifier activity levels, such as power states as such power levels, activity eatures of the indi des of operationnon-coher-des – coherent, their performance level level performance their energy consumption. D energy cache coherent domain and exchanges coher- and exchanges cache coherent domain cal coherent cluster by allocatingcoherentcalcluster virtual proces- by ) requirements. In addition) requirements. to the reduction in dynamic herence. The coherence manager posts snoop requests pendent variables to adjust performance levels within toadjustperformance pendentlevels variables cluster resources. Integral clusterparts resources. of Integral sys- those software tion can impact power exponentially if supply voltage is supply if voltage exponentially tion can impactpower requirements - e.g. a requirements - e.g. a standardized bit rate; and explicit parasitic capacitances (P ~ CfV2), lower voltage also voltage parasitic(P ~ CfV2), capacitances lower r state controls CPU r state controls in the CPS. Therefore, a Therefore, in the CPS. operating system. These power states reflect different lev- states reflect different power operating system. These rrupt, toor be used as thr , which communicate to hardware resources via dedicated resources hardware to whichcommunicate , noop port of the CPU. Thenoop globalCPU. port of theinterrupt controller can or format, determine an application’s overall performance performance overall application’s format, determine an or em separately for control purposes. Performance levels can be can levels Performance control purposes. em separately for ad allocation and processing frequency accordingly. ad allocation and processing frequency accordingly. domain, is maintained at equal speeds. Within coherentdomain, is maintained mode, at equal designers speeds. Within odes. A cluster CPU provides four mo Acluster provides CPU odes. dual CPU can assume a range of power states which are managed by the clus- dual CPU whichstates are managed by can assume a range of power drawn by nanometer CMOS technologies. CMOS technologies. nanometer by drawn ating system access and manage power f ating system access and manage power pective, cluster CPUs are characterized by by CPUs are characterized cluster pective, ls based on temporal demand largely affects affects demand ls based on temporal largely Figure 2Figure Power to Optimize Scaling Performance ): This CPU operates as member of an L1 member of CPU operates as This Figure 3): ence messages with processor peers to maintain cache co line at the s a particular cache cores towards peer of sustain optimal performance,route communication interrupts this between CPU. towards To this CPU and the coherent of the and other members CM, resides within the CPS to provide oper to provide the CPS within resides nents. granted by the OS. The OS will adjust hardware thre adjust hardware will The OS the OS. granted by requirements, such as user choices of a display quality user as requirements, such leve Adapting performance management and laythefoundation for power the cluster, Thread allocation inde two and provide processing frequency device drivers. Typically, application inherentperformance Typically, drivers. device interactions. operati Designers can directly model and environmental els of CPU activity thread communication. Linux directlysupportSMP such as systems Operating the symmetri threadssors or on-demand andmigrating processes between management featuresload balancingtems are power and reduc frequency But linearly. scales clusterual CPUs power reduces the amount of leakage current From an operating system pers and coherence behavior. each indivi the coherent cluster, Within the and controller(CPC) proposed by hardware power ter m power hardware-based these towards lowered according to the lower silicon carrier mobilityaccording (speed to the lower lowered of technologies’inis rooted which CMOS recharge power, variant severity levels such as masked or non-masked inte or non-masked masked such as levels severity variant ent, clock-off and power-down. and power-down. ent, clock-off • Coherent Mode ( Both are interlinked, but it is advantageous Both itto are is handle interlinked,advantageous th but whereas the processo and voltage, used to adjust frequency Power ManagementEmbedded in anMultiprocessorRevision 1.00 Cluster, 3 CPU Power Management Modes CPU Power

e. Therefore, the to perform interruptrout- ited for control plane opera- ited The power controller prevents power- prevents controller The power is particularlywell-su requests. Operating as a standalonerequests.as a Operating CPU, the snoop ion needs. Supply voltage can accompany frequency frequency can accompany voltage Supply ion needs. interrupt controllercontinues processing demand rises withinthe coherent domain, a ntroller, can send this CPU into a clock-off power- or a clock-off into CPU this send can ntroller, e CPU based on system events. After a wake-up, the CPU the wake-up, After a events. CPU based on system e ce manager will not forward snoopy messages generated messages ce managersnoopy will not forward not required, the operating frequency of a CPU in non- of required, not the operating frequency ecause snoop of its remaining duties. response Coherent rding to a given cluster frequency. cluster frequency. given rding to a ing to a non-coherent operation mode. the cluster again at any time. any at again the cluster ally, based on applicat based on ally, Figure 3Figure Mode Coherent ins its internal stat internal its ins mainta but events, external to esponsive Figure 4Figure Mode Non-Coherent ): In this mode, the CPU operates outsidecoherentmode,andthe): In this the CPU operates does not emit cluster through frequency changes to all members of the coherent domain. Cluster-wide changesof to all membersthrough domain. the coherent Cluster-wide frequency ): A CPU operating outside of the coherent mode. domain Clock can assume clock-off Figure 4 Figure 5 cluster power controller can perform fast wakeup of th wakeup controllerfast can perform cluster power resumes a non-coherent mode of operation. changes. Software, interacting with the cluster power co interacting with the cluster power Software, changes. onstatesystem operating demand. Non-coherent mode down in non-coherentCPU mode can join thecompleteits CPUand and sets tree clock as cut this CPUgenerator at the clock is level towards distribution The CPUbecomes non-r inactive. snoop messages towards peer cores. Also, the coheren towards messagessnoop by other coherent continuesby toprocess CPUs, memory but applications running on this CPU using the coherent domain will be broughtor migrate down Typically, to other The global CPUs before non-coherent mode is invoked. this core. Since couplingto other CPUs is ingtowards individu coherent mode is adjusted coherentof a data processing CPU system. can Such a andtionssurrounding housekeeping tasks activities the As down. power or even states power also assume lower port is deactivated. port is deactivated. down, and software attempts to deactivate this CPU b this deactivate to attempts software and down, lead via software, exited be mode can can adjust performance levels performance can adjust acco permitted are adjustments voltage • Mode Clock-Off ( • Non-Coherent Mode ( 4 Power Management in an Embedded Multiprocessor Cluster, Revision 1.00

wer controller (CPC) queue. wer CPUPower Management Modes the supply grid, so it is not neces- supply grid, the wakeup requests. If no retention or fast wakeup is wakeup or fast retention requests. If no wakeup state retention requirements of standard cell registers olated from its surroundings, while other cores in non- sequence to maintain logical and electrical consistency sequence to and maintain logical electrical consistency ternal state and is required to observe a reset ternal state and is required and initial- to observe commands into the cluster po mains alive to initiate a power-up and reset sequence. reset and to initiate a power-up alive mains componentthreadsand can notify about completion of an rlock over-command sequences to ensure power and CPU and power to ensure sequences rlock over-command ecognizes when all CPUs have reached power-down mode, and mode, and power-down reached have all CPUs when ecognizes On-chip power gating cells disconnect gating On-chip power ) are initiated through the operating system talking to coherence manager Figure 5 Clock-Off Mode Figure 6Figure Mode Power-Down Figure 7 ): The CPU is electrically is electrically ): The CPUis all CPUs have reached power-down mode, the coherence manager and selectively selectively and mode, the coherence manager reached power-down CPUs have all wer controller also r Figure 6 ization sequence upon power-up. Neither dynamic nor leakage power isconsumed. Designers can program the dynamicleakage Neither power nor ization sequence upon power-up. power-down schedules which a controller, cluster power the before leaving CPUs inthroughout coherent down the mode system. from This powering includes preventing hardware system-level request or sequence based on a peer core coherent domain,initiating and power-up a cluster po The intervention. power-down mode continue operation. power-down This CPU will lose its in supply. switchsary to external In clock-off mode, power consumption mode, is power reducedIn to clock-off leakage currents and can be further adjustingreduced the by are determined reduction by levels supply voltage. Voltage and cache RAMs, but also by desired power-up times upon times power-up desired also by but and cache RAMs, or situation Such a a shutdown also enables unused coherencemanager. the now for initiates a power-down as the L2 cache. such memory, higher level mode for clock-off required, a CPU in clock-off mode can be powered down. can be powered mode a in clock-off CPU required, registers, migratingregisters, threads between placingCPUs and by states for each feedbackpower aboutCPC provides The at response integrity all times. If re The CPC however, down. 2 cache are powered the level initiated sequence. The CPC also provides hardware inte hardware also provides The CPC initiated sequence. Transitions between CPU modes ( CPU modes between Transitions • Mode( Power-Down Power ManagementEmbedded in anMultiprocessorRevision 1.00 Cluster, 5

choose to power up more more up power to choose constants for both choices ent address spaces, or they ent address spaces, or they ock-off state thatheld was ock-off remain isolated and powered-down. of the two virtual CPUs within a physical CPUs within a physical virtual of the two asking run levels, the OS can the run levels, asking levels. Operating system performance level requests are requests Operating system performance level levels. Designers must consider time ntial dependency of power to ntial voltage, and therefore dependency of power ckly join the coherentdomain.This can trigger the pow- perform tasks perform tasks within independ to performance levels obtainable for this CPU. obtainable Obvi- for to performance levels ising voltage for a CPU in cl CPU in for a voltage ising per physical core) can weigh-in towards decidingfor more per physical core) can weigh-in towards cessing loads that can be met through of additional spawning states to meet processing and processor states to meet processing levels ormance Thereafter, CPU0 executes boot code and initializes the CPU0 executes Thereafter, s. Further, the thread granularity s. Further, 2+k)), helps determine those tradeoff the system also provides the lowest power footprint power the and system limits also the lowest provides inrush cur- e coherent domain. Other cores might e coherent domain. Other cores architects the number mighttrade of coherent operating threads off fre- versus Figure 7Figure CPU States Cluster in non-coherent mode to To meet performance demands rapidly, one meet performance demands rapidly, To As described earlier, an operating an systemCPU perf uses As described earlier, Powering up the CPS consists of several phases. In addition phases. In required to initialization and bootstrap operation of an consistsof several CPS the up Powering SMP system, operating a staged ramp-up of at power-on-reset. rent and sequence is applied. a reset First, CPU0 is powered multi-t reaches system the operating After coherence manager. CPUs. Those CPUs might remain CPUs CPUs. Those spaces and join th can combine address ously, power-down and clock-off modes represent the lowest modes represent the lowest and clock-off power-down ously, demand and manage power. Each processor state gives rise Each processor state gives demand and manage power. to CPU operatinglinked frequencies.directly How- to optimizesnoop latency. Membersrequired level of a coherent domainoperate toare frequency at an equal for certain applications, system ever, consumption.The expone energy tooptimize quency overall (P~fV2;P~V( f=F(V)operating => frequency of coherent cluster CPUs (thethreadstwo CPS provides threads at reduced voltage to optimize energy. to optimize threads energy. at reduced voltage in pro changes are dynamic tradeoff Other aspects of this hardware threads, or voltage/frequency ramp-up threads, on demand.hardware or voltage/frequency before at a retention supply level. for each particular application. CPU core can be kept asleep and prepared in advance to qui in advance asleep and prepared core can be kept CPU state, or ra CPUs from theirmoreering-up power-down of 6 Power Management in an Embedded Multiprocessor Cluster, Revision 1.00 CPU and CPS Performance Levels CPU and CPS Performance

level is translated to fre- translated is level ation circuits route and divide PLL divide route and ation circuits Aspects of PhysicalImplementation mory libraries enable the previously dis- the previously enable libraries mory r or performance core single refill requests become more relaxed. Similarly, bus bus Similarly, requests become more relaxed. refill rating system can evaluate the overall demand on L2 and on L2 demand overall the can evaluate rating system ypes of standard gates, isolation cells – power cells, level- in operating frequency relative to the coherence managertheto coherence in relative operating frequency any short-term drops in performance levels do short-term not influ-any drops inperformance levels ntrol, frequency synthesis and clock distribution are are distribution clock and synthesis frequency ntrol, program clock generationfor those components based on standard cell and me adjust operating voltages accordingly. adjust operating voltages mance level. clock Programmable prepar mance level. e CPU and interface clock speeds. Operating voltages are derived from fre- are derived voltages clock speeds. Operating CPU and interface e of-the-art EDA flows and enhanced flows of-the-art EDA outlines the and changes frequency propagation to voltage requests ofopti- OS performancetowards level Figure 8Figure SOC in an Control Voltage and Driven Frequency Level Performance OS ence voltage supplies. supplies. ence voltage synthesized frequencies and determin Therefore, requestsof and desired speed recovery. quency Changing clocks and the power supplychallenges dynamicallyfor SoC Changingclocks between and the power SoCsubcomponentsnew creates State- integrators. CPUs in non-coherent mode can be individually controlled in mode non-coherent CPUs can be individually and coherent domain CPUs. Designers can Designers domain CPUs. and coherent Reductionin reductions CPUoperating higher in frequenciesalso memorypower makes room for hierarchies. L1 cache towards two a level for time requirements Response tocouldrequests the SoCbecome demanding. less The ope and re performance level, given for a bridge traffic bus demand. Figure 8 consumptiondecisiona SoC.of An OS fora clusteenergy mize quencies and expected processor states. CPC, voltage co voltage CPC, states. processor and expected quencies perfor reach the new reprogrammed to cussed power management t techniques.At its core are four cussed power shifting cells and retention flops. Aspects of Physical Implementation Aspects of Physical Power ManagementEmbedded in anMultiprocessorRevision 1.00 Cluster, 7

logic levels driven into into driven levels logic formats, and is consis- application of voltage scal- application of voltage effects of isolation cells isolation of effects logic design using standardized for- using logic design age characteristics. Further, age characteristics. Further, isolation cells with predefined isolation values. The values. isolation with predefined cells isolation . It remains. It isolateduntil supply estab- stable is power onforming to those power intent onforming to thosepower retention flopsthat contain holding circuitssmall drive of cludingprogrammable to properly dimension a regulators between physical implementation, originalintent power g neighboring active or retention sleepregions—requires g neighboringactive gh impedance,the and mimics sistors, inserted in supply or ground rails to gate supply voltages for a for sistors, insertedground supply supply in to voltages or gate rails proper function forregion. that wakeup also requires cache contents, which and data also requires retention of instruction wakeup each region is described separately from is described separately each region as the CPC to support SoC integrators. supportas the CPCtointegrators. SoC nate leakage currents of standard cell regions. However, the applicationretention of However, currents nate leakage of standardregions. cell Figure Figure 9 Cell Management Application Power mats. Logic simulation drives un-powered regions to hi regions un-powered mats. Logic simulation drives Design synthesis and logic simulation supports flop state retention behavior. Similarly, regions. powered towards related standard cells withoutinsert user andpower intent, physical implementationthe descriptionsreuse of power comparison tools ensure consistency Formal intervention. intent, c and designpower languages.its The CPS describes controls such tent with higher-level On-chip switching of SoCimplementers must pay close attentionto supply integrity. dimensioning rail andpower design thatrails regions—without supply influencin large drop analysis and must includevoltage pad, bonding and pack Retention techniques can elimi currents. to leakage contribute management techniquesthrough ofprocess. all the design support phases application the of these power flows EDA intent for power Through these flows, flops increases silicon area slightly. Fast area flops increases silicon slightly. system. active chip regions, powered-down region outputsto connect region powered-down chip regions, active is powered-down before it a region isolation of invokes CPC again and the CPClished has ascertained translation cells are required. to communicate. Level-shifting need logic supply level voltages different of Regions it is possible to maintainthe state of flops throughFurther, strength,high which impedance are supplied whilesupply are disconnected. main regions separately with relatively ing techniques supply must in networks reflect board-level Power gate cells are switching cells are switching CMOS tran gate Power design region. These are controlled by the cluster power manager (CPC). To guarantee proper guarantee (CPC). To manager power the cluster are controlled by These region. design 8 Power Management in an Embedded Multiprocessor Cluster, Revision 1.00

Conclusion reductions are achieved through reductionsare achieved ical processor cores. Temporarily unused cores can leave unused cores canleave ical processor cores. Temporarily gating of CPU power islands. Symmetrical processor clus- power CPU of gating oherent address space. The operating system manages power managesoperating Thespace. system power oherent address enables the interaction and the oper- implementation cal cluster between physi Matthias Knoth is a Design Engineer for MIPS Technologies, Inc., responsible for low-power micro-architecture and for low-power micro-architecture Inc., responsible Matthias Knoth is a Design Engineer for MIPS Technologies, in the semiconductorindustrythan experience 13years’ with implementation. Knoth has more 1004K processor and Quicksilver Technologies Infineon Siemens Microelectronics, companies including Siemens Research, Central Chemnitz, Germany. the University of Technology, from in Electronics Knoth holds aDegree Masters Technology. dynamic voltage and frequency changes as well as power as changes well as power and frequency dynamic voltage managementfea- the physical power les are used to drive andvariab state. processor These through level performance controller A power tures of the system. ating system. Within an embedded multiprocessor cluster like MIPS Technologies’ 1004K CPS, power consumptionismanaged power 1004K CPS, embeddedMIPS Technologies’ an multiprocessor like cluster Within through performance scalingon based temporal demand. performance Power ters allow the migrationofbetween tasks and threads ters allow phys can operate out- cores Alternatively, to a retention theirreduce level. voltage or down domainthe coherentand power in non-c operations side the coherentdomain to fulfill About the Author Conclusion Power ManagementEmbedded in anMultiprocessorRevision 1.00 Cluster, 9 Unpublished rights (if any) reserved under the copyright laws of the United States of America and other countries.

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Power Management in an Embedded Multiprocessor Cluster, Revision: 1.00