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High-Performance Simulator for Mixed Language Designs IEEE VHDL, SystemVerilog, Verilog-AMS, SystemC/C/C++ Veri cation Libraries: UVM, OS-VVM e ca on co em Assertion-Based Veri cation: SVA, PSL o A o e n e a
A trusted name in EDA since 1984, Aldec understands that today’s engineers require innovative solutions to enable rapid deployment at every stage of development. A A I I A I IEEE VHDL, Verilog, SystemVerilog (Design) Aldec works closely with customers to understand Multi-FPGA & EDA Tool Design Flow Manager HTML and PDF Design Documentation their real-world challenges and requirements, and Text, Schematic, FSM Design Entry Tools deliver a personal blueprint of solutions customized to t their needs. Ac e A I I A I A I A A Clock and Reset Networks Analysis Acceleration, SCE-MI Emulation, Prototyping I Avoiding post RTL and post Synthesis Simulation Mismatches Virtual Platform Integration – HW/SW Co-Verification A I Extensive CDC checks with ALDEC_CDC rule plug-in Transactor Library - Bus Models and Peripherals I Code Portability and Reuse Extensive Debugging Capabilities I A Scalable up to 633 million ASIC gates High-Performance RTL Simulator & Adv. RTL Debugging ARM® Cortex®-A9 Support with Xilinx® Zynq® SoC Zynq® Development Board (FPGA + dual ARM® Cortex-A9 core) HDMI, USB, Bluetooth, Wi-Fi, Ethernet, and more Supports Xilinx® Vivado™ and SDK™ development flow Expandable, Non-proprietary Connectors IoT, Factory Automation, UAV, Automotive, Robotics and More
Traceability to HDL Design and Testbench I Requirements Coverage Analysis I Change Impact Analysis A A Test-Results Management A ec A I A I Supported Microsemi Devices/Capacities Increase verification coverage by test RTAX-S/SL Up To 4000S, RTAX-DSP & RTSX-SU Device I I Testbench reuse as hardware test vectors Automated Device Netlist Converter A A 100% device I/O controllability and visibility Memory & Physical Design Constraint (PDC) File Conversion I Testing at-speed on target device: A Altera®, Microsemi®, Xilinx®
www.aldec.com R THE DESIGN VERIFICATION COMPANY Customer Stories
Active-HDL™ Riviera-PRO™ “With a good editor/compiler and a versatile, “Designers seeking superb verification tools will easy to use simulator, Active-HDL was considered benefit from Riviera-PRO’s complete verification the best featured design tool compared to environment for high-performance RTL and leading competitors. The quality of the design gate-level simulation.” environment and good integration with source control tools definitely saves time on both new development and maintaining existing code.”
DO-254/CTS™ Technical Support EASA approved our verification process based on “Thanks to Aldec’s support team, learning how to Aldec DO-254/CTS, accepted our test results, and simulate a new and rather complex design took the audit passed without any findings. This is the nearly no time at all. It is quite clear that Aldec’s first time in Elbit’s history that we have been able engineers have left no stone unturned in their to bring more than 5 FPGA devices to the audit. quest for excellence.” Aldec helped us solve several of our verification challenges and delivered quick and professional responses for all our requests.
Aldec, Inc. Ph +1.702.990.4400 [email protected] Visit us at www.aldec.com R THE DESIGN VERIFICATION COMPANY
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