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Protocol Processing in Network Terminals Linköping Studies in Science and Technology Dissertation No. 865 Protocol Processing in Network Terminals Ulf Nordqvist Department of Electrical Engineering Linköpings universitet, SE-581 83 Linköping, Sweden Linköping 2004 Protocol Processing in Network Terminals © 2004 Ulf Nordqvist Department of Electrical Engineering Linköpings universitet, SE-581 83 Linköping, Sweden Linköping 2002 ISBN: 91-7373-914-6 ISSN: 0345-7524 Abstract The bandwidth and number of users in computer networks are rapidly growing today. The need for added functionality in the network nodes is also increasing. The requirements on the processing devices get harder and harder to meet using traditional hardware architectures. Hence, a lot of effort is currently focused on finding new improved hardware architectures dedicated for processing of packets and network protocols. In the emerging research area of protocol processing, there exist many hardware platform proposals. Most of them aim for router applications, not so many for ter- minals. As a starting point for terminal research this thesis explores a number of different router design alternatives and some common computer architecture con- cepts. These concepts and architectures have been examined and evaluated to see if some ideas apply also to protocol processing in network terminals. • Requirements on protocol processors for terminals can be summarized as: • Low silicon area • Low power consumption • Low processing latency • High processing throughput • Flexible implementation Fulfilling these requirements while supporting offloading of as much protocol processing as possible to the network interface is the key issue of this thesis. Off- loading means that the protocol processing can be executed in a special unit that does not need to execute the host applications as well. The protocol processor unit basically acts as a smart network interface card. A novel terminal platform solution is proposed in this thesis. The dual processor platform is accelerated using a programmable protocol processor. The processor uses a number of different dedicated hardware blocks, which operate in parallel, to accelerate the platform in a configurable way. These hardware blocks have been selected and specified to fulfill requirements set by a number of common network protocols. To find these requirements, the protocol processing procedure has been i ii Abstract investigated and divided into processing tasks. These different tasks have been explored to see which are suitable for hardware acceleration and which should be processed in the other part of the platform which is a general purpose micro con- troller. The dedicated datapath, simplified control, and minimal usage of data buffers make the proposed processor attractive from a power perspective. Further it accel- erates the platform so that high speed operation is enabled. Different implementa- tion alternatives are provided in this thesis. Which one to select depends on what kind of terminal the platform is going to be used for. Further this thesis includes a discussion around how the ability to reassembly fragmented packets demands architectural modifications. I hope You will enjoy reading this dissertation! Linköping in December 2003 Ulf Nordqvist 1Preface This thesis is intended for a Doctoral degree in Technical Sciences. The thesis presents the results of my research during the period 1999-2003 at Linköping Uni- versitet, Sweden. The following publications are included in the thesis: • Publication 1: Dake Liu, Ulf Nordqvist, Christer Svensson "Configuration based architecture for high speed and general purpose protocol processing", in proceedings of SIPS 1999, Taipei, Taiwan, p.p. 540-547 • Publication 2: Ulf Nordqvist, Tomas Henriksson, and Dake Liu, “CRC Genera- tion for Protocol Processing”, in proceedings of NORCHIP 2000, Turku, Fin- land, November 6-7, 2000, pp. 288-293 • Publication 3: Ulf Nordqvist, Dake Liu, “Configurable CRC Generator”, in proceedings of the IEEE Design and Diagnostics of Electronic Circuits and Systems, DDECS, Brno, April 17-19, 2002, pp. 192-199 • Publication 4: Ulf Nordqvist, Dake Liu, “Packet Classification and Termina- tion in a Protocol Processor”, in proceedings of the second Workshop on Net- work Processors (HPCA/NP2), Anaheim, USA, February 2003, pp 88-99 • Publication 5: Ulf Nordqvist and Dake Liu, “Power Optimized Packet Buffer- ing in a Protocol Processor”, to appear in the proceedings of the ICECS 2003, held in Sharjah, United Arab Emirates, Dec. 2003 • Publication 6: Ulf Nordqvist and Dake Liu, “Control Path in a Protocol Proces- sor”, to appear in the proceedings of the Midwest Symposium on Circuit and Systems, MWCAS 2003, Cairo, Egypt, Dec. 2003 • Publication 7: Ulf Nordqvist and Dake Liu, “Chapter 8: Packet Classification and Termination in a Protocol Processor”, Book chapter in the Network Pro- cessor Design; Issues and Practices, Volume 2, Chapter 8, Morgan Kaufman Publishers, 2003, ISBN: 0-12-198157-6 iii iv Preface Other publications related to the scope of this thesis and to the author, but not included in the thesis are: • Publication 8: Ulf Nordqvist, "On Protocol Processing", in proceedings of CCSSE 2001, Norrkoping, Sweden, 2001, Mar 14-15, pp. 83-89 • Publication 9: Ulf Nordqvist, “A Comparative Study of Protocol Processors”, in proceedings of CSSCE 2002, Norrkoping, Sweden, Oct 23-24 2002, pp. 107- 113 • Publication 10: Ulf Nordqvist, “Power Efficient Packet Buffering in a Protocol Processor”, Swedish System on a Chip Conference, Vol. SSOCC’03, Apr 2003 • Publication 11: Ulf Nordqvist, “A Programmable Network Interface Accelera- tor”, Licentiate degree thesis, Linköpings Universitet, Thesis no. 998, Jan 2003 • Publication 12: Tomas Henriksson, Ulf Nordqvist, and Dake Liu, “Embedded Protocol Processor for Fast and Efficient Packet Reception”, in proceedings of International Conference on Computer Design, Freiburg, Germany, pp. 414- 419, Sep 2002 • Publication 13: Tomas Henriksson, Ulf Nordqvist, and Dake Liu, “Specifica- tion of a configurable general-purpose protocol processor”, in the IEE proceed- ings of Circuits, Devices and Systems,. Vol. 149, No. No. 3, pp. 198-202, Juni 2002 • Publication 14: Tomas Henriksson, Henrik Eriksson, Ulf Nordqvist, Per Lars- son-Edefors, and Dake Liu, “VLSI Implementation of CRC-32 for 10 Gigabit Ethernet”, In proceedings of The 8th IEEE International Conference on Elec- tronics, Circuits and Systems, Malta, September 2-5, 2001, vol. III, pp. 1215- 1218 • Publication 15: Tomas Henriksson, Ulf Nordqvist and Dake Liu, “Specification of a configurable General-Purpose Protocol Processor”, In proceedings of Sec- ond International Symposium on Communication systems, Networks and Digi- tal Signal Processing, Bournemouth, UK, July 19-20, 2000, pp. 284-289 • Publication 16: Tomas Henriksson, Ulf Nordqvist, and Dake Liu, “Config- urable Port Processor Increases Flexibility in the Protocol Processing Area”, In proceedings of COOLChips III An International Symposium on Low-Power and High-Speed Chips, Kikai-Shinko-Kaikan, Tokyo, Japan, April 24-25, 2000, pp. 275 • Publication 17: A Herzog, Nahid Shahmehri, A Bednarski, I Cisalita, Ulf Nor- dqvist, L Saldahni, D Szentivanyi och Måns Östring, “Security Issues in E- Home Network and Software Infrastructures”, Proceedings of CCSSE, Nor- rköping, Sweden, Okt 2001 Acknowledgments The credit for making this thesis possible to accomplish does not belong only to one single person. Instead it is the sincerely appreciated support of many different persons who have helped during my research work that deserves a hats-off from me. First of all, I would like to thank my supervisor, Professor Dake Liu, for guid- ance, inspiring discussions, proofreading, and for giving me the opportunity to do this work. I would like to acknowledgment my fellow Ph.D. student Dr Tomas Henriksson for valuable discussions, for coauthoring papers and for sharing information and ideas. Lic. Eng. Kalle Folkesson and Lic. Eng Daniel Wiklund are acknowledged for proof reading this thesis. I would also like to thank the professor at my former research group, Electronic Devices, Professor Christer Svensson and the former professor at that group, Pro- fessor Per Larsson-Edefors for inspiring and helping me. Especially during the beginning of my career as a Ph.D. student. Sharing the working environment with an inner circle of Ph.D. students like Dr. Daniel Eckerbert, Dr. Henrik Eriksson, Mikael Olausson, Erik Tell, Stefan Ander- sson, Peter Caputa, Andreas Ehliar and Sumant Sathe has been a true pleasure. All of the former and present members of the Electronic Devices and the Com- puter Engineering groups are acknowledged for the technical and administrative support. I would like to thank the swedish strategic research foundation (SSF) for the funding of my research through ECSEL and Stringent projects. Finally I would like to thank my relatives for supporting but not understanding my work. v vi Acknowledgments 1Abbreviations ARP Address resolution Protocol ASIC Application Specific Integrated Circuit ASIP Application Specific Instruction set Processor ATM Asynchronous Transfer Mode CAM Content Addressable Memory CMAA Control Memory Access Accelerator CRC Cyclic Redundancy Check FP Functional Page FPGA Field Programmable Gate Array GMII Gigabit Media Independent Interface HBA Host Bus Adaptor ILP Instruction Level Parallelism IP Internetwork Protocol IPv4 Internetwork Protocol version 4 IPv6 Internetwork Protocol version 6 iSCSI Internet Small Computer System Interface LAN Local Area Network MAC
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