56 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 1, MARCH 2002 Nanotechnology Goals and Challenges for Electronic Applications Mark T. Bohr, Senior Member, IEEE

Abstract—Si metal–oxide–semiconductor field-effect (MOSFET) scaling trends are presented along with a description of today’s 0.13- m generation . Some of the foreseen limits to future scaling include increased subthreshold leakage, increased gate oxide leakage, increased transistor parameter variability and interconnect density and performance. Basic device and circuit requirements for electronic logic and memory products are described. These requirements need to be kept in mind when evaluating nanotechnology options such as carbon nanotube field-effect transistors (FETs), nanowire FETs, single electron transistors and molecular devices as possible future replacements for Si . Index Terms—Carbon nanotube, Complimentary metal–oxide– semiconductor (CMOS), dynamic random access memory (DRAM), logic, memory, metal–oxide–semiconductor (MOS), metal–oxide–semiconductor field-effect transistor (MOSFET), molecular electronics, nanotechnology, nanowire, scaling, single electron transistor, static random access memory (SRAM). Fig. 1. Semiconductor technology minimum feature size trend.

I. INTRODUCTION ILICON-BASED integrated circuits have experienced phe- S nomenal growth since the invention and demonstration of the earliest devices: the first bipolar transistor in 1948, the first planar in 1961 and the first general purpose metal–oxide–semiconductor field-effect transistor (MOSFET) in 1964. Today the semiconductor industry has combined rev- enues of over 140 billion dollars and its technical progress is exemplified by leading edge products such as: microprocessors operating at 1 GHz or more [1]–[5], microprocessors with 100 million transistors [4] and [5], and memory chips with 1 Gb den- sities [6]–[9]. This rapid technological progress was first pre- dicted in 1965 by Gordon Moore in the now famous “Moore’s Law” which stated that integrated circuit density and perfor- mance would double every 18 months. These improvements would come from reduced transistor dimensions, increased tran- sistor counts, and increased operating frequencies. His predic- tion was remarkably prescient as illustrated in Figs. 1–3. Fig. 2. Intel (CPU) transistor count trend. Silicon-based metal–oxide–semiconductor (MOS) tech- nology will eventually run into fundamental limits and not progress demonstrated up to this point. A new and revolu- be able to provide the expected increases in density and tionary integrated circuit technology will be needed to replace performance. Several potential limits to further MOS device MOS transistors as the driver behind continued improvements scaling will be discussed in this paper. Because of these limits, in electronic products. Some new types of nanotechnology the type of evolutionary technology improvements that have devices are interesting candidates to explore, but the success of been the foundation of integrated circuit development for the silicon MOS transistors will be hard to duplicate. It took many past 40 years may no longer be able to sustain the rate of years for bipolar and MOS transistors to make the transition from laboratory devices to useful products. A serious effort by Manuscript received January 14, 2002; revised February 7, 2002. academic and industrial researchers is needed now to explore The author is with Intel Corporation, Hillsboro, OR 97124-6497 USA (e-mail: [email protected]). nanotechnology options as possible replacements for MOS Publisher Item Identifier S 1536-125X(02)04586-6. transistors, whose scaling limit may not be that far away.

1536-125X/02$17.00 © 2002 IEEE BOHR: NANOTECHNOLOGY GOALS AND CHALLENGES FOR ELECTRONIC APPLICATIONS 57

Fig. 4. Negative-channel metal–oxide–semiconductor (NMOS) transistor Fig. 3. Intel CPU MHz trend. g†as gate delay versus gate length.

II. MOS TRANSISTOR SCALING One of the main driving forces behind the rapid improve- ments in integrated circuit products has been the excellent performance and scaling properties of the MOS transistor, first described by Dennard in 1974 [10]. By scaling transistor hori- zontal dimensions, vertical dimensions and operating voltage, simultaneous improvements in transistor density, switching speed and switching energy can be realized. For ideal scaling, a 0.7 reduction in MOS transistor dimensions and operating voltage, along with an increase in silicon dopant concentration, will provide transistors with the following improvements: 2 areal density, 0.7 switching delay time and 0.5 switching energy. Since the 1960s, the semiconductor industry has been developing technology generations with 0.7 minimum fea- ture size scaling every 2–3 years (Fig. 1), and each generation provides transistors that are smaller, faster and use less energy. Fig. 5. NMOS transistor g† switching energy versus gate length. A method to estimate the switching speed, or gate delay, of MOS transistors is by use of the metric [11]. In this switching energy is , using transistor gate capacitance and metric, the switching speed can be estimated when gate ca- operating voltage. Again, this is a simplified metric that leaves pacitance C , operating voltage V and drive cur- out some second order factors, but is useful for estimating gen- rent I are known. This simple metric underestimates gate erational trends. Fig. 5 shows the trend in MOS switching en- delay because it leaves out some important performance factors, ergy for the same set of publications used in Fig. 4. Transistor such as junction capacitance and the fact that typical MOS cir- gate width (W ) is assumed to be twice the gate length (L ) for cuits have fanouts of greater than one (therefore, greater load these calculated energy values. Switching energy has been re- capacitance). However, this is a useful metric for tracking gener- ducing by 0.44 for each technology generation, where each ational delay improvements and is useful when a complete set of generation is defined as a 0.7 feature size reduction. Tran- transistor parameters is not available for a more rigorous com- sistor switching energy has become increasingly important due parison. Fig. 4 shows the trend in MOS transistor gate delay to overall circuit power constraints, as will be discussed in the using the metric applied to a large number of published next section. transistor papers from industry and academia over the past ten The trends shown in Figs. 1, 4, and 5 should be viewed as years. The sub-100 nm gate length publications are included more than just historical trends, they are also roadmaps for fu- in references [12]–[23], the older publications can be found ture transistor requirements. The semiconductor industry has in [11]. As expected for MOS transistor scaling, dimensional recognized the need to stay on these trend lines in order to con- scaling of 0.7 per generation has been providing roughly 0.7 tinue to provide the denser and faster products expected by the gate delay improvements per generation. market. If some new form of nanotechnology is to someday re- Another important feature of scaled MOS transistors is the re- place MOS technology, then ideally it should provide similar duction in the amount of energy used during a switching event. benefits. Switching energy reduction is derived from the combination of Table I summarizes typical NMOS transistor characteristics lower parasitic capacitance from smaller feature sizes and from for the older 0.5- m generation [26]–[28] and today’s 0.13- m lower operating voltage. A metric for estimating MOS transistor generation [22]–[25]. Note that L values, which used to be 58 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 1, MARCH 2002

TABLE I TYPICAL TRANSISTOR CHARACTERISTICS FOR 0.5- AND 0.13-"mGENERATIONS OF LOGIC TECHNOLOGY AND ESTIMATE OF TRANSISTOR CHARACTERISTICS FOR THE END OF CMOS SCALING ($22 nm GENERATION)

Fig. 6. Representative logic circuit with two inverters.

Also included in Table I is this author’s estimate of what sil- icon CMOS devices may be like near their scaling limit, around the year 2014. Physical gate lengths will be 10 nm and the de- vice structure will likely be fully depleted silicon-on-insulator or double gate transistors. At this point further CMOS scaling will be prevented by the inability to scale the gate dielectric the same as other typical feature sizes on a generation, are now (even with high- materials), V control problems, the inability almost half the typical feature size. L dimensions have been to scale V due to leakage constraints and, thus, the inability to scaling faster than other feature sizes in order to accelerate scale V due to performance constraints. Because of the inter- MOSFET performance improvements, and, therefore, accel- dependency of CMOS scaling parameters, dimensional scaling, erate product performance improvements. Transistor gate delay performance scaling and energy scaling will all run into hard has reduced by almost an order of magnitude and switching roadblocks around this point. This is not to say that some form of energy has improved by a factor of 50 between 0.5- m and CMOS scaling could continue beyond this point with a limited 0.13- m generations (assuming W m and 0.13 m benefit (e.g., dimensional scaling with a performance penalty, for each respective generation). The even smaller devices or energy scaling with a performance penalty). Other good pa- plotted in Figs. 4 and 5 suggest that scaled MOS transistors pers discussing the ultimate limits of Si MOSFET scaling are will continue to provide expected improvements in delay and references [38] and [39]. energy for some time to come. However, there are emerging signs that MOS transistors are reaching their scaling limit. Scaled MOS transistors require reduced threshold voltage (V ) III. LOGIC APPLICATIONS that leads to higher subthreshold leakage current (I ). As shown in Table I, typical 0.13 m generation transistors have To illustrate the fundamentals of logic circuits we will use the I values of 10 nA/ m, more than a 100 increase over circuit example in Fig. 6 and look at only first-order effects to 0.5- m generation transistors. This trend may be unavoidable estimate circuit speed (admittedly a very rough estimate). This for MOS technology as indicated by all the sub-40 nm transistor is the simplest of circuits having one inverter (INV ) driving publications in Fig. 4 having I values of 100 nA/ mor the input of a second inverter (INV ). In real logic products, NAND, NOR and other more complex logic functions would be more. It is doubtful whether future microprocessors with a commonly used, but the circuit operation principles are sim- billion transistors can tolerate leakage values of more than a ilar. In the case where INV is trying to pull down the input few hundred nA/ m due to standby power limitations. Another of INV , transistor N is trying to discharge the input capaci- limiter to MOSFET scaling is gate oxide scaling. Today’s tance of INV ( ), which consists roughly of the gate capac- 0.13- m technologies use SiO gate dielectrics as thin as itance of transistors N and P . We will initially assume that 1.5 nm [23], less than seven atomic layers thick. Gate oxide the resistance (R ) and wire capacitance (C ) of the in- leakage is increasing exponentially with each new generation terconnect between the two inverters is negligible. We will as- due to oxide thickness scaling and is beginning to approach sume this problem is being solved for a microprocessor built transistor subthreshold leakage values ( 1 nA/ m). To address on a 0.13 m process with transistor characteristics as summa- this limitation, a significant amount of research is underway rized in Table I and operating at a 1 GHz clock frequency (1 ns on high- gate dielectrics to replace SiO [29]–[31]. The clock cycle). Modern microprocessors typically have 20 logic controllability of MOSFET device characteristics at very small stages in every clock cycle, therefore, each logic stage needs to dimensions will become an issue due both to lithography be completed in 50 ps on average. For the example in Fig. 6, variation and random dopant fluctuation in channel regions af- W of N is 0.13 m and, thus, has a drive current of 0.1 mA. fecting V control [32] and [33]. Despite these serious scaling would be the combined gate capacitance of the two transistors in concerns, novel 3-dimensional double gate transistor structures INV , but logic circuits more typically have a fanout of 4 (i.e., are emerging [34]–[37] that could push MOS technology 4 gate inputs on every gate output), so we will use 4 the indi- beyond limits foreseen for traditional planar bulk CMOS. vidual gate capacitance (0.12 fF) for . Using the delay BOHR: NANOTECHNOLOGY GOALS AND CHALLENGES FOR ELECTRONIC APPLICATIONS 59 metric, each stage will take 0.48 fF 1.2 V/0.1 mA 5.8 ps, TABLE II well below the goal of 50 ps. SEMICONDUCTOR MEMORY ATTRIBUTES The situation is more challenging when interconnect capac- itance is included. Interconnects on modern technologies have a capacitance per unit length of 0.2 fF/ m. Some may have lengths on the order of 1 mm, which would have a C of 200 fF, far outweighing and resulting in a stage delay of 2.4 ns, far slower than needed. To adjust the circuit to drive this interconnect dominated load, the W of the inverter transistors can be increased, in this case to 6.5 m, to increase drive cur- rent and achieve a stage delay of 50 ps. Now let us consider the impact of interconnect resistance (R ). The resistance per unit length of copper interconnects on 0.13- m technologies is 0.3 / m, thus, a 1 mm wire will have a resistance of 300 . This is negligible resistance compared to the channel resistance of a 0.13- mW transistor (12-k ), but is comparable to the channel resistance of a 6.5- mW transistor (240 ). Now the speed of this logic stage is no longer dominated, but is be- coming dominated. At this point a circuit designer’s job gets interesting! The point of the above analysis is to show that logic operations are primarily a task of charging and discharging parasitic capacitance while propagating signals through various logic functions. Logic transistors need low input capacitance, high output conductance, a voltage gain of at least 1, low standby leakage, and a minimal switching energy. For 0.13- m generation transistors with a minimum W , 900 electrons (or holes) are needed on the gate electrode to provide a drive current of 6.5 10 electrons per second. For the gate Fig. 7. DRAM circuit schematic (2 memory cells depicted). dominated example above, the total charge packet on the output of INV is 3600 electrons. For the interconnect dominated is nonvolatile and does not require refresh, but access time is example above, the total charge packet on the output of INV is slow, program/erase time is very slow and the cell wears out 1.5 10 electrons. The size of these charge packets has been after 10 –10 program/erase cycles. decreasing as MOS technologies scaled, but the need will likely DRAM operates by storing charge in individual storage ca- always be for packets with many electrons as opposed to few pacitors with a capacitance of C and each is accessed electrons to avoid signal noise and thermal noise limitations. through a transistor connected to an array of bit lines and word Having to move millions of these charge packets at ever higher lines as illustrated in Fig. 7. In order for the to have frequencies has led to much higher CPU power levels, soon a long refresh time, the leakage of the access transistor must be surpassing 100 W [40], which intensifies the need to reduce very low ( 1 pA/ m) and, thus, have a relatively high threshold transistor switching energy. However, CPU performance and voltage ( 0.5 V). The leakage requirements for DRAM tran- power improvements are becoming increasingly limited by the sistors are much more stringent than for logic transistors. As a interconnects as opposed to the transistors [41] and [42]. As we result, DRAM transistors have not scaled as fast as logic tran- look forward to nanotechnology options for logic applications, sistors and generally have longer channel lengths, thicker gate both transistor and interconnect requirements need to be oxides and higher operating voltages. During DRAM operation, comprehended. charge stored on C is dumped onto a bit line by turning on the access transistor. The bit line is shared with a number of other cells (typically 128–512), which leads to an unavoidable para- IV. MEMORY APPLICATIONS sitic bit line capacitance (C ) coming from transistor junction Three types of memory devices are most commonly used in capacitance and bit line wire capacitance. C needs to be as large semiconductor products today: dynamic RAM, static RAM and as possible to in order to create a large enough signal ( 100 mV) Flash Memory. The key attributes of each are listed in Table II. on the bit line for the sense to detect. C also needs to DRAM has a small cell size and reasonable access time, but will be large enough to minimize the sensitivity of the cell to ionizing lose its stored information when the power supply is removed radiation such as alpha particles and cosmic rays. Ionizing radia- (a volatile memory) and will also lose charge during normal tion can corrupt the stored information in a bit resulting in unac- operation due to cell leakage, thus, the information in each cell ceptably high soft error rates. Typical C values are in the range must be refreshed more than once per second. SRAM has the of 20–30 fF and cell operating voltage is 2 V providing storage fastest access time and does not require refresh, but is volatile charge packets of 300 000 electrons. C values have remained and has the largest cell size. Flash memory has a small cell size, fairly constant over many generations of DRAM technology and 60 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 1, MARCH 2002

Fig. 9. Flash memory circuit schematic (2 memory cells depicted).

Fig. 8. 6-T SRAM cell circuit schematic (1 memory cell depicted). tunneling oxide suggest that the Flash cell may not be scaled for very much longer. As a result, other nonvolatile memory tech- nologies are being actively investigated such as: ferroelectric have done so while scaling cell size by first scaling the capac- RAM [45] and [46], magnetic RAM [47] and [48] and ovonic itor dielectric thickness in planar , then converting to memory which is based on a heat-induced phase change of a 3-dimensional capacitor structures such as trench capacitors and chalcogenide alloy [49]. stacked capacitors, and more recently by incorporating high- dielectrics in the capacitor [43]. Despite these impressive inno- vations, some believe that the DRAM memory cell will not scale V. N ANOTECHNOLOGY OPTIONS much further due to the inherent need to maintain a minimum Exciting progress has been made over the past year in C and provide low leakage access transistors. demonstrating carbon nanotube FETs with reasonable tran- SRAM memory cells are commonly used as on-die cache sistor characteristics [50] and [51]. Reference [50] even memories on microprocessors. Although this memory cell is demonstrated functioning logic elements and an SRAM the largest of the three options, the access time is the fastest memory cell, albeit using -transistor logic because and the process requirements are generally the same as for logic only p-channel devices were available. Drive current of these devices. The 6-transistor structure of the SRAM cell is illus- transistors is low because the channel width is defined by the trated in Fig. 8. Of importance to the operation of this cell is carbon nanotube width (1.0–1.4 nm), but when calculated in that the two cross-connected inverters have well-matched tran- units of mA/ m, these devices are beginning to approach what sistor characteristics. A growing concern here is the increased Si MOSFETs can do. I /I ratios are a healthy 10 , about variability of threshold voltage caused by random dopant fluc- the same as modern MOSFETs. However, it is still not clear tuation. If transistors N and N have different V s (due to RDF how carbon nanotube FETs will scale and whether they will be or other defects), the cell will not be balanced and will be stuck capable of surpassing Si MOSFETs with L values of 50 nm. in either the “1” or “0” state. Large memory arrays on future Key problems with carbon nanotubes at this point include the technologies could end up having a noticeable percentage of difficulty of forming low resistance contacts and difficulty their bits fail due to RDF. Another concern with scaled SRAM forming nanotubes with the desired physical features (length, cells is their increased sensitivity to ionizing radiation and the chirality, single versus double walled). Also, the question of resultant increased soft error rate as feature size and operating how to position large numbers of these nanotubes where you voltage scale. want them in a cost-effective way remains unanswered. Flash memory cells operate on the principle of storing charge Functioning FETs and logic elements have also been demon- on a floating gate between the normal gate electrode and channel strated using a combination of Si and GaN nanowires [52]. In region of a MOSFET (see Fig. 9). Flash memory arrays have two this case drive currents are still 10 lower than Si MOSFETs, different configurations: NOR and NAND. NOR cells use channel but the I /I ratio is a respectable 10 . This approach has hot electron injection to program the floating gate. NAND cells the advantage of having both W and L dimensions defined use Fowler–Nordheim tunneling to program the floating gate. by molecular dimensions, as opposed to lithography. Both NOR and NAND cells use Fowler–Nordheim tunneling to Single electron transistors (SETs) is another class of devices erase the cell. The presence or absence of the stored charge that may be applied to logic [53] and [54] or memory [55] and changes the V of the cell transistor, which can be detected by [56] circuits. Such devices are inherently very small, but appear sensing the current through the bit line while accessing the cell. to face many technical hurdles. In order to achieve room tem- Some Flash technologies store different amounts of charge on perature operation, the conducting islands (or quantum dots) the floating gate to allow two bits of information to be stored need to be very small, on the order of one nanometer. This is in each cell [44]. Both hot electron injection and tunneling pro- beyond what any envisioned lithographic technology can do, cesses are slow, resulting in typical program times of 1 s and so some type of chemical self-assembly technique is required 10 ms respectively. The tunneling oxide must be thin enough for their mass fabrication. These devices are very sensitive to for reasonable program/erase times, but not so thin as to cause random background charge and their peak-to-valley current ra- the charge to eventually leak off. The tunneling oxide must also tios (similar to MOSFET I I ) are only in the range of be robust enough to tolerate 10 program/erase cycles during 10–100. An SET feature that is very useful for logic applications the life of the product. These very stringent requirements for the is that voltage gain and transconductance can change sign with BOHR: NANOTECHNOLOGY GOALS AND CHALLENGES FOR ELECTRONIC APPLICATIONS 61

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