DOCSLIB.ORG

Electronic Design & Fabrication

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Electronic Design & Fabrication Oklahoma State University EET 3124 - Electronic Design & Fabrication Techniques Fall 2019 4 Credit Hours and 6 Contact Hours Instructor: Mr. Brian Norton, M.S., P.E. 557 Engineering North, Phone: 405-744-7618 Email: [email protected] Text Understanding NEC Requirements for Grounding vs. Bonding, ISBN: 978-1932685787 Required Course Material You are responsible for purchasing all tools, materials, components, boards, and any other items necessary to complete your design and project build. Software Used for Class NI Multisim and Ultiboard or AutoCad Eagle (These programs are available through CEAT IT as a free distribution) Prerequisites EET 1244, EET 2544 and EET 2635 or equivalents MANDATORY SAFETY TRAINING All Students, TAs, and professors must watch the ENDEAVOR safety orientation and pass the quiz. The Orientation and Quiz can be found on the CEAT ENDEAVOR and NCL Canvas site. Directions – (canvas.okstate.edu) 1. Go to the dashboard and select the CEAT ENDEAVOR and NCL Canvas site 2. Join the site (highlighted in yellow) 3. Go to the Safety Orientating and Quiz page and follow the directions Course Material EET 3124 is a required course for the Electrical Engineering Technology program. This course has three major components. 1) The first portion of the class will cover the safety issues of Bonding and Grounding techniques based on NEC code. 2) Second is the discussion and practice of the techniques of electronic system design and fabrication. Instruction includes the design process from abstract idea to final assembly and testing. Areas covered are Computer Aided Design (CAD) software including schematic layout and printed circuit board design layout, project design considerations, prototyping techniques, soldering and wire Page 1 of 7 wrapping, equipment packaging, hazardous materials, and interconnection techniques. 3) The third portion of the course is a review and evaluation of your retention and application of the knowledge and skills you have acquired in the EET program’s first two years of class work. The evaluation will consist of a comprehensive exam of your first two years of course work. Failure to successfully complete this exam may mean you will be required by the EET program to take remedial coursework before you will be allowed to complete the EET program.. RELATIONSHIP OF COURSE TO EET PROGRAM OUTCOMES 3 = Strong Emphasis, 2 = Some Emphasis, 1 = Little or No Emphasis. (1) an ability to apply knowledge, techniques, skills and modern tools of mathematics, science, engineering, and technology to solve broadly-defined engineering problems appropriate to the discipline; 1 (2) an ability to design systems, components, or processes meeting specified needs for broadly-defined engineering problems appropriate to the discipline; 1 (3) an ability to apply written, oral, and graphical communication in broadly defined technical and non-technical environments; and an ability to identify and use appropriate technical literature; 2 (4) an ability to conduct standard tests, measurements, and experiments and to analyze and interpret the results to improve processes; and 2 (5) an ability to function effectively as a member as well as a leader on technical teams. 2 GRADING PROCEDURES: Examinations: There will be approximately 3 examinations scheduled for the course, including the comprehensive review exam. It is your responsibility to be present for all announced exams. If you know beforehand of any absences, inform me by email so I will have the opportunity to schedule any exams around that absence. Quizzes: There may be occasional quizzes given during class periods. If you miss a quiz it will not be made up, unless you have arranged with me beforehand an excused absence for that class. Project: A project will be assigned for the class. You will design, build and manufacture a project. Milestones will be given for the project with hard due dates. A final project Page 2 of 7 report is due at the end of the semester and will be of you own work. If you miss a deadline a grade reduction will be given for that report or milestone. If for any reason you fail your semester project assignment you will be given a grade of “F” for the class. Assignments It is your responsibility to remain current in this course. All assignments are due at the date given. Late work will be penalized severely. If you have an issue in getting an assignment completed on time contact the instructor before the due date. Incomplete work is not acceptable. Summary of Points: Exams, Quizzes 50% Project 50% A= 90 to100% B= 80 to 89% F= Below 60% C= 70 to 79% D= 60 to 69% Drop Policy and Academic Misconduct: You must do your own work. Software files and/or other materials copied from another person’s work and claimed as your own is grounds for a letter of academic misconduct. If evidence shows you have engaged in this type of activity you may receive a letter of misconduct and receive a zero for that portion of the course. You are encouraged to work together and learn how to solve problems. However, your hands must do the actual work whether it be drawing a schematic or soldering a circuit board. Important Dates 20 Aug – Explore the Syllabus 22 Aug – Grounding, Bonding and the NEC 27 Aug – Grounding, Bonding and the NEC https://www.youtube.com/watch?v=mpgAVE4UwFw 29 Aug – Grounding, Bonding and the NEC https://www.youtube.com/watch?v=3vvvv5QVZoA&t=167s 3 Sept – Grounding, Bonding and the NEC, https://www.youtube.com/watch?v=Yg6G5VUSsWA&t=19s 5 Sept – Exam One 10 Sept – Assignment of Semester Project 12 Sept – Schematic Capture in Eagle 17 Sept – Board Layout in Eagle 19 Sept – Planning and Designing a Board 24 Sept – BOM Due, Package Design 26 Sept – Schematic Due, Cableing 1 Oct – Board Layout Due, Milling a PCB, Class will be held in END 330 3 Oct – Class Decision on Board Layout and BOM, Soldering Page 3 of 7 8 Oct – Soldering 10 Oct – Soldering 15 Oct – PCB Materials 17 Oct – Single Sided PCBs 22 Oct – Multilayer PCBs 24 Oct – PCB Hardware and Component Assembly 29 Oct – Heat Sinks 31 Oct – Heat Sinks 5 Nov – Thru-Hole Mounted Components 7 Nov – Surface Mounted Components 8 Nov – Last Day W with No Grade 12 Nov – Review for Exam Two 14 Nov – Exam Two 19 Nov – Project Report Description 21 Nov – Review For Comprehensive Exam, dc Circuit Analysis 22 Nov Last Day W with Grade 26 Nov – Review For Comprehensive Exam, ac Circuit Analysis 3 Dec – Review For Comprehensive Exam, Analog Devices 5 Dec – Review For Comprehensive Exam, Digital Logic 12 Dec (Thursday 8AM) Final Exam and Project Report Due with Completed Instrument Page 4 of 7 Who Am I I grew up in the Oklahoma Panhandle town of Beaver. That has influenced who I am as any of could say were you lived as a child; has had influence over you. After graduating from high school; I attended a small Bible College in Oklahoma City. A couple of years after that I married my wife Sherri. We have been married since 1982. Our son Rusty was born in 1994 and he is married to Kourtney and they have a beautiful girl named McKinley. My wife and I served in church ministry for a few years after we were married. Then I decided to go back to school to be an engineer. In May of 1991, Oklahoma State University graduated me with a B.S. in Electrical Engineering Technology. Upon receiving that diploma, Texas Instruments in Midland TX was the next stop. From there I went to Washington State University and earned a M.S. in Electrical Engineering degree. Upon graduating from WSU, I taught in a Junior College in Pendleton, Oregon; worked at a U.S. government nuclear site in Washington state and also spent some time oversees performing contract engineering work, spending your parents tax money. While in Thailand, I found an add for a position at OSU in the EET program and applied for the job. For some reason OSU hired me to be a professor of EET. I have been here since January 2007 and teaching is still fun for me and I hope it is profitable for you, my students. Just to let you know when I was studying here at OSU for the EET degree it was not easy especially at first. I did not have the best study habits to begin an engineering plan of study. That first year could have been better. In EET 1104 which you are taking now I worked very hard to earn a ‘B’ for the semester and did not understand the material very well. Starting the next semester the material was still difficult. During that second semester I started to figure out what it took to be successful and developed better study habits. By the end of the second semester I felt like for the first time I was understanding the material. So, if while you are doing homework and attending lectures you feel like you are not understanding the material; do not feel that you are alone in that predicament. There is one more important personal fact about me that I want you to know, for two reasons (1) so that you will understand where I am coming from and (2) so that I will be accountable, and be consistent with my belief system. I have considered many of the religions and philosophies of the world and have become convinced that the way of Jesus of Nazareth provides meaningful answers to life’s most important questions, most of which are not found at the back of an engineering text. Because I have considered thoughtfully many options and have examined evidence, I call myself a “convinced believer in Jesus.” While belief is by faith, faith in my view; is not believing in something without evidence.
Load more

Recommended publications
  • Kenntnisse Engineering & IT
    Kenntnisse Engineering & IT IT-Fähigkeiten Version* Dauer** Niveau*** IT-Fähigkeiten Version* Dauer** Niveau*** Delphi PL/1 Designer/2000 PLA Developer/2000 PL/SQL EJB Pascal Eclipse AIX Enterprise Architect Android Erwin BS2000 Fortran CICS Free Pascal Echtzeit-Betriebssysteme GNU Debugger (gdb) HP-UX GNU Compiler Linux HTML MS Windows Hibernate MS Windows 98 Interactive Disassembler MS Windows CE ISO 12207 MS Windows NT ISO 15504 MS Windows Server 2003 ITIL MS Windows Vista Intel C++ Compiler MS Windows XP/2000 iTRACE MS Windows 7 JCreator MS Windows Server 2008 Jdeveloper MS Windows Mobile/Phone Junit MVS J2EE MAC OS X JAVA OS/2 JSP OS/400 JavaScript SCO Unix Jikes Sinix Kernel Debugger (kdb) Sun Solaris Lisp Symbian OS Lauterbach Debugger Unix LotusScript VMS MFC MS Visual C++ Betriebssysteme Version* Dauer** Niveau*** Adobe Flash MS Windows 98 HP Quality Center MS Windows CE HP Testdirector MS Windows NT HP Winrunner MS Windows Server 2003 Modula MS Windows Vista Natura MS Windows XP/2000 Net Beans MS Windows 7 OCX MS Windows Server 2008 OOA MS Windows Mobile/Phone OOD MVS Motif MAC OS X OSI-Modell OS/2 OWL OS/400 OllyDbg SCO Unix PHP Sinix *Version: letzte Version angeben **Dauer: < 6 Monate, 6 – 12 Monate, > 12 Monate ***Niveau: wählen aus Grundlagen, Erweitert oder Fortgeschritten Betriebssysteme Version* Dauer** Niveau*** SIGRAPH Sun Solaris SmartPlant Symbian OS Solid Designer Unix Solid Edge VMS SolidWorks Tribon CAD Version* Dauer** Niveau*** NX Unigraphics Advance Steel WSCAD Altium Designer AutoCAD Datenbanken Version* Dauer**
    [Show full text]
  • Удк 62-82:658.512.011.56 Ляпин П.С., Мельничук Р.М
    УДК 62-82:658.512.011.56 ЛЯПИН П.С., МЕЛЬНИЧУК Р.М., ФИНОГЕНОВ А.Д. ГРАФИЧЕСКИЕ РЕДАКТОРЫ ДЛЯ СХЕМОТЕХНИЧЕСКОГО ПРОЕКТИРОВАНИЯ Целью статьи является формирование общих требований для разработки редактора электронных схем в рамках создания средств автоматизированного проектирования с доступом через Internet. На основе анали- за существующих решений в данной области предложен набор стандартных функций, необходимых инже- неру-разработчику и приоритетных для реализации в веб-редакторе. The purpose of this paper is the establishment of common requirements for the design editor of electronic cir- cuits in a computer-aided design tools to access the Internet. Analysis capabilities available today decisions in this field will conclude on a set of standard functions necessary development engineer and priorities for implementation in a web editor. 1. Введение – ГСР общего назначения. Под специализированными ГСР будем История разработки специализированных понимать схемные редакторы, которые входят графических редакторов насчитывает не одно в состав программных средств EDA (Electronic десятилетие. Параллельно с усовершенствовани- Design Automation). Комплексы EDA предна- ем аппаратных средств и, в первую очередь, значены для облегчения разработки электрон- средств визуализации, менялись и подходы к со- ных устройств, создания микросхем, печатных зданию графического интерфейса пользователя и плат [1]. Типичным представителем данного в частности схемных редакторов. Наличие ре- класса графических схемных редакторов явля- дактора на сегодняшний день стало стандартом ется OrCAD [2]. де-факто для САПР. К ГСР общего назначения относятся ре- Одним из современных направлений развития дакторы, которые помимо графических при- САПР является создание веб-средств проектиро- митивов и текста позволяют использовать вания (не путать со средствами веб- различные символические объекты, в том проектирования), что, соответственно, влечет за числе и элементы принципиальных электри- собой необходимость в создании соответствую- ческих схем, и не направлены на дальнейшую щих графических редакторов.
    [Show full text]
  • NI Circuit Design Suite Professional Edition Release Notes (Trilingual)
    PROFESSIONAL EDITION RELEASE NOTES NI Circuit Design Suite Version 10.1.1 These release notes contain system requirements for NI Circuit Design Suite 10.1.1, and information about product tiers, new features, documentation resources, and other changes since NI Multisim 10.1 and NI Ultiboard 10.1. NI Circuit Design Suite includes the familiar NI Multisim and NI Ultiboard software products from the National Instruments Electronics Workbench Group. The NI Multisim MCU Module functionality is now included with NI Multisim. Contents Installing NI Circuit Design Suite 10.1.1................................................ 2 Minimum System Requirements ..................................................... 2 Installation Instructions.................................................................... 3 Product Activation ........................................................................... 3 What’s New in NI Circuit Design Suite 10.1.1....................................... 3 Locking Toolbars............................................................................. 4 Advanced Multisim Component Search .......................................... 4 Units for RLC Components ............................................................. 4 Default Background Color for Instruments and Grapher ................ 5 No Automatic Rewire of Large Pin-Count Components................. 5 Improved Parameter Support for Semiconductor Devices .............. 5 Added Support for Cadence® PSpice® Temperature Parameters .... 6 Improvements to SPICE DC Convergence
    [Show full text]
  • Visible Light Communication an Alternative to the Wireless Transmission with RF Spectrums Through Visible Light Communication
    Visible Light Communication An alternative to the wireless transmission with RF spectrums through visible light communication. University of Central Florida Department of Electrical Engineering and Computer Science EEL 4915 Dr. Lei Wei, Dr. Samuel Richie, Dr. David Hagen Senior Design II Final Paper Documentation Group 12 – CREOL Garrett Bennett Photonic Science and Engineering Benjamin Stuart Photonic Science and Engineering George Salinas Computer Engineering Zhitao Chen Electrical Engineering i Table of Contents 1. Executive Summary 1 2. Project Description 3 2.1 Project Background 3 2.1.1 Existing Projects and Products 3 2.1.2 Wireless Optical Communication 6 2.2 Objectives 7 2.2.1 Motivation 7 2.2.2 Goals 8 2.3 Requirements Specifications 8 2.4 Market and Engineering Requirements 8 2.5 Distribution and Hierarchical Layout 10 2.5.1 Contribution Breakdown 11 2.6 Design Comparison 11 3. Research related to Project 13 3.1 Relevant Technologies 13 3.1.1 Transmitter Technology 13 3.1.2 Receiver Technology 23 3.1.3 Detection Statistics 28 3.1.4 Electrical Processing 29 3.2 Strategic Components and Part Selections 30 3.2.1 Differential Receiver Amplifier 30 3.2.2 Operational Amplifier 34 3.2.3 Differential Driver 38 3.2.4 Comparator 40 3.2.5 Voltage Converters 42 3.2.6 LED 46 3.2.7 Photodiode 47 3.2.8 Laser Criteria 48 3.2.9 Focusing Optics 51 ii 4. Related Standards and Realistic Design Constraints 54 4.1 Standards 54 4.1.1 IEEE 802.3i 54 4.1.2 Design Impact of IEEE 802.3i standard 54 4.1.3 IEEE 802.15.7 55 4.1.4 Design Impact of IEEE 802.15.7
    [Show full text]
  • ECE203 Lab Manual
    ECE 203 — DC CIRCUITS LABORATORY MANUAL Rose-Hulman Institute of Technology Spring 2016-2017 ECE 203 – DC Circuits Spring 2016 This page intentionally left blank ECE203 DC Circuits Laboratory Manual 2 ECE 203 – DC Circuits Spring 2016 ECE 203 DC Circuits Laboratory Manual Table of Contents Lab 0 Laboratory Introduction ........................................................................................ 5 1.0 Purpose of Laboratories .................................................................................... 5 1.1 Familiarity with equipment ................................................................................. 5 1.2 Tie-in to theory .................................................................................................. 5 1.3 Develop problem-solving skills .......................................................................... 5 2.0 Materials............................................................................................................ 5 3.0 Equipment ......................................................................................................... 5 4.0 What is Expected of You ................................................................................... 5 5.0 Lab Journal ....................................................................................................... 6 6.0 Circuit Diagrams ................................................................................................ 7 7.0 Tables & Graphs ..............................................................................................
    [Show full text]
  • Scientific Tools for Linux
    Scientific Tools for Linux Ryan Curtin LUG@GT Ryan Curtin Getting your system to boot with initrd and initramfs - p. 1/41 Goals » Goals This presentation is intended to introduce you to the vast array Mathematical Tools of software available for scientific applications that run on Electrical Engineering Tools Linux. Software is available for electrical engineering, Chemistry Tools mathematics, chemistry, physics, biology, and other fields. Physics Tools Other Tools Questions? Ryan Curtin Getting your system to boot with initrd and initramfs - p. 2/41 Non-Free Mathematical Tools » Goals MATLAB (MathWorks) Mathematical Tools » Non-Free Mathematical Tools » MATLAB » Mathematica Mathematica (Wolfram Research) » Maple » Free Mathematical Tools » GNU Octave » mathomatic Maple (Maplesoft) »R » SAGE Electrical Engineering Tools S-Plus (Mathsoft) Chemistry Tools Physics Tools Other Tools Questions? Ryan Curtin Getting your system to boot with initrd and initramfs - p. 3/41 MATLAB » Goals MATLAB is a fully functional mathematics language Mathematical Tools » Non-Free Mathematical Tools You may be familiar with it from use in classes » MATLAB » Mathematica » Maple » Free Mathematical Tools » GNU Octave » mathomatic »R » SAGE Electrical Engineering Tools Chemistry Tools Physics Tools Other Tools Questions? Ryan Curtin Getting your system to boot with initrd and initramfs - p. 4/41 Mathematica » Goals Worksheet-based mathematics suite Mathematical Tools » Non-Free Mathematical Tools Linux versions can be buggy and bugfixes can be slow » MATLAB
    [Show full text]
  • Računalniško Podprto Načrtovanje Digitalnih Struktur Računalniško Podprto Načrtovanje Dig
    Računalniško podprto načrtovanje digitalnih struktur Računalniško podprto načrtovanje dig. struktur Pregled programskih orodij • minimizator (angl. minimizer) je programsko orodje za avtomatizirano poenostavljanje preklopnih funkcij •z urejevalnikom shematskih prikazov (angl. schematic editor) izrišemo simbolno shemo vezja • simulator vezij (angl. circuit simulator) omogoča simulacijo in analizo delovanja načrtovanega vezja •v strojno opisnem jeziku (angl. hardware description language, HDL) opišemo gradnike vezja in povezave med njimi v obliki, ki omogoča realizacijo vezja s programirljivo makrostrukturo • sintetizator geometrije (angl. layout designer) izdela načrt postavitve elementov in povezav na nivoju tiskanega vezja (postavitev integriranih vezij in ostalih komponent na tiskani plošči, angl. PCB layout) ali na nivoju integriranega vezja (postavitev tranzistorjev in ostalih elementov v čipu, angl. IC layout) Računalniško podprto načrtovanje dig. struktur Minimizatorji • minimizatorji omogočajo poenostavljanje preklopnih funkcij z različnimi metodami minimizacije (Quine-McCluskeyev algoritem, Petrickova metoda, algoritem Espresso, ...), prevedbe operatorjev (AND-OR ↔ OR-AND ↔ XOR ↔ NAND ↔ NOR ...) in realizacije funkcij (z MUX, PROM, PAL ...): - Logic Friday*(http://sontrak.com/download_lf.aspx) - Minilog*(http://www.brothersoft.com/minilog-download-26547.html) - ... • mnoga programska orodja za simulacijo in sintezo že vsebujejo algoritme za minimizacijo in prevedbo funkcij; če imamo na razpolago takšno orodje, ne potrebujemo ločenega
    [Show full text]
  • An Oversampled Analog to Digital Converter for Acquiring Neural Signals Grant Williams Washington University in St
    Washington University in St. Louis Washington University Open Scholarship All Theses and Dissertations (ETDs) January 2009 An Oversampled Analog To Digital Converter For Acquiring Neural Signals Grant Williams Washington University in St. Louis Follow this and additional works at: https://openscholarship.wustl.edu/etd Recommended Citation Williams, Grant, "An Oversampled Analog To Digital Converter For Acquiring Neural Signals" (2009). All Theses and Dissertations (ETDs). 462. https://openscholarship.wustl.edu/etd/462 This Thesis is brought to you for free and open access by Washington University Open Scholarship. It has been accepted for inclusion in All Theses and Dissertations (ETDs) by an authorized administrator of Washington University Open Scholarship. For more information, please contact [email protected]. WASHINGTON UNIVERSITY IN ST. LOUIS School of Engineering and Applied Science Department of Electrical and Systems Engineering Thesis Examination Committee: Robert E. Morley, Jr Daniel L. Rode R. Martin Arthur AN OVERSAMPLED ANALOG TO DIGITAL CONVERTER FOR ACQUIRING NEURAL SIGNALS by Grant Taylor Williams A thesis presented to the School of Engineering of Washington University in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE August 2009 Saint Louis, Missouri copyright by Grant Taylor Williams 2009 ABSTRACT OF THE THESIS A Third Order Modulator and Digital Filter for Neural Signals by Grant Taylor Williams Master of Science in Electrical Engineering Washington University in St. Louis, 2009 Research Advisor: Professor Robert E. Morley, Jr. A third order delta-sigma modulator and associated low-pass digital filter is designed for an analog to digital converter (ADC) for sensing bioelectric phenomena. The third order noise shaping reduces the quantization noise in the baseband and the digital low- pass filter greatly attenuates the out of band quantization noise, increasing the effective number of bits.
    [Show full text]
  • Ultiboard Free
    Ultiboard free click here to download Ultiboard is a rapid printed circuit board (PCB) prototyping environment used by engineering professionals, educators, makers, and students across many applications. Its seamless integration with Multisim helps circuit designers save hours of development time with the ability to complete circuit schematics, SPICE. With NI Multisim and Ultiboard, you can complete homework problems faster, prepare for laboratory assignments better, and define entire circuit board design projects easier with the same circuit simulation and design tools used in industry. Only Multisim provides you the complete set of tools to learn analog, digital, and. The NI Circuit Design Suite update brings quality improvements, new database parts and new features. For more information, read the New Features and Improvements section in the Help file. Soon thereafter, ULTIboard became marketing leader in Europe in the field of PC based PCB design products. The company held worldwide User Meetings where customers could attend free and even got a free gourmet lunch. Optionally, customers could take an afternoon training to get up and running with the latest. NI Ultiboard software helps students learn about the layout process and industry practices by providing a flexible environment for PCB layout and routing. Students can retrieve designs from NI Multisim interactive SPICE-based simulation or begin from scratch using parts from the built-in Ultiboard database. MultiSim 11 Ultiboard PowerPro Free Download Latest Version for Windows. It is full offline installer standalone setup of MultiSim 11 Ultiboard PowerPro. NI Multisim Ultiboard Electronics Circuit Design Suite 14 Free Download. Apart from this it can also be used for creating schematic with the help if library component.
    [Show full text]
  • Aditya Sharma
    ADITYA SHARMA 2073 W Lindsey St, Apartment Number 2059F [email protected] Norman, OK 73069 405-510-9942 EDUCATION QUALIFICATIONS & TRAINING PhD in Petroleum Engineering (August 2019-Present) University of Oklahoma, Norman, Oklahoma Master of Science in Electrical and Computer Engineering (Graduation: May2019) University of Oklahoma, Norman, Oklahoma GPA: 3.55/4.00 Bachelor of Engineering in Electronics & Communication Engineering (Graduation: July 2016) Chitkara University, Baddi, Himachal Pradesh, India CGPA: 8.02/10.00 Six Weeks Training on Embedded Systems Design (June-July 2014) NIELIT, Chandigarh, India RELEVANT EXPERIENCE • Graduate Research Assistant: • Petroleum and Geological Engineering Production Research Lab (January 2019–Present): Design and implementation of instrumentation and control setup to analyze the vibration of a drill string. Equipping a scaled drilling rig setup with sensors, interfacing it with a data acquisition system and designing a LabVIEW VI to monitor and control the system. • Laboratory for Electrical Energy and Power Systems (September 2018–May 2019): Design and implementation of instrumentation and control setup to study the effects of Geomagnetically Induced Current on a Power Transmission System. Building control panel, interfacing various sensors with NI data acquisition devices to analyze power dynamics and designing a LabVIEW VI to monitor and control the system. • Graduate Teaching Assistant: Graduate teaching assistant for Digital Design Lab (Spring 2017, Spring 2018, Fall 2018) and Energy Conversion (Spring 2018). • Internship at Bharat Electronics Limited, Panchkula, Haryana. (January-May 2016): Bharat Electronics Limited (BEL) is a company owned by the Indian Government which primarily manufactures advanced electronic equipment for Defense Forces. Analysis of circuits, soldering circuit boards and the testing of the manufactured equipment was done.
    [Show full text]
  • NI Multisim - Electronic Design, Circuit Simulation and Prototyping
    NI Multisim - Electronic Design, Circuit Simulation and Prototyping Patrick Noonan Business Development Manager Electronics Workbench Tools Integrated Design Flow | Simulation and Virtual Instrumentation Design Environment Part Schematic Design Layout & Prototype Test Evaluation & Capture Simulation Routing & Validation Research NI Multisim NI Ultiboard NI LabVIEW • Integrated capture and simulation Flexible, easy-to-use PCB layout tool • Graphical development environment environment Design tools optimized for manual control or • Tight integration of real-world I/O automated speed • Easy measurement analysis, and • Interactive mixed-mode simulation Integration with NI Multisim data presentation • 20 SPICE Analyses ni.com/ultiboard • ni.com/labview • 22 Measurement Instruments • ni.com/multisim National Instruments Confidential 2 NI Multisim | Schematics Simulation and Analysis • Graphical based schematic capture and integrated simulation . Rapidly build and simulate circuits . Analog and Digital co-simulation (SPICE/XSPICE) • Thousands of components immediately ready for simulation . Place components, wire and click run to start the simulation • Integration with Measurements . Simulation is an mathematical approximation . Measurements are the REAL answer • Virtual Instruments for immediate testing • Advanced analyses for design validation • Integration with NI Ultiboard for Full PCB Design National Instruments Confidential 3 What is SPICE? | Examples Schematic Representation Equivalent SPICE Netlist 1 Example 1: Voltage divider netlist R1 * Voltage Divider - comment 1kΩ vV1 1 0 12 V1 12 V 2 rR1 1 2 1000 R2 rR2 2 0 2000 2kΩ 0 Example 2: Subcircuit model .subckt biplarjunctiontrans base collector emitter R1 base n100 200 C1 n100 emitter 1.000E-9 D1 n100 emitter DX e1 base n100 collector emitter 12.842917 R2 collector emitter 10 .MODEL DX D(IS=1e-15 RS=1) National Instruments Confidential 4 SPICE and Virtual Instrumentation Simulation, Measurements and Automation • Bring Measurements inside of Multisim .
    [Show full text]
  • Yuniel Freire Hernández.Pdf
    Universidad Central “Marta Abreu” de Las Villas Facultad de Ingeniería Eléctrica Departamento de Telecomunicaciones y Electrónica TRABAJO DE DIPLOMA Simulación de Circuitos Digitales con Software Libre Autor: Yuniel Freire Hernández Tutor: Ing. Erisbel Orozco Crespo Santa Clara 2012 Universidad Central “Marta Abreu” de Las Villas Facultad de Ingeniería Eléctrica Departamento de Telecomunicaciones y Electrónica TRABAJO DE DIPLOMA Simulación de Circuitos Digitales con Software Libre Autor: Yuniel Freire Hernández Tutor: Ing. Erisbel Orozco Crespo Profesor, Dpto. Telec. Y Electrónica Santa Clara 2012 Hago constar que el presente trabajo de diploma fue realizado en la Universidad Central “Marta Abreu” de Las Villas como parte de la culminación de estudios de la especialidad de Ingeniería en Telecomunicaciones y Electrónica, autorizando a que el mismo sea utilizado por la Institución, para los fines que estime conveniente, tanto de forma parcial como total y que además no podrá ser presentado en eventos, ni publicados sin autorización de la Universidad. Firma del Autor Los abajo firmantes certificamos que el presente trabajo ha sido realizado según acuerdo de la dirección de nuestro centro y el mismo cumple con los requisitos que debe tener un trabajo de esta envergadura referido a la temática señalada. Firma del Tutor Firma del Jefe de Departamento donde se defiende el trabajo Firma del Responsable de Información Científico-Técnica PENSAMIENTO No fracasé, sólo descubrí 999 maneras de cómo no hacer una bombilla. Thomas Alva Edison AGRADECIMIENTOS A todos los profesores que brindaron sus conocimientos para mi formación. A mi tutor por su paciencia, esmero y dedicación. A mis amigos y compañeros por resistirme.
    [Show full text]