6.012 - Microelectronic Devices and Circuits Lecture 19 - Differential Amplifier Stages - Outline Announcements Design Problem - coming out tomorrow; PS #10 looks at pieces; neglect the Early effect in large signal analyses Review - Single-transistor building block stages Common source: general purpose gain stage, workhorse
Common gate: small Rin, large Rout, unity Ai, same Av as CS Source follower: large Rin, small Rout, unity Av, same Ai as CS Series and Shunt feedback: we'll see in special situations Differential Amplifier Stages - Large signal behavior General features: symmetry, inputs, outputs, biasing (Symmetry is the key!) Large signal transfer characteristic Difference- and common-mode signals Decomposing and reconstructing general signals Half-circuit incremental analysis techniques Linear equivalent half-circuits Difference- and common-mode analysis Example: analysis of source-coupled pair
Clif Fonstad, 11/17/09 Lecture 19 - Slide 1 Linear amplifier layouts: The practical ways of putting inputs to, and taking outputs from, transistors to form linear amplifiers +V +V There are 12 choices: three possible nodes to connect to the input, and for each one, two nodes from which to take 2 2 an output, and two choices of what to do with the remaining 1 1 node (ground it or connect it 3 3 to something). Not all these choices work IBIAS IBIAS well, however. In fact only -V -V three do: Name Input Output Grounded Common source/emitter 1 2 3 Common gate/base 3 2 1 Common drain/collector 1 3 2 (Source/emitter follower) Source/emitter degeneration 1 2 none
Clif Fonstad, 11/17/09 Lecture 19 - Slide 2 • Three MOSFET single-transistor amplifiers VV++ V+ V+
+ CO CCOO CO vin - + ++ + v vout vout vout v IBIAS - ++ out CI - vvinin -- I -- + + V- IIBIASBIAS v IBIAS vIINN SOURCE FOLLOWER CCE E - Input: gate Output: source V- V- V- Common: drain COMMON SOURCE COMMON GATE Substrate: to source Input: gate Input: source; Output: drain Output: drain Common: gate Common: source Substrate: to ground + Substrate: to source + + + + vin + vout vin vout vout vin ------
Clif Fonstad, 11/17/09 Lecture 19 - Slide 3 • Single-transistor amplifiers with feedback V+ V+
RF CO CO + + v vout + out + vin - vin - - RF - IBIAS IBIAS CE CE
V- V- SERIES FEEDBACK PARALLEL FEEDBACK* RF + + + vout + vout vin vin RF - - - -
Clif Fonstad, 11/17/09 * Also termed "source degeneracy" Lecture 19 - Slide 4 • Summary of the single transistor stages (MOSFET)
Voltage Current Input Output MOSFET gain, Av gain, Ai resistance, Ri resistance, Ro $ ' gm ' 1 Common source " (= "gm rl ) # # ro & = ) [go + gl ] % go ( + . ' 1 [gm + gmb + go] Common gate * [gm + gmb ]rl *1 * * ro,1 + / [gm + gmb ] - gt 0
[gm ] 1 1 Source follower *1 # # * [gm + gmb + go + gl ] [gm + go + gl ] gm
Source degeneracy rl * " # # * ro (series feedback) RF $ ' [gm " GF ] gl 1 1 Shunt feedback " * "gm RF " ro || RF & = ) [go + GF ] GF GF [1" Av ] % [go + GF ](
Power gain, Ap = Av " Ai !
Clif Fonstad, 11/17/09 Note: When vbs = 0 the gmb factors should be deleted. Lecture 19 - Slide 5 ! • Summary of the single transistor stages (bipolar)
Voltage Current Input Output BIPOLAR gain, Av gain, Ai resistance, R i resistance, R o % ( gm ' # gl 1 Common emitter " (= "gm rl ) " r$ ro ' = * [go + gl ] [go + gl ] & go )
gm ' r$ Common base (= gm rl ) +1 + + [# +1]ro [go + gl ] [# +1]
[gm + g$ ] # gl ' rt + r$ Emitter follower +1 + # r$ + [# +1]rl [gm + g$ + go + gl ] [go + gl ] [# +1]
rl Emitter degeneracy + " + # + r$ + [# +1]RF + ro RF % ( [gm " GF ] gl 1 1 Shunt feedback " + "gm RF " ro || RF ' = * [go + GF ] GF g$ + GF [1" Av ] & go + GF )
Power gain, Ap = Av " Ai !
Clif Fonstad, 11/17/09 Lecture 19 - Slide 6 ! Differential Amplifiers: emitter- and source-coupled pairs V+ V+
+ + + + vOUT1 vOUT2 vOUT1 vOUT2 + - - + + - - + vIN1 vIN2 vIN1 vIN2 - - - -
IBIAS IBIAS
V- V- Emitter-coupled pair Source-coupled pair Why do we care? - They amplify only difference-mode signals They are easy to interconnect and cascade They help us eliminate coupling capacitors They are optimally suited to integration
Clif Fonstad, 11/17/09 Lecture 19 - Slide 7 Differential Amplifiers: large signal analysis of source coupled pairs Source-coupled pair Below: Schematic with resistor loads Right: Large signal equiv. circuit in saturation +VDD
RD RD
+ vO - + + M1 vO1 vO2 M2 + - - + vI1 vI2 - - IBIAS
-VSS Analysis:
3 KVL loops: vI1 - vGS1 +vGS2 - vI2 = 0, vO1 = VDD - RDiD1, vO2 = VDD - RDiD2
KCL at one node: iD1 + iD2 = IBIAS 2 2 MOSFET relationships: iD1 = K(vGS1-VT) /2; iD2 = K(vGS2-VT) /2
Clif Fonstad, 11/17/09 (see text for details of analysis) Lecture 19 - Slide 8 Diff. Amps: large signal analysis of source coupled pairs, cont. Results: The outputs again only depend on the difference between
the two inputs, (vI1 - vI2):
2 # K v " v + I ' R % [ IN1 IN 2] BIAS % v = V " D $ ( O1 DD K 4IBIAS 2 2 % + [vIN1 " vIN 2] " [vIN1 " vIN 2 ] % & 2 K ) 2 # K v " v + I ' R % [ IN1 IN 2] BIAS % v = V " D $ ( O2 DD K 4IBIAS 2 2 % " [vIN1 " vIN 2] " [vIN1 " vIN 2 ] % & 2 K )
RDK 4IBIAS 2 vO = " [vIN1 " vIN 2 ] " [vIN1 " vIN 2] 2 K
vo
! Symmetrical
Slope around origin = -gmRD
Clif Fonstad, 11/17/09 Only the difference in the inputs matters!! Lecture 19 - Slide 9 Differential Amplifiers: large signal analysis of emitter coupled pairs Emitter-coupled pair Below: Schematic with resistor loads Right: Large signal equivalent circuit in FAR
+VCC
RC RC
+ v - + O + Q1 vO1 vO2 Q2 + - - + vI1 vI2 - - IBIAS
-V Analysis: EE
3 KVL loops: vI1 - vBE1 +vBE2 - vI2 = 0, vO1 = VCC - RCαFiF1, vO2 = VCC - RCαFiF2 KCL at one node: iF1 + iF2 = IBIAS Ideal diode relationships: iF1 ≈ IES exp (qvBE1/kT), iF2 ≈ IES exp (qvBE2/kT) (see text for details of analysis) Clif Fonstad, 11/17/09 Lecture 19 - Slide 10 Diff. Amps: large signal analysis of emitter coupled pairs, cont. Results: The outputs only depend on the difference between the inputs, (v - v ): F RC IBIAS I1 I2 vO1 = VCC [1+ e q(v I 1 v I 2 ) kT ]