Comparison of Multi-Purpose Cores of Keccak and AES
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A Quantitative Study of Advanced Encryption Standard Performance
United States Military Academy USMA Digital Commons West Point ETD 12-2018 A Quantitative Study of Advanced Encryption Standard Performance as it Relates to Cryptographic Attack Feasibility Daniel Hawthorne United States Military Academy, [email protected] Follow this and additional works at: https://digitalcommons.usmalibrary.org/faculty_etd Part of the Information Security Commons Recommended Citation Hawthorne, Daniel, "A Quantitative Study of Advanced Encryption Standard Performance as it Relates to Cryptographic Attack Feasibility" (2018). West Point ETD. 9. https://digitalcommons.usmalibrary.org/faculty_etd/9 This Doctoral Dissertation is brought to you for free and open access by USMA Digital Commons. It has been accepted for inclusion in West Point ETD by an authorized administrator of USMA Digital Commons. For more information, please contact [email protected]. A QUANTITATIVE STUDY OF ADVANCED ENCRYPTION STANDARD PERFORMANCE AS IT RELATES TO CRYPTOGRAPHIC ATTACK FEASIBILITY A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree of Doctor of Computer Science By Daniel Stephen Hawthorne Colorado Technical University December, 2018 Committee Dr. Richard Livingood, Ph.D., Chair Dr. Kelly Hughes, DCS, Committee Member Dr. James O. Webb, Ph.D., Committee Member December 17, 2018 © Daniel Stephen Hawthorne, 2018 1 Abstract The advanced encryption standard (AES) is the premier symmetric key cryptosystem in use today. Given its prevalence, the security provided by AES is of utmost importance. Technology is advancing at an incredible rate, in both capability and popularity, much faster than its rate of advancement in the late 1990s when AES was selected as the replacement standard for DES. Although the literature surrounding AES is robust, most studies fall into either theoretical or practical yet infeasible. -
Low-Latency Hardware Masking with Application to AES
Low-Latency Hardware Masking with Application to AES Pascal Sasdrich, Begül Bilgin, Michael Hutter, and Mark E. Marson Rambus Cryptography Research, 425 Market Street, 11th Floor, San Francisco, CA 94105, United States {psasdrich,bbilgin,mhutter,mmarson}@rambus.com Abstract. During the past two decades there has been a great deal of research published on masked hardware implementations of AES and other cryptographic primitives. Unfortunately, many hardware masking techniques can lead to increased latency compared to unprotected circuits for algorithms such as AES, due to the high-degree of nonlinear functions in their designs. In this paper, we present a hardware masking technique which does not increase the latency for such algorithms. It is based on the LUT-based Masked Dual-Rail with Pre-charge Logic (LMDPL) technique presented at CHES 2014. First, we show 1-glitch extended strong non- interference of a nonlinear LMDPL gadget under the 1-glitch extended probing model. We then use this knowledge to design an AES implementation which computes a full AES-128 operation in 10 cycles and a full AES-256 operation in 14 cycles. We perform practical side-channel analysis of our implementation using the Test Vector Leakage Assessment (TVLA) methodology and analyze univariate as well as bivariate t-statistics to demonstrate its DPA resistance level. Keywords: AES · Low-Latency Hardware · LMDPL · Masking · Secure Logic Styles · Differential Power Analysis · TVLA · Embedded Security 1 Introduction Masking countermeasures against side-channel analysis [KJJ99] have received a lot of attention over the last two decades. They are popular because they are relatively easy and inexpensive to implement, and their strengths and limitations are well understood using theoretical models and security proofs. -
Investigating Profiled Side-Channel Attacks Against the DES Key
IACR Transactions on Cryptographic Hardware and Embedded Systems ISSN 2569-2925, Vol. 2020, No. 3, pp. 22–72. DOI:10.13154/tches.v2020.i3.22-72 Investigating Profiled Side-Channel Attacks Against the DES Key Schedule Johann Heyszl1[0000−0002−8425−3114], Katja Miller1, Florian Unterstein1[0000−0002−8384−2021], Marc Schink1, Alexander Wagner1, Horst Gieser2, Sven Freud3, Tobias Damm3[0000−0003−3221−7207], Dominik Klein3[0000−0001−8174−7445] and Dennis Kügler3 1 Fraunhofer Institute for Applied and Integrated Security (AISEC), Germany, [email protected] 2 Fraunhofer Research Institution for Microsystems and Solid State Technologies (EMFT), Germany, [email protected] 3 Bundesamt für Sicherheit in der Informationstechnik (BSI), Germany, [email protected] Abstract. Recent publications describe profiled single trace side-channel attacks (SCAs) against the DES key-schedule of a “commercially available security controller”. They report a significant reduction of the average remaining entropy of cryptographic keys after the attack, with surprisingly large, key-dependent variations of attack results, and individual cases with remaining key entropies as low as a few bits. Unfortunately, they leave important questions unanswered: Are the reported wide distributions of results plausible - can this be explained? Are the results device- specific or more generally applicable to other devices? What is the actual impact on the security of 3-key triple DES? We systematically answer those and several other questions by analyzing two commercial security controllers and a general purpose microcontroller. We observe a significant overall reduction and, importantly, also observe a large key-dependent variation in single DES key security levels, i.e. -
Hardware Performance Evaluation of Authenticated Encryption SAEAES with Threshold Implementation
cryptography Article Hardware Performance Evaluation of Authenticated Encryption SAEAES with Threshold Implementation Takeshi Sugawara Department of Informatics, The University of Electro-Communications, Tokyo 182-8585, Japan; [email protected] Received: 30 June 2020; Accepted: 5 August 2020; Published: 9 August 2020 Abstract: SAEAES is the authenticated encryption algorithm instantiated by combining the SAEB mode of operation with AES, and a candidate of the NIST’s lightweight cryptography competition. Using AES gives the advantage of backward compatibility with the existing accelerators and coprocessors that the industry has invested in so far. Still, the newer lightweight block cipher (e.g., GIFT) outperforms AES in compact implementation, especially with the side-channel attack countermeasure such as threshold implementation. This paper aims to implement the first threshold implementation of SAEAES and evaluate the cost we are trading with the backward compatibility. We design a new circuit architecture using the column-oriented serialization based on the recent 3-share and uniform threshold implementation (TI) of the AES S-box based on the generalized changing of the guards. Our design uses 18,288 GE with AES’s occupation reaching 97% of the total area. Meanwhile, the circuit area is roughly three times the conventional SAEB-GIFT implementation (6229 GE) because of a large memory size needed for the AES’s non-linear key schedule and the extended states for satisfying uniformity in TI. Keywords: threshold implementation; SAEAES; authenticated encryption, side-channel attack; changing of the guards; lightweight cryptography; implementation 1. Introduction There is an increasing demand for secure data communication between embedded devices in many areas, including automotive, industrial, and smart-home applications. -
ASIC-Oriented Comparative Review of Hardware Security Algorithms for Internet of Things Applications Mohamed A
ASIC-Oriented Comparative Review of Hardware Security Algorithms for Internet of Things Applications Mohamed A. Bahnasawi1, Khalid Ibrahim2, Ahmed Mohamed3, Mohamed Khalifa Mohamed4, Ahmed Moustafa5, Kareem Abdelmonem6, Yehea Ismail7, Hassan Mostafa8 1,3,5,6,8Electronics and Electrical Communications Engineering Department, Cairo University, Giza, Egypt 2Electronics Department, Faculty of Information Engineering and Technology, German University in Cairo, Cairo, Egypt 4Electrical, Electronics and Communications Engineering Department, Faculty of Engineering, Alexandria University, Egypt 7,8Center for Nanoelectronics and Devices, AUC and Zewail City of Science and Technology, New Cairo, Egypt {[email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected] } Abstract— Research into the security of the Internet of Applications have different requirements for the Things (IoT) needs to utilize particular algorithms that offer cryptographic algorithms that secure them, varying in the ultra-low power consumption and a long lifespan, along with throughput needed, the extent of immunity against attacks, other parameters such as strong immunity against attacks, power consumption, the area needed on-chip, etc. The lower chip area and acceptable throughput. This paper offers Internet of Things (IoT) focuses mainly on low-power an ASIC-oriented comparative review of the most popular and implementations of security algorithms. This is because powerful cryptographic algorithms worldwide, namely AES, most of them are related to autonomous applications or 3DES, Twofish and RSA. The ASIC implementations of those embedded systems applications (i.e. an ultra-thin sensor algorithms are analyzed by studying statistical data extracted system [2] embedded inside clothes or biomedical from the ASIC layouts of the algorithms and comparing them to determine the most suited algorithms for IoT hardware- applications). -
Development of the Advanced Encryption Standard
Volume 126, Article No. 126024 (2021) https://doi.org/10.6028/jres.126.024 Journal of Research of the National Institute of Standards and Technology Development of the Advanced Encryption Standard Miles E. Smid Formerly: Computer Security Division, National Institute of Standards and Technology, Gaithersburg, MD 20899, USA [email protected] Strong cryptographic algorithms are essential for the protection of stored and transmitted data throughout the world. This publication discusses the development of Federal Information Processing Standards Publication (FIPS) 197, which specifies a cryptographic algorithm known as the Advanced Encryption Standard (AES). The AES was the result of a cooperative multiyear effort involving the U.S. government, industry, and the academic community. Several difficult problems that had to be resolved during the standard’s development are discussed, and the eventual solutions are presented. The author writes from his viewpoint as former leader of the Security Technology Group and later as acting director of the Computer Security Division at the National Institute of Standards and Technology, where he was responsible for the AES development. Key words: Advanced Encryption Standard (AES); consensus process; cryptography; Data Encryption Standard (DES); security requirements, SKIPJACK. Accepted: June 18, 2021 Published: August 16, 2021; Current Version: August 23, 2021 This article was sponsored by James Foti, Computer Security Division, Information Technology Laboratory, National Institute of Standards and Technology (NIST). The views expressed represent those of the author and not necessarily those of NIST. https://doi.org/10.6028/jres.126.024 1. Introduction In the late 1990s, the National Institute of Standards and Technology (NIST) was about to decide if it was going to specify a new cryptographic algorithm standard for the protection of U.S. -
Cryptography Whitepaper
Cryptography Whitepaper Threema uses modern cryptography based on open source components that strike an optimal balance between security, performance and message size. In this whitepaper, the algorithms and design decisions behind the cryptography in Threema are explained. VERSION: JUNE 21, 2021 Contents Overview 4 Open Source 5 End-to-End Encryption 5 Key Generation and Registration 5 Key Distribution and Trust 6 Message Encryption 7 Group Messaging 8 Key Backup 8 Client-Server Protocol Description 10 Chat Protocol (Message Transport Layer) 10 Directory Access Protocol 11 Media Access Protocol 11 Cryptography Details 12 Key Lengths 12 Random Number Generation 13 Forward Secrecy 14 Padding 14 Repudiability 15 Replay Prevention 15 Local Data Encryption 15 iOS 15 Android 16 Key Storage 16 iOS 16 Android 16 Push Notifications 17 iOS 17 Android 17 Threema • Cryptography Whitepaper Address Book Synchronization 17 Linking 18 ID Revocation 19 An Example 19 Profile Pictures 19 Web Client 20 Architecture 20 Connection Buildup 21 WebRTC Signaling 22 WebRTC Connection Buildup 22 Trusted Keys / Stored Sessions 23 Push Service 23 Self Hosting 24 Links 24 Threema Calls 24 Signaling 24 Call Encryption 24 Audio Encoding 25 Video Encoding 25 Privacy / IP Exposure 25 Threema Safe 26 Overview 26 Backup Format 27 Encryption 27 Upload/Storage 27 Backup Intervals 28 Restore/Decryption 28 Running a Custom Threema Safe Server 28 Threema • Cryptography Whitepaper Overview Threema uses two different encryption layers to protect messages between the sender and the recipient. • End-to-end encryption layer: this layer is between the sender and the recipient. • Transport layer: each end-to-end encrypted message is encrypted again for transport between the client and the server, in order to protect the header information. -
State of the Art in Lightweight Symmetric Cryptography
State of the Art in Lightweight Symmetric Cryptography Alex Biryukov1 and Léo Perrin2 1 SnT, CSC, University of Luxembourg, [email protected] 2 SnT, University of Luxembourg, [email protected] Abstract. Lightweight cryptography has been one of the “hot topics” in symmetric cryptography in the recent years. A huge number of lightweight algorithms have been published, standardized and/or used in commercial products. In this paper, we discuss the different implementation constraints that a “lightweight” algorithm is usually designed to satisfy. We also present an extensive survey of all lightweight symmetric primitives we are aware of. It covers designs from the academic community, from government agencies and proprietary algorithms which were reverse-engineered or leaked. Relevant national (nist...) and international (iso/iec...) standards are listed. We then discuss some trends we identified in the design of lightweight algorithms, namely the designers’ preference for arx-based and bitsliced-S-Box-based designs and simple key schedules. Finally, we argue that lightweight cryptography is too large a field and that it should be split into two related but distinct areas: ultra-lightweight and IoT cryptography. The former deals only with the smallest of devices for which a lower security level may be justified by the very harsh design constraints. The latter corresponds to low-power embedded processors for which the Aes and modern hash function are costly but which have to provide a high level security due to their greater connectivity. Keywords: Lightweight cryptography · Ultra-Lightweight · IoT · Internet of Things · SoK · Survey · Standards · Industry 1 Introduction The Internet of Things (IoT) is one of the foremost buzzwords in computer science and information technology at the time of writing. -
AES) Is the Desirable Encryption Core for Any Practical Low-End Embedded
CENTRE FOR NEWFOUNDLAND STUDIES TOTAL OF 10 PAGES ONLY MAY BE XEROXED (Without Author's Permission) COMPACT HARDWARE IMPLEMENTATION OF ADVANCED ENCRYPTION STANDARD WITH CONCURRENT ERROR DETECTION by Namin Yu A thesis submitted to the School of Graduate Studies in partial fulfillment of the requirements for the degree of Master Faculty of Engineering and Applied Science Memorial University of Newfoundland August 2005 St. John's Newfoundland Canada Abstract A compact, efficient and highly reliable implementation of the Advanced Encryption Standard (AES) is the desirable encryption core for any practical low-end embedded application. In this thesis we design and implement a compact hardware AES system with concurrent error detection. We investigate various architectures for compact AES implementations in 0.18 f!m CMOS technology. We first explore a new compact digital hardware implementation of the AES s-boxes applying the discovery of linear redundancy in the AES s-boxes. Although the new circuit has a small size, the speed of this implementation is also reduced. Encryption architectures without key scheduling that employ four s-boxes and only one s-box are implemented using the new AES s-boxes, as well as based on other compact s-box structures. The comparison of the implementations based on different architectures and s-box structures indicates that the implementation using four s-boxes 4 based on arithmetic operations in GF(2 ) has the best trade-off of area and speed. Therefore, using this s-box implementation, a complete encryption-decryption architecture with key scheduling employing the four s-box structure is implemented. In order to be adaptive to various practical applications, we optimize the implementation with the fours-box structure to support five different operation modes. -
Motivation AES Throughput Advanced Encryption Standard
Utilizing Hardware AES Encryption for WSNs by Felix Büsching, Andreas Figur, Dominik Schürmann, and Lars Wolf Technische Universität Braunschweig | Institute of Operating Systems and Computer Networks Felix Büsching | [email protected] | Phone +49 (0) 531 391-3289 Motivation Implementations Encryption is essential in many Wireless Sensor Network (WSN) appli- Four different AES algorithms were implemented for INGA Wireless cations. Several encryption frameworks exist which are mostly based Sensor Nodes. While the first algorithm (1) SW-AES-1 was realized for on software algorithms. However, nearly every up-to-date radio trans- Contiki in C in a straight forward way, the (2) SW-AES-2 implementa- ceiver chip is equipped with an integrated hardware encryption en- tion was improved by a static lookup table. gine. Here we show the benefits of utilizing an integrated hardware To compare our C implementations with a software reference, we uti- encryption engine in comparison to pure software-based solutions. lized (3) RijndaelFast, an optimized assembler implementation for the Atmel ATmega family. We see this external implementation as a the- oretical limit, knowing that this performance could never be reached when using an operating system like TinyOS or Contiki. Advanced Encryption Standard - AES Most of the currently available radio transmitters and have an integrat- ed hardware AES unit. These units can usually be addressed by special ▪ ... is a variant of Rijndael with a fixed block size of 128 bits. registers via SPI bus. When using an ▪ ... is based on a substitution-permutation network, which shall op- operating system like Contiki or Ti- erate fast in both software and hardware. -
ERHARD-RNG: a Random Number Generator Built from Repurposed Hardware in Embedded Systems
ERHARD-RNG: A Random Number Generator Built from Repurposed Hardware in Embedded Systems Jacob Grycel and Robert J. Walls Department of Computer Science Worcester Polytechnic Institute Worcester, MA Email: jtgrycel, [email protected] Abstract—Quality randomness is fundamental to crypto- only an external 4 MHz crystal oscillator and power supply. graphic operations but on embedded systems good sources are We chose this platform due to its numerous programmable pe- (seemingly) hard to find. Rather than use expensive custom hard- ripherals, its commonality in embedded systems development, ware, our ERHARD-RNG Pseudo-Random Number Generator (PRNG) utilizes entropy sources that are already common in a and its affordability. Many microcontrollers and Systems On a range of low-cost embedded platforms. We empirically evaluate Chip (SoC) include similar hardware that allows our PRNG to the entropy provided by three sources—SRAM startup state, be implemented, including chips from Atmel, Xilinx, Cypress oscillator jitter, and device temperature—and integrate those Semiconductor, and other chips from Texas Instruments. sources into a full Pseudo-Random Number Generator imple- ERHARD-RNG is based on three key insights. First, we mentation based on Fortuna [1]. Our system addresses a number of fundamental challenges affecting random number generation can address the challenge of collecting entropy at runtime by on embedded systems. For instance, we propose SRAM startup sampling the jitter of the low-power/low-precision oscillator. state as a means to efficiently generate the initial seed—even for Coupled with measurements of the internal temperature sensor systems that do not have writeable storage. Further, the system’s we can effectively re-seed our PRNG with minimal overhead. -
How to Eat Your Entropy and Have It Too — Optimal Recovery Strategies for Compromised Rngs
How to Eat Your Entropy and Have it Too — Optimal Recovery Strategies for Compromised RNGs Yevgeniy Dodis1?, Adi Shamir2, Noah Stephens-Davidowitz1, and Daniel Wichs3?? 1 Dept. of Computer Science, New York University. { [email protected], [email protected] } 2 Dept. of Computer Science and Applied Mathematics, Weizmann Institute. [email protected] 3 Dept. of Computer Science, Northeastern University. [email protected] Abstract. We study random number generators (RNGs) with input, RNGs that regularly update their internal state according to some aux- iliary input with additional randomness harvested from the environment. We formalize the problem of designing an efficient recovery mechanism from complete state compromise in the presence of an active attacker. If we knew the timing of the last compromise and the amount of entropy gathered since then, we could stop producing any outputs until the state becomes truly random again. However, our challenge is to recover within a time proportional to this optimal solution even in the hardest (and most realistic) case in which (a) we know nothing about the timing of the last state compromise, and the amount of new entropy injected since then into the state, and (b) any premature production of outputs leads to the total loss of all the added entropy used by the RNG. In other words, the challenge is to develop recovery mechanisms which are guaranteed to save the day as quickly as possible after a compromise we are not even aware of. The dilemma is that any entropy used prematurely will be lost, and any entropy which is kept unused will delay the recovery.