Design of a High-Density Power Supply for Fpgas

www.linear.com POWER SUPPLY DESIGN 27 Design of a High-Density Power Supply for FPGAs Although the versatile and configurable nature of Field Programmable Gate Arrays (FPGAs) is attractive to system designers, the complex nature of design rules that govern the inner working of these devices and their outer interface protocols require extensive training, reference design evaluation, design simulation and verification. As a result, FPGA suppliers provide detailed hardware and firmware support to assist system architects with new challenges in the digital domain. However; obscure intricacies in the analog domain, specifically in the realm of delivering power and regulation voltages with DC/DC regulators for core, I/O, memory, clocks, and other rails, demand new solutions. Alan Chern and Afshin Odabaee, Linear Technology Corp., USA

To power each rail efficiently and in a be located at different corners of the of supply rails, an error of 17% can easily smallest possible space requires a DC/DC system. degrade performance. For example, a regulator circuit that contains, on average, Fast I/O nodes often demand the most 100mV difference in Vt can scale the 10 components (inductor, MOSFETs, power in FPGA-based applications. It’s very leakage current by factor of 10 or more. capacitors, DC/DC regulator, etc.). A 6-rail usual to see 1.8V and 2.5V I/O voltages Standard DC/DC regulators provide FPGA may require as many as 60 that create loads in tens of Amperes. The precise regulation but only if the load is components to power it. Aside from the very high-end systems have requirements very close to its output. It cannot long list of components needed to power for 40A up to 80A I/O designs. compensate for the IxR voltage drop. The the FPGA, there are hidden costs of Due to the logistics of a board design, error correction must be handled with the component insertion, reliability, circuit the DC/DC regulator must be placed at a help of a remote sense amplifier. The board complexity and more. distance from its load and requires a long tightest regulation is possible with PCB trace from its output to the point of differential remote sensing of the load, Managing multiple voltage rails regulation. At large load current levels, PCB which requires a precision op amp and Prior generations of FPGAs required two or traces introduce a voltage error equal to precision resistors. An ideal regulator three power rails. Now, some of the high- the value of the load current (I) multiplied should provide better than ±1.5% end multiple-core devices require as many by the impedance (R) of the trace. This IxR regulation accuracy right-at-the-load even as seven rails; a mixture of 3.3V legacy voltage error has become more over -40ºC to 85ºC temperature range. power rails and recent lower voltages, problematic since the load voltages have This accuracy may be insignificant for a ranging from 2.8V to 1.0V and below. been decreasing and load currents 3.3V rail where the digital ICs can tolerate Moreover, a mix of other voltage rails that increasing. For example, a 200mV IxR drop ±0.5V variation, but a 90nm or 65nm are needed for devices other than FPGAs for a 3.3V rail produces 6% error, whereas device with 1.8V, 1.0V or 0.9V rails will such as memory, network processors, for a 1.2V rail it introduces a 17% error. require higher accuracy. graphics processors, digital-to-analog or Therefore, although the DC/DC regulator Once the output voltage of the regulator analog-to-digital converters as well as op can be set to regulate a 1.2V output, the is set by the user, the differential remote amps and RF ICs. load will only see 1.0V due to IxR voltage sensing automatically adjusts the regulated To ensure a “clean” start-up of a system drop. voltage at the point of the load by with multiple voltage rails such that none With today’s 90- and 65nanometer compensating for any IxR voltage drop of the rails conflict with each other requires processes where Vt and performance of across the PCB trace for a wide range of a DC/DC regulator equipped with the FPGA are dependent on the precision load currents. As a result, the regulation is sequencing and tracking functions. Simply stated, each regulator must be able to track the output voltage of other regulators. The good news is that FPGAs no longer require any sequencing on their rails. However, sequential ramp-up or ramp- down of several voltages across different sections within a system are still required to prevent possible latch-offs that may occur when a voltage rail comes up too fast or too slow. In the past, tracking and sequencing of power rails was handled by a separate power management IC. Today, designers require that both the sequencing and tracking functions are embedded into Figure 1: Four DC/DC µModule regulator systems current share to regulate 1.5V at 48A with only the regulators, particularly when they must 2.8mm profile and 15mm x 15mm of board area www.power-mag.com Issue 6 2010 Power Electronics Europe 28 POWER SUPPLY DESIGN www.linear.com

Figure 2: Paralleling and output capacitors can be added to the of multiple DC/DC circuit to dampen peak-to-peak ripple µModule regulators voltage. However, dampening the systems to achieve switching noise is more challenging. One higher output current possible approach is to synchronize the DC/DC regulator’s operating frequency to an external clock which forces the regulator to operate within a set frequency chosen to have minimum interference with other noise-sensitive parts of the system. This method is especially effective when several switchmode regulators are all synchronized to a clock frequency that is safe for the rest of the system. These methods help with design of a less noisy switchmode point-of-load regulator; however the problem of noise can be greatly reduced if the DC/DC regulator is designed from the ground up with the proper architecture, functions and layout. Such a regulator minimizes its dependency on capacitors, filtering, and EMI (electromagnetic interference) shielding.

Fine tuning voltages during system qualification and assembly The performance of an FPGA or its supporting ICs can differ when they are assembled into a complete system versus when they are individually tested on a lab bench. Elements such as the type of solder, temperature, PCB layout, trace impedances and assembly process influence the performance of a component. For example, if the core of the very precise when the system is in standby energy and simplifying thermal FPGA is regulated at a voltage other than mode, or at full speed when load current management of the portable product. expected and this leads into a slower and IxR voltage drop are their peak. A switchmode DC/DC regulator offers a speed, the system’s computational higher performance solution than a linear capability will be degraded. In some Lowering voltage ripple noise and regulator in either portable or non-portable instances, the quality control personnel capacitor requirements applications, especially for high power must reject a system that deviates from its In non-portable applications, as the requirements. For example, a switchmode expected performance. requirements for voltages drop and regulator providing 1.2V at 5A from a 3.3V For this reason, as engineers evaluate currents rise, heat dissipation and input supply at 90% efficiency compares the performance during qualification or operating efficiency become more to a linear regulator’s 36% efficiency; assembly, they need the ability to raise or important factors in the selection of a furthermore, whereas the switchmode lower the output voltage in small DC/DC regulator. In portable applications, regulator dissipates 0.7W, the linear increments. This function is called although load current per rail is less, the regulator dissipates 10.5W. margining. In the previous example, the operating and standby efficiencies still play On the other hand, a switchmode core voltage could be increased so that the an important role in preserving a battery’s regulator introduces switching noise and operating frequency of the FPGA reaches higher output ripple noise (output voltage its desired level. The margining function peak-to-peak ripple) because of its can also help the system manufacturer inherent switching operation. increase the overall yield during Unfortunately, the lower voltage rails of production. new FPGAs and tighter eye-diagrams of In a recent application discussion with a faster I/O signals are less tolerant of power system designer, the requirement for his supply “noise”. power supply was to regulate 1.5V and To alleviate the ripple noise, more input deliver up to 40A of current to a load that consisted of four FPGAs. This means that Figure 3: By operating each DC/DC µModule up to 60W of power must be delivered in regulator 90º out-of-phase, the input and output a small area with lowest profile (height) ripples are reduced, which also reduces the possible to allow smooth flow of air for requirement for input and output capacitors cooling. The power supply had to be (shown are individual µModule switching surface-mountable and operate at high waveforms for Figure 2) enough efficiency to minimize heat

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minimal or no heat sinks. These contribute which provides four clock outputs, each to a lower cost system that consumes less 90° phase shifted (for 2- or 3phase power to remove heat. relationships, the LTC6902 can be adjusted Figure 1 shows a test board for such via a resistor). By operating the regulators circuit. The design regulates 1.5V output out-of-phase, peak input and output while delivering 40A (up to 48A) of load current is reduced by approximately 20% current. Each “black square” is a complete depending on the duty cycle (see the DC/DC circuit and is housed in a 15mm x LTM4601 data sheet). This reduction in 15mm x 2.8mm surface mount package. turn, reduces the requirement for input With a few input and output capacitors and and output capacitors. The clock signals resistors, the design using these DC/DC serve as input to the PLLIN (phase-lock µModules is as simple as shown. loop in) pins of the four LTM4601s. The The LTM4601 µModule DC/DC phase-lock loop of the LTM4601 regulator is a high performance power comprises a phase detector and a voltage module shrunk down to an IC form factor. controlled oscillator, which combine to lock It is a completely integrated solution, onto the rising edge of an external clock including the PWM controller, inductor, with a frequency range of 850kHz. The input and output capacitors, low RDS(ON) phase lock loop is turned on when a pulse FETs, Schottky diodes and compensation of at least 400ns and 2V amplitude at the circuitry. Only external bulk input and PLLIN pin is detected, though it is disabled Figure 4: Efficiency of dissipation. He also demanded the output capacitors and one resistor are during start-up. Figure 3 shows the the four DC/DC simplest possible solution so his time needed to set the output from 0.6V to 5V. switching waveforms of four LTM4601 µModule regulators could be dedicated to the more complex The supply can produce 12A (more if regulators in parallel. in parallel remains tasks. Aside from precise electrical paralleled) from a wide input range of Only one resistor is required to set the high over a wide performance, this solution had to remove 4.5V to 20V. The pin-compatible output voltage. In a parallel setup, the range of output the heat generated during DC to DC LTM4601HV extends the input range to value of the resistor depends on the voltages conversion quickly so that the circuit and 28V. number of LTM4601s used. This is the ICs in its vicinity did not over heat. A significant advantage of the LTM4601 because the effective value of the top Such solution requires an innovative over power-module or IC-based systems is (internal) feedback resistor changes as you design to meet these criteria such as very its ability to easily scale up as loads parallel LTM4601s. The LTM4601’s low profile to allow efficient air flow and to increase. If load requirements are greater reference voltage is 0.6V and its internal prevent thermal shadow on surrounding than one µModule regulator can produce, top feedback resistor value is 60.4k ⍀, so ICs; high efficiency to minimize heat simply add more modules in parallel. The the relationship between V OUT , the output

dissipation; current sharing capability to design of a parallel system involves little voltage setting resistor (R FB ) and the spread the heat evenly to eliminate hot more than copying and pasting the layout number of modules (n) placed in parallel spots and minimize or eliminate the need of each 15mm _ 15mm µModule is according to equation 1: for heat sinks; and a complete DC/DC regulator. Electrical layout issues are taken circuit in a surface mount package that care of within the µModule package, there includes the DC/DC controller, MOSFETs, are no external inductors, switches or other inductor, capacitors and compensation components to worry about. circuitry for a quick and easy solution. Output features include output voltage tracking and margining. The switching (1) Innovation in DC/DC design frequency, typically 850kHz at full load, Figure 5: Controlled The innovation is a modular but surface constant on time, zero latency controller Figure 4 illustrates the system’s high soft start is important mount approach that uses efficient DC/DC delivers fast transient response to line and efficiency over the vast output current in proper start-up of conversion, precise current sharing and low load changes while maintaining stability. range up to 48A. The system performs the FPGA or the thermal impedance packaging to deliver Should frequency harmonics be a concern, impressively with no dip in the efficiency system as a whole the output power while requiring minimal an external clock can control curve for a broad range of output voltages. (soft-start current and cooling. Because of the low profile and synchronization via an on-chip phase lock voltage ramp for four power sharing among four devices, a loop. Soft-Start and Current Sharing DC/DC µModules in system using this solution depends on The soft-start feature of the LTM4601 parallel) fewer fans or slower fan speed as well as Four parallel regulators provide 48A prevents large inrush currents at start-up Figure 2 shows a regulator comprising four by slowly ramping the output voltage to its parallel LTM4601s, which can produce a nominal value. The relation of start-up time 48A (4 _12A) output. The regulators are to VOUT and the soft-start capacitor (C SS ) synchronized but operate 90° out of phase according to equation 2 is: with respect to each other, thereby reducing the amplitude of input and output ripple currents through cancellation (Figure 3). The attenuated ripple in turn decreases the external capacitor RMS current rating and size requirements, further reducing solution cost and board (2) space. Synchronization and phase shifting is For example, a 0.1µF soft-start capacitor implemented via the LTC6902 oscillator, yields a nominal 8ms ramp (see Figure 5)

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Figure 6: Each DC/DC µModule regulator starts the flow over the thinner packages such and ends by sharing the load current evenly and FPGAs or a memory ICs. In the case of balanced, a crucial feature to prevent one pre-fabricated DC/DC point-of-load regulator from overheating (two parallel regulators, the blockage is severe as these LTM4601s, as each rises to a nominal 10A each, devices reach a height that is between 20A total) 6 to 10 times the height of the FPGA and other ICs. of this design minimizes development The thin ball grid array (BGA) packaging time while saving board space. of the FPGAs is extremely helpful in efficient dissipation of internally generated Thermal performance and layout heat from the top of the package. This In the first portion of this article, we benefit is diminished when a taller device discussed the circuit and electrical such as a pre-fabricated DC/DC regulator performance of a compact and low profile inhibits air flow and casts a “shadow” on with no margining. 48A, 1.5V DC/DC regulator solution for a the device next to it. Current sharing among parallel 4-FPGA design. The new approach uses Figure 7 is a thermal image of the board regulators is well balanced through start-up four DC/DC regulators in parallel (Figure shown in Figure 1 with readings of the to full load. Figure 6 shows an evenly 1) to increase output current while sharing temperatures at specific locations. Cursors distributed output current curve for a 2- the current equally among each device. 1 to 4 show an estimation of the surface parallel LTM4601 system, as each rises to This solution relies on the accurate current temperature on each module. Cursors 5 to a nominal 10A each, 20A total. sharing of these regulators to prevent hot- 7 indicate the surface temperature of the In summary, the DC/DC µModule spots by dissipating the heat evenly over a PCB. Note the difference in temperature regulators are self-contained and complete compact surface area. between the inner two regulators, cursors systems in an IC form factor. The low The move to shrink the size of FPGA- 1 and 2, and the outside ones, cursors 3 profile, high efficiency and current sharing based systems while increasing and 4. The LTM4601 µModule regulators capability allow practical high power functionality, memory storage and placed on the outside have large planes to solutions for the new generation of digital computational power, have prompted the left and right promoting heat sinking to systems. Thermal performance is designers to refine the techniques used to cool the part down a few degrees. The impressive at 48A of output current with cool the components. One simple method inner two only have small top and bottom balanced current sharing and smooth is to provide an efficient air flow over the planes to draw heat away, thus becoming uniform start-up. The ease and simplicity components. Tall components obscure slightly warmer than the outside two. XPT-IGBT the newest generation of short-circuit rated IGBTs Drive with the XPT-IGBT Features: • Easy paralleling due to the positive temperature coefficient • Rugged XPT design results in: – Short Circuit rated for 10 +sec. – Very low gate charge – Square RBSOA @ 3x Ic – Low EMI • Advanced wafer technology results in low Vce(sat) • 10-50 A in 1200 V TYPE Configuration Package MIXA20WB1200TED CBI E2-Pack MIXA60WB1200TEH CBI E3-Pack IXA37IF1200HJ CoPack ISOPLUS 247 IXA20I1200PB Single TO 220 For more part numbers, go to www.ixys.com Used in: • AC motor drives • Solar inverter • Medical equipment • Uninterruptible power supply

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Figure 7: Thermograph of 48A, 1.5V circuit of thermal heat sinking. The footprint itself Figure 1 shows balanced power sharing among simplifies layout of the power and ground each DC/DC µModule regulator and low planes, as shown in Figure 7. Laying out

temperature rise even without airflow (V IN =20V four parallel regulators is just as easy. If

to 1.5V OUT at 40A) laid out properly, the LGA packaging and the power planes alone can provide slightly higher temperature because of enough heat sinking to keep the LTM4601 spillover heat from the other regulators. cool. Heat transfer to the PCB also changes with airflow. Conclusions Simple copy and paste layout Delivering 60W of power in a compact Further heat dissipation is possible by space without efficient means to remove adding vias underneath the part. Vias the heat from the power supply ex- provide a path to the power planes and acerbates the already challenging task of into the PCB, which helps draw heat away. system heat management and cooling. Vias should not be placed directly under The DC/DC µModule family is designed Airflow also has a substantial effect on the pads. Figure 6 shows the layout of the with careful attention to the layout of its the thermal balance of the system. Note vias on the DC1043A demonstration internal components, package type, and the difference in temperature between circuit. The cross marks indicate the vias in electrical operation, which ease thermal Figures 2 and 3. In Figure 7, a 200LFM between the LGA pads. management of a very dense power airflow travels evenly from the bottom to Layout of the parallel regulators is supply circuit. The LGA package and simple the top of the demo board, causing a 20°C relatively simple, in that there are few layout allow 100% surface mountable and drop across the board compared to the no electrical design considerations. low profile design for maximum efficiency air flow case in Figure 7. Nevertheless, if the intent of a design is to in air flow. This new approach in power The direction of airflow is also minimize the required PCB area, thermal supply design takes advantage of important. In Figure 4 the airflow travels considerations become paramount, so the paralleling multiple DC/DC µModule from right to left, pushing the heat from important parameters are spacing, vias, regulators and following a copy & paste one regulator to the next, creating a airflow and planes. approach in layout design, to provide a stacking effect. The device on the right, The LTM4601 regulator has a unique 60W power supply with minimum the closest to the airflow source, is the LGA package footprint, which allows solid components while operating efficiently in a coolest. The leftmost regulator has a attachment to the PCB while enhancing compact, low profile space.

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