Find Your Way Through the X86 Firmware Maze
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Boot Mode Considerations: BIOS Vs UEFI
Boot Mode Considerations: BIOS vs. UEFI An overview of differences between UEFI Boot Mode and traditional BIOS Boot Mode Dell Engineering June 2018 Revisions Date Description October 2017 Initial release June 2018 Added DHCP Server PXE configuration details. The information in this publication is provided “as is.” Dell Inc. makes no representations or warranties of any kind with respect to the information in this publication, and specifically disclaims implied warranties of merchantability or fitness for a particular purpose. Use, copying, and distribution of any software described in this publication requires an applicable software license. Copyright © 2017 Dell Inc. or its subsidiaries. All Rights Reserved. Dell, EMC, and other trademarks are trademarks of Dell Inc. or its subsidiaries. Other trademarks may be the property of their respective owners. Published in the USA [1/15/2020] [Deployment and Configuration Guide] [Document ID] Dell believes the information in this document is accurate as of its publication date. The information is subject to change without notice. 2 : BIOS vs. UEFI | Doc ID 20444677 | June 2018 Table of contents Revisions............................................................................................................................................................................. 2 Executive Summary ............................................................................................................................................................ 4 1 Introduction .................................................................................................................................................................. -
VIA RAID Configurations
VIA RAID configurations The motherboard includes a high performance IDE RAID controller integrated in the VIA VT8237R southbridge chipset. It supports RAID 0, RAID 1 and JBOD with two independent Serial ATA channels. RAID 0 (called Data striping) optimizes two identical hard disk drives to read and write data in parallel, interleaved stacks. Two hard disks perform the same work as a single drive but at a sustained data transfer rate, double that of a single disk alone, thus improving data access and storage. Use of two new identical hard disk drives is required for this setup. RAID 1 (called Data mirroring) copies and maintains an identical image of data from one drive to a second drive. If one drive fails, the disk array management software directs all applications to the surviving drive as it contains a complete copy of the data in the other drive. This RAID configuration provides data protection and increases fault tolerance to the entire system. Use two new drives or use an existing drive and a new drive for this setup. The new drive must be of the same size or larger than the existing drive. JBOD (Spanning) stands for Just a Bunch of Disks and refers to hard disk drives that are not yet configured as a RAID set. This configuration stores the same data redundantly on multiple disks that appear as a single disk on the operating system. Spanning does not deliver any advantage over using separate disks independently and does not provide fault tolerance or other RAID performance benefits. If you use either Windows® XP or Windows® 2000 operating system (OS), copy first the RAID driver from the support CD to a floppy disk before creating RAID configurations. -
Custom X86 Hardware and Embedded BIOS™ Design Note #3
Custom x86 Hardware Design Note #3 and Embedded BIOS™ Orchid Technologies Engineering and Consulting, Inc. Orchid excels at providing deeply embedded customized x86 personal computer product designs. Orchid offers rapid hardware development using processor technology from Intel, AMD, Cyrix, and ST-Microelectronics. Orchid embedded designs are customized to suite your feature set, packaging, power and unit cost requirements. Select from a wide variety of peripheral options. Orchid reduces product cost by redesigning older multi-board systems into new single board embedded x86 architectures. Among our successes are: • Celeron Telephony Switch • Pentium II Gaming Motherboard • Pentium II/440BX Raid Controller • Multiprocessor Simulation Engine • Pentium Set Top Box • Mobile Module Based Kiosk • Celeron MP3 Audio Server • Elan SC400 Ruggedized SBC • 386EX Voice/FAX Mail System • Elan SC400 Low Cost Alarm CPU General Software Embedded BIOS™ Embedded BIOS is selected as the BIOS of preference for boards from many of the industry’s most important manufacturers including Intel, AMD, Cyrix and ST- Microelectronics. Embedded BIOS is a full-featured BIOS for x86-based handheld, Orchid Technologies’ unparalleled embedded and volume consumer electronics applications. With over 400 source- experience and its close partnership level configuration options, Embedded BIOS is the most configurable BIOS in with General Software make it the world. Your design can include built-in support for ROM Disks, RAM Disks, the ideal choice for custom x86 Resident Flash Disks (RFD), power management, LCD Panel drivers, console hardware design. redirection, Windows CE-launcher, configurable Setup Screen, and much more. Technology Partnership As a General Software Technology Partner, Orchid Technologies Engineering and Consulting, Inc. -
Status Update on PCI Express Support in Qemu
Status Update on PCI Express Support in QEmu Isaku Yamahata, VA Linux Systems Japan K.K. <[email protected]> Xen Summit North America April 28, 2010 Agenda ● Introduction ● Usage and Example ● Implementation Details ● Future Work ● Considerations on further development issues Introduction From http://en.wikipedia.org/wiki/PCI_Express PCI Express native Hotplug Electro Mechanical Lock(EMI) Slot Number From http://docs.hp.com/ Eventual Goal Dom0 qemu-dm interrupt root DomU Inject the error up Virtual PCIe Bus down Interrupt to notify the error Xen VMM hardware PCI express bus PCI Express root port PCI Express upstream port PCI Express Error Message native passthrough PCI Express downstream port With native hot plug support Error PCI Express device Eventual Goal ● More PCI features/PCI express features – The current emulated chipset(I440FX/PIIX3) is too old. – So new Chipset emulator is wanted. ● Xen PCI Express support – PCI Express native hotplug – PCI Express native passthourgh ● When error is detected via AER(Advanced Error Reporting), inject the error into the guest. ● these require several steps, so the first step is... First Phase Goal ● Make Qemu PCI Express ready – Introduce new chipset emulator(Q35) ● PCI Express native hot plug ● Implement PCI Express port emulators, and make it possible to inject errors into guest Current status Qemu/PCI express ● PCIe MMCONFIG Merged. the qemu/guest Q35 chipset base working PCIe portemulator working PCIe native hotplug working firmware PCIe AER WIP PCIe error injection WIP VBE paravirtualization working enhancement is seabios mcfg working almost done. e820 working host bridge initiazatlin working ● pci io/memory The next step is space initialization working passing acpi table outside qemu working qemu upstream vgabios VBE paravirtualization working merge. -
BIOS Update/Crisis Disk for BEETLE with I815 Standard Motherboard (D2/D2*) Release "WN STD 0B/22"
README.PDF 17.12.2003 BIOS update/crisis disk for BEETLE with i815 standard motherboard (D2/D2*) release "WN STD 0B/22" Contents of DOWNLOAD.ZIP: D2UPDATE0B22ARJ.EXE Selfextracting archive of flash update disk for MS-DOS Needs a prepared bootable floppy or MemCard D2UPDATE0B22IMG.EXE Directly creates a bootable flash update disk on 1,44MB/3,5" floppy. To be used with Windows only. D2UPDATE0B22DD.BIN Floppy image file of flash update disk for Linux; to be extracted by: "dd if=filename of=/dev/fd0" D2CRISIS0B22ARJ.EXE Selfextracting archive of flash crisis disk for MS-DOS Needs a prepared bootable floppy or MemCard D2CRISIS0B22IMG.EXE Directly creates a bootable flash crisis disk on 1,44MB/3,5" floppy To be used with Windows only. D2CRISIS0B22DD.BIN Floppy image file of flash crisis disk for Linux; to be extracted by: "dd if=filename of=/dev/fd0" README.HTM This information Please read these remarks first, before downloading and extracting ZIP file ... This release is not valid for D2 basic motherboard ! THIS RELEASE IS NEEDED, IF YOU WANT TO PERFORM AUTOMATIC UPDATE OF BEETLE BIOS RELEASES OVER INTERNET. The in future (higher than 0B/22) BIOS releases of D2 STD BIOS will also be available as an BEETLE VIEW update package, provided in www - you need to update to this release before! Some new features of the update procedure (UPBIOS.EXE) rel. 3.1: If any of these advanced features is wanted, you need to adapt the update floppy disk! See chapter "How to use flashtool UPBIOS.EXE" for further information about options. -
Multiprocessor Initialization of INTEL SOC in Coreboot
Multiprocessor Initialization OF INTEL SOC in Coreboot Pratik Prajapati ([email protected]) Subrata Banik ([email protected]) 1 Agenda • Intel Multiple Processor (MP) Initialization • Coreboot + Intel FSP Boot Flow • Problem with existing model • Solution space • Design • Future Scope 2 Intel Multiple Processor (MP) Initialization • The IA-32 architecture (beginning with the P6 family processors) defines a multiple-processor (MP) initialization protocol called the Multiprocessor Specification Version 1.4. • The MP initialization protocol has the following important features: • It supports controlled booting of multiple processors without requiring dedicated system hardware. • It allows hardware to initiate the booting of a system without the need for a dedicated signal or a predefined boot processor. • It allows all IA-32 processors to be booted in the same manner, including those supporting Intel Hyper-Threading Technology. • The MP initialization protocol also applies to MP systems using Intel 64 processors. • Entire CPU multiprocessor initialization can be divided into two parts – BSP (Boot Strap Processor) Initialization – AP (Application Processor) Initialization Reference: Intel SDM Multiple Processor Init - section 8.4 3 Coreboot + Intel FSP (Firmware support package) Boot Flow Coreboot/BIOS FSP * Coreboot uses its own temp ram init code. 4 Problem Statement with existing model • Background: Coreboot is capable enough to handle multiprocessor initialization on IA platforms. So ideally, CPU features programming can be part of Coreboot MP Init sequence. • But, there might be some cases where certain feature programming can't be done with current flow of MP init sequence. Because, Intel FSP-S has to program certain registers to meet silicon init flow due to SAI (Security Attributes of Initiator) and has to lock other registers before exiting silicon init API. -
Chapter 3. Booting Operating Systems
Chapter 3. Booting Operating Systems Abstract: Chapter 3 provides a complete coverage on operating systems booting. It explains the booting principle and the booting sequence of various kinds of bootable devices. These include booting from floppy disk, hard disk, CDROM and USB drives. Instead of writing a customized booter to boot up only MTX, it shows how to develop booter programs to boot up real operating systems, such as Linux, from a variety of bootable devices. In particular, it shows how to boot up generic Linux bzImage kernels with initial ramdisk support. It is shown that the hard disk and CDROM booters developed in this book are comparable to GRUB and isolinux in performance. In addition, it demonstrates the booter programs by sample systems. 3.1. Booting Booting, which is short for bootstrap, refers to the process of loading an operating system image into computer memory and starting up the operating system. As such, it is the first step to run an operating system. Despite its importance and widespread interests among computer users, the subject of booting is rarely discussed in operating system books. Information on booting are usually scattered and, in most cases, incomplete. A systematic treatment of the booting process has been lacking. The purpose of this chapter is to try to fill this void. In this chapter, we shall discuss the booting principle and show how to write booter programs to boot up real operating systems. As one might expect, the booting process is highly machine dependent. To be more specific, we shall only consider the booting process of Intel x86 based PCs. -
HP Iscsi Boot for Windows User Guide
HP iSCSI Boot for Windows User Guide Part Number 434706-00A September 2007 © Copyright 2007 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. The only warranties for HP products and services are set forth in the express warranty statements accompanying such products and services. Nothing herein should be construed as constituting an additional warranty. HP shall not be liable for technical or editorial errors or omissions contained herein. Confidential computer software. Valid license from HP required for possession, use or copying. Consistent with FAR 12.211 and 12.212, Commercial Computer Software, Computer Software Documentation, and Technical Data for Commercial Items are licensed to the U.S. Government under vendor’s standard commercial license. Audience assumptions This document is for the person who installs, administers, and troubleshoots servers and storage systems. HP assumes you are qualified in the servicing of computer equipment and trained in recognizing hazards in products with hazardous energy levels. Contents Overview..................................................................................................................................... 4 iSCSI boot for Windows overview ............................................................................................................... 4 Limitations ................................................................................................................................................ 5 System -
Chelsio T5/T4 Unified Boot for Linux & Windows
noteIf no This document and related products are distributed under licenses restricting their use, copying, distribution, and reverse-engineering. No part of this document may be reproduced in any form or by any means without prior written permission by Chelsio Communications. All third party trademarks are copyright of their respective owners. THIS DOCUMENTATION IS PROVIDED “AS IS” AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE USE OF THE SOFTWARE AND ANY ASSOCIATED MATERIALS (COLLECTIVELY THE “SOFTWARE”) IS SUBJECT TO THE SOFTWARE LICENSE TERMS OF CHELSIO COMMUNICATIONS, INC. Chelsio Communications (Headquarters) Chelsio (India) Private Limited 370 San Aleso Ave. Subramanya Arcade, Floor 3, Tower B Suite 100 No. 12, Bannerghatta Road, Sunnyvale, CA 94085 Bangalore-560029 U.S.A Karnataka, India www.chelsio.com Tel: +1-91-80-4039-6800 Tel: 408.962.3600 Fax: 408.962.3661 Chelsio KK (Japan) SHIMA Akasaka Bldg. Minato-ku, Tokyo Japan 107-0052 Tel: 03-6234-4353 Sales For all sales inquiries please send email to [email protected] Support For all support related questions please send email to [email protected] Copyright © 2015. Chelsio Communications. All Rights Reserved. Chelsio ® is a registered trademark of Chelsio Communications. All other marks and names mentioned herein may be trademarks of their respective companies. Chelsio T5/T4 Unified Boot for Linux & Windows ii Document Revision History Version Revision Date 1.0.0 05/18/2012 1.0.1 07/30/2012 1.0.2 10/05/2012 1.0.3 16/05/2012 1.0.4 07/31/2013 1.0.5 04/29/2014 1.0.6 09/05/2014 1.0.7 09/26/2014 1.0.8 10/13/2014 1.0.9 02/24/2015 1.1.0 05/05/2015 1.1.1 07/07/2015 Chelsio T5/T4 Unified Boot for Linux & Windows iii TABLE OF CONTENTS I. -
UEFI Firmware Overview on the HP Z210 Workstation
UEFI Firmware Overview on the HP Z210 Workstation The HP Z210 Workstation is the first model with system firmware based on UEFI standards; it also includes HP legacy BIOS compatibility. UEFI (Unified Extensible Firmware Interface) provides a modern 64-bit interface between the operating system and system firmware, and removes several limitations present in BIOS, including disk size, option ROM size, pre-boot access to files and the network. UEFI will also enable new features over time. HP recommends Windows® 7. Overview Feature Benefits Unicode Support Allows displaying a wider range of non-Latin characters Graphics support UEFI applications have direct access to high-resolution graphics. Menus are rendered graphically using a built-in forms browser. GPT support GPT (GUID Partition Table) is a disk partitioning mechanism that allows booting UEFI operating systems from disks larger than 2.2 TB. Booting on large drives will be enabled on models on which HP makes them available. Large option UEFI option ROMs for add-in cards can be any size. BIOS options ROMs were required to fit together in a 160 KB area. ROM support Add-in cards can contain both BIOS and UEFI option ROMs. Note that a BIOS-based operating system cannot boot using a UEFI option ROM, although a UEFI-based OS can boot using a BIOS option ROM. File system support Allows pre-boot access to files on any FAT12/FAT16/FAT32 or El Torito (optical) device. EFI shell The EFI shell is a simple command-line environment that is not hampered by DOS limitations. On the HP Z210, the EFI shell is available as a web download, as part of the “HP Workstation BIOS Utilities” Softpaq. -
CS3210: Booting and X86
1 CS3210: Booting and x86 Taesoo Kim 2 What is an operating system? • e.g. OSX, Windows, Linux, FreeBSD, etc. • What does an OS do for you? • Abstract the hardware for convenience and portability • Multiplex the hardware among multiple applications • Isolate applications to contain bugs • Allow sharing among applications 3 Example: Intel i386 4 Example: IBM T42 5 Abstract model (Wikipedia) 6 Abstract model: CPU, Memory, and I/O • CPU: execute instruction, IP → next IP • Memory: read/write, address → data • I/O: talk to external world, memory-mapped I/O or port I/O I/O: input and output, IP: instruction pointer 7 Today: Bootstrapping • CPU → what's first instruction? • Memory → what's initial code/data? • I/O → whom to talk to? 8 What happens after power on? • High-level: Firmware → Bootloader → OS kernel • e.g., jos: BIOS → boot/* → kern/* • e.g., xv6: BIOS → bootblock → kernel • e.g., Linux: BIOS/UEFI → LILO/GRUB/syslinux → vmlinuz • Why three steps? • What are the handover protocols? 9 BIOS: Basic Input/Output System • QEMU uses an opensource BIOS, called SeaBIOS • e.g., try to run, qemu (with no arguments) 10 From power-on to BIOS in x86 (miniboot) • Set IP → 4GB - 16B (0xfffffff0) • e.g., 80286: 1MB - 16B (0xffff0) • e.g., SPARCS v8: 0x00 (reset vector) DEMO : x86 initial state on QEMU 11 The first instruction • To understand, we first need to understand: 1. x86 state (e.g., registers) 2. Memory referencing model (e.g,. segmentation) 3. BIOS features (e.g., memory aliasing) (gdb) x/1i 0xfffffff0 0xfffffff0: ljmp $0xf000,$0xe05b 12 x86 -
Embedded Graphics Drivers and Video BIOS V6.1 User's Guide
Intel® Embedded Graphics Drivers and Video BIOS v6.1 User’s Guide December 2006 Document Number: 274041-011US INFORMATIONLegal Lines and Disclaimers IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families.