Model-Based Design and Adaptive Scheduling of Distributed Real-Time Systems
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Contention-Free Periodic Message Scheduler Medium Access Control in Wireless Sensor / Actuator Networks
Contention-Free Periodic Message Scheduler Medium Access Control in Wireless Sensor / Actuator Networks Thomas W. Carley Moussa A. Ba Rajeev Barua David B. Stewart ECE Department Embedded Research ECE Department Embedded Research University of Maryland Solutions University of Maryland Solutions [email protected] mba@embedded- [email protected] dstewart@embedded- zone.com zone.com Abstract actuator network applications have timeliness constrains, both on activities on individual nodes, and across multiple This paper presents a time division multiple access nodes. This results in timeliness constraints on both tasks medium access control protocol for wireless sensor / running on nodes and messages exchanged by nodes. actuator networks implemented with a contention-free Medium access control (MAC) is one of the most message scheduler. A message scheduler is used to important, and most studied, protocol layers in wireless determine which message has access to the medium at sensor / actuator networks. Wireless sensor / actuator any time. A set of messages is contention-free if only one networks are often characterized by extreme constraints message is ready at a time. Otherwise, some other on size, cost, power, and timeliness. This imposes criterion such as priority must be used to resolve constraints on every aspect of the design of these contention. In this case the message scheduler at each networks, especially the protocol stack. Wireless node in the network must schedule all messages in order networks are inherently broadcast media; all nodes in the to resolve contention. If the schedule is contention-free network share one common communication medium. however, then each node only schedules the messages that Therefore, a method for resolving contention when interest it. -
Open Dissertation Draft Revised Final.Pdf
The Pennsylvania State University The Graduate School ICT AND STEM EDUCATION AT THE COLONIAL BORDER: A POSTCOLONIAL COMPUTING PERSPECTIVE OF INDIGENOUS CULTURAL INTEGRATION INTO ICT AND STEM OUTREACH IN BRITISH COLUMBIA A Dissertation in Information Sciences and Technology by Richard Canevez © 2020 Richard Canevez Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy December 2020 ii The dissertation of Richard Canevez was reviewed and approved by the following: Carleen Maitland Associate Professor of Information Sciences and Technology Dissertation Advisor Chair of Committee Daniel Susser Assistant Professor of Information Sciences and Technology and Philosophy Lynette (Kvasny) Yarger Associate Professor of Information Sciences and Technology Craig Campbell Assistant Teaching Professor of Education (Lifelong Learning and Adult Education) Mary Beth Rosson Professor of Information Sciences and Technology Director of Graduate Programs iii ABSTRACT Information and communication technologies (ICTs) have achieved a global reach, particularly in social groups within the ‘Global North,’ such as those within the province of British Columbia (BC), Canada. It has produced the need for a computing workforce, and increasingly, diversity is becoming an integral aspect of that workforce. Today, educational outreach programs with ICT components that are extending education to Indigenous communities in BC are charting a new direction in crossing the cultural barrier in education by tailoring their curricula to distinct Indigenous cultures, commonly within broader science, technology, engineering, and mathematics (STEM) initiatives. These efforts require examination, as they integrate Indigenous cultural material and guidance into what has been a largely Euro-Western-centric domain of education. Postcolonial computing theory provides a lens through which this integration can be investigated, connecting technological development and education disciplines within the parallel goals of cross-cultural, cross-colonial humanitarian development. -
Slate XNS TSN Network Scheduler with Browser-Based Topology Modeling
Slate XNS TSN Network Scheduler with Browser-based Topology Modeling Key Benefits Intuitive graphical topology modeling Incremental scheduling of new components and data streams Open, standard configuration for any TSN device One-click scheduling for complex networks Optimized bandwidth use for non-scheduled traffic Slate XNS is a browser-based, user-friendly software that makes it easy to model topologies, create schedules and deploy configurations for TSN networks. Offline network configuration is made possible by the intuitive GUI which provides a topology view or table-based editor for managing components and data streams. Schedules are calculated with just one click via TTTech’s built-in scheduling engine, and network components are configured using open, standard YANG models. Topology Modeling Network Scheduler Graphical One-Click Scheduling The graphical view is ideal for modeling small and TTTech’s high performance scheduling engine is medium sized network topologies. New components built-in to the Slate XNS software. After building the can be added by dragging and dropping into the topology and defining the data streams, the schedule topology. Data streams can also be represented as can be created with just one click. Schedules can logical connections between components. even be updated incrementally when new components or data streams are added. Table-Based Slate XNS schedules IEEE 802.1Qbv and 802.1Qbu The table editor is designed for modeling large traffic as well as supporting cut-through data network topologies and mass editing. Components, streams. Scheduling can be adjusted to optimize data streams and other parameters can be inputted bandwidth for non-scheduled traffic. -
Hybrid Event-Time-Triggered Networked Control Systems: Scheduling-Event
Information Sciences 305 (2015) 269–284 Contents lists available at ScienceDirect Information Sciences journal homepage: www.elsevier.com/locate/ins Hybrid event-time-triggered networked control systems: Scheduling-event-control co-design ⇑ Shixi Wen a, Ge Guo a, , Wing Shing Wong b a School of Information Science and Technology, Dalian Maritime University, Dalian 116026, China b Department of Information Engineering, The Chinese University of Hong Kong, Hong Kong, China article info abstract Article history: This paper is concerned with the simultaneous stabilization of a collection of plants Received 19 August 2014 remotely controlled via a wireless network. The so-called most regular binary sequences Received in revised form 21 December 2014 (MRBSs) are used to allocate the limited network channels. To further reduce unnecessary Accepted 27 January 2015 transmissions, an event-triggered transmitter is introduced at each plant. Under the hybrid Available online 7 February 2015 event-time-triggered transmission strategy, a sufficient stability condition is derived for each plant. Then, a unified co-design framework is presented with which the scheduling Keywords: functions (i.e., the MRBSs), the event-triggering condition and the controller gains can be Networked control systems determined simultaneously. The main results are established using piecewise Lyapunov Capacity limitation Event-triggered transmission functional method and average dwell time technique. The effectiveness of the co-design Protocol sequence method is demonstrated by a numerical example. Scheduling-event-control co-design Ó 2015 Elsevier Inc. All rights reserved. 1. Introduction In wireless networked systems (such as wireless sensor networks) consisting of a large number of nodes, network capa- city limitation is often a serious issue. -
Graphpulse: an Event-Driven Hardware Accelerator for Asynchronous Graph Processing
2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing Shafiur Rahman Nael Abu-Ghazaleh Rajiv Gupta Computer Science and Engineering Computer Science and Engineering Computer Science and Engineering University of California, Riverside University of California, Riverside University of California, Riverside Riverside, USA Riverside, USA Riverside, USA [email protected] [email protected] [email protected] Abstract—Graph processing workloads are memory intensive GraphLab [31], GraphX [16], PowerGraph [17], Galois [37], with irregular access patterns and large memory footprint result- Giraph [4], GraphChi [28], and Ligra [49]. ing in low data locality. Their popular software implementations Large scale graph processing introduces a number of chal- typically employ either Push or Pull style propagation of changes through the graph over multiple iterations that follow the Bulk lenges that limit performance on traditional computing systems. Synchronous Model. The performance of these algorithms on First, memory-intensive processing stresses the memory system. traditional computing systems is limited by random reads/writes Not only is the frequency of memory operations relative of vertex values, synchronization overheads, and additional over- to compute operations high, the memory footprints of the heads for tracking active sets of vertices or edges across iterations. graph computations are large. Standard techniques in modern In this paper, we present GraphPulse, a hardware framework for asynchronous graph processing with event-driven schedul- processors for tolerating high memory latency, such as caching ing that overcomes the performance limitations of software and prefetching, have limited impact because irregular graph frameworks. Event-driven computation model enables a parallel computations lack data locality. -
RCD: Rapid Close to Deadline Scheduling for Datacenter Networks
RCD: Rapid Close to Deadline Scheduling for Datacenter Networks Mohammad Noormohammadpour1, Cauligi S. Raghavendra1, Sriram Rao2, Asad M. Madni3 1Ming Hsieh Department of Electrical Engineering, University of Southern California 2Cloud and Information Services Lab, Microsoft 3Department of Electrical Engineering, University of California, Los Angeles Abstract—Datacenter-based Cloud Computing services provide platform runs on multiple datacenters located in different a flexible, scalable and yet economical infrastructure to host continents. online services such as multimedia streaming, email and bulk Many applications require traffic exchange between data- storage. Many such services perform geo-replication to provide necessary quality of service and reliability to users resulting centers to synchronize data, access backup copies or perform in frequent large inter-datacenter transfers. In order to meet geo-replication; examples of which include content delivery tenant service level agreements (SLAs), these transfers have to networks (CDNs), cloud storage and search and indexing be completed prior to a deadline. In addition, WAN resources services. Most of these transfers have to be completed prior are quite scarce and costly, meaning they should be fully utilized. to a deadline which is usually within the range of an hour to Several recently proposed schemes, such as B4 [1], TEMPUS [2], and SWAN [3] have focused on improving the utilization of inter- a couple of days and can also be as large as petabytes [2]. datacenter transfers through centralized scheduling, however, In addition, links that connect these datacenters are expensive they fail to provide a mechanism to guarantee that admitted to build and maintain. As a result, for any algorithm used to requests meet their deadlines. -
Design and Performance of DDS-Based Middleware for Real- Time Control Systems
188 IJCSNS International Journal of Computer Science and Network Security, VOL.7 No.12, December 2007 Design and Performance of DDS-based Middleware for Real- Time Control Systems Tarek Guesmi, Rojdi Rekik, Salem Hasnaoui and Houria Rezig SysCom Laboratory, National School of Engineering of Tunis, Tunisia directly with subscribers (consumers) of data is more Summary efficient and flexible. Such a solution would allow the Data-centric design is emerging as a key tenet for building publishers of data to produce the data at a rate that is advanced data-critical distributed real-time and embedded consistent with the data production, and would allow systems. These systems must find the right data, know where to subscribers (consumers) of the data to receive the data at a send it, and deliver it to the right place at the right time. Data rate that consistent with the needs of the application. As Distribution Service (DDS) specifies an API designed for theory and practice in distributed real-time computing, enabling real-time data distribution and is well suited for such complex distributed systems and QoS-enabled applications. It is data-centric publish-subscribe (DCPS) and middleware also, widely known that Control Area Networks (CAN) are used networking mature, there is an increasing demand for in real-time, distributed and parallel processing. automated solutions in real-time DCPS middleware to Thus, the goal idea of this paper is to study an implementation of support scheduling end-to-end timing constraints. publish-subscribe messaging middleware that supports the DDS Data-centric design is key to systems which exhibit some specifications and that is customized for real-time networking. -
Power Architecture® Roadmap
TM Nikolay Guenov Rich Schnur Matt Short NPD June 2012 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MagniV, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. Overview • QorIQ Portfolio Overview • Market Overview • Roadmap • What’s new? (P5040, T2080, T1040) • Announcing our next generation networking architecture • Enablement Product Deep Dive • P5040/P5021 • T4240 • T2080 • T1042 The Next Generation – Initial Products Summary Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MagniV, MXC, Platform in a Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, TM 2 Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service -
(12> Ulllted States Patent (10) Patent N0.: US 6,801,943 B1
US006801943B1 (12> Ulllted States Patent (10) Patent N0.: US 6,801,943 B1 Pavan et al. (45) Date of Patent: Oct. 5, 2004 (54) NETWORK SCHEDULER FOR REAL TIME OTHER PUBLICATIONS APPLICATIONS Abbott, R.K., et al., “Scheduling I/O Requests With Dead (75) Inventors: Allalaghatta Pavan, Roseville, MN lines: a Performance Evaluation”, IEEE, pp- 113424, (US); Deepak R. (1990) Kenchammana'Hosekote, Sunnyvale, Arvind, K., et al., “A Local Area Network Architecture for CA (Us); Nemmara R- Vaidyanthan, Communication in Distributed Real—Time Systems,”, The Irvine> CA (Us) Journal of Real—Time Systems, 3(2), pp. 115—147, (May. (73) Assignee: Honeywell International Inc., 1991). Morristown, NJ (Us) B1yaban1, S.R., et al., The Integration of Deadline Cr1t1 calness in Hard Real—Time Scheduling”, Proceedings: Real —Time Systems Symposium, Huntsville, Albama, pp. ( * ) Notice: Subject to any disclaimer, the term of this 152—160, (1988)‘ patent is extended or adjusted under 35 USC 154(k)) by 0 days_ Boyer, RB, et al., “A reservation principle With applications to the ATM traf?c control”, Computer Networks and ISDN (21) Appl NO . 09/302 592 Systems, 24, North—Holland, pp. 321—334, (1992). .. , _ Chipalkatti, R., et al., “Scheduling Policies for Real—Time (22) Flled: Apr‘ 30’ 1999 and Non—Real—Time Traffic in a Statistical Multiplexer”, (51) Int. c1.7 .............................................. .. G06F 13/00 IEEE Infocom) The Con/"mme 0” Con/Pure’ Communica (52) US. Cl. ..................... .. 709/226; 718/103; 719/314; "0'18; PP~ 774483’ (1989) 719/321 L' I I‘ d I . (58) Field of Search ............................... .. 709/202, 205, ( 15 Comm on m Page) 709/223, 224, 226; 719/313, 314, 315, 316, 317, 319, 320, 321; 718/102, 103, Pnmary Exammer_vlet D‘ W (74) Attorney, Agent, or Firm—SchWegman, Lundberg, 104’ 105’ 107 Woessner & Kluth, PA. -
Partner Directory Wind River Partner Program
PARTNER DIRECTORY WIND RIVER PARTNER PROGRAM The Internet of Things (IoT), cloud computing, and Network Functions Virtualization are but some of the market forces at play today. These forces impact Wind River® customers in markets ranging from aerospace and defense to consumer, networking to automotive, and industrial to medical. The Wind River® edge-to-cloud portfolio of products is ideally suited to address the emerging needs of IoT, from the secure and managed intelligent devices at the edge to the gateway, into the critical network infrastructure, and up into the cloud. Wind River offers cross-architecture support. We are proud to partner with leading companies across various industries to help our mutual customers ease integration challenges; shorten development times; and provide greater functionality to their devices, systems, and networks for building IoT. With more than 200 members and still growing, Wind River has one of the embedded software industry’s largest ecosystems to complement its comprehensive portfolio. Please use this guide as a resource to identify companies that can help with your development across markets. For updates, browse our online Partner Directory. 2 | Partner Program Guide MARKET FOCUS For an alphabetical listing of all members of the *Clavister ..................................................37 Wind River Partner Program, please see the Cloudera ...................................................37 Partner Index on page 139. *Dell ..........................................................45 *EnterpriseWeb -
Falcon – Low Latency, Network-Accelerated Scheduling
Falcon – Low Latency, Network-Accelerated Scheduling Ibrahim Kettaneh1, Sreeharsha Udayashankar1, Ashraf Abdel-hadi1, Robin Grosman2, Samer Al-Kiswany1 1University of Waterloo, Canada 2Huawei Technologies, Canada ABSTRACT for short real time tasks [9]. We present Falcon, a novel scheduler design for large scale data To overcome the limitations of a centralized scheduler, large scale analytics workloads. To improve the quality of the scheduling data analytics engines [8, 10, 11, 12] have adopted a distributed decisions, Falcon uses a single central scheduler. To scale the scheduling approach. This approach employs tens of schedulers to central scheduler to support large clusters, Falcon offloads the increase scheduling throughput and reduce scheduling latency. scheduling operation to a programmable switch. The core of the These schedulers do not have accurate information about the load Falcon design is a novel pipeline-based scheduling logic that can in the cluster, they either use stale cluster data or probe a random schedule tasks at line-rate. Our prototype evaluation on a cluster subset of nodes to find nodes to run a given set of with a Barefoot Tofino switch shows that the proposed approach tasks [8, 10, 11]. The disadvantage of this approach is that the can reduce scheduling overhead by 26 times and increase the scheduling decisions are suboptimal, as they are based on partial scheduling throughput by 25 times compared to state-of-the-art or stale information, and the additional probing step increases the centralized and decentralized schedulers. scheduling delay. Furthermore, this approach is inefficient as it requires using tens of nodes to run the schedulers. -
High-Level Programming Model for Heterogeneous Embedded Systems Using
HIGH-LEVEL PROGRAMMING MODEL FOR HETEROGENEOUS EMBEDDED SYSTEMS USING MULTICORE INDUSTRY STANDARD APIS A Dissertation Presented to the Faculty of the Department of Computer Science University of Houston In Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy By Peng Sun August 2016 HIGH-LEVEL PROGRAMMING MODEL FOR HETEROGENEOUS EMBEDDED SYSTEMS USING MULTICORE INDUSTRY STANDARD APIS Peng Sun APPROVED: Dr. Chapman, Barbara Dept. of Computer Science, University of Houston Dr. Gabriel, Edgar Dept. of Computer Science, University of Houston Dr. Shah, Shishir Dept. of Computer Science, University of Houston Dr. Subhlok, Jaspal Dept. of Computer Science, University of Houston Dr. Chandrasekaran, Sunita Dept. of CIS, University of Delaware Dean, College of Natural Sciences and Mathematics ii Acknowledgements First and foremost, I would like to thank my advisor, Dr. Barbara Chapman, for her invaluable advice and guidance in my Ph.D. study. I appreciate all her dedi- cated guidance, and great opportunities to participate in those worthwhile academic projects, and the funding to complete my Ph.D. study. Her passion and excellence on academic and contributions to communities encourage me to finish my Ph.D. degree. Specifically, I am very grateful to Dr. Sunita Chandrasekaran for the mentoring and guidance for my research and publications. That help is paramount to my Ph.D. Journey. I truly could not achieve the degree without her mentoring and advisory. Special thanks to all my committee members: Dr. Edgar Gabriel, Dr. Shishir Shah, Dr. Jaspal Subhlok, for their time, insightful comments and help. I would also like to thank my fellow labmates of the HPCTools group: Dr.