PIC32 Family Reference Manual

Section 27. USB On-The-Go (OTG) HIGHLIGHTS This section of the manual contains the following major topics: 27 USB On-The-Go 27.1 Introduction .................................................................................................................. 27-2 27.2 Control Registers ......................................................................................................... 27-4 27.3 Operation ...................................................................................................................27-36 (OTG) 27.4 Host Mode Operation................................................................................................. 27-51 27.5 Interrupts.................................................................................................................... 27-59 27.6 I/O Pins ...................................................................................................................... 27-62 27.7 Operation in Debug and Power-Saving Modes.......................................................... 27-64 27.8 Effects of a Reset....................................................................................................... 27-66 27.9 Related Application Notes.......................................................................................... 27-67 © 2011 Microchip Technology Inc. DS61126F-page 27-1 PIC32 Family Reference Manual Note: This family reference manual section is meant to serve as a complement to device data sheets. Depending on the device variant, this manual section may not apply to all PIC32 devices. Please consult the note at the beginning of the “USB On-The-Go (OTG)” chapter in the current device data sheet to check whether this document supports the device you are using. Device data sheets and family reference manual sections are available for download from the Microchip Worldwide Web site at: http://www.microchip.com 27.1 INTRODUCTION The PIC32 USB OTG module includes the following features: • USB Full-Speed Support for Host and Device • Low-Speed Host Support • USB On-The-Go (OTG) Support • Integrated Signaling Resistors • Integrated Analog Comparators for VBUS Monitoring • Integrated USB Transceiver • Transaction Handshaking Performed by Hardware • Endpoint Buffering Anywhere in System RAM • Integrated Bus Master to Access System RAM and Flash • USB OTG module does not require the PIC32 DMA module for its operation The USB OTG module contains analog and digital components to provide a USB 2.0 full-speed and low-speed embedded host, full-speed device, or OTG implementation with a minimum of external components. This module in Host mode is intended for use as an embedded host and therefore does not implement a UHCI or OHCI controller. The USB OTG module consists of the clock generator, the USB voltage comparators, the transceiver, the Serial Interface Engine (SIE), a dedicated USB Bus Master, pull-up and pull-down resistors and the register interface. A block diagram of the USB OTG module is presented in Figure 27-1. The clock generator provides the 48 MHz clock, which is required for USB full-speed and low-speed communication. The voltage comparators monitor the voltage on the VBUS pin to determine the state of the bus. The transceiver provides the analog translation between the USB bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint buffers, and generates the hardware protocol for data transfers. The USB Bus Master transfers data between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the need for external signaling components. The register interface allows the CPU to configure and communicate with the module. IMPORTANT: The implementation and use of the USB specifications, as well as other third-party specifications or technologies, may require licensing; including, but not limited to, USB Implementers Forum, Inc. (also referred to as USB-IF). The user is fully responsible for investigating and satisfying any applicable licensing obligations. DS61126F-page 27-2 © 2011 Microchip Technology Inc. Section 27. USB On-The-Go (OTG) Figure 27-1: PIC32 USB OTG Interface Diagram USBEN FRC USB Suspend Oscillator 8 MHz Typical CPU Clock Not POSC (4) Sleep TUN<5:0> Primary Oscillator (5) (POSC) UFIN Div x PLL Div 2 (3) 24xPLL UFRCEN OSC1 (6) 27 FUPLLIDIV(6) UPLLEN USB Suspend To Clock Generator for Core and Peripherals USB On-The-Go OSC2 Sleep or Idle (1) (PBOUT) (OTG) USB OTG Module USB SRP Charge Voltage VBUS Comparators SRP Discharge 48 MHz USB Clock(7) Full-Speed Pull-up D+(2) Registers and Control Host Pull-down Interface SIE Transceiver Low-Speed Pull-up D-(2) Bus System Master RAM Host Pull-down ID Pull-up ID(8,9) (8) VBUSON VUSB Transceiver Power 3.3V Note 1: PB clock is only available on this pin for select EC modes. 2: Pins can be used as digital inputs when USB is not enabled. 3: This bit field is contained in the OSCCON register. 4: This bit field is contained in the OSCTRM register. 5: USB PLL UFIN requirements: 4 MHz ≤ UFIN ≤ 5 MHz. 6: This bit field is contained in the DEVCFG2 register. 7: A 48 MHz clock is required for proper USB operation. 8: Pins can be used as GPIO when the USB OTG module is disabled. 9: Pin is pulled high internally when USB OTG module is enabled. © 2011 Microchip Technology Inc. DS61126F-page 27-3 PIC32 Family Reference Manual 27.2 CONTROL REGISTERS The USB OTG module includes the following Special Function Registers (SFRs): • U1OTGIR: USB OTG Interrupt Status Register This register records changes on the ID, data and VBUS pins, enabling software to determine which event caused an interrupt. The interrupt bits are cleared by writing a ‘1’ to the corresponding interrupt. • U1OTGIE: USB OTG Interrupt Enable Register This register enables the corresponding interrupt status bits defined in the U1OTGIR register to generate an interrupt. • U1OTGSTAT: USB OTG Status Register This register provides access to the status of the VBUS voltage comparators and the debounced status of the ID pin. • U1OTGCON: USB OTG Control Register This register controls the operation of the VBUS pin, and the pull-up and pull-down resistors. • U1PWRC: USB Power Control Register This register controls the power-saving modes, as well as the module enable/disable control. • U1IR: USB Interrupt Register This register contains information on pending interrupts. Once an interrupt bit is set, it can be cleared by writing a ‘1’ to the corresponding bit. • U1IE: USB Interrupt Enable Register(1) The values in this register provide gating of the various interrupt signals onto the USB interrupt signal. These values do not interact with the USB OTG module. Setting any of these bits enables the corresponding interrupt source in the U1IR register. • U1EIR: USB Error Interrupt Status Register This register contains information on pending error interrupt values. Once an interrupt bit is set, it can be cleared by writing a ‘1’ to the corresponding bit. • U1EIE: USB Error Interrupt Enable Register(1) The values in this register provide gating of the various interrupt signals onto the USB interrupt signal. These values do not interact with the USB OTG module. Setting any of these bits enables the respective interrupt source in the U1EIR register, if the UERRIE bit (U1IE<1>) is also set. • U1STAT: USB Status Register(1) U1STAT is a 16-deep First In, First Out register (FIFO). It is read-only by the CPU and read/write by the USB OTG module. U1STAT is only valid when the TRNIF bit (U1IR<3>) is set. • U1CON: USB Control Register This register provides miscellaneous control and information about the module. • U1ADDR: USB Address Register U1ADDR is a read/write register from the CPU side and read-only from the USB OTG module side. Although the register values affect the settings of the USB OTG module, the content of the registers does not change during access. In Device mode, this address defines the USB device address as assigned by the host during the SETUP phase. The firmware writes the address in response to the SETUP request. The address is automatically reset when a USB bus Reset is detected. In Host mode, the module transmits the address provided in this register with the corresponding token packet. This allows the USB OTG module to uniquely address the connected device. DS61126F-page 27-4 © 2011 Microchip Technology Inc. Section 27. USB On-The-Go (OTG) • U1FRML: USB Frame Number Low Register and U1FRMH: USB Frame Number High Register U1FRML and U1FRMH are read-only registers. The frame number is formed by concatenat- ing the two 8-bit registers. The high-order byte is in the U1FRMH register, and the low-order byte is in U1FRML. • U1TOK: USB Token Register U1TOK is a read/write register required when the module operates as a host. It is used to specify the token type, PID<3:0> (Packet ID), and the endpoint, EP<3:0>, being addressed by the host processor. Writing to this register triggers a host transaction. • U1SOF: USB SOF Threshold Register U1SOF is a read/write register that contains the count bits of the Start of Frame (SOF) 27 threshold value, and are used in Host mode only. USB On-The-Go To prevent colliding a packet data with the SOF token that is sent every 1 ms, the USB OTG module will not send any new transactions within the last U1SOF byte times. The USB OTG (OTG) module will complete any transactions that are in progress. In Host mode, the SOF interrupt occurs when this threshold is reached, not when the SOF occurs. In Device mode, the interrupt occurs when a SOF is received. Transactions started within the SOF threshold are held by the USB OTG module until after the SOF token is sent. • U1BDTP1: USB BDT Register, U1BDTP2: USB BDT PAGE 2 Register, and U1BDTP3: USB BDT PAGE 3 Register These registers are read/write registers that define the upper 23 bits of the 32-bit base address of the Buffer Descriptor Table (BDT) in the system memory. The BDT is forced to be 512 byte-aligned. This register allows relocation of the BDT in real time. • U1CNFG1: USB Configuration 1 Register U1CNFG1 is a read/write register that controls the Debug and Idle behavior of the module.

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