Will Avalanche Photodiode Arrays Ever Reach 1 Megapixel? Edoardo Charbon Swiss Federal Institute of Technology, CH-1015 Lausanne, Switzerland Abstract— In this paper the miniaturization and performance one microsecond in CCD [4] and a few nanoseconds in potential of solid-state avalanche photodiodes is discussed in CMOS APS [5] have been demonstrated. While CCD streak the context of large multi-pixel sensors. Technological and cameras can achieve a resolution of a few picoseconds, they design trade-offs are discussed in view of recent advances in require a 2D pixel array to resolve a string of photon CMOS imaging technologies and the emergence of new arrivals. Moreover, long acquisition latency and the added multiplication based architectures. complexity to form and deflect the photoelectron beam I. INTRODUCTION make this device unsuitable for miniaturization and low- cost operation. In the last four decades, solid-state multiplication based Sensors based on solid-state APDs have been proposed photodetectors have gradually evolved from relatively decades ago to simultaneously achieve high sensitivity and crude devices to the sophistication of today. Almost every dynamic range, and low timing uncertainty [6]. In APDs, imaging technology has one such device and the range of carriers generated by the absorption of a photon in the p-n implementations is quite wide [1]. In this context, silicon junction, are multiplied by impact ionization thus producing avalanche photodiodes (APDs), thanks to their relative an avalanche. APDs can reach timing uncertainties as low simplicity and ease of fabrication, have recently attracted as a few tens of picoseconds, thanks to the speed at which significant interest. an avalanche evolves from the initial carrier pair forming in There are two main lines of research in silicon APDs: the multiplication region. one that advocates the use of highly optimized processes to An APD is implemented as photodiode reverse biased boost performance and one that proposes to adapt APD near or above breakdown, where it exhibits optical gains design to existing processes to reduce cost and to maximize greater than one. When an APD is biased below breakdown miniaturization. it is known as proportional or linear APD. It can be used to In this paper we focus on the latter approach and we detect clusters of photons and to determine their energy. discuss how the latest advances in imaging CMOS When biased above breakdown, the optical gain becomes processes may be used to maximize performance and to virtually infinite. Thus, with a relatively simple ancillary boost miniaturization. We also discuss how advanced electronics, the APD becomes capable of detecting single processes can ensure in-pixel and on-chip processing of photons. The APD operating in this regime, known as ultra-high-speed signals that are typical of single-photon Geiger mode of operation, is called single-photon detectors. avalanche diode (SPAD). II. SINGLE-PHOTON DETECTION AND SILICON APDS III. APD DESIGN IN STANDARD CMOS PROCESSES Devices for single-photon detection are realizable in many solid-state and non-solid-state implementations. A. Basic Structure Design While an in-depth discussion on the subject is beyond the There exist two main implementation styles for APDs. scope of this paper, we mention here two classes of The first, known as reach-through APD (RAPD) [7], is a detectors that are currently the solution of choice in many vertical structure, incompatible with planar CMOS applications: multichannel or microchannel plates (MCPs) processes. The second involves a shallow p or n layer to and photomultiplier tubes (PMTs) [2]. form high-voltage pn junctions. Cova and others have A number of solid-state solutions have been proposed as investigated devices designed in this style since the 1970s, a replacement of MCPs and PMTs using conventional yielding a number of structures equipped with a zone imaging processes. The challenge though has been to meet designed to prevent premature edge breakdown (PEB) [8]. single-photon sensitivity and low timing uncertainty. An early example of one such structure is shown in Fig. 1. To address the sensitivity problem, cooled and/or intensified CCDs, and ultra-low-noise CMOS APS n+ architectures have been proposed. Multiplication of p+ photogenerated charges by impact ionization has also been p-epi used in conventional CCDs [3]. Meeting PMT’s picosecond timing uncertainty however, n-substrate to the best of our knowledge, has not been possible in FIG. 1. CROSS-SECTION OF APDS THAT CAN BE FABRICATED IN A PLANAR CCD/CMOS imagers, even though uncertainties as low as PROCESS. 246 More recently, researchers have developed APDs both of charges to be easily detected and thus requiring no in linear and Geiger mode using dedicated processes, further amplification. achieving superior performance in terms of sensitivity and SPADs however require mechanisms to quench the noise. A good example is the work of Kindt [9]. The main avalanche. There exist two main quenching mechanisms: disadvantage of using dedicated processes is the lack of passive and active. In passive quenching the avalanche libraries that can support complex functionalities and deep- current is used to drop the voltage across the diode. This is submicron feature sizes, thus limiting array sizes. An generally accomplished via a ballast resistor placed on the interesting alternative is the use of a hybrid approach anode or the cathode of the diode, as shown in Fig. 3. whereby the APD array and ancillary electronics are Avalanche detection is accomplished measuring the voltage implemented in two different processes, each optimized for across the ballast resistance (Fig. 3a, b) or the current APD performance and speed, respectively [10]. across a low- or zero-resistivity path (Fig. 3c, d). Pulse In 2003 the integration of linear and Geiger mode APDs shaping may be performed using a comparator (Fig. 3e). in a low-cost CMOS process has become feasible [11]. Excess bias voltage equals |VOP| - |Vbd|, where Vbd is the PEB prevention is accomplished forcing the electric field breakdown. The resistances may be implemented in everywhere to be lower than that on the planar polysilicon [11],[12] or exploiting the non-linear multiplication region, where it should be uniform. characteristics of PMOS or NMOS devices [13],[14]. V V V V p p+ OP OP OP OP n+ p- I R x X V Vx X x n n Vth IxR a) b) e) a) b) c) d) p p FIG. 3. PASSIVE QUENCHING VARIANTS. VOLTAGE DETECTION MODE (LEFT); CURRENT DETECTION MODE (RIGHT). In active quenching mode, the avalanche activates an n active device to stop it. The literature on the subject is c) extensive. In [15] some of the existing schemes can be found. Other authors have recently revisited the issue [16]. After quenching, the device enters another phase known as recharge. During this phase the photodiode bias voltage FIG. 2. TECHNIQUES FOR PREVENTION OF PREMATURE EDGE BREAKDOWN must return to the pre-avalanche state as quickly as (PEB) IN PLANAR PROCESSES. possible. Again, there are passive and active schemes to Fig. 2 shows some of the most used structures. In a) the achieve recharge. The simplest approach is shown in Fig. 3. n+ layer maximizes the electric field in the middle of the The diode will automatically recharge to VOP via the ballast diode. In b) a lightly doped p- implant reduces the electric resistance. The recharge, in this case, follows the RC field at the edge of the p+ implant. In c) a floating p exponential, where R is the equivalent quenching resistance implant locally increases the breakdown voltage. With a and C the total parasitic capacitance at node X. polysilicon gate one can further extend the depletion region In active recharge schemes, the photodiode is forced to (gray line in the figure). The figure also shows a 3D cross- the initial state generally via a fast switch controlled by a section of b) including a p-substrate and an n-well isolation. current sense amplifier. Even though these schemes are Modern imaging processes (with or without STI) attractive, they usually require extra complexity to a pixel, provide several lightly doped implants at three or more thus potentially hindering miniaturization. depths. Thus, an optimal layer combination (p+/p-/n-well) The quenching and recharge times are collectively generally exists that can yield a good trade-off between known as dead time. Dead time in passive timing uncertainty and noise. However, care should be used quenching/recharge methods is potentially longer than in so as to avoid full depletion of the well and punch- their active counterparts. However, the advantage of a through’s between shallow tubs and substrate. Buried reduced dead time in large array may be preempted by layers should also be used with care to prevent punch- limited speeds of pixel readout schemes. through across the n-well. C. The Importance of Miniaturization B. Quenching and Recharge Mechanisms The first SPAD implementations in 0.35µm CMOS Linear APDs are multi-photon detectors, when used as technology have demonstrated fully scalable pixels at a charge accumulators. Charges generated at each avalanche pitch of 25µm. However, for a realistic Mpixel sensor are integrated and amplification may not be needed. In realization, this limit should be further reduced. single-photon detection mode, fast amplifiers are generally Pixel miniaturization has other benefits too. The used, adding to jitter and dark noise. SPADs on the reduction of anode and cathode areas, in SPADs generally contrary can only operate in single-photon mode. This is reduces the dark count rate (DCR), i.e. the average achieved operating the diode above breakdown by a voltage frequency of spurious pulses in the dark [11]. It also known as excess bias voltage. Upon photon absorption, an reduces parasitic capacitance at node X (Fig.