Datasheet UltraSPARC® IV On the Web www.sun.com/processors

UltraSPARC® IV Processor

Designed for mission-critical enterprise, high performance technical computing (HPTC), and compute-intensive applications.

Key Highlights Executing on Sun’s Throughput Computing Strategy

® • 64-bit open standards-based SPARC® V9 Throughput Computing is the underlying strategy of Sun’s new family of UltraSPARC processors, architecture compatible with VISTM which are designed to significantly increase real-world application processing throughput. At the Instruction Set heart of this new strategy is Chip Multithreading (CMT), a design concept that would eventually allow processors to execute tens of threads simultaneously. The dual-threaded UltraSPARC IV • First milestone in the CMT processor processor marks the first milestone in Sun’s CMT processor roadmap. roadmap from Sun Developed in concert with the SolarisTM Operating Environment to meet the performance, • Dual-threaded processor based on reliability, and scalability requirements of mission-critical enterprise, HPTC, and other compute- UltraSPARC III pipeline intensive applications, the UltraSPARC IV processor can almost double the current UltraSPARC III

• Provides up to 2 times the application processor-based system throughput. throughput of UltraSPARC III processor The UltraSPARC IV processor is binary compatible with previous generations of SPARC processors and will support both versions 8 and 9 of the Solaris Operating Environment. This is • Binary compatibility with previous consistent with Sun’s commitment to protecting customers’ investments in software and generations of SPARC processors training. The UltraSPARC IV processor can also provide an upgrade path for servers powered by • Can provide an upgrade path for servers the existing UltraSPARC III processor. powered by UltraSPARC III processor

• On-chip tags for 16 MBs of off-chip level 2 cache (8 MB per pipeline)

• On-chip supporting up to 16 GBs of DRAM

• Shared system interface to the SunTM interconnect

• Maximum power consumption: 108 W at 1.35 V, 1.2 GHz

• 1368-pin LGA package

• Clock frequencies: 1.05 and 1.2 GHz

UltraSPARC IV Processor Datasheet UltraSPARC® IV Processor On the Web www.sun.com/processors

UltraSPARC® IV Processor Features and Benefits

Processor Features Speculative execution of instructions after branches Enhanced Support from Solaris Dual thread execution based on two UltraSPARC III pipelines Speculative memory loads Multiprocessor (MP) support provided by the Solaris Operating L1 cache (per pipeline): 64 KB data, 32 KB instruction, 2 KB write, 95% branch prediction accuracy (16 K-entry branch prediction table) Environment 2KB prefetch System models for tightly coupled, shared memory and for large Level 2 cache : On-chip tags for 16 MBs off-chip, 2-way set- Data Integrity multi-processor clustered architectures (snoop and directory-based) associative, LRU eviction policy, and reduced sub-blocked cache. EDC (Error Detection and Correction) using ECC (Error Correction Exclusive access to 8MB per pipeline Codes) or parity on all major SRAMs and data buses inside and System Bus Architecture On-chip SDRAM memory controller outside the processor 150 MHz clock frequency with peak bandwidth of 2.4 GB/s Shared system interface to Sun Fireplane interconnect system bus Error removal and recovery system to help prevent the propaga- Distributed bus arbitration Enhanced Floating Point Unit with additional hardware support tion of copy-back errors Fast on-chip snoop tags to maintain system bus performance for IEEE 754-1985 exceptions Diagnostic bus to monitor processor internals and address Large, wide data crossbar switches system errors, independent of the main system interface CMT enhancements support Sun Standard CMT model helping to Processor memory bandwidth scales with number of processors assure compatibility with current and future operating system interaction Memory Subsystem Physical Characteristics Integrated memory controller Package: 1368-pin LGA Pipeline Design Memory size: 16 GB per processor Transistor count: 66 million 14-stage non-stalling pipeline Memory Interface: SDRAM Maximum power dissipation: 108 W at 1.35 V, 1.2 GHz Sustainable 4-way superscalar Process: TI's CMOS 0.13µ, 7-layer copper Six parallel execution units (2 integer, 1 branch, 1 load/store, 2 FP/VIS)

SDRAM Memory (16 GB total)

Memory Controller L2 Cache Tags UltraSPARC III Pipeline (L1 Caches) System I/O Interconnect

External L2 Cache Arbiter 8 MB per pipeline (16 MB total)

Arbiter L2 Cache Tags UltraSPARC III Pipeline (L1 Caches)

System UltraSPARC IV Processor

UltraSPARC IV Processor Block Diagram

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