Power and Energy Impact by Loop Transformations Hongbo Yang†, Guang R. Gao†, Andres Marquez†, George Cai‡, Ziang Hu† † Dept of Electrical and Computer Engineering ‡ Intel Corp University of Delaware 1501 S. Mopac Expressway, Suite 400 Newark, DE 19716 Austin, TX 78746 hyang,ggao,marquez,hu ¡ @capsl.udel.edu
[email protected] Power dissipation issues are becoming one of the closely coupled, and we should not evaluate in- major design issues in high performance processor dividual effects in complete isolation. Instead, it architectures. is very useful to assess the combined contribu- In this paper, we study the contribution of com- tion of both, high-level and low-level loop opti- piler optimizations to energy reduction. In particu- mizations. lar, we are interested in the impact of loop optimiza- ¢ In particular, results of our experiments are tions in terms of performance and power tradeoffs. summarized as follow: Both low-level loop optimizations at code generation (back-end) phase, such as loop unrolling and soft- – Loop unrolling reduces execution time ware pipelining, and high-level loop optimizations at through effective exploitation of ILP from program analysis and transformation phase ( front- different iterations and results in energy end), such as loop permutation and tiling, are stud- reduction. ied. – Software pipelining may help in reducing In this study, we use the Delaware Power-Aware total energy consumption – due to the re- Compilation Testbed (Del-PACT) — an integrated duction of the total execution time. How- framework consisting of a modern industry-strength ever, in the two benchmarks we tested, compiler infrastructure and a state-of-the-art micro- the effects of high-level loop transforma- architecture-level power analysis platform.