DRM012, USB 3D Mouse Interface Reference Design

Freescale Semiconductor, Inc.

. USB 3D Mouse

c Interface

Reference Design

o t Designer Reference

c u Manual

M68HC08

Microcontrollers

DRM012/D

Rev. 0.0, 3/2003

MOTOROLA.COM/SEMICONDUCTORS

For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc.

USB 3D Mouse Interface

. Reference Design

c Designer Reference Manual — Rev 0

n by: Derek Lau

Motorola Ltd

Hong Kong

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Designer Reference Manual DRM012 — Rev — DRM012 0 4 Designer Reference Manual Freescale Semiconductor,Inc.

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n t f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m d u c t , MOTOROLA

Freescale Semiconductor, Inc.

Designer Reference Manual — DRM012

Table of Contents

Section 1. USB 3D Mouse Interface

. . 1.1 Introduction...... 7

I 1.2 Overview...... 7

r 1.3 MC68HC08JB1 Features ...... 7

o t 1.4 Hardware Descriptions ...... 8

c u 1.5 Firmware Descriptions ...... 8

1.6 Firmware Files ...... 16

i 1.7 Test Description ...... 16

1.8 Customization ...... 16

1.9 Extra Features ...... 17

1.10 Further Information ...... 17

Section 2. Glossary

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Table of Contents al fCnet MOTOROLA Rev — DRM012 0 Table of Contents 6 Designer Reference Manual Freescale Semiconductor,Inc.

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Freescale Semiconductor, Inc.

Designer Reference Manual — DRM012

Section 1. USB 3D Mouse Interface

1.1 Introduction

This document describes a reference design of a Universal Serial Bus

. 3D Mouse Interface for Microsoft Windows by using the MC68HC08JB1.

c For detailed specification on the MC68HC08JB1 device, please refer to

I the data sheet; Motorola order number: MC68HC08JB1/D.

c 1.2 Overview

d The Motorola MC68HC08JB1 (hereafter referred as JB1) is a member of

n the HC08 Family of microcontrollers (MCUs). The features of the JB1

include a Universal Serial Bus (USB), which makes this MCU suited for

personal computer Human Interface Devices (HID), such as mice. A

USB 3D Mouse is demonstrated using the JB1. The main features of the

mouse include:

e • Fully USB Specification 1.1 compliant

• Windows 98, ME and 2000 compatible

• 3D wheel support

r F 1.3 MC68HC08JB1 Features

The JB1 is targeted for USB and PS/2 interface mouse applications with minimum external components needed. Features to note are:

• USB D+ and D– pins shared with PS/2 data and clock pins • Eight Keyboard interrupt pins for button press and release detection • 50mA direct drive pins for the infrared X, Y and Z LEDs

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1.4 Hardware Descriptions 1.4 Hardware Interface Mouse USB 3D S DMueItraeMOTOROLA Rev — DRM012 0 USB 3D Mouse Interface 8 Designer Reference Manual Descriptions 1.5 Firmware The firmware consistsofthree parts:main Figure 1-1 • USB USB Interrupt Routine • USB Handler Routine • Routine Main • Threebuttons locatedatthe left, under thewheel and at the right • Threecorresponding sensors fortheX, directionsZY and • ThreeLEDs for the YX,and directionsZ • JB1, theUSB microcontroller • Freescale Semiconductor,Inc.

F o

M Y Sensor X Sensor Z SensorZ Y LED Y LED X Z LED shows the blocksolutionincludes:diagram. The

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n t f o o : r w m w a Figure 1-1.BlockDiagram.Figure t w i o . f n r e O e n MC68HC08JB1 s c T a h l i e s . c P o r o m d u c t , Wheel Button Wheel Right Button Right Left Button Left USB Plug

Freescale Semiconductor, Inc. USB 3D Mouse Interface

Main Routine USB Interrupt Routine USB Handler

Movement Detection Handle EOP Standard Requests

Button Detection Control Transfer (EP0) HID Requests

USB Data Processing Interrupt Transfer (EP1)

Other Interrupts Resume

. . Figure 1-2. Firmware Routines. .

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USB 3D Mouse Interface Mouse USB 3D 0UB3 os nefc MOTOROLA Rev — DRM012 0 USB 3D Mouse Interface 10 Designer Reference Manual NO NO CALCULATE MOVEMENT CALCULATE DIRECTION TO REPORT TO DIRECTION CHANGES TO REPORT TO CHANGES USB INITIALIZATION INITIALIZATION USB DISPLACEMENT AND DISPLACEMENT CONVERT BUTTON CONVERT NEW ENDPOINT 1 USB USB BUTTON STATUS CONFIGURED? MOVEMENT ? MOVEMENT SUSPEND CHANGED ? CHANGED REPORT? DEVICE IDLE 6 ms? DEVICE DEVICE IS IN SUSPEND IN IS DEVICE ES FOR YES YES YES YES Freescale Semiconductor,Inc.

F o

M YES

o Figure 1-3. Main Routine Main 1-3. Figure NO

NO r G e PRESSED ? PRESSED BUTTON o I

n t f o o : r w m

EP YES w a 1 t w EMPTY? BUFFER TX NO i o NO . f n r e O e n s c INTERRUPT? T a h RESUME IRQ PIN FORCE l i e s . c P NO YES o r o m d u c t YES YES , TX EP1 IN REPORT MOVEMENT? FOR 5MS? BUS IDLE BUS NO YES NO .

Freescale Semiconductor, Inc. USB 3D Mouse Interface

1.5.1 USB Main Routine

Figure 1-3 shows the flow of the main routine. It detects if there is any movement in the X, Y and Z directions. If there is any movement, it calculates the displacements and directions of the movements, converts them into report format and stores the data in the report buffer. It then checks if there is any button status changes from pressed to released or from released to being pressed. The information is converted into report format and stored in the report buffer. If the USB Endpoint 1 transmit buffer is not full, it copies data from the report buffer to the Endpoint 1

. transmit buffer and waits for the host to send an IN token to read the . data.

I If the USB bus idles for more than 6ms, the routine puts the JB1 into

r STOP. While JB1 is in STOP, any button press or external IRQ interrupt

o can wake up the JB1. External RC in the IRQ pin periodically wakes up

c JB1 to detect if any movement happens as shown in Figure 1-4. If any u button press or movement is detected, JB1 sends a resume signal to the d host for remote wakeup. If a resume signal from host is detected, JB1

will be woken up and it will not send any resume signal to the host.

Vcap

Vthreshold

interrupt a

e 450ms5ms 450ms

MCU e RUN STOP Status STOP

F Wait for interrupt Check Wait for interrupt Check Task from external RC timer movement from external RC timer movement

Figure 1-4. RC Timer in Suspend Mode

1.5.2 USB Interrupt Routine

Figure 1-5 shows the flow of the USB interrupt routine. The USB engine automatically responds to a valid USB token with either ACK, NAK or

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USB 3D Mouse Interface Mouse USB 3D 2UB3 os nefc MOTOROLA Rev — DRM012 0 USB 3D Mouse Interface 12 Designer Reference Manual thecorresponding preparation for the nextstage. The firmware first distinguishes the kinds of transferscontrol and does Data(optional) Statusand as shown below: Transfers. Control transfers have two or three transaction stages: Setup, Figure 1-7 commandor datareceived. preparation forthenext transactionUSB handlesany and valid received dataor transmitted.The interrupt USB routinealsomakes executed whenever there is an EOP, resume signal from host, valid data response in to the token differentThe stages.beinterrupt USB will The firmware has to set the registers for the USB engine to give correct dependingSTALL on the registers setting,and ignores it it if isinvalid. NoData Control: SETUP, IN • OUT IN... IN, IN, SETUP, Read: Control • Control Write: SETUP, OUT, OUT... IN • Freescale Semiconductor,Inc.

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Freescale Semiconductor, Inc. USB 3D Mouse Interface

USB INTERRUPT ROUTINE

NO EOP?

YES

RESET SUSPEND COUNTER

c n YES I SETUP HANDLER SETUP?

r o NO

c OUT TOKEN YES u OUT EP0 HANDLER TO EP0?

c YES

IN EP0 HANDLER

EP0 TX COMPLETED?

YES

e DISABLE EP1 TRANSMIT & EP1 TX COMPLETED?

CLEAR EP1 TX FLAG

YES RESUME FROM CLEAR RESUME FLAG e HOST?

F NO

RETURN FROM INTERRUPT

Figure 1-5. USB Interrupt Routine

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USB 3D Mouse Interface Mouse USB 3D 4UB3 os nefc MOTOROLA Rev — DRM012 0 USB 3D Mouse Interface 14 Designer Reference Manual 4.SET NAK TO IN EP0 IN TO NAK 4.SET FLAG RX EP0 3.CLEAR 2.COPY 8 BYTE SETUP OUT & IN 0 EP 1.UNSTALL DATA TO RAM BUFFER RAM TO DATA Freescale Semiconductor,Inc.

STANDARD DEVICE DEVICE STANDARD OUT EP0 HANDLER EP0 OUT SETUP HANDLER SETUP F STATUS STAGE ? STAGE STATUS RETURN STALL RETURN o RETURN STALL RETURN

REQUEST ?

VALID DATA VALID REQUEST ? REQUEST r HID CLASS HID

NO r NO NO G e NO o I

n t Figure 1-7. OUT Endpoint 0 Handler 0 Endpoint 1-7. OUT Figure f o o : r w m w a Figure 1-6. Setup Routine Setup 1-6. Figure t w i YES YES YES o YES . f n r e O e n s c T a h (CONTROL TRANSFER TRANSFER (CONTROL OUT EP0 TO STALL SET 2. IN EP0 TO NAK SET 1. 2. PROCESS OUT DATA OUT PROCESS 2. BUFFER TO DATA COPY 1. l i e s COMPLETED) . HANDLE STANDARD STANDARD HANDLE c CLASSE REQUEST P DEVICE REQUEST DEVICE o r HANDLE HID HANDLE o m d u c t , RETURN RETURN

Freescale Semiconductor, Inc. USB 3D Mouse Interface

IN EPO HANDLER

SET NAK TO IN EP0

SET STALL TO EP0 OUT YES STATUS STAGE ? (CONTROL TRANSFER COMPLETED)

. NO [DATA STAGE]

n YES I ALL DATA PREPARE FOR OUT STAGE

, SENT?

o NO

t PREPARE FOR c RETURN NEXT DATA STAGE

Figure 1-8. IN Endpoint 0 Handler

1.5.3 USB Mouse Report

The mouse implements an HID mouse in interface 0 (endpoint 1) with an

e extended report to boot protocols. This implementation enables the

a mouse to work in BIOS setup and in DOS mode. The first 3 bytes of the

input reports are identical to the standard mouse boot protocol report

(see Table 1-1) as documented in the Device Class Definition for Human

e Interface Device (HID) version 1.1. This implementation adds one more r byte for Z movement to form 4-byte input reports.

Table 1-1. Interface 0 Input Report Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Middle Right Left 0 0I0000 Button Button Button 1 X Movement 2 Y Movement 3 Z Movement

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1.6 Firmware Files 1.6 Firmware Interface Mouse USB 3D 6UB3 os nefc MOTOROLA Rev — DRM012 0 USB 3D Mouse Interface 16 Designer Reference Manual 1.8.1 Hardware 1.8 Customization Description 1.7 Test Table 1-2Table Microcomputer Systems,Inc. Firmware compiled isversion under CASM08Z.EXE 3.16 from P&E B-Q. JB8 registers and memory definitions JB8-EQS.H USB interrupt USB-MSE3.H USB handler MARCO.ASM 8USB-ISR.ASM 8-HIDPRO.ASM JB8-MSE3.ASM Adjustthevalues ofthe serial resistors of the infraredLEDs • Compatibility tests 750,under AMD Intel 810 set chip Desktops, • Compatibility tests under Windows 98SE. • USBCheck version3.2and HIDView version3.6. • The solution was tested under differentWindowsoperating • Freescale Semiconductor,Inc.

F o according to the LEDcharacteristics. and IBMThinkpad 570, 600E. systemson severalbrands of PCs.

M summarizesthe functions of firmwareeach file: ie Functions Files

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n t f o o Table Examples Report Input 1-2. : r w m w a t w i o . f n r USB control transfer handler USB interrupt USB Data handling Buttons Status detection Movement detection Define constants and variables and report descriptors configure,Device, interface, endpoint, HID, string e O e n s c T a h l i e s . c P o r o m d u c t ,

Freescale Semiconductor, Inc. USB 3D Mouse Interface

1.8.2 Firmware

• Change USB interrupt and handler routines to meet the new USB testing requirements in Command Verifier. • Change vendor ID, product ID and product revision number in the device descriptor table in "USE-MSE3.H" • Change vendor name and product name in the string descriptor table in "USB-MSE3.H" • Change the report descriptor in "USB-MSE3.h" if necessary.

n 1.9 Extra Features

o t 1.10 Further Information

n 1.10.1 Related Documents

MC68HC908JB1 Technical Data

Universal Serial Bus Specification, version 1.1

Device Class Definition for Human Interface Device (HID), version 1.1

USB HID Usage Tables, version 1.1

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USB 3D Mouse Interface Mouse USB 3D 8UB3 os nefc MOTOROLA Rev — DRM012 0 USB 3D Mouse Interface 18 Designer Reference Manual Freescale Semiconductor,Inc.

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Freescale Semiconductor, Inc.

Designer Reference Manual — DRM012

Section 2. Glossary

A — See “accumulator (A).” accumulator (A) — An 8-bit general-purpose register in the CPU08. The CPU08 uses the accumulator to hold operands and results of arithmetic and logic operations.

. acquisition mode — A mode of PLL operation during startup before the PLL locks on a frequency. Also

. see “tracking mode.”

c n address bus — The set of wires that the CPU or DMA uses to read and write memory locations.

, addressing mode — The way that the CPU determines the operand address for an instruction. The

r M68HC08 CPU has 16 addressing modes.

o t ALU — See “arithmetic logic unit (ALU).”

c u arithmetic logic unit (ALU) — The portion of the CPU that contains the logic circuitry to perform d arithmetic, logic, and manipulation operations on operands.

asynchronous — Refers to logic circuits and operations that are not synchronized by a common

c reference signal.

baud rate — The total number of bits transmitted per unit of time.

BCD — See “binary-coded decimal (BCD).”

binary — Relating to the base 2 number system.

binary number system — The base 2 number system, having two digits, 0 and 1. Binary arithmetic is

convenient in digital circuit design because digital circuits have two permissible voltage levels, low

and high. The binary digits 0 and 1 can be interpreted to correspond to the two digital voltage

levels.

e binary-coded decimal (BCD) — A notation that uses 4-bit binary numbers to represent the 10 decimal r digits and that retains the same positional structure of a decimal number. For example, F 234 (decimal) = 0010 0011 0100 (BCD) bit — A binary digit. A bit has a value of either logic 0 or logic 1. branch instruction — An instruction that causes the CPU to continue processing at a memory location other than the next sequential address. break module — A module in the M68HC08 Family. The break module allows software to halt program execution at a programmable point in order to enter a background routine. breakpoint — A number written into the break address registers of the break module. When a number appears on the internal address bus that is the same as the number in the break address registers, the CPU executes the software interrupt instruction (SWI).

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CPU clock CPU08 CPU clock counter COP control unit control bit condition code register (CCR) (COP) module properly operating computer comparator clock clock generator module (CGM) clock clear CGM central processor unit (CPU) CCR C byte bus bus clock bus interrupt break Glossary 0Gosr MOTOROLA DRM012 — Rev 0.0 Glossary 20 Designer Reference Manual — The carry/borrow bit in the condition code register. The CPU08 sets the carry/borrow bit when an an when bit carry/borrow the sets CPU08 The register. code condition the in bit carry/borrow The — Aset— of wires that transfers logic signals. — A — ofset eight bits. — See “central processor unit (CPU).” unit processor “central See — — See “computer operating properly module (COP).” module properly operating “computer See — — See “condition code register.” code “condition See — — To change a bit from logic 1 to logic 0; the opposite of of set. opposite 0; the to logic 1 logic from bit a change To — — A square wave signal used to synchronize events in a computer. a in events to synchronize used signal wave square A — — See “clock generator module (CGM).” module generator “clock See — — central The processor unit of theFamily. M68HC08 frequency isequal to the frequency of the oscillator output, by divided CGMXCLK, four. interface. bus and control unit drive the execution unit, which contains the arithmetic logic unit (ALU), CPU registers, the of outputs The operations. requested the perform that signals control internal the generates the synchronize machine and direct various operations. The control unit decodes and instructions five bits that indicate the results of the instruction just executed. theMCU if allowed to overflow. numbers. binary two between differences relative or equality and or phase-locked loop (PLL) circuit. (PLL) loop phase-locked or and signal from which the system clocks are derived. The CGM may include a crystal oscillator circuit the execution of of instructions. execution the the carry/borrow bit (as in bit test and branch instructions and shifts and rotates). requires a borrow. Some logical operations and data manipulation instructions also clear or set addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation f registers. address break the in written is that value same op , isequal to the frequencyof the oscillator output, CGMXCLK, divided four.by — The bus clock is derived from the CGMOUT output from the CGM. The bus clock frequency, — One bit of a register manipulated by software to control the operation of the module. the of operation the to control software by manipulated register a of bit One — — CPUclock The isderived from the CGMOUT output from the clockCGM. The CPU — — ofOne two major units of the CPU. control The unit containslogic functions that — A device that compares the magnitude of two inputs. A digital comparator defines the the defines comparator digital A inputs. two of magnitude the compares that device A — — The input clock to the TIM counter. This clock is the output of the TIM prescaler. TIM the of output the is clock This counter. TIM the to clock input The — — A software interrupt caused by the appearance on the internal address bus of the the of bus address internal the on appearance the by caused interrupt software A — Freescale Semiconductor,Inc.

— The primary functioning unit of any computer system. The CPU controls F — An 8-bit register in the CPU08 that contains the interrupt mask bit and — A module in the M68HC08 Family. The CGM generates a base clock o

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— A counter module in the M68HC08 Family that resets resets that Family M68HC08 in the module counter A — w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m d u c t ,

Freescale Semiconductor, Inc. Glossary

CPU cycles — A CPU cycle is one period of the internal bus clock, normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal. The length of time required to execute an instruction is measured in CPU clock cycles. CPU registers — Memory locations that are wired directly into the CPU logic instead of being part of the addressable memory map. The CPU always has direct access to the information in these registers. The CPU registers in an M68HC08 are: • A (8-bit accumulator) • H:X (16-bit index register) • SP (16-bit stack pointer) • PC (16-bit program counter)

. • CCR (condition code register containing the V, H, I, N, Z, and C bits)

c CSIC — customer-specified integrated circuit

I cycle time — The period of the operating frequency: tCYC =1/fOP.

r decimal number system — Base 10 numbering system that uses the digits zero through nine.

t direct memory access module (DMA) — A M68HC08 Family module that can perform data transfers

c between any two CPU-addressable locations without CPU intervention. For transmitting or u receiving blocks of data to or from peripherals, DMA transfers are faster and more code-efficient d than CPU interrupts.

DMA — See “direct memory access module (DMA).”

i DMA service request — A signal from a peripheral to the DMA module that enables the DMA module to

transfer data.

e duty cycle — A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is usually

S represented by a percentage.

EEPROM — Electrically erasable, programmable, read-only memory. A nonvolatile type of memory that

can be electrically reprogrammed.

c EPROM — Erasable, programmable, read-only memory. A nonvolatile type of memory that can be erased

by exposure to an ultraviolet light source and then reprogrammed.

e exception — An event such as an interrupt or a reset that stops the sequential execution of the r instructions in the main program.

F external interrupt module (IRQ) — A module in the M68HC08 Family with both dedicated external interrupt pins and port pins that can be enabled as interrupt pins. fetch — To copy data from a memory location into the accumulator. firmware — Instructions and data programmed into nonvolatile memory. free-running counter — A device that counts from zero to a predetermined number, then rolls over to zero and begins counting again. full-duplex transmission — Communication on a channel in which data can be sent and received simultaneously.

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logic 1 logic leastsignificant bit (LSB) latency LVI low voltage inhibit (LVI)module byte low IRQ I/O request interrupt latch jitter logic 0 logic H H Glossary 2Gosr MOTOROLA DRM012 — Rev 0.0 Glossary 22 Designer Reference Manual interrupt instructions input/output (I/O) index register (H:X) I illegalopcode illegaladdress high byte hexadecimal — The The — interrupt maskbit in the conditioncode register of the CPU08. I When is set, all interruptsare — half-carry The bitin the conditioncode register of CPU08. the Thisbit indicates a carry from the — upper The byteof the 16-bit index register (H:X)in theCPU08. — “low See voltageinhibit module(LVI).” — See “input/output (I/0).” “input/output See — — See “external interrupt module (IRQ).” module interrupt “external See — — — Short-term signal instability. — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power is applied — A voltage level approximately equal to the input power voltage (V voltage power input to the equal approximately level voltage A — — A voltage level approximately equal to the ground voltage (V voltage ground to the equal approximately level voltage A — to the circuit. subroutine. subroutine. a executing by devices peripheral instruction. and operand(s) and associated its opcode an interprets CPU A mnemonics. language assembly signal. external an on the level and to an to change writes of output the level an reads signal to sense input an external location. storage data temporary a as serve also can H:X operand. of the address effective the byte is called X. In the indexed addressing modes, the CPU uses the contents of H:X to determine disabled. factor. correction appropriate the determine to bits C and H the of state the uses for binary-coded decimal arithmetic operations. The decimal adjust accumulator (DAA) instruction low-order four bits of the accumulator value to the high-order four bits. The half-carry bit is required — The time lag between instruction completion and data movement. data and completion instruction between lag time The — — — The leastsignificant eight bitsof a word. — Atemporary breakin the sequential executionof a program to respond tosignals from — The The — most significant eight bitsof a word. — Operations that a CPU can perform. Instructions are expressed by programmers as as programmers by expressed are Instructions perform. can CPU a that Operations — — Base 16 numbering system that uses the digits 0 through 9 and the letters A through F. through A letters and 9 the 0 the through digits uses that system numbering 16 Base — — Anonexistent opcode. An— address not within the memory map — A signal from a peripheral to the CPU intended to cause the CPU to execute a to execute CPU the cause to intended CPU the to peripheral a from signal A — — Input/output interfaces between a between system interfaces — and the computer external Input/output world. A CPU — A16-bit register in the CPU08. Theupper byteof H:Xis called H.Thelower — The rightmost digit of a binary number. binary of a digit rightmost The — Freescale Semiconductor,Inc.

F o

r — A module that monitors power supply voltage. supply power monitors that module A —

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Freescale Semiconductor, Inc. Glossary

M68HC08 — A Motorola family of 8-bit MCUs. mark/space — The logic 1/logic 0 convention used in formatting data in serial communication. mask — 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used in integrated circuit fabrication to transfer an image onto silicon. mask option — A optional microcontroller feature that the customer chooses to enable or disable. mask option register (MOR) — An EPROM location containing bits that enable or disable certain MCU features. MCU — Microcontroller unit. See “microcontroller.” memory location — Each M68HC08 memory location holds one byte of data and has a unique address.

. To store information in a memory location, the CPU places the address of the location on the

. address bus, the data information on the data bus, and asserts the write signal. To read c information from a memory location, the CPU places the address of the location on the address

I bus and asserts the read signal. In response to the read signal, the selected memory location

, places its data onto the data bus.

o memory map — A pictorial representation of all memory locations in a computer system.

t microcontroller — Microcontroller unit (MCU). A complete computer system, including a CPU, memory,

u a clock oscillator, and input/output (I/O) on a single integrated circuit. d modulo counter — A counter that can be programmed to count to any number from zero to its maximum

possible modulus.

monitor ROM — A section of ROM that can execute commands from a host computer for testing

purposes.

MOR — See “mask option register (MOR).”

most significant bit (MSB) — The leftmost digit of a binary number.

l multiplexer — A device that can select one of a number of inputs and pass the logic level of that input

on to the output.

N — The negative bit in the condition code register of the CPU08. The CPU sets the negative bit when

an arithmetic operation, logical operation, or data manipulation produces a negative result.

e nibble — A set of four bits (half of a byte).

F object code — The output from an assembler or compiler that is itself executable machine code, or is suitable for processing to produce executable machine code. opcode — A binary code that instructs the CPU to perform an operation. open-drain — An output that has no pullup transistor. An external pullup device can be connected to the power supply to provide the logic 1 output voltage. operand — Data on which an operation is performed. Usually a statement consists of an operator and an operand. For example, the operator may be an add instruction, and the operand may be the quantity to be added. oscillator — A circuit that produces a constant frequency square wave that is used by the computer as a timing and sequencing reference.

DRM012 — Rev 0.0 Designer Reference Manual

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polarity pointer PLL loop(PLL) phase-locked peripheral PC PWM period push page zero zero page overflow OTPROM Glossary 4Gosr MOTOROLA DRM012 — Rev 0.0 Glossary 24 Designer Reference Manual parity pulse-width modulation (PWM) (PWM) modulation pulse-width pulse-width pullup pull counter (PC) program program prescaler port polling — See “program counter (PC).” counter “program See — Aninstruction — that copies into the accumulator thecontents of a stack RAMlocation. The stack — See “phase-locked loop (PLL).” loop “phase-locked See — — A — ofset wires for communicating withoff-chip devices. — An instruction that copies the contents of the accumulator to the stack RAM. The stack RAM RAM stack The RAM. stack the to accumulator the of contents the copies that instruction An — — An error-checking scheme that counts the number of logic 1s in each byte transmitted. In a a In transmitted. byte each in 1s of logic number the counts that scheme error-checking An — — A transistor in the output of a logic gate that connects the output to the logic 1 voltage of the of the voltage 1 logic the to output the connects that gate logic a of output the in transistor A — levels, V levels, are used in the calculation of the address of an operand, and therefore points to the operand. the to points therefore and operand, an of address the of calculation the in used are signal. reference a to 1s. of logic number if incorrect with it an a signal finds byte error an generates checker The parity byte. each in 1s logic of number the counts receiver the in checker parity A parity. even for even or parity odd for odd 1s of logic the number byte to make to each bit extra an appends generator parity system, every byte should have an even number of logic 1s. In the transmitter, a parity system that uses odd parity, every byte is expected to have an odd number of logic 1s. In an even address is in the stack pointer. stack the in is address frequency. constant a reprogrammed. — Periodically reading a status bit to monitor the condition of a peripheral device. peripheral a of condition the to monitor bit status a reading Periodically — power supply. power pointer. stack the in is address RAM instructionor operand that theCPU will use. operations. etc. 1/10 1/8, 1/2, as such — Pointer register. An index register is sometimes called a pointer register because its contents its because contents a called An is pointer register index — register register. Pointer sometimes — The two opposite logic levels, logic 1 and logic 0, which correspond to two different voltage voltage different to two correspond which 0, logic and 1 logic levels, logic opposite two The — — A set of computer instructions that cause a computer to perform a desired operation or or operation desired a to perform computer a cause that instructions computer of set A — — A quantity that is too large to be contained in one byte or one word. one or byte one in contained be to large too is that quantity A — — One-time programmable read-only memory. A nonvolatile type of memory that cannot be be cannot that memory of type nonvolatile A memory. read-only programmable One-time — — A circuit that generates an output signal related to the input signal by a fractional scale factor — — A circuit not under direct control.CPU — The first 256 bytes of memory (addresses $0000–$00FF). (addresses of memory bytes 256 first The — — — Theamount of timea signal is as on toopposed being in its off state. — time The required for one complete cycle of a waveform.PWM DD and V and — A 16-bit register in the CPU08. The PC register holds the address of the next the address holds register PC The in CPU08. the register A 16-bit — SS . —A oscillator circuit in which the frequencyof oscillatorthe is synchronized Freescale Semiconductor,Inc.

F o

— Controlled variation (modulation) of the pulse width of a signal with with signal a of width pulse the of (modulation) variation Controlled — r

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Freescale Semiconductor, Inc. Glossary

RAM — Random access memory. All RAM locations can be read or written by the CPU. The contents of a RAM memory location remain valid until the CPU writes a different value or until power is turned off. RC circuit — A circuit consisting of capacitors and resistors having a defined time constant. read — To copy the contents of a memory location to the accumulator. register — A circuit that stores a group of bits. reserved memory location — A memory location that is used only in special factory test modes. Writing to a reserved location has no effect. Reading a reserved location returns an unpredictable value. reset — To force a device to a known condition.

. ROM — Read-only memory. A type of memory that can be read but cannot be changed (written). The

. contents of ROM must be specified before manufacturing the MCU.

n SCI — See “serial communication interface module (SCI).”

, serial — Pertaining to sequential transmission over a single line.

r serial communications interface module (SCI) — A module in the M68HC08 Family that supports

o t asynchronous communication.

c serial peripheral interface module (SPI) — A module in the M68HC08 Family that supports

d synchronous communication.

set — To change a bit from logic 0 to logic 1; opposite of clear.

c shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to them and

that can shift the logic levels to the right or left through adjacent circuits in the chain.

signed — A binary number notation that accommodates both positive and negative numbers. The most

significant bit is used to indicate whether the number is positive or negative, normally logic 0 for

positive and logic 1 for negative. The other seven bits indicate the magnitude of the number.

software — Instructions and data that control the operation of a microcontroller.

c software interrupt (SWI) — An instruction that causes an interrupt and its associated vector fetch.

SPI — See “serial peripheral interface module (SPI).”

e stack — A portion of RAM reserved for storage of CPU register contents and subroutine return r addresses.

F stack pointer (SP) — A 16-bit register in the CPU08 containing the address of the next available storage location on the stack. start bit — A bit that signals the beginning of an asynchronous serial transmission. status bit — A register bit that indicates the condition of a device. stop bit — A bit that signals the end of an asynchronous serial transmission.

DRM012 — Rev 0.0 Designer Reference Manual

MOTOROLA Glossary 25 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc...

variable V location memory unimplemented unbuffered two’s complement mode tracking toggle timer timer interface module (TIM) TIM Z X write word wired-OR waveform voltage-controlled oscillator (VCO) vector VCO subroutine Glossary 6Gosr MOTOROLA DRM012 — Rev 0.0 Glossary 26 Designer Reference Manual synchronous — — The zero bit in condition the code register of the sets CPU08 CPU08. The thezero bit when an — lower The byteof theindex register (H:X) in the CPU08. —The bit overflow in the condition code of register the CPU08. The sets CPU08 the V bit when a two's — See “timer interface module (TIM).” module interface “timer See — — See “voltage-controlled oscillator.” “voltage-controlled See — — — The transfer of a byte of data from the to CPU a memory location. — Aset of twobytes (16 bits). — Amodule used to relate events in a system to a point in time. — A location memory that the contains address of the of beginning a subroutine written to service — changeTo the state of an output from a logic 0 to a logic 1 or from a logic to 1 a logic 0. arithmetic operation, logical operation, or data manipulation produces a result of of $00. result a produces manipulation data or operation, logical operation, arithmetic input. control a to applied voltage dc a by is controlled that reset. or interrupt an bit. overflow complement overflow occurs. signed The branch instructions BGT,BGE, BLE, BLT and use the Executing an opcode at an unimplemented location causes an illegal address reset. value. unpredictable an returns location unimplemented an Reading effect. no has location result. the to adding1 then and number in the bit each inverting by obtained is number of a negative complement two’s The negative). indicates (1 number the of sign the indicates number complement two’s of a bit significant mode.” “acquisition see signal. to the main program where it left off. execute the instructions in the subroutine. When the RTS instruction is executed, the CPU returns BSR) instructionis used to call thesubroutine. The CPU leavesthe flow of the main program to or (JSR subroutine to branch or jump a needed, are instructions subroutine the where program in instruction a subroutine is a from return At (RTS) subroutine instruction. each place in the main — A value that changes during the course of program execution. program of course the during changes that A value — — Connection of circuit outputs so that if any output is high, the connection point is is high. point connection the high, is output any if that so outputs circuit of Connection — — A graphical representation in which the amplitude of a wave is plotted against time. against plotted is wave of a amplitude the in which representation graphical A — — A sequence of instructions to be used more than once in the course of a program. The last — Utilizes — onlyone register for data; data new overwrites current data. — Refers to logic circuits and operations that are synchronized by a common reference reference common a by synchronized are that and operations circuits logic to Refers — — Mode of low-jitter PLL operation during which the PLL is locked on a frequency. Also Also frequency. a on is locked the PLL which during operation PLL low-jitter of Mode — — A means of performing binary subtraction using addition techniques. The most most The addition techniques. using subtraction binary of performing means A — Freescale Semiconductor,Inc.

— A module used to relate events in a system to a point in time. F o

— A memory location that is not used. Writing to an unimplemented is to that an not location used. Writing unimplemented A — memory M

o — — A circuit that produces an oscillating output signal of a frequency

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