Perceptually Guided Inexact DSP Design for Power, Area Efficient Hearing

Total Page:16

File Type:pdf, Size:1020Kb

Perceptually Guided Inexact DSP Design for Power, Area Efficient Hearing Perceptually Guided Inexact DSP Design for Power, Area Efficient Hearing Aid S. P. Kadiyala, Aritra Sen, Shubham Mahajan, Qingyun Wang, Avinash Lingamneni, James Sneed German, Xu Hong, Ansuman Banerjee, Krishna Palem, Arindam Basu To cite this version: S. P. Kadiyala, Aritra Sen, Shubham Mahajan, Qingyun Wang, Avinash Lingamneni, et al.. Per- ceptually Guided Inexact DSP Design for Power, Area Efficient Hearing Aid. 2015 IEEE Biomed- ical Systems and Circuits Conference (BioCAS), Oct 2015, Atlanta, United States. 10.1109/Bio- CAS.2015.7348319. hal-01498940 HAL Id: hal-01498940 https://hal.archives-ouvertes.fr/hal-01498940 Submitted on 24 Apr 2019 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Perceptually Guided Inexact DSP Design for Power, Area Efficient Hearing Aid Sai Praveen Kadiyala∗, Aritra Sen∗, Shubham Mahajan, Qingyun Wang∗, Avinash Lingamneniy, James Sneed Germanz, Xu Hongz, Ansuman Banerjee, Krishna V. Palemy, and Arindam Basu∗ ∗School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore yDepartment of Computer Science, Rice University, Houston, USA zSchool of Humanities and Social Sciences, Nanyang Technological University, Singapore Email: [email protected] Abstract—Inexact design has been recognized as very viable its kind wherein a neurocognitive model of human hearing approach to achieve significant gains in the energy, area and is used to quantify glitches or loss in accuracy, through a speed efficiencies of digital circuits. By deliberately trading error novel metric of intelligibility of spoken sound. The model in return for such these gains, inexact circuits and architectures have been shown to be especially useful in contexts where and the intelligibility metric are used to guide the design of our senses such as sight and hearing, can compensate for an inexact processor for an assistive device–a hearing aid. the loss in accuracy. It is therefore important to understand, Using the techniques described earlier, we can get reduction characterize the manner in which our sensorial systems interact in the power area product (PAP) of the filter bank by 1:8X and compensate for the loss in accuracy. Further use this for an intelligibility loss of only 10% over conventional exact knowledge to optimize and guide the manner in which inexactness is introduced. For the first time, we achieve both of these goals in designs. this paper in the context of human audition-specifically, using the architecture of a hearing-aid and the DSP primitive of an FIR II. PERCEPTUALLY GUIDED PRUNING FOR EFFICIENT filter as our candidate. Our algorithms for designing an inexact INEXACT CIRCUITS hearing-aid thus use intelligibility as the metric. The resulting Probabilistic Pruning [1], [2] is an inexact design technique inexact FIR filter in the hearing aid is 1:5X or 1:8X more efficient in terms of power-area product while producing 5% that exploits the knowledge of the significance of a circuit or 10% less intelligible speech respectively when compared with component to derive a systematic approach to prune the “least the corresponding exact version. 1 useful” components in a circuit. In this paper, we will use this technique as the basis for introducing “inexactness” and en- I. INTRODUCTION AND MOTIVATION abling the energy-accuracy tradeoffs. The novel contributions Recently, there is a huge interest in developing low power of this paper in the area of pruning is the introduction of an wearable sensors for medical applications and power aware efficient optimization strategy for pruning that is scalable to digital designs are playing a crucial role in this process. large digital systems. Most of the available digital processors however do not take A. Optimization Framework the advantage of information processing done by the natural auditory and visual path ways, hence leaving a scope to Earlier work on pruning [2] has considered the removal dig in this direction. The ability of human compensatory of gates in arithmetic circuits like adders and multipliers by neurocognitive processing to tolerate relatively less accurate using explicit cost functions. However, such approaches are inputs may provide an excellent opportunity to lower the intractable for large systems because of the non-availability of power and area requirement of processors in assistive devices such explicit cost functions and the severe overheads involved by deliberately introducing errors in computation. This novel in determining those cost functions computationally at the approach termed as inexact design has proved to yield signifi- granularity of individual gates. Hence, we propose to have cant gains in the context of hardware for DSP primitives [1], a library E of NE elemental circuits, Ei, each of which can atmospheric modelling [3], MPEG coding [4] and recognition admit only one of several pre-characterized pruned topologies. and classification tasks [5]. These topologies can be indexed by an integer l that denotes However, past work on inexact circuits has quantified the the level or degree of pruning; larger values of l indicate glitches or errors introduced by arithmetic magnitude–as op- more savings at the cost of increased error magnitude [2]. posed to using metrics that capture their impact on our senses Let Li denote an integer that indicates the maximum level of 2 in a natural way. Naturally, incorporating this effect adds to the pruning of Ei E while l = 1 corresponds to the unpruned complexity of design significantly since the human designer structure. Now, we can define a set C of all components cj f g 2 has to bridge the gap between the arithmetic error on the one allowed in our design by denoting cj = l; Ei where Ei E ≤ 2 hand, and its impact on our senses on the other. To remedy and l( Li) N. The circuit we want to optimize can this situation, in this paper, we present the first result of be represented as a directed acyclic graph G whose nodes are NG components selected from C, inputs, or outputs and 1Financial support from MOE, Singapore through grant ARC8/13 is ac- whose edges are wires. We can now formulate an optimization knowledged. problem where the performance of G can be modified by LD Speech Mic Amp ADC WDRC WDRC ∑ WDRC Input speech Hearing loss Hearing Aid model Error estimate Candidate Intelligibility Topology estimate Power/ Area Original Quality Intelligibility estimate Speech Regres sion H Pruner A Psychophysi Stage 1 cal Experiment Fig. 1: Framework for evaluation of cost in the context of a hearing-aid and using that to introduce inexactness in the design. The optimization loop uses a library of pre-characterized inexact VLSI components to quickly achieve a near optimal solution which is then evaluated rigorously through detailed synthesis procedures. ~ • varying L = [l1l2:::lNG ] in exchange of cost savings. To make To give preference to those components which can reduce this dependence explicit, we shall henceforth refer to the graph M without compromising P er too much, we modify the as G(L~ ). cost function to be: The quality of outputs fOg of G(L~ ) for the same set of M inputs fIg depends on the value of L~ with the best quality of C = + λu(P er − P er ); P er =6 0 (3) P er TH outputs being obtained for L~ = [11::1] = L~u corresponding to the unpruned circuit. We formally define the performance where λ is a large positive number to prevent choices ~ as a function of L by: which reduce the performance below threshold and u is Xν the heaviside function. ~ ~ 2 <+ P er = pkQp(Ok(L);Ok(Lu)); P er (1) • To prevent large jumps in error, we only allow changes in k=1 pruning levels of the q(< s) components which have the q where Ok(L~ ) represents the output of G(L~ ) for input Ik largest gradient values by using a ‘rank’ function, rankq that occurs with a probability pk for 1 ≤ k ≤ ν. Qp that assigns values 1; 1=2; ::1=q to the selected ones while denotes a function that measures the perceptual quality of the assigning a value of 0 to others. Hence, the final update output of the pruned circuit with respect to the output of the equation is given by: unpruned one based on models of human sensory processing ~ ~ with larger values denoting better quality. The problem can L(n + 1) = L(n) + rankq(Is(n)rC) (4) now be defined as finding the optimal value of L~ , L~ opt such that: where Is is the identity matrix with all rows set to zero other than ‘s’ randomly chosen ones. L~ opt = arg min M subject to P er ≥ P erTH (2) L~ where M is some cost metric of the circuit (like area or power) III. SIMULATION FRAMEWORK:HEARING AID that needs to be minimized and P erTH denotes a threshold ARCHITECTURE,HEARING LOSS MODEL,COGNITIVE for minimum acceptable perceptual quality. MODEL AND GAIN/ERROR ESTIMATOR B. Greedy Optimization Algorithm To demonstrate the operation of this algorithm, we choose a The optimization problem posed in (2) can be solved by a digital hearing aid, which interacts with our auditory sense, as modified greedy version of a gradient descent approach with the platform. Figure 1 depicts our entire simulation framework the following features: implemented in MATLAB that includes the hearing aid archi- • We evaluate only s(< NG) randomly selected compo- tecture, hearing loss model, cognitive model and gain/error nents of the gradient and this random candidate set is estimator.
Recommended publications
  • Sustaining Moore's Law Through Inexactness
    Sustaining Moore’s Law Through Inexactness A Mathematical Foundation John Augustine,1∗ Krishna Palem,2 Parishkrati1 1Department of Computer Science and Engineering, Indian Institute of Technology Madras, Chennai, India. 2Department of Computer Science, Rice University, Houston, USA. ∗Corresponding author; E-mail: augustine@iitm:ac:in. Abstract Inexact computing aims to compute good solutions that require considerably less resource – typically energy – compared to computing exact solutions. While inexactness is motivated by concerns derived from technology scaling and Moore’s law, there is no formal or foundational framework for reasoning about this novel approach to designing algorithms. In this work, we present a fundamental relationship between the quality of computing the value of a boolean function and the energy needed to compute it in a mathematically rigorous and general setting. On this basis, one can study the tradeoff between the quality of the solution to a problem and the amount of energy that is consumed. We accomplish this by introducing a computational model to classify problems based on notions of symmetry inspired by physics. We show that some problems are symmetric in that every input bit is, in a sense, equally important, while other problems display a great deal of asymmetry in the importance of input bits. We believe that our model is novel and provides a foundation for inexact Computing. Building on this, we show that asymmetric problems allow us to invest resources favoring the important bits – a feature that can be leveraged to design efficient inexact algorithms. On the negative side and in contrast, we can prove that the best inexact algorithms for symmetric problems are no better than simply reducing the resource investment uniformly across all bits.
    [Show full text]
  • An Efficient Memory Operations Optimization Technique for Vector Loops on Itanium 2 Processors
    An Efficient Memory Operations Optimization Technique for Vector Loops on Itanium 2 Processors William JALBY, Christophe LEMUET, Sid-Ahmed-Ali TOUATI April 10, 2009 Abstract To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. In this paper, we study the impact of these cache systems on memory instructions scheduling. We demonstrate that, if no care is taken at compile time, the non-precise memory disambiguation mechanism and the banking structure cause severe performance loss, even for very simple regular codes. We also show that grouping the memory operations in a pseudo-vectorized way enables the compiler to generate more effective code for the Itanium 2 processor. The impact of this code optimization technique on register pressure is analyzed for various vectorization schemes. keywords Performance Measurement, Cache Optimization, Memory Access Optimization, Bank Conflicts, Memory Address Disambiguation, Instruction Level Parallelism. 1 Introduction To satisfy the ever increasing data request rate of modern microprocessors, large multilevel memory hierarchies are no longer the unique efficient solution [8]: computer architects have to rely on more and more sophisticated mech- anisms [10, 6], in particular, load/store queues (to decouple memory access and arithmetic operations), banking and interleaving (to increase bandwidth), prefetch mechanisms (to offset latency). One key mechanism to tolerate/hide memory latency is the out-of-order processing of memory requests. With the advent of superscalar processors, the concept of load/store queues has become a standard. The basic principle is simple: consecutively issued memory requests are stored in a queue and simultaneously processed.
    [Show full text]
  • School of Electrical and Computer Engineering 2000-2001 Annual Report
    School of Electrical and Computer Engineering 2000-2001 Annual Report School of Electrical and Computer Engineering TABLE OF CONTENTS HIGHLIGHTS OF THE YEAR . .1 ACADEMIC OPERATIONS Undergraduate Instructional Operations . .25 PERSONNEL Graduate Instructional Operations . .25 Faculty Profile . .7 International Study Opportunities . .25 Academic Faculty . .7 GTREP Faculty . .13 EXTERNAL AFFAIRS Professors Emeriti . .13 College of Engineering Hall of Fame . .27 Joint Faculty Appointments . .14 Council of Outstanding Young Engineering Alumni . .27 Adjunct and Part-time Appointments . .14 Academy of Distinguished Engineering Alumni . .27 Faculty Service on Institute Governing Bodies and Committees . .14 Georgia Tech Foundation Grants and Gifts . .28 Technical Interest Groups . .15 ECE Alumni/Professional Advisory Board . .29 Standing Committees . .16 Continuing Education Conferences and Courses . .17 RESEARCH ACTIVITY . .30 Research and Administrative Personnel . .18 FINANCIAL SUMMARY STUDENTS Financial Summary . .30 Student Body Profile . .20 Expenditure Summary . .30 Degrees Awarded . .20 i Student Honors and Awards . .20 CONTACT INFORMATION . .inside back cover Ph.D. Students Graduated . .21 IEEE Student Branch Officers . .24 Eta Kappa Nu Officers . .24 ECE Student Advisory Council . .24 SCHOOL OF ELECTRICAL AND COMPUTER ENGINEERING MISSION STATEMENT UNITY OF PURPOSE Our purpose is to provide students at all degree levels with the highest quality preparation for successful professional careers, and through dedicated scholarship, to advance
    [Show full text]
  • Flexible Error Handling for Embedded Real-Time Systems – Operating System and Run-Time Aspects –
    Flexible Error Handling for Embedded Real-Time Systems – Operating System and Run-Time Aspects – Dissertation zur Erlangung des Grades eines Doktors der Ingenieurwissenschaften der Technischen Universität Dortmund an der Fakultät für Informatik von Andreas Heinig Dortmund 2015 Tag der mündlichen Prüfung: 30. April 2015 Dekan / Dekanin: Prof. Dr. Gernot A. Fink Gutachter / Gutachterinnen: Prof. Dr. Peter Marwedel Prof. Dr. Hermann Härtig (TU Dresden) Acknowledgments I would like to thank my advisor Prof. Peter Marwedel for the initial ideas that lead to this dissertation. Without his advises, writing this thesis in this form would not be feasible. Very special thanks go to Dr. Michael Engel for all the discussions, the advices he gave over the years, and his intensive proof-reading support of this thesis and my publications. I would also like to thank my collaborating colleagues at the Department of Computer Science 12 with special thanks to Florian Schmoll. He provided the compiler support which is required by the flexible error handling approach presented in this thesis. Furthermore, he was available for high valuable technical discussions. Thanks go also to Björn Bönninghoff for providing the timing model for the H.264 decoder and to Ingo Korb for providing various bug fixes for the H.264 library. For proof-reading, I would like to thank Helana Kotthaus, Olaf Neugebauer, Florian Schmoll, and Björn Bönninghoff. My research visit at NTU Singapore was enabled by Prof. Dr. Vincent Mooney and Prof. Dr. Krishna Palem. I like to thank both for the advices that leaded to a publication which received a best paper award.
    [Show full text]
  • Lecture Notes in Computer Science 1742 Edited by G
    Lecture Notes in Computer Science 1742 Edited by G. Goos, J. Hartmanis and J. van Leeuwen 3 Berlin Heidelberg New York Barcelona Hong Kong London Milan Paris Singapore Tokyo P.S. Thiagarajan R. Yap (Eds.) Advances in Computing Science – ASIAN’99 5th Asian Computing Science Conference Phuket, Thailand, December 10-12,1999 Proceedings 13 Series Editors Gerhard Goos, Karlsruhe University, Germany Juris Hartmanis, Cornell University, NY, USA Jan van Leeuwen, Utrecht University, The Netherlands Volume Editors P.S. Thiagarajan Chennai Mathematical Institute 92 G.N. Chetty Road, T. Nagar, Chennai 600 017, India E-mail: [email protected] Roland Yap National University of Singapore, School of Computing Lower Kent Ridge Road, Singapore 119260 E-mail: [email protected] Cataloging-in-Publication data applied for Die Deutsche Bibliothek - CIP-Einheitsaufnahme Advances in computing science - ASIAN ’99 : proceedings / 5th Asian Computing Science Conference, Phuket, Thailand, December 10 - 12, 1999. P. S. Thiagarajan ; R. Yap (ed.) - Berlin ; Heidelberg ; New York ; Barcelona ; Hong Kong ; London ; Milan ; Paris ; Singapore ; Tokyo : Springer, 1999 (Lecture notes in computer science ; Vol. 1742) ISBN 3-540-66856-X CR Subject Classification (1998): F.3, F.4, I.2.3, C.2, C.3, D.3 ISSN 0302-9743 ISBN 3-540-66856-X Springer-Verlag Berlin Heidelberg New York This work is subject to copyright. All rights are reserved, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, re-use of illustrations, recitation, broadcasting, reproduction on microfilms or in any other way, and storage in data banks. Duplication of this publication or parts thereof is permitted only under the provisions of the German Copyright Law of September 9, 1965, in its current version, and permission for use must always be obtained from Springer-Verlag.
    [Show full text]
  • Hardware and Software for Approximate Computing
    HARDWAREANDSOFTWARE FORAPPROXIMATECOMPUTING adrian sampson A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy University of Washington 2015 Reading Committee: Luis Ceze, Chair Dan Grossman, Chair Mark Oskin Program Authorized to Offer Degree: Computer Science & Engineering © 2015 Adrian Sampson abstract HARDWAREANDSOFTWARE FORAPPROXIMATECOMPUTING Adrian Sampson Chairs of the Supervisory Committee: Associate Professor Luis Ceze Associate Professor Dan Grossman Computer Science & Engineering Approximate computing is the idea that we are hindering computer systems’ ef- ficiency by demanding too much accuracy from them. While precision is crucial for some tasks, many modern applications are fundamentally approximate. Per- fect answers are unnecessary or even impossible in domains such as computer vi- sion, machine learning, speech recognition, search, graphics, and physical simu- lation. Today’s systems waste time, energy, and complexity to provide uniformly pristine operation for applications that do not require it. Resilient applications are not, however, a license for computers to abandon predictability in favor of arbitrary errors. We need abstractions that incorporate approximate operation in a disciplined way. Application programmers should be able to exploit these richer abstractions to treat accuracy as a resource and trade it off for more traditional resources such as time, space, or energy. This dissertation explores new abstractions for approximate computing across hardware
    [Show full text]
  • Overcoming the Power Wall by Exploiting Application Inexactness and Emerging COTS Architectural Features: Trading Precision for Improving Application Quality 1
    ARGONNE NATIONAL LABORATORY 9700 South Cass Avenue Lemont, Illinois 60439 Overcoming the Power Wall by Exploiting Application Inexactness and Emerging COTS Architectural Features: Trading Precision for Improving Application Quality 1 Mike Fagan, Jeremy Schlachter, Kazutomo Yoshii, Sven Leyffer, Krishna Palem, Marc Snir, Stefan M. Wild, and Christian Enz Mathematics and Computer Science Division Preprint ANL/MCS-P6040-0816 August 2016 Updates to this preprint may be found at http://www.mcs.anl.gov/publications 1This material was based upon work supported by the U.S. Department of Energy, Office of Science, Offices of Basic Energy Sciences and Advanced Scientific Computing Research under Contract No. DE-AC02-06CH11357. Overcoming the Power Wall by Exploiting Inexactness and Emerging COTS Architectural Features Trading Precision for Improving Application Quality Mike Fagan†, Jeremy Schlachter‡, Kazutomo Yoshii∗, Sven Leyffer∗, Krishna Palem†, Marc Snir∗, Stefan M. Wild∗, and Christian Enz‡ ∗Mathematics and Computer Science Division Argonne National Laboratory, Lemont, IL 60439, USA †Department of Computer Science Rice University, Houston, TX, USA ‡Integrated Circuits Laboratory (ICLAB) Ecole Polytechnique Fed´ erale´ de Lausanne (EPFL), Neuchatel,ˆ Switzerland Abstract—Energy and power consumption are major limita- engaged in a project aimed at leading to the deployment of tions to continued scaling of computing systems. Inexactness an exascale computer by 2023. Power consumption is a major where the quality of the solution can be traded for energy savings obstacle to the timely deployment of an exascale platform. has been proposed as a counterintuitive approach to overcoming those limitation. However, in the past, inexactness has been neces- The current top supercomputer, Sunway, consumes 15.3MW sitated the need for highly customized or specialized hardware.
    [Show full text]
  • GRADUATE STUDY in COMPUTER SCIENCE Rice University Graduate
    Graduate Study at MESSAGE FROM THE DEPARTMENT CHAIR GRADUATE STUDY IN Computers and computing are an integral part of our lives today. Computing is revolutionizing the process of research, development, and discovery in all fields of COMPUTER SCIENCE engineering and science. The societal impact of computing continues to increase Rice University as computers become more broadly accessible. Meanwhile, the foundations of computing also continue to change at a dizzying pace. New technologies, such as manycore processors, mobile computing, and cloud computing are reshaping the landscape of computing, and new challenges are emerging as computer science WWW.COMPSCI.RICE.EDU becomes increasingly multidisciplinary. Leading-edge skills in Computer Science are in demand by employers across a wide range of industries. A strong Computer Science department is essential to Rice’s mission to be a world-class research university that prepares students to contribute to the advancement of society. Rice has a long history of leadership in computing, starting with development of the R1 computer in the late 1950s. The Department of Computer Science is continuing this legacy by advancing the frontiers of computing. We have a three- fold mission: to create knowledge, to disseminate knowledge, and to provide ser- vice to our communities—the local Rice community and the broader community beyond the campus. We serve as a center of expertise in computing technologies for our university, our research collaborators, and our industry partners. On the research front, our faculty, staff, and students are exploring innovative ideas in areas that range from parallel computing through text and data analytics, from ways to program computers through ways to build them, and from funda- mental principles of logic and discrete mathematics through the application of those principles to gaming, voting, and driving robots.
    [Show full text]
  • An Optimum Inexact Design for an Energy Efficient Hearing
    An Optimum Inexact Design for an Energy Efficient Hearing Aid Sai Praveen Kadiyala, Aritra Sen, Shubham Mahajan, Quingyun Wang, Avinash Lingamaneni, James Sneed German, Hong Xu, Krishna Palem, Arindam Basu To cite this version: Sai Praveen Kadiyala, Aritra Sen, Shubham Mahajan, Quingyun Wang, Avinash Lingamaneni, et al.. An Optimum Inexact Design for an Energy Efficient Hearing Aid. Journal of Low Power Electronics, American Scientific Publishers, 2019, 15 (2), pp.129-143. 10.1166/jolpe.2019.1610. hal-02546135 HAL Id: hal-02546135 https://hal.archives-ouvertes.fr/hal-02546135 Submitted on 17 Apr 2020 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Copyright © 2019 American Scientific Publishers Journal of All rights reserved Low Power Electronics Printed in the United States of America Vol. 15, 129–143, 2019 An Optimum Inexact Design for an Energy Efficient Hearing Aid Sai Praveen Kadiyala1 ∗,AritraSen2, Shubham Mahajan2, Quingyun Wang2, Avinash Lingamaneni3, James Sneed German4, Hong Xu5, Krishna V. Palem6, and Arindam Basu2 1School of Computer Science
    [Show full text]
  • Exploiting Errors for Efficiency: a Survey from Circuits to Algorithms
    Exploiting Errors for Efficiency: A Survey from Circuits to Applications The MIT Faculty has made this article openly available. Please share how this access benefits you. Your story matters. Citation Stanley-Marbell, Phillip et al. "Exploiting Errors for Efficiency: A Survey from Circuits to Applications." ACM Computing Surveys 53, 3 (July 2020): dx.doi.org/10.1145/3394898 © 2020 ACM As Published http://dx.doi.org/10.1145/3394898 Publisher Association for Computing Machinery (ACM) Version Original manuscript Citable link https://hdl.handle.net/1721.1/129955 Terms of Use Creative Commons Attribution-Noncommercial-Share Alike Detailed Terms http://creativecommons.org/licenses/by-nc-sa/4.0/ Exploiting Errors for Efficiency: A Survey from Circuits to Algorithms PHILLIP STANLEY-MARBELL, University of Cambridge ARMIN ALAGHI, University of Washington MICHAEL CARBIN, Massachusetts Institute of Technology EVA DARULOVA, Max Planck Institute for Software Systems LARA DOLECEK, University of California at Los Angeles ANDREAS GERSTLAUER, The University of Texas at Austin GHAYOOR GILLANI, University of Twente DJORDJE JEVDJIC, National University of Singapore THIERRY MOREAU, University of Washington MATTIA CACCIOTTI, École Polytechnique Fédérale de Lausanne ALEXANDROS DAGLIS, École Polytechnique Fédérale de Lausanne NATALIE ENRIGHT JERGER, University of Toronto BABAK FALSAFI, École Polytechnique Fédérale de Lausanne SASA MISAILOVIC, University of Illinois at Urbana-Champaign ADRIAN SAMPSON, Cornell University DAMIEN ZUFFEREY, Max Planck Institute for
    [Show full text]
  • Error-Efficient Computing Systems
    Full text available at: http://dx.doi.org/10.1561/1000000049 Error-Efficient Computing Systems Phillip Stanley-Marbell University of Cambridge [email protected] Martin Rinard Massachusetts Institute of Technology [email protected] Boston — Delft Full text available at: http://dx.doi.org/10.1561/1000000049 Foundations and Trends® in Electronic Design Automation Published, sold and distributed by: now Publishers Inc. PO Box 1024 Hanover, MA 02339 United States Tel. +1-781-985-4510 www.nowpublishers.com [email protected] Outside North America: now Publishers Inc. PO Box 179 2600 AD Delft The Netherlands Tel. +31-6-51115274 The preferred citation for this publication is P. Stanley-Marbell and M. Rinard. Error-Efficient Computing Systems. Foundations and Trends® in Electronic Design Automation, vol. 11, no. 4, pp. 362–461, 2017. ® This Foundations and Trends issue was typeset in LATEX using a class file designed by Neal Parikh. Printed on acid-free paper. ISBN: 978-1-68083-358-4 © 2017 P. Stanley-Marbell and M. Rinard All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or trans- mitted in any form or by any means, mechanical, photocopying, recording or otherwise, without prior written permission of the publishers. Photocopying. In the USA: This journal is registered at the Copyright Clearance Center, Inc., 222 Rose- wood Drive, Danvers, MA 01923. Authorization to photocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by now Publishers Inc for users registered with the Copyright Clearance Center (CCC).
    [Show full text]
  • Microarchitecture-Aware Physical Planning for Deep Submicron Technology Mongkol Ekpanyapong
    Microarchitecture-Aware Physical Planning for Deep Submicron Technology A Thesis Presented to The Academic Faculty by Mongkol Ekpanyapong In Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy School of Electrical and Computer Engineering Georgia Institute of Technology May 2006 Microarchitecture-Aware Physical Planning for Deep Submicron Technology Approved by: Asst. Professor Sung Kyu Lim, Advisor Professor Abhijit Chatterjee School of Electrical and School of Electrical and Computer Engineering Computer Engineering Georgia Institute of Technology, Adviser Georgia Institute of Technology Professor Sudhakar Yalamanchili Asst. Professor Gabriel H. Loh School of Electrical and College of Computing Computer Engineering Georgia Institute of Technology Georgia Institute of Technology Asst. Professor Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Institute of Technology Date Approved Novermber 14, 2005 Dedicated to my mother, Anongrath Saesua and my father, Veerachai Ekpanyapong iii ACKNOWLEDGEMENTS I would like to express my sincere gratitude to Professor Sung Kyu Lim for his guidance of my research and his patience during my Ph.D. study at Georgia Tech. I would like to thank my thesis committee members, Professor Sudhakar Yalamanchili, Professor Hsien-Hsin Sean Lee, Professor Abhijit Chatterjee, Prof. Gabriel H. Loh for their valuable suggestions, especially Professor Yalamanchili and Professor Lee who served me as my reading committee members. I also would like to thank my thesis proposal committee member, Professor Alan Doolittle for his valuable suggestion. I would like to thank all the members of GTCAD and CREST groups for their support and friendship, especially, Jacob Minz, Michael B. Healy, Thaisiri Watewai, Ismail F. Baskaya, J.C.
    [Show full text]