JEDEC SSD Specifications Explained
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Product Guide SAMSUNG ELECTRONICS RESERVES the RIGHT to CHANGE PRODUCTS, INFORMATION and SPECIFICATIONS WITHOUT NOTICE
May. 2018 DDR4 SDRAM Memory Product Guide SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. © 2018 Samsung Electronics Co., Ltd. All rights reserved. - 1 - May. 2018 Product Guide DDR4 SDRAM Memory 1. DDR4 SDRAM MEMORY ORDERING INFORMATION 1 2 3 4 5 6 7 8 9 10 11 K 4 A X X X X X X X - X X X X SAMSUNG Memory Speed DRAM Temp & Power DRAM Type Package Type Density Revision Bit Organization Interface (VDD, VDDQ) # of Internal Banks 1. SAMSUNG Memory : K 8. Revision M: 1st Gen. A: 2nd Gen. 2. DRAM : 4 B: 3rd Gen. C: 4th Gen. D: 5th Gen. -
Sandisk Sdinbdg4-8G
Data Sheet - Confidential DOC-56-34-01460• Rev 1.4 • August 2017 Industrial iNAND® 7250 e.MMC 5.1 with HS400 Interface Confidential, subject to all applicable non-disclosure agreements www.SanDisk.com SanDisk® iNAND 7250 e.MMC 5.1+ HS400 I/F data sheet Confidential REVISION HISTORY Doc. No Revision Date Description DOC-56-34-01460 0.1 October-2016 Preliminary version DOC-56-34-01460 0.2 January-2017 Updated tables 2, 5 and 6 DOC-56-34-01460 1.0 March-2017 Released version DOC-56-34-01460 1.1 May-2017 Updated SKU names DOC-56-34-01460 1.2 June-2017 Updated performance targets, SKU ID in ext_CSD DOC-56-34-01460 1.3 July-2017 Updated ext_CSD MAX_ENH_SIZE_MULT DOC-56-34-01460 1.4 August-2017 Updated drawing marking SanDisk® general policy does not recommend the use of its products in life support applications where in a failure or malfunction of the product may directly threaten life or injury. Per SanDisk Terms and Conditions of Sale, the user of SanDisk products in life support applications assumes all risk of such use and indemnifies SanDisk against all damages. See “Disclaimer of Liability.” This document is for information use only and is subject to change without prior notice. SanDisk assumes no responsibility for any errors that may appear in this document, nor for incidental or consequential damages resulting from the furnishing, performance or use of this material. No part of this document may be reproduced, transmitted, transcribed, stored in a retrievable manner or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without the prior written consent of an officer of SanDisk . -
MULTI-STREAM SSD TECHNOLOGY 2X READ PERFORMANCE & WRITE ENDURANCE T10 SCSI STANDARD
MULTI-STREAM SSD TECHNOLOGY 2x READ PERFORMANCE & WRITE ENDURANCE T10 SCSI STANDARD NAND flash solid-state drives (SSDs) are increasingly deployed within enterprise datacenters thanks to their high performance and low power consumption. Decreasing NAND flash cost-per-gigabyte is also accelerating SSD adoption to replace hard disk drives (HDDs) in storage applications. One SSD drawback is that, as a device continually writes data, valid data can be fragmented across the NAND flash medium (See Figure 1). To reclaim free space, garbage collection activity copies user data to new storage blocks and erases invalid data storage blocks, thereby allowing the media to store new write data. However, garbage collection processing decreases both SSD read and write performance. In addition, garbage collection increases write amplification because individual host data write requests can result in multiple internal SSD writes to the NAND medium. Here, valid data is first read from a media block about to be erased, then rewritten to another media storage block, accompanied by the write to store new host data. Consequently, write amplification decreases SSD lifetime because each NAND chip can endure a certain number of writes before it begins to fail. MULTI-STREAM SSD TECHNOLOGY With multi-stream technology, an innovative new technology System Configuration FIO Configuration standardized in T10, implemented in Samsung PM953S NVMe SSD, garbage collection can be eliminated or reduced by storing • Hardware system • I/O workload: associated or similar lifetime data in the same erase block. This Quad Core Intel i7-4790 70% Read/ 30% Write helps avoid NAND erase block fragmentation for data with the CPU 3.60GHz • 4 sequential write jobs same lifetime. -
CY3672-USB Clock Programming Kit
CY3672-USB Clock Programming Kit Features Functional Description ■ Supports these field-programmable clock generators: The CY3672-USB programming kit enables any user with a PC CY2077FS, CY2077FZ, CY22050KF, CY22150KF, CY22381F, to quickly and easily program Field-programmable Clock CY22392F, CY22393F, CY22394F, CY22395F, CY23FP12, Generators. The only setup requirements are a power CY25100ZXCF/IF, CY25100SXCF/IF, CY25200KF, connection and a USB port connection with the PC, as shown in CY25701FLX Figure 2. ■ Allows quick and easy prototyping Using CyClockWizard software, users can configure their parts to a given specification and generate the corresponding JEDEC ® ® ■ Easy to use Microsoft Windows 95, 98, NT, 2K, ME, file. XP-compatible interface The JEDEC file is then loaded into CY3672-USB software that ■ User-friendly CyClockWizard™ software for JEDEC file devel- communicates with the programmer. The CY3672-USB software opment has the ability to read and view the EPROM table from a programmed device. The programming flow is outlined in CY3672-USB Kit Contents Figure 1. ■ CY3672 programmer base unit Setup ■ CD ROM with CY3672 software and USB driver Hardware ■ USB cable The CY3672-USB programming kit has a simple setup ■ AC/DC power adapter procedure. A socket adapter must be inserted into the CY3672 base unit. Available socket adapters are listed in Table 1, and are ■ User’s manual ordered separately. No socket adapters are included in the CY3672-USB Clock Programming Kit. As shown in Figure 2, only two connections are required. The programmer connects to a PC through a USB cable, and receives power through the AC/DC adapter that connects to a standard 110 V/220 V wall outlet. -
Things You Should Know About Solid State Storage
ThingsPRESENTATION You Should TITLE Know GOES HERE About Solid State Storage Snippets from SNIA Tutorials and other Giblets Marty Czekalski - President SCSI Trade Association, Sr. Staff Program Manager - Seagate Technology SNIA Legal Notice The material contained in this tutorial is copyrighted by the SNIA unless otherwise noted. Member companies and individual members may use this material in presentations and literature under the following conditions: Any slide or slides used must be reproduced in their entirety without modification The SNIA must be acknowledged as the source of any material used in the body of any document containing material from these presentations. This presentation is a project of the SNIA Education Committee. Neither the author nor the presenter is an attorney and nothing in this presentation is intended to be, or should be construed as legal advice or an opinion of counsel. If you need legal advice or a legal opinion please contact your attorney. The information presented herein represents the author's personal opinion and current understanding of the relevant issues involved. The author, the presenter, and the SNIA do not assume any responsibility or liability for damages arising out of any reliance on or use of this information. NO WARRANTIES, EXPRESS OR IMPLIED. USE AT YOUR OWN RISK. What You Should Know About Solid State Storage © 2013 Storage Networking Industry Association. All Rights Reserved. 2 Abstract What You Should Know About Solid State Storage This session will appeal to Data Center Managers, Development Managers, and those that are seeking an overview of Solid State Storage. It’s comprised of excerpts from SNIA Solid State Tutorials and other sources. -
Optimizing NAND Flash-Based Ssds Via Retention Relaxation
Optimizing NAND Flash-Based SSDs via Retention Relaxation Ren-Shuo Liu∗, Chia-Lin Yang∗, and Wei Wu† ∗National Taiwan University and †Intel Corporation [email protected], [email protected], [email protected] Abstract durance have to retain data for 1 year. As NAND Flash technology continues to scale down and more bits are As NAND Flash technology continues to scale down and stored in a cell, the raw reliability of NAND Flash de- more bits are stored in a cell, the raw reliability of NAND creases substantially. To meet the retention specifica- Flash memories degrades inevitably. To meet the reten- tion for a reliable storage system, we see a trend of tion capability required for a reliable storage system, we longer write latency and more complex ECCs required in see a trend of longer write latency and more complex SSDs. For example, comparing recent 2-bit MLC NAND ECCs employed in an SSD storage system. These greatly Flash memories with previous SLC ones, page write la- impact the performance of future SSDs. In this paper, we tency increased from 200 ms [34] to 1800 ms [39], and present the first work to improve SSD performance via the required strength of ECCs went from single-error- retention relaxation. NAND Flash is typically required correcting Hamming codes [34] to 24-error-correcting to retain data for 1 to 10 years according to industrial Bose-Chaudhuri-Hocquenghem (BCH) codes [8,18,28]. standards. However, we observe that many data are over- In the near future, more complex ECC codes such as low- written in hours or days in several popular workloads in density parity-check (LDPC) [15] codes will be required datacenters. -
How Controllers Maximize SSD Life
SSSI TECH NOTES How Controllers Maximize SSD Life January 2013 by SNIA SSSI Member: Jim Handy Objective Analysis “The SSD Guy” www.snia.org1 About the Solid State Storage Initiative The SNIA Solid State Storage Initiative (SSSI) fosters the growth and success of the market for solid state storage in both enterprise and client environ- ments. Members of the SSSI work together to promote the development of technical standards and tools, educate the IT communities about solid state storage, perform market outreach that highlights the virtues of solid state storage, and collaborate with other industry associations on solid state stor- age technical work. SSSI member companies come from a wide variety of segments in the SSD industry www.snia.org/forums/sssi/about/members. How Controllers Maximize SSD Life by SNIA SSSI Member: Jim Handy “The SSD Guy”, Objective Analysis Table of Contents Introduction 2 How Controllers Maximize SSD Life 2 Better Wear Leveling 3 External Data Buffering 6 Improved ECC 7 Other Error Management 9 Reduced Write Amplification 10 Over Provisioning 11 Feedback on Block Wear 13 Internal NAND Management 14 1 Introduction This booklet contains a collection of posts from Jim Handy’s SSD Guy blog www.TheSSDGuy.com which explores the various techniques designers use to increase SSD life. How Controllers Maximize SSD Life How do controllers maximize the life of an SSD? After all, MLC flash has a lifetime of only 10,000 erase/write cycles or fewer and that is a very small number compared to the write traffic an SSD is expected to see in a high- workload environment, especially in the enterprise. -
Write Amplification Analysis in Flash-Based Solid State Drives
Write Amplification Analysis in Flash-Based Solid State Drives Xiao-Yu Hu, Evangelos Eleftheriou, Robert Haas, Ilias Iliadis, Roman Pletka IBM Research IBM Zurich Research Laboratory CH-8803 Rüschlikon, Switzerland {xhu,ele,rha,ili,rap}@zurich.ibm.com ABSTRACT age computer architecture, ranging from notebooks to en- Write amplification is a critical factor limiting the random terprise storage systems. These devices provide random I/O write performance and write endurance in storage devices performance and access latency that are orders of magnitude based on NAND-flash memories such as solid-state drives better than that of rotating hard-disk drives (HDD). More- (SSD). The impact of garbage collection on write amplifica- over, SSDs significantly reduce power consumption and dra- tion is influenced by the level of over-provisioning and the matically improve robustness and shock resistance thanks to choice of reclaiming policy. In this paper, we present a novel the absence of moving parts. probabilistic model of write amplification for log-structured NAND-flash memories have unique characteristics that flash-based SSDs. Specifically, we quantify the impact of pose challenges to the SSD system design, especially the over-provisioning on write amplification analytically and by aspects of random write performance and write endurance. simulation assuming workloads of uniformly-distributed ran- They are organized in terms of blocks, each block consist- dom short writes. Moreover, we propose modified versions ing of a fixed number of pages, typically 64 pages of 4 KiB of the greedy garbage-collection reclaiming policy and com- each. A block is the elementary unit for erase operations, pare their performance. -
Why Data Retention Is Becoming More Critical in Automotive
White Paper Why Data Retention is Becoming More Critical in Automotive Applications Understanding and Improving Managed NAND Flash Memory for Higher Data Retention and Extended Product Life Christine Lee – Kevin Hsu – Scott Harlin KIOXIA America, Inc. Assisted and self-driving vehicles are fully loaded with electronics that support the infrastructure within. They have become mobile data centers that require an immense amount of computing power to capture, process and analyze data ‘near-instantaneously’ from a myriad of sensors, recorders, algorithms and external connections. A massive amount of this data is either stored locally or uploaded to cloud storage to be leveraged and transformed into real-time intelligence and value. Data storage has now become a critical part of automotive design, placing a precedence on high data retention and continual data integrity. The automotive environment creates unique challenges and presents a much different scenario from computing equipment in air-conditioned server rooms under controlled temperatures. Due to the extreme temperatures that can affect the NAND flash storage used within vehicles, there are information technology (IT) considerations that require different design approaches. Understanding how data wears out, how temperature and NAND flash memory characteristics can affect data retention and product life, and what practices can be used to improve them, are the focuses of this paper. ‘Under the Hood’ in Automotive Data Storage Depending on the source, assisted and self-driving vehicles generate terabytes (TB)1 of data daily. One prediction2 forecasts that between 5 TB and 20 TB of data will be consumed per day per vehicle, which is overwhelmingly more data than the average person consumes on a smartphone3. -
Getting the Most out of SSD: Sometimes, Less Is More
Getting the Most Out of SSD: Sometimes, Less is More Bruce Moxon Chief Solutions Architect STEC Flash Memory Summit 2012 Santa Clara, CA 1 Overview • A Quick Solid State Backgrounder • NAND Flash, Log structured file systems, GC, and Overprovisioning – less really is more! • Benchmarking • Operationally representative testing • Applications • Why Flash, why now? Enough • Caching – Less *is* more • Optimizing the Stack and Changing Application Architectures Flash Memory Summit 2012 Santa Clara, CA 2 Solid State Performance Characteristics (General) HDD (SAS) Sequential Random General Performance Characteristics. Read 200 MB/s 200 IOPS YMMV, depending on Write 200 MB/s 200 IOPS . Device architecture . Interface (SATA, SAS, PCIe) 2-8x 100-1000x • 2-4x performance range SSD / PCIe Sequential 4K Random . Transfer sizes Read .5 – 1.5 GB/s 60-200K IOPS . QDs (concurrency) Write .3 – 1 GB/s 15-40K IOPS Cost Differential . $0.50 - $1.50 / GB SAS HDD . $2 - $12 / GB SSD/PCIe Rand Read Write Sweet Spot Response . High Random IOPS (esp. Read) HDD 8 ms 0.5 ms* . Low Latency SSD 60 us 20 us Solid State Storage Fundamentals Everything I Needed to Know I learned at FMS … . Data is read/written in pages (typically 4-8 KB) . Data is *erased* in multi-page blocks (e.g., 128) . Data can only be written (programmed) into a previously erased block (no “overwrite”) . Background garbage collection (GC) copies valid pages to “squeeze out” deleted pages and make room for new data • OS/FS integration (TRIM) . Additional write amplification can occur in support of wear leveling and GC . Flash memory can only be programmed/erased (P/E) a limited number of times (Endurance) • Performance degrades over device lifetime . -
UNIVERSITY of CALIFORNIA, SAN DIEGO Model and Analysis of Trim
UNIVERSITY OF CALIFORNIA, SAN DIEGO Model and Analysis of Trim Commands in Solid State Drives A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Electrical Engineering (Intelligent Systems, Robotics, and Control) by Tasha Christine Frankie Committee in charge: Ken Kreutz-Delgado, Chair Pamela Cosman Philip Gill Gordon Hughes Gert Lanckriet Jan Talbot 2012 The Dissertation of Tasha Christine Frankie is approved, and it is acceptable in quality and form for publication on microfilm and electronically: Chair University of California, San Diego 2012 iii TABLE OF CONTENTS Signature Page . iii Table of Contents . iv List of Figures . vi List of Tables . x Acknowledgements . xi Vita . xii Abstract of the Dissertation . xiv Chapter 1 Introduction . 1 Chapter 2 NAND Flash SSD Primer . 5 2.1 SSD Layout . 5 2.2 Greedy Garbage Collection . 6 2.3 Write Amplification . 8 2.4 Overprovisioning . 10 2.5 Trim Command . 11 2.6 Uniform Random Workloads . 11 2.7 Object Based Storage . 13 Chapter 3 Trim Model . 15 3.1 Workload as a Markov Birth-Death Chain . 15 3.1.1 Steady State Solution . 17 3.2 Interpretation of Steady State Occupation Probabilities . 18 3.3 Region of Convergence of Taylor Series Expansion . 22 3.4 Higher Order Moments . 23 3.5 Effective Overprovisioning . 24 3.6 Simulation Results . 26 Chapter 4 Application to Write Amplification . 35 4.1 Write Amplification Under the Standard Uniform Random Workload . 35 4.2 Write Amplification Analysis of Trim-Modified Uniform Random Workload . 37 4.3 Alternate Models for Write Amplification Under the Trim-Modified Uniform Random Workload . -
Micron: NAND Flash Architecture and Specification Trends
NAND Flash Architecture and Specification Trends Michael Abraham ([email protected]) Applications Engineering Manager Micron Technology, Inc. Santa Clara, CA USA August 2009 1 Abstract As NAND Flash continues to shrink, page sizes, block sizes, and ECC requirements are increasing while data retention, endurance, and performance are decreasing. These changes impact systems including random write performance and more. Learn how to prepare for these changes and counteract some of them through improved block management techniques and system design. This presentation also discusses some of the tradeoff myths – for example, the myth that you can directly trade ECC for endurance Santa Clara, CA USA August 2009 2 NAND Flash: Shrinking Faster Than Moore’s Law 200 100 Logic 80 DRAM on (nm) ii 60 NAND Resolut 40 Micron 32Gb NAND (34nm) 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 Semiconductor International, 1/1/2007 Santa Clara, CA USA August 2009 3 Memory Organization Trends Over time, NAND block size is increasing. • Larger page sizes increase sequential throughput. • More pages per block reduce die size. 4,194,304 1,048,576 262,144 65,536 16,384 4,096 1, 024 256 64 16 Block size (B) Data Bytes per Page Pages per Block Santa Clara, CA USA August 2009 4 Consumer-grade NAND Flash: Endurance and ECC Trends Process shrinks lead to less electrons ppgger floating gate. ECC used to improve data retention and endurance. To adjust for increasing RBERs, ECC is increasing exponentially to achieve equivalent UBERs. For consumer applications, endurance becomes less important as density increases.