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NAND Flash Architecture and Specification Trends Michael Abraham ([email protected]) Applications Engineering Manager Micron Technology, Inc. Santa Clara, CA USA August 2009 1 Abstract As NAND Flash continues to shrink, page sizes, block sizes, and ECC requirements are increasing while data retention, endurance, and performance are decreasing. These changes impact systems including random write performance and more. Learn how to prepare for these changes and counteract some of them through improved block management techniques and system design. This presentation also discusses some of the tradeoff myths – for example, the myth that you can directly trade ECC for endurance Santa Clara, CA USA August 2009 2 NAND Flash: Shrinking Faster Than Moore’s Law 200 100 Logic 80 DRAM on (nm) ii 60 NAND Resolut 40 Micron 32Gb NAND (34nm) 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 Semiconductor International, 1/1/2007 Santa Clara, CA USA August 2009 3 Memory Organization Trends Over time, NAND block size is increasing. • Larger page sizes increase sequential throughput. • More pages per block reduce die size. 4,194,304 1,048,576 262,144 65,536 16,384 4,096 1, 024 256 64 16 Block size (B) Data Bytes per Page Pages per Block Santa Clara, CA USA August 2009 4 Consumer-grade NAND Flash: Endurance and ECC Trends Process shrinks lead to less electrons ppgger floating gate. ECC used to improve data retention and endurance. To adjust for increasing RBERs, ECC is increasing exponentially to achieve equivalent UBERs. For consumer applications, endurance becomes less important as density increases. 30 100,000 25 ) ycles) 20 s s C C 10,000 15 10 ECC (bit durance ( nn E 5 1,000 0 2005 Future SLC Endurance MLC-2 Endurance MLC-2 ECC SLC ECC Santa Clara, CA USA August 2009 5 Myth: More ECC Extends Block Endurance Block endurance is how long a block is usable before program or erase status failures occur. Appppl yin g more ECC than re quired does not automatically extend the block endurance. NAND devices are configured to trigger program and erase status failures for a specific, fixed ECC value predetermined at the factory to meet qualification requirements. Applying extra ECC does not change these predtdeterm ine dthd thres hldholds, w hihhich means thtthat program and erase status failures begin to occur at the same cycling intervals regardless of the amount of ECC applied. Santa Clara, CA USA August 2009 6 Larger Page Sizes Improve Sequential Write Performance For a fixed page size , write throughput decreases as NAND process shrinks NAND vendors increase the page size to compensate for slowing array performance Write throughput decreases with more bits per cell 80 60 SLC MLC-2 MLC-3 40 20 0 512 2048 4096 8192 2048 4096 8192 4096 8192 Data Bytes per Page Sequential Programming Throughput (MB/s) Santa Clara, CA USA August 2009 7 More Pages Per Block Affect Random Write Performance The block copy time is the largest limiting factor for random write performance. As block copy time increases, random performance decreases. • Number of pages per block is the dominant factor. • Increase of tPROG is the next largest factor. • Increase in I/O transfer time due to increasing page size (effect not shown below) is also a factor. Some card interfaces have write timeout specs at 250ms, which means that block management algorithms manage partial blocks. 500 SLC MLCMLC--22MLCMLC--33 400 300 200 100 0 32 / 30064 / 25064 / 300128 / 250 128 / 600128 / 900256 / 900 256 / 192 / 1200 2000+ Pages per Block & tPROG (typ) Block Copy Time (ms) Santa Clara, CA USA August 2009 8 NAND Interface The NAND interface is increasing in throughput • Allows be tter u tiliza tion o f I/O c hanne ls – hig her bandwidth • Immediatelyyg useful for single die read performance • Modest improvement for write performance with multiple die Important for SSDs, enterprise applications • Reduces I/O channels Santa Clara, CA USA August 2009 9 NAND Interface Trends Max Throughput Interface Standard (x8) (MB/s) NtddNo standard 40 ONFI 1.0 Async (12/06) 50 ONFI 2. 0 Sync (2/08) 133 ONFI 2.1-2.2 Sync (1/09, 9/09) 200 Toggle Mode (not published) 133 ONFI 3.0 Sync 400 The ONFI Advan tage Single Channel Package Dual Channel Package 900 Target Supports simultaneous read, 800 800 program, and erase operations on multiple die on the same chip 700 enable since ONFI 1.0 600 Only industry-standard NAND interface capable of 200MB/sec 500 data rate from a single die /s Target BB 400 400 400 Tw o independent channels in a M 333 single package (doubles the 300 bandwidth) 200 200 167 In volume production today Headroom for 400MB/sec and 100 80 40 beyond 0 Work has already begun on ONFI ONFi 1. 0 ONFi 2. 0 ONFi 2. 1 ONFi 3. 0 303.0 Async Synchronous Santa Clara, CA USA August 2009 11 A-Data Afa Technologies Alcor Micro Aleph One Anobit Tech. Apacer Arasan Chip Systems ASMedia Technology ATI Avid Electronics BitMicro Biwin Technology Chipsbank Cypress DataFab Systems Data I/O Datalight Denali Software ENE Technology Entorian FCI FormFactor Foxconn Fresco Logic Fusion Media Tech Genesys Logic Hagiwara Sys-Com HiperSem Hitachi GST Hyperstone InCOMM Indilinx Inphi Members Intelliprop ITE Tech Jinvani Systech Kingston Technology Lauron Technologies Lotes LSI Macronix Marvell Mentor Graphics Metaram Moai Electronics Molex NVidia Orient Semiconductor P.A. Semi Powerchip Semi. Power Quotient International Prolific Technology Qimonda Sandforce Seagate Shenzhen Netcom Sigmatel Silicon Integrated Systems Silicon Motion Silicon Storage Tech Silicon Systems STEC Skymedi Smart Modular Tech. Solid State System Super Talent Electronics Syypynopsys Tandon Tanisys Telechips Teradyne, Inc. Testmetrix Transcend Information Tyco UCA Technology Santa Clara, CA USA University of York Virident Systems WinBond August 2009 12 Improving System Performance Syypstem performance is increased b y addin g more channels or more die per channel. Ignoring effects of ECC and block management algorithms, total throughput is either array or I/O throughput limited. NAND NAND NAND NAND Flash Flash Flash Flash NAND NAND NAND NAND Flash Flash Flash Flash Controller NAND NAND NAND NAND Flash Flash Flash Flash NAND NAND NAND NAND Flash Flash Flash Flash Santa Clara, CA USA August 2009 13 SLC 4KB 2-plane Throughput Example: Async vs. Sync Interface 800 800 800 800 800 700 600 s) // 500 480 400 400 400 400 448 ormance (MB ff 300 400 Per 240 200 136160160160 200 200 200 224 100 152 160 160 224 68 80 80 80 120 76 200 34 40 40 40 112 0 76 80 80 112 38 112 1 2 38 56 4 8 19 40 40 1 2 56 4 8 28 4 1 2 4 8 1 # of Channels # of NAND Die per Channel 1 2 4 8 Santa Clara, CA USA August 2009 14 MLC 4KB 2-plane Throughput Example: Async vs. Sync Interface 800 800 800 700 704 600 s) // 500 400 352 400 400 352 ormance (MB ff 300 Per 200 160160160 120 176 256 176 200 200 100 60 80 80 160 80 112 30 40 88 128 40 40 56 0 28 80 128 28 56 64 1 2 14 32 64 4 8 7 14 28 40 1 2 16 32 64 4 8 8 16 32 4 1 2 4 8 1 # of Channels # of NAND Die per Channel 1 2 4 8 Santa Clara, CA USA August 2009 15 Conclusions Larger block sizes to become more difficult to manage Page size doubles increasing sequential performance while reducing random performance to compensate for overall slower array throughput ECC increases to compensate for data retention and endurance; even still endurance is decreasing for consumer NAND memory 2bpc MLC has a lower manufacturing cost per bit as long as it is on a smaller process node than 3bpc MLC memory – and it fits more customer applications! Pages per block increasing to reduce die size Interface performance increasing to open up a whole new market – enterprise solutions – while helping improve SSD performance ONFI provides a proactive, scalable interface for the future with broad industry support Santa Clara, CA USA August 2009 16 Questions? Santa Clara, CA USA August 2009 17 About Michael Abraham Manager of Micron ’ ssNANDFlash NAND Flash Applications Engineering group BSB.S. in Compu ter Eng ineer ing from Brigham Young University ThilTechnical represen ttifMitative for Micron in ONFI and JEDEC for NAND Flash Key role in defining and standardizing the high- speed, synchronous DDR NAND interface within Micron and at ONFI ©2007-2009 Micron Tec hno logy, Inc. All r ig hts reserve d. PdProduc ts are warran tdted on ltly to mee tMit Micron ’s pro duc tidttion data s hee t spec ifitiifications. IfInforma tion, pro duc ts and/or specifications are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates only. Drawings not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. Santa Clara, CA USA August 2009 18.
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