MPC8260FACT/D Fact Sheet Rev. 1

M OTOROLA’ S MPC8260 P OWERQUICC II™ M ICROPROCESSOR

The MPC8260 PowerQUICC II is the most advanced integrated communication microprocessor ever designed for the telecommunications and networking markets. By combining a high-speed embedded PowerPC™ core along with unparalleled integration of networking and communications peripherals, Motorola provides cus- tomers with an innovative, total system solution for building high-end communications systems. The MPC8260 PowerQUICC II can best be described as the next generation MPC860 PowerQUICC™, providing higher performance in all areas of device operation, including greater flexibility, extended capabilities, and higher integration. Like the MPC860, the MPC8260 integrates two main components, the embedded PowerPC core and the Communications Processor Module (CPM). This dual-processor architecture consumes less power than traditional architectures because the CPM offloads peripheral tasks from the embedded PowerPC core. The CPM simultaneously supports three fast serial communications controllers (FCCs), two multichannel controllers (MCCs), four serial communications controllers (SCCs), two serial management controllers (SMCs), one serial peripheral interface (SPI) and one I2C interface. The combination of the PowerPC core and the CPM, along with the versatility and performance of the MPC8260, provides customers with enormous potential in developing networking and communications products while significantly reducing time-to-market development stages. M OTOROLA MPC8260 P OWERQUICC II PROCESSOR Product Highlights 200 MHz 603e™ core (embedded PowerPC microprocessor with floating point) Enhanced 32-bit RISC communications controller Communication Processor Module with three FCCs, two MCCs, four SCCs, two SMCs, one SPI and one I2C Multi-port 10/100 Mbps MAC (up to 3) 155 Mbps ATM-SAR (up to 2) 256 HDLC channels (each channel 64 Kbps, full-duplex) 10 Mbps Ethernet MAC (up to 4) System logic (memory controllers, timers, real-time clock interrupt ctrl, etc.)

Typical Applications Remote Access Concentrators MPC8260 Derivatives Regional Office Routers Cellular Infrastructure equipment 8260 8255 8266 Telecom Switching equipment SCC's 444 Ethernet Switches FCC's 3 2 3 T1/E1-to-T3/E3 Bridges LAN-to-WAN Bridges/Routers AT M 155 Mbps 155 Mbps 155 Mbps xDSL Systems ICache 16 Kb 16 Kb 16 Kb DCache 16 Kb 16 Kb 16 Kb Technical Specifications PCI ––yes 603e microprocessor (embedded PowerPC Est. Availability now Q3 2000 late 2001 core) available from 100–200 MHz 140.0 MIPS at 100 MHz (Dhrystone 2.1) 280.0 MIPS at 200 MHz (Dhrystone 2.1) High-performance, superscalar microprocessor Disable CPU mode Supports the Motorola external L2 cache chip (MPC2605) Improved low-power core 16 Kbyte data and 16 Kbyte instruction cache, four-way set associative No floating point unit Common on-chip processor (COP) System Interface Unit (SIU) , including two dedicated SDRAM machines PCI up to 66 MHz (available in subsequent versions) Hardware bus monitor and software watchdog timer IEEE 1149.1 JTAG test access port High-Performance Communications Processor Module (CPM) with operating frequency up to 133 or 166 MHz PowerPC core and CPM may run at different frequencies Supports serial bit rates up to 710 Mbps at 133 MHz Parallel I/0 registers On-board 24 KBytes (32 KBytes for 8266) of dual-port RAM Two multi-channel controllers (MCCs), each supporting 128 full-duplex, 64 Kbps, HDLC lines Virtual DMA functionality Three FCCs supporting: • Full 155 Mbps ATM SAR (up to two) (AAL0, AAL1, AAL5) • 10/100 Mbps Ethernet (up to three) (IEEE 802.3X with Flow Control) • 45 Mbps HDLC / Transparent (up to three) Two bus architectures: one 64-bit PowerPC bus & one 32-bit PCI or local bus Two UTOPIA Level II master/slave ports, both with multi-PHY support. MPC8260 Microprocessor Block Diagram

One can be 8/16-bit data 16 KB I-Cache Three MII interfaces PowerPC Bus I Eight TDM interfaces (T1/E1), two 603e MMU TDM ports can be interfaced with PowerPC Core 16 KB T3/E3 D-Cache SYSTEM INTERFACE UNIT 2.0V internal and 3.3V I/O D MMU PowerPC-to-PCI 133 MHz power Bridge PowerPC-to-Local to consumption: 2.5 W Bridge PCI/Local 480 TBGA package COMMUNICATION PROCESSOR MODULE (CPM) Memory Bus Controller Four 24 KB (37.5 x 37.5 mm) Timers Interrupt Serial Bus Interface Dual-Port Controller DMAs Unit RAM Parallel I/O Real Time Contact Information Clock Baud Rate µ 32-bit RISC Controller Two Virtual System Generators and Program ROM IDMAs Motorola offers users manuals, Timer Functions application notes and sample code for all of its communications processors. In addition, local support

for these products is also provided. MCC2 MCC1 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI I2C This information can be found at: Time Slot Assigner Serial Interface http://motorola.com/netcomm/ 8 TDMs MII Two UTOPIA Other Peripherals For all other inquiries about Motorola products, please contact the Motorola Customer Response Center at: Phone: 800-521-6274 or http://motorola.com/semiconductors

©2000 Motorola, Inc. All rights reserved. Printed in the U.S.A. Motorola, and the are registered trademarks and Digital DNA and the Digital DNA logo, PowerQUICC, PowerQUICC II, the PowerQUICC II logo, and EC603e are trademarks of Motorola, Inc. PowerPC and the PowerPC logo are trademarks of International Business Machines Corporation and used under license therefrom. This document con- tains information on a new product under development. Specifications and information herein are subject to change without notice.

1ATX45339-1 Printed in USA 5/00 Hibbert LITRISC-UCCJ