Psi Or Theta: Which One Should You Choose?

Psi or Theta: Which One Should You Choose?

By Roger Stout, Senior Research Scientist, ON Semiconductor, Technology Development, Advanced Packaging, Phoenix

Many device data sheets now list both of these thermal characterization parameters, but to apply them accurately in power-supply designs, engineers must understand the subtle diferences in how these terms are defned.

ver the years, standards organizations have But recognizing certain limitations of these standards, undertaken numerous eforts to standardize EIA and JEDEC later came along and defned their own the test methods that are used to characterize standards for measuring the performance of semiconductor the thermal performance of semiconductor devices. In the process, they clarifed the applicability and devices. Groups such as Semiconductor narrowed the scope of the existing theta terms for thermal OEquipment and Materials International (SEMI), the Elec- resistance, while also creating a new set of thermal charac- tronic Industries Alliance (EIA) and the Joint Electron terization parameters, symbolized by the Greek letter psi Device Engineering Council (JEDEC) have developed (Ψ). As with theta, the psi terms usually carry subscripts several standards or specifcations that defne methods of that refect measurement conditions. measuring a variety of thermal characterization parameters. As the EIA/JEDEC standards describe, the psi and theta For example, the SEMI organization drafed standards terms are related but have diferent meanings and impli- for measuring the thermal resistance of ceramic packages, cations for use. Now that both terms are appearing more integrated circuit packages and semiconductor packages frequently on device data sheets, it’s imperative that system under diferent environmental and test conditions. Tese designers understand the distinctions between the terms standards defned the familiar theta (q) terms for thermal and how these terms are defned, so that they understand q q resistance such as JA and JC . how the device vendors are characterizing their parts. Theta (Greek letter ) Psi (Greek letter Ǡ )

TLOCATION X – TLOCATION Y TLOCATION X – TLOCATION Y XY = ǠXY = PowerPATH X-Y PowerTOTAL DEVICE

Heat in Heat in

y y ?? x x

We know the actual We only know the heat along the path total device power Fig. 1. Theta defned, showing that you have to know the heat fowing Fig. 2. Psi defned, showing that when you don’t know the heat fowing along the specifc path from location x to location y to properly use along the specifc path from location x to location y, and all you know the term. is the total heat into the system, you have a psi, not a theta.

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0308OnSemi-Figure 2

0308OnSemi-Figure 1 THERMAL CHARACTERIZATION

From these defnitions, it should be clear that it is very TJ difcult to defne a thermal parameter that’s going to apply to a package under all circumstances. Yet, for some reason, JB (path down JCtop (path device manufacturers — even the ones following these stan- to board) through case top) constant at 20 constant at 80 dards — tend to gloss over this fact in their data sheets. However, in the industry at large there was a recognition Package T T Environment B C that the SEMI standards were inadequate. Consequently, in the early 1990s, EIA/JEDEC (www.jedec.org), the developer BA (board CtopA (case to air resistance) vary path resistance) of standards for the solid-state industry, drafed its own from 1 to 1000 constant at 500, comprehensive thermal standards. or 20 timesǰ BA As can be seen in the following excerpt from JESD51-2 “Integrated Circuits Termal Test Method Environmental

TAMB Conditions — Natural Convection (Still Air),” published in 1995, JEDEC recognized the same issues as SEMI: Fig. 3. Four-resistor network illustrates how psi values change depending “Te purpose of this document is to outline the environ- on the external environment, even when the package is constant. mental conditions necessary to ensure accuracy and repeat- q ability for a standard junction-to-ambient ( JA) thermal Tis article will frst review, in some detail, the nuances of resistance measurement in natural convection. Te intent q the standards themselves. It will then illustrate, by using a of JA measurements is solely for a thermal performance relatively simple0308OnSemi-Figure system model, 3 why these seemingly subtle comparison of one package to another in a standardized diferences in defnitions between theta and psi are, in fact, environment. Tis methodology is not meant to and will profound. Armed with that knowledge, designers can make not predict the performance of a package in an application- more accurate predictions about the thermal performance specifc environment.” of the semiconductor devices in their systems. So, how did JEDEC improve the situation? In my view, the most signifcant improvement was the defnition of Thermal Parameters Defned some new terms. In particular, farther into JESD51-2, Many of the now-familiar thermal-resistance param- § 4.3 states: eters were originally defned by the SEMI organization. “... Te junction-to-top center-of-package thermal charac - Ψ Tree standards in particular are worth noting. In quoting terization parameter, JT , is calculated using the following Ψ excerpts from these standards, I have italicized certain pas- equation: JT = (TJss - TTss)/ PH. ... Te relationship between q sages to highlight some of their limitations. the junction-to-ambient thermal resistance, JA , and the 1. SEMI G30-88 “Test Method for Junction-to-Case junction-to-top center-of-package thermal characterization Ψ q Ψ Ψ Ψ Termal Resistance Measurements of Ceramic Packages.” parameter, JT , is described by: JA = JT + TA , where TA Tis test method deals only with junction-to-case or mount- equals thermal characterization parameter from top surface ing surface measurements of thermal resistance and limits of package-to-air (°C/W). ... Te thermal characterization Ψ Ψ itself to heatsink and fuid bath testing environments. Te parameters, JT and TA , have the units °C/W but are math- heatsink mounting method for measuring junction-to-case ematical constructs rather than thermal resistances because thermal resistance is a conservative measure of the package’s not all of the heating power fows through the exposed case Ψ ability to transfer heat to the ambient environment, because surface. ... Also, TA is very dependent on the application- heatsinking is provided only on one side of the package, specifc environment.” whereas the fuid bath mounting method has the potential It took another decade, but the logical extension of Ψ to for equally cooling both sides of the package. other points of interest was codifed in 2005, when JEDEC 2. SEMI G38-0996 “Test Method for Still- and Forced-Air published JESD51-12 “Guidelines for Reporting and Using Junction-to-Ambient Termal Resistance Measurements Electronic Package Termal Information,” and in which can of Integrated Circuit Packages.” Tis test method deals be found, among other statements: only with junction-to-ambient measurements of thermal “... Te purpose of the JESD51 standards is to compare resistance and limits itself to still- and forced-air convection the thermal performance of various packages under stan- testing environments. dardized test conditions. While standardized thermal test 3. SEMI G68-0996 “Test Method for Junction-to-Case information cannot apply directly to the many specifc ap- Termal Resistance Measurements in an Air Environment plications, the standardized results can help compare the for Semiconductor Packages.” Te measurement results are relative thermal performance of diferent packages. A more usually diferent from the results obtained by testing in the meaningful comparison is possible if the test conditions are fuid bath environment described in SEMI G30-88 and in understood along with the factors afecting package thermal SEMI G43-87 “Test Method for Junction-to-Case Termal performance. Brief discussions of key topics are included Resistance Measurements of Molded Plastic Packages,” not in this guideline.” Ψ summarized here. Within the guidelines, it is noted that JB was not in-

Power Electronics Technology March 2008 22 www.powerelectronics.com THERMAL CHARACTERIZATION

q temperature. It can be approximated using JCtop , measur- 1000 ing the heatsink temperature in the application as close to 900 the package interface as possible, and accounting for the 800 temperature diference across the heatsink to case interface. JA — var brd only

(°C/W) 700 — var airﬂow Alternatively, some suppliers may provide a junction-to- JA JA 600 Ψ e, sink JS thermal parameter that may be used analogously 500 Ψ Ψ to JT , recognizing that the JS value is dependent on the 400 package-to-heatsink interface.” 300

Thermal resistanc 200 A Closer Examination 100 Figs. 1 and 2 introduce a very generic “thermal system” 0 that illustrates what’s diferent between the defnitions of q 110 100 1000 and Ψ. Referring to Fig. 1, if you can defne the path along PC-board thermal resistance, BA (ºC/W) which heat fows and quantify the heat along that path, only Fig. 4. Four-resistor network (of Fig. 3) results in these widely then can you call it q. With this restriction, it may be seen varying U values, even when the package contribution is fxed. q q JA that the traditional defnitions of JA and JC are applicable. q Regarding JA, all the heat that can fow must originate at cluded in the natural 0308OnSemi-Figureconvection standard 4 because it had the junction and end up at ambient (even if the path isn’t not yet been defned, but that it may be added in the future. pinned down, at least you know the heat can’t sneak away JESD51-12 further went on to clarify some existing termi- to somewhere not encompassed by the system). Regarding q q q nology, in particular JC and JB : JC, you can presume that something approaching 100% of q q “Te conduction thermal resistances JCx and JB are total device heat is fowing out through the heatsink, which measured with nearly all of the component power dissipa- it is supposed to do. Of course, you have to know what location fowing through either the top or the bottom of the tion on the package, exactly, is meant by the word “case” in package. Te values may be useful for comparing packages thePETech speci fMedcations. Adptrs 3-08 3/4/08 3:53 PM Page 1 but the test conditions don’t generally match the user’s ap- On the other hand, referring to Fig. 2, if all you can do is q plication. … JCx is the junction-to-case thermal resistance.

Te ‘x’ indicates the case surface where TCase is measured and through which the heat is forced to fow during the q JCx measurement, ‘top’ for the top surface or ‘bot’ for the q bottom surface. … Ideally, during JCx measurement, close to 100% of the power fows from the junction to the ‘x’ case q surface. Te JCx nomenclature is used to avoid the confu- q q sion associated with JC. Historically, the JC case surface is defned as the ‘outside surface of the package (case) clos- est to the chip mounting area when that same surface is properly heat sunk.’ Tis could be either the top or bottom surface, but it is not always clear which surface was used q Fold-In AC when a JC value is reported.” US/CAN/ASIA Ψ Ψ In § 5.2.3 of the JESD51-12 Guidelines, JT and JB thermal characterization parameters are discussed: Ψ Ψ “Te thermal characterization parameters JT and JB are measured by suppliers at the same time and in the same Europe q q Ψ Australia environments as JA or JMA. Users can apply the equa- tions to estimate the component junction temperature in their application by measuring a component temperature 6 --.,2!*/-%. U.K. in the application environment and using the appropriate '*,"!**4 Ψ thermal characterization parameter. Tis estimated junc- 6 *)$%,+30%.+!**1'/ &,.1.,1/0.!*)! 6 !**,1+0)+'*%10-10 tion temperature can then be compared with a junction 6 ,*$)+*!$%/,+!/% 1.+)+ temperature specifcation. A component power estimate &,.1/%)+!+!$!/)! 6 ,1"*%/!/!+)2%./!*(!.'%. Ψ Ψ 6 ,$%*/0, 6 -0),+!*10-10,++%#0,./ is required. … Using JT or JB values together with package top or board temperature measurements in a system 5 0, 2!)*!"*% requires good temperature measurement technique, com- Ψ parable to that used when the supplier measured JT or Ψ Ventronics, Inc., 346 Monroe Ave., Kenilworth, NJ 07033 JB. … When a heatsink or added heat spreader is present, Ψ Ψ +) + '!&$"!%#$"*!& neither JT nor JB can be used to estimate the junction www.powerelectronics.com 23 Power Electronics Technology March 2008 THERMAL CHARACTERIZATION

as the true path resistance from the junction to the top of 25 the package, where it’s exposed to the air; in a moment,

, Ψ I’ll relate it to the original JEDEC-defned JT to represent 2020 the characterization parameter to the top center of the plastic case.) 155 As you see, what I’ve really done is to create a two-resistor “compact thermal model” of the package, along with two

(ºC/W) JB — var brd only 10JB 0 — var airﬂow external resistances that digest the entire external system JB behavior into a very minimal set of parameters. 5 Taking the system as a whole, the overall thermal resistance, junction to ambient, can be written as follows: Thermal characterization parameter 0 TTJ 1 111 100 100 1000 Q AMB PC-boardPC board thermal resistancresistancee, JA ¥ ´ (ºC/W) QTOTAL ¥ 11´ BA ¦ QQ µ ¦ QQ µ § JB BA ¶ § JCtopCtopA ¶ Fig. 5. Four-resistor network (of Fig. 3) results in these widely varying

ΨJB (junction to board) values, even when the package contribution It takes a little more efort, but if you work it out, you’ll is fxed. Observe that over certain limited conditions, ΨJB actually also be able to derive the following: 0308OnSemi-Figure 5 approximates UJB (20°C/W). TTJB QJB YJB Q ¥ QQ ´ 60 TOTAL JB BA 1 ¦ µ , QQ § JCtopCtopA ¶ 50 TT Q — var brd only JB JC 40 JT Y JT Q ¥ QQ ´ JT — var airﬂow TOTAL JCTOP CtopA 1 ¦ µ

(ºC/W) 30 § QQJB BA ¶ JT

20 What this says, if you think about it, is that even when the two-package thermal resistances are absolutely and truly 10 constant (the two-parameter compact thermal model values Thermal characterization parameter q and q ), the corresponding Ψ values Ψ and Ψ are 0 JB JCtop JB JC 110 100 1000 PC-board thermal resistance, not constants (unless the overall ratio of the two individual BA (ºC/W) paths happens to remain constant). To put some meat onto this skeleton, look at Figs. 4, 5 q Fig. 6. Four-resistor network (of Fig. 3) results in these widely varying Ψ and 6. All I’ve done to generate these graphs is hold JB and JT q q q (junction to case-top) values, even when the package contribution is JCtop constant, and let BA and CtopA vary. (For one scenario q q fxed. Here, observe that ΨJT never even comes close to the actual path in each graph, I let the ratio of CtopA to BA be fxed — and q resistance UJCtop (80°C/W) over any conditions explored in this simple called the plot “var airfow.” In the other scenario, I held CtopA model. q constant and allowed BA to vary by itself — and called the 0308OnSemi-Figure 6 plot “var brd only.”) measure the total device power and you have no idea of how Now you might not have as much as three orders of mag- much of it fows up, down, out the leads or through the air nitude of possible variation in your particular application gap (pretty typical in the semiconductor packaging thermal board or airfow. But that’s not totally outrageous over all lab), yet you really would like to measure the temperature possible users and applications of a particular device. Te Ψ at one or more points around the boundary of the package point is that JT , in particular, can easily vary by 300% in (which is actually pretty easy), then you can’t call it a q, but a variable airfow situation and by more than 1000% when Ψ Ψ Ψ must instead call it a . Tus, JEDEC’s new terms JT , TA, the board resistance alone changes by a factor of 1000. Ψ Ψ Ψ JL and JB are all concessions to the reality that it’s easy to Unfortunately, JT is the value very ofen reported by measure temperature and really difcult to measure heat another name in data sheets in which vendors haven’t been fux — especially on miniscule semiconductor devices. careful to defne their terms; through oversight or unfa- Still, you may be asking, why is this distinction between miliarity with the newer JEDEC standards, it might even q Ψ q Ψ and so important? Take a look at the simple four-resistor be called JC. So if you wondered what that JT parameter package model shown in Fig. 3. I’ve used q’s here for the meant when you saw it recently, now you know. And if you four individual resistors, because I’m defning them to be aren’t sure how your device supplier measured and reported q PETech true thermal path resistances. (In particular, I’m using JCtop its data sheet thermal values, now you should care!

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