VLSI NMOS hardware design of a linear phase FIR low pass digital filter

A thesis presented to the faculty of the college of engineering and technology Ohio University

In partial fulfillment

of the requirements for the degree

Master of science

by Charef chabbi/ - I june,l985

OHIO UNIVERSITY LIBRARY iii

ACKNOWLEDGEMENTS

I would like to thank my.advisor, Dr. KOGI OGINO TANAKA for his advice and help throughout the development of this thesis. I found it an endjoyable project , and I am glad to have had this opportunity.

I am also grateful to my government for supporting my advanced study in the United States • iv

Contents

Chapterl Introduction ------1

Chapter2 The full adder ------3 Full adder architecture ------3 Layout of the pair of full adders

with latches ------29 Simulation of the pair of full

adders with latches ------28 Carry lookahead adder ------38

Carry save adder ------39

Chapter3 Linear phase FIR digital filter --40

proprieties of FIR digital filter 40

Optimum linear phase FIR low pass digital filter with even

impulse response duration ------48 Optimum linear phase FIR low pass

digital filter with N even and a discrete powers-oi-two coefficient

space ------56 Chapter4 VLSI NMOS hardware design of a multiplierless pipelined linear phase

FIR low pass digital filter with even

impulse response duration ------64 Network structures of FIR digital.

filters ------64 Multiplication by a power-of-two----67 v

Ptpelln1ng -~---~--.------~69

Operation speed ~f the p1pellned

linear phase FIR lev pass d1gital

f~lter ------~-·---·------~-~70

Structure of the FIR lev paas digital

ttlt.r-~------~------~--~------~--75

Fl••rplan .r the structure ~f the

lev pass dl,ltal filter ------75 Chapter5 COICLUSIOI ------80 APPEIDIX -.------~--~------8~ p!a.clf------52 pfa.l.g------·-·------~------94

pfa.n4des---~------·-----92 pra.a1a------95' pf•••pice-----~~------97 alaulatl.n------99

resp.D.e------~---.-.--~------••• REFERENCES------~----.t2 1

Chapterl INTRODUCTION A digital filter operates on an input-sampled signal to produce an output sampled signal by means of a computational algorithm. It can be simulated on general purpose computer or can be constructed with special purpose digital hardware. For a number of years , software implementation was the only possible mode of performing digital filtering, however the rapid development of very large scale integrated (VLSI) circuit has opened up the area of hardware implementation of digital filters. Currently , the industry can produce adders , shift registers and multipliers needed for hardware implementation of digital filters. The multiplier is the most expensive and the slowest component in digital filters, however multiplications by powers-af-two are very easy to implement in hardware and can improve the speed of the digital filter The FIR digital filters are always stable and can have a linear phase • ,There are essentially three well known classes of design techniques for linear phase FIR digital filters namely the window method, the frequency sampling method and the optimal ( in the Chebyshev sense) digital filter design methods. In the optimal design , by the use of integer linear programming with branch and bound algorithm , one can restrict the coefficient space to any discrete space • 2 We are looking to a minimum hardware and a high speed in our design of a linear phase FIR low pass digital filter. In chapter2, we discuss the full adder as being the basic building block of our digital filter , we layout a pair of full adders with latches that we simulate on the VAX 11-750, using the spice2g6 ,to check the transient response •

In chapter3 , we give the conditions for the phase of the FIR digital filter to be linear, we find that the impulse response can be either symmetric or antisyrnmetric. Our FIR is a low pass I then h(nT) is symmetric. we also give the specifications to achieve in terms of tolerances •

In chapter4, we adopt the transposed direct form structure of the FIR digital filter, very well suited for the pipelining , then we use also pipelining of the multiplication with a coefficient in order to achieve a sampling frequency of 17.7 MHZ with a 2.5 ~m NMOS technology • 3

Chapter2 THE FULL ADDER One of the basic building blocks of the hardwired digital filters is the full adder • A detailed discussion of the full adder architecture is then worthwhile , some other usual adders like , carry save and carry lookahead adders are rnentionned for comparison with ripple adder •

2 • 1 Full adder architecture

2 • 1 • 1 Half adder A half adder is a combinational circuit that adds two binary bits to produce a sum and a carry bit

be two binary bits to be added and be sum and carry bits produced •

Using Karnaugh maps, we can set down equations for St and Ct as

SL is an exclusive-or of At and Bt , and a half adder circuit will be as shown below

B~ V'--_---+----I--I 4 2 • 1 • 2 Implementation of the exclusive-or

Using the equation above, the exclusive-or is implemented as follows

Bi, 0--.------4

and the half adder circuit will be

2 • 1 • 3 Full adder architecture

A full adder is a combinational circuit that accepts one bit of each operand and an input carry to produce a sum bit and an output carry •

Let An ' B.., and Cn-i be bits of each operand and 5 the input carry respectively,

Let Sn and C~ be sum and output carry bits respectively • Using Karnaugh maps , we can set down equations of

S\1 and C., as

and the carry output en equation will be

Using the two equations of Sn and C~ , we can construct a full adder from two half adders as follows we input A~ and Bn to the first half adder, the sum output of the first half adder constitutes with the carry Cn- 1 the two inputs to the second half adder to produce Sn' the carry output C~ will be obtained by ORing the carry output of the second half adder and the carry output of the first half adder • The circuit of the full adder will be then , 6 and implementing the full adder using AND and NOR gates

A~ Uo--....--+---I Bno----....--...... f

CM o------..----1 2 • 1 • 4 Parallel adder

A cascade of N full adders forms an N-bit parallel adder , as shown below

The limiting speed of the parallel adder is certainly the carry propagation delay, the carry must propagate through at least two levels of logic in each full adder before C - and S~_1 can assume their final N i values • A minimization of the carry delay is then necessary , fortunately , an examination of the architecture of the full adder reveals that by taking 7

~ instead of C~ saves one inverter delay •

Then , let us find the equations of Sn+i and Crl+i in the next full adder in terms of en ,

since

E (Ah +i e B"+1- ) .c, = ( A n+1. Bn+ 1 + en then

) St"'l+! = ( A n+ 1. Ee Bn+1.. ) .e n + ( A l1+1 Q1 Bn+i + en and

the carry output Cn+i will be expressed as

An+i • BYl...i

To implement the next full adder, we need then first implement the exclusive-nor (XNOR) , 8

Using the two equations of Sn+i and en .... ! , the

full adder wi th inputs At'\1-1. ,B.,+! and -en wi 11 have the following implementation

u------o Cn+i A~1°---"'---'

Bn+i &---+-----.....---.

I :\ en 0------lID

In the carry path from en to Cn+~ , we have also

saved one inverter delay. Then if we allow the carry

outputs C" and Cn+i to alternate , where n = 0,2,4,6,8, ••• we will save inverter delays in the carry

path We saved two inverter delays in the carry path

Because of the alternation of the carry

outputs, the circuits of the full adders (Ah , Bn , en-i)

and I I ) are different and the

parallel adder will be formed by cascading a repetition

of pairs of full adders • 9

The most important parameter of a parallel adder is its addition time. Considering an N-bit parallel adder , if ~ is the carry propagation time through two full adders and tHAis the delay of an exclusive-or, the N-bit parallel adder addition time is given by _ N- i I)' Ta = 2LHA + 2 "C 2 • 1 • 5 Pair of full adders with latches.

Pipelining is a well known hardware design technique for utilizing parallelism to increase the computation rate of a digital system. We use pipelining in our design of FIR digital filter and we will discuss it in chapter4. In a pipeline the outputs of each stage are the inputs to the next stage, to avoid the alternative of a task overtaken by the following, the outputs of each stage should be latched •

The latch circuit is designed with two non- overlapping clocked transfer transistors with an inverter between them and an inverter at the output •

The circuit of the latch is the following

The data at IN will appear at OUT after one clock period ( period of two non-overlapping clocks) • 10

2. 2 VLSI NMOS design of a pair of full adders with

latches •

2 • 2 • 1 MOS transistor

Integrated systems in MOS technology contain three levels of conducting material separated by intervening layers of insulating material. From top to bottom I the layers are metal , polysilicon and diffusion •

A MOS transistor will be produced on the integrated system if a po Lys i Licori path crosses a diffusion path as shown below _____IJorain

___--~-,--__f- Gate I . , ~Source

A more detailed view of the MOS transistor is given below L-J

Source oxide ~+ / Channe\ ~

Land Ware the length and the width of the channel respectively •

Let Vgg, vss and Vdd be voltages on the gate , 11 the source and the drain respectively •

In typical circuit operation, the source and the substrate are connected together to the ground •

If (Vdd - Vss) is positive and (V99 - Vss) is greater than a threshold voltage Vth , the region below the gate and between the source and the drain changes from P-type concentration to N-type concentration I and

an N-channel connects the source to the drain I the transistor is an NMOS transistor •

But if (V99 - Vss) < Vth, the transistor is like an open switch •

If Vth > 0 , the transistor is an enhancement mode

NMOS transistor •

If Vth <0, the transistor is a depletion mode

NMOS transistor •

The basic operation of an NMOS transistor is the use of a charge on its gate to control the movement of electrons through the channel. the transit time Tr that an electron takes to move from the source to the drain is ~ L Tr L =~£ = ~Vds ~I mobility of the electrons

L, length of the channel

E I electric field The charge in transit is given by . €WL Q = - Cg(Vgs - Vth) , wlth Cg = 0 where t , permittivity ( farads/em) of the oxide 12

W,L are width and length of the channel

respectively o , thickness of the oxide The current resulting will be then

Q -€,WLp Ids = = (Vgs - Vth)Vds Tr Dt!

In the saturation region, the current Ids is given by Ids

2 • 2 • 2 Basic inverter

2 • 2 • 2 • 1 Circuit diagram

The simplest circuit , used in highly complex VLSI

NMOS systems is the basic digital inverter. Its logic

function is to produce an output which is the complement of its input. it can be realized by using an enhancement mode NMOS transistor with its gate being

input, and a depletion mode NNOS transistor connected between the supply and the drain •

The enhancement mode NMOS transistor is called pull-down , and the depletion mode NMOS transistor is called pull-up The common connection between the pull-down drain, the pull-up source and gate is the output of the inverter •

The basic inverter circuit diagram is as shown below 13 ~Vdd

~--.--..a VOUT

=

2 • 2 • 2 • 2 Inverter logic threshold voltage

The most important parameter of the basic inverter

is its logic threshold voltage Vinv which is the

voltage at the input that produces the same voltage at

the output • For Vin = Vinv , Vout = Vinv Vin < Vinv , Vout > Vinv Vin >Vinv Vout < Vinv Vinv is the input voltage that would cause pull-

down saturation to be equal to the pull-up saturation

current •

The pull-down saturation current is _ ee:VJpJ. ", ~l Ids - -pc'0 (v i nv - Vth) The pull-up saturation current will be , since Vgs is Zero , ru pe\lJ (- " , Vdep is the threshold Ids = 24uD Vdep) voltage of the pull-up • Ids of the pull-up = Ids of the pull-down

~ \JoJ pel.(v i nv - Vth ) = --r=\,Ju (_vo-ep)t L?d pu Zpd = ~ is the length-to-width ratio of the pull- down channel • 14 zpu = the length-to-width ratio of the pull-up channel •

Vinv = Vth - Vdep ~.zt!!... Zpd

The negative threshold voltage of depletion mode transistors is set during fabrication such that with gate tied to source, they turn on approximately as strongly as would an enhancement mode transistor with

Vdd connected to its gate and its source grounded.

The pull-up and the pull-down transistors of equal gate dimensions would have equal Ids currents if ~ ~ (-Vdep) = (Vdd - Vth) and I since Vth = O.2Vdd then Vdep = - O.8Vdd • for a small pull-up area , Vdep = -O.6Vdd and Vinv is

O.GVdd Vinv = O.2Vdd + ~.~~

It is desirable to have Vinv lie midway between

Vdd and ground

~ = 4 Zpd In order to achieve a proper inverter logic threshold , a ratio of pull-up to pull-down of 4-to-l is then required •

2 • 2 • 2 • 3 Inverter delay

The minimum requirement for an inverter is to 15

drive another identical inverter as shown below

~-r I 1 i I YiG--IL

Assuming at t

at Vdd •

within one transit time Tr, the pull-down of the

first inverter will remove from the output node V2 an

amount of charge equal to (Vdd.Cg~) , where cg~ is the

gate capacitance of the pull-down of the second

inverter • The pull-up of the second inverter will have

to supply a similar charge to the gate of the third

inverter, to raise it to Vdd • In the second inverter

the pull-up receives only of the current Zpu supplied by the the pull-down , where k = Zfd therefore , the delay in the second inverter is k times the transit time and

Inverter pair delay = (1 + k)Tr • 2 • 2 • 2 • 4 Layout of the basic inverter

The color coding in layout geometries are

Green , diffusion and transistor channel region

Yellow , ion implantation for depletion mode 16 transistors ;

Red , polysilicon ; Blue, metal; Black , contact cut ; using the color codes given above, along with Mead and Conway design rules, and on one lambda grid paper , the hand layout of the basic inverter is as shown on page 17 •

Vdd and GND are crossing in metal ; There is a contact cut between Vdd and diffusion of the drain of the pull-up ;

For inverter logic threshold requirement , a pull- up to pull-down ratio of 4-to-l is imposed • The length of the pull-up channel is 8.48 lambda instead of 8 lambda because of one lambda length of the channel intercepting 4 lambda width on the overlapping region of polysilicon and diffusion , then we have It>u Lpcl ~A = 4 and = = 1 , and \JJfu ""prJ ~A the ratio pull-up to pull-down is met • The connection of pull-up gate and source, with pull-down drain is done using butting contact •

The inverter input leads directly to the gate of the pull-down ; the inverter output may be easily routed out on any of the three conducting levels metal, polysilicon and diffusion; the output in our case is routed out on the diffusion level •

Finally , there is a contact cut between GND and 17

D

r

Wpu= 2A -,. .- "" 1 I I I

I.... i YJpu: 4-A i J I 1 I II I I I 1---- I \ OUT

j

!.N Wbd: R,,\ I~ --" I 0 GROUND

Layout of the basic inverter. 18 diffusion of the source of the pull-down • 2 • 2 • 3 Basic NAND and NOR logic circuits

NAND and NOR logic circuits may be constructed in integrated systems as simple expansions of the basic inverter logic circuit. The circuit diagram of a two input NAND is that of a basic inverter with an additionnal enhancement mode transistor in series with the pull-down transistor. NAND gates with more inputs may be constructed by simply adding more enhancement transistors in series with the pull-down path • As inputs are added and pull-up length is increased I the delay time of the NAND gate is also increased , the delay for an n-input NAND is then

"tKAHtf n~NV The circuit diagram of a two-input 'NOR is that of a basic inverter with an additionnal enhancement mode transistor in parallel with the pull-down. The delay time of the NOR gate depends on the number of its active inputs •

2. 2. 4 Partition of the pair of full adders with latches into cells • The partition is as seen on page 19 • The pair of full adders with latches is partitionned into five cells: celll, cel12, cell3 cel14 and cellS • Celll is repeated three times I cellS is repeated four times in the overall circuit of the pair of full adders with latches • Each cell is 19

Celi4-

----j j I 1

I 1-. I I Celti t Cerf1·

with latches pair of full adders Partition of the into cells • 20 hand layouted, simulated and then we merge the cells layouts to form the layout of the pair of full adders with latches •

2 • 2 • 5 Circuit diagrams of the cells

To build up the cells , we use appropriate combination of basic NANDs and NORs • Each cell circuit diagram is decomposed i-nto one or more NAND or NOR circuit diagrams I for easy NMOS realization • 2 • 2 • 5 • 1 Circuit diagram of the celll

The celli logic circuit is the following

The celll circuit diagram includes two NOR circuit diagrams as can be seen from celll logic circuit. The first NOR circuit diagram has An an B~ as inputs the second NOR circuit diagram has the first NOR circuit diagram output and (An.B")as the two inputs.

The cellI circuit diagram is given below 21

2 • 2 • 5 • 2 Circuit diagram of the cel12 The cel12 logic circuit is the following

J=f>

f Ah+1o--- t----.-- --\.

B(l+ i o----.--, --~

The cel12 circuit diagram includes two NAND circuit diagrams, as can be seen from the cell2 logic circuit • The first NAND circuit diagram has A~~i and

BM~i as the two inputs, the second NAND circuit diagram has the first NAND circuit diagram output and

(A"+i + Bn+ 1. ) as the two i nputs • The cell2 circuit diagram is as seen below

---.------~.----_."'J'Qq

2 • 2 • 5 • 3 Circuit diagram of the cel13 The cell3 logic circuit is the following 22

'WV--- -I Zn o---~

0--1 Ct1

The cel13 circuit diagram needs only one NAND circuit diagram with Wand (Z + C) as inputs • The cell3 circuit diagram is given below

2 • 2 • 5 • 4 Circuit diagram of the cel14 The cel14 logic circuit is the following

~ ::: D :=J',~, - '(n (\ Cn-i O D

The cel14 circuit diagram needs only one NOR 23 circuit diagram with (An.B~) and (Yn.Cn)as the two inputs • The cel14 circuit diagram is the following

------Vdd

---....----0 en ~~In

It---e Ct1-i ----.-~r- :::.

2 • 2 • 5 • 5 Circuit diagram of the cellS The cellS logic circuit is

cP 1M 5no---1-f_-[>X)_~o Sn

The cellS circuit diagram is the one of the basic inverter with a pass transistor •

The cellS circuit diagram is given below 24

2. 2. 6 Layout of the pair of full adders with latches • As we said previously, we first layout and

simulate each cell separately , in the way such that by merging the cells layouts in order to get the layout of

the pair of full adders with latches , the data , power

and clocks lines are automatically connected •

2 • 2 • 6 • 1 Layout of the celll •

The celll layout includes two NOR layouts • In the

second NOR layout, we have two pull-down in series ,

to maintain pull-up to pull-down ratio of 4-to-l , we

need to bring length to width ratio of the channel of 1 each pull-down from 1 to ...... ~ • 2 • 2 • 6 • 2 layout of the cel12 •

The layout of the cel12 includes two NAND layouts

In the first NAND layout, we have two pull-down in series, length to width ratio of the channel of each 1 pull-down has to be ~ •

2 • 2 • 6 • 3 Layout of the cel13 •

The cell3 layout includes one NAND layout • The carry in en and the carry out Cn-1 are routed in and out of the cell3 layout using polysilicon •

2 • 2 • 6 • 4 Layout of the cel14

The cel14 layout includes one NOR layout Two pull-down transistors 'are in series in each branch of

the NOR , a length to width ratio of each pull-down

channel has to be then i 2 25

2 • 2 • 6 • 5 Layout of the cellS In the layout of the pair of full adders with latches , we have to connect two cellS to obtain a latch , this will result in inverters coupled by a pass transistor. The circuit diagram of two inverters coupled by a pass transistor is as follows

\ /. ··----.11_ ·L.t12 I T

If Vouii = Vdd , Vinz = Vdd - Vthp for eLK = Vdd Vthp is the threshold voltage of the pass transistor •

To have vout LOW with Vini = Vdd , the second inverter must have a pull-up to pull-down ratio larger than 4-to-l • Compare two inverters, one with Vin = Vdd and the other with Vin = Vdd - Vthp ,

Vdd fI~ 26

If Vin = Vdd , the pull-up of inverters are in saturation and the pull-down are in the resistive region •

For Vouti = Vout~ ,

~ is a saturation current and is given by

z (0 - vth) (V~,,)2

Vdd- Yth in a similar manner, we get I~R~ as

Vdd - V:Ch - Vehp

Zrui (Vdd - \In, ) Zru:t(Vdd- V~h-Vthp) and Ii Ri = 11.. R2 ' = Zrdi Zrd~ since Vth -' O.2Vdd and vthp = O.3Vdd

~Thus ,

A ratio of pull-up to pull-down of 8-to-l is used for inverters coupled by pass transistors • In a latch, we use two-phase non-overlapping clocks to control the transfer of the data • The latch circuit diagram is the following 27

~M ~~ are The two-phase non-overlapping clocks and such that

¢M(t) • G\(t) = 0 for all t The operation of the latch is as follows will propagate When

inverted will flow through the second pass transistor and onto the pull-down gate of the second inverter , pass the data present at the input of the first of transistor will appear , delayed by one clock period 28 the two non-overlapping clocks, at the output of the second inverter • A pull-up to pull-down ratio of 8-to-l or 4-to­ ~ for cellS is required •

A capacitance at the input gate of the pull-down of the inverter of cellS is needed for the latch to work properly •

2. 2. 6. 6 Layout of the pair of full adders with latches • By connecting the layouts of celll , cell4 , celll cellS and cellS, we get the first full adder with a latch and with the inputs (An' Bn I Cn-l and the outputs «Sn)L' en» , and by connecting the layouts of cel12 ,cel13 ,celll ,cellS and cellS, we get the second full adder with a latch and with inputs (An+1 ,

Bn+i , -en) and the outputs «Sn+i)L' Cn .... i » • Vdd and GND for the two full adders are connected on each side of the hand layout circuit. The layout of the pair of full adders with latches is shown on page 29 • 2. 2. 3 Simulation of the pair of full adders with latches •

2 • 2 • 3 • 1 elF format

A CIF(Caltech intermediate form) is a means of desribing graphic items of interest to VLSI systems • The hand layout of the pair of full adders with latches is translated to elF file as an intermediate r------~~fi\- ~ ,...I~--=-~-_------~ l- ~++_++_~~~--_l­ Icf5~' _ 0 , lJ .Ll.l-,I~!--~D f I@ @J Q ~ ~. - ~~ I __ ~ 1- Ell I u lL:::- fl t==[§ t--+--+-o-+-t-+--+---+--+--

-o I'-

U L ,r L.::.-:+----.-+-+----+--t.--+--+-----'!'"""'1----+--+--I ~-- o o u I I J CJ CJ

.- I--- - ~ 0 n', II I 0 0 I 0 10- ~ f(Jt lim ~ L.J w ~ - - ..J-, - <: ~ 30 form , the Clf file is then translated to other files for design rules checking and simulation • A ClF file is composed of a sequence of characters in a limited character set The elF file contains a list of commands, followed by an end marker "E" • The commands are separated with semi-colons. The commands are of the form ,

B length width XY where

B means box

length width mean the length and the width of the box measured in..A ( A = 2. 5 pm) , X Yare the coordinates of the center of the box

also measured in ,note the semi-colon at the end of the command •

For layer specifications, the following layers are defined :

L ~D , layer NMOS diffusion

L NP , layer NMOS polysilicon

L NC , layer NMOS contact cut

L NM , layer NMOS metal

L NI , layer NMOS depletion mode implant In the elF file of the pair of full adders with latches , that we called pfa.cif , we also used symbols and calls to these symbols • As mentionned previously , we partition the pair of full adders with latches into some cells , we wrote a ClF file for each cell , in 31 order to get the elF file for the pair of full adders , we use the elF files of the cells that we connect together in the previously mentionned order , and using

DS (definition start) and DF (definition finish) , we can give to each cell a symbol number that we put after

DS at the beginning of the cell elF file and after OF at the end of the cell elF file I and we can use calls to these symbols to translate the old origin to the origin of the called symbol •

The command for the call is as follows

C symbol number T X,Y;

here e means call I symbol number is the number given previously to DS and DF, T means translation of the old origin to the origin (X,Y) •

The elF file of the pair of full adders with latches , that we call pfa.cif is given in the appendix

2 • 2 • 3 • 2 MEXTRA

MEXTRA means Manhattan circuit extractor. MEXTRA will read the pfa.cif and creates four new files , pfa.log, pfa.al, pfa.sim and pfa.nodes • The pfa.log file contains general information about the extraction it has a count of the number of transistors and the number of nodes, also, it contains messages about possible errors. The pfa.al is a list of aliases which can be used by esim. The pfa.nooes file is a list of node names and teir elF locations in elF format. The pfa.siro file is the circuit description for use with 32 simulation programs •

we use MEXTRA for extraction and design rules checking , then we check with the pfa.al the total number of transistors and if there are any other errors

Flom the pfa.sim file , we can create the pfa.spice file using sim2spice •

In the pfa.sim, for each transistor found by the extractor , there is a line of the form

type gate drain source length width where type can be either "e" for enhancement mode , or

"d" for depletion mode • gate drain source are the gate, drain and source nodes of the transistor • length width are the length and the width of the channel in elF units • (A= 2S0 units = 2.Spm

In the pfa.siro we have also lines containing capacitance information of the form

C nodel node2 cap-value where cap-value is the capacitance between nodel and node2 I expressed in femto-farads (lfemto-farad = F) In the pfa.spice, suitable for our transient analysis simulation , for each NMOS transistor there is a line of the form

Mxxxxxx NS NG ND L W where

M means MOS transistor

xxxxxx means a number given to the MOS transistor 33

NS NG ND are the source I gate and drain nodes of the MOS transistor L ware the length and the width of the channel and for each capacitance , there is a line which is the same as in pfa.sim • The pfa.log, the pfa.siro and the pfa.spice are given in the appendix at the end The circuit diagram of the pair of full adders with latches as given by pfa.spice with its 38 specified nodes is given on page 34 • 2 • 2 • 3 • 3 Transient analysis

We use the pfa.spice file and we change the order of the MOS transistor nodes, form the order source gate drain to the order drain gate source • we call the pfa.spice file where we changed the order of the MOS transistor nodes as pfa.spice also, this because we are going to use it with a different software package.

From now on , pia.spice file is the file where the

MOS transistor nodes order is drain gate source •

In the pfa.spice file, we use the following cards

CONTROL CARDS, where we specify in. OPTIONS

CARD the OPTIONS OPTS which causes the option values to be printed • MODEL CARD , where we specify the threshold voltage VTO for enhancement mode and depletion mode NMOS transistor, and MODI for enhancement mode , MOD2 for depletion mode • 34

Circuit diagram of the pair of full adders with latches with the 38 nodes as specified by the pfa.spice. 35

TRAN CARD , where we specify time increment for line printer output and the final time. The initial time is assumed to be zero by default •

PLOT CARD, this card defines the contents of one plot from one to eight output variables • ~e specify in this card the type of analysis which is transient in our case, by TRAN following .PLOT , then we list the outputs • The overlap of two or more traces on any plot is indicated by X•

• END , finally the end card •

For each NMOS transistor , there is also a line of the form

Mxxxxxx ND NG NS NB MODx <~ = > where

M means a MOS transistor

xxxxxx means a number associated to the MOS transistor

ND NG NS NB are the drain, gate, source and substrate nodes of the MOS transistor •

MODx means the mode of the MOS transistor which is either modI for enhancement or mode2 for depletion •

L Ware the channel length and width measured in U

(lunit = 0.01 rro) For each capacitance, we have also a line in the same form as in pfa.sim •

he have also to specify the inputs of the pair of full adders with latches, we have the following inputs 36

An ,Bn and C.,_~ for the first full adder An+i ,Bn+i and en for the seco.nd full adder -en does not have to be specified since it is an output for the first full adder • we specify each input by using a line of the form Vxxxxxx N+ N- DC value where V means voltage xxxxxx means alphanumeric characters associated with the voltage V

N+ N- are the positive and negative nodes respectively.

DC value means the DC value of the voltage • we have also two more inputs , which are and of the two non-overlapping clocks, we will use two non-overlapping pulses •

The sampling rate of the linear phase FIR filter corresponds to the clock rate of the two noo- overlapping clocks and of the pipelined transposed direct form strcture. Since the sampling frequency of our digital filter is 17.7 MHZ, the period of the two non-overlapping clocks is then

T = = 56.50 nsec. i'7.7 In the pfa.spice, for each pulse we have a line of the form

PULSE ( Vl V2 TO TR TF PW PER ) 37 where

VI is the initial value V2 is the pulsed value TD TR TF are the delay time, rise time• and fall time respectively

PW PER are the pulse width and the pulse period respectively •

Since the period is 56.50nsec the pulses

s are as seen below

~ 'l'M A ioo+-1 -- _ II \ o 26 ¢St i- I I \ I t -+-- __ ---..,. • .L(nsec ~ o '31 ~ \. 'J

We give to the five inputs, certain logic levels then we check the transient response, we took six cases which are the followings : Casel

Case2

An = 1

Bn = Cn_1 = A.,...i = Bn+i = 0 Case3 38

An = Bn = 1

Cn-1 = An+i = Bn+i = 0 Case4

An = Bn = Cn-i = 1

An+i = Bn+i = 0 CaseS

An = Bn = Cn- i = An+1. = 1

Bn+1. = 0 Case6

An = Bn = Cn-i = An+i = B n+i = 1 The result of all these six cases are shown in the appendix , and from that we can say that we do not have problems with the transient output response since the desired logic level is obtained by the end of the period •

2 • 2 • 4 Other usual adders

In the ripple adder that we studied previously , the major problem encountered in attempting to speed up the additions results from the carry propagation delay The delay due to the carry propagation can be minimized using carry lookahead or carry save adders

2 • 2 • 4 • 1 Carry lookahead adder

The carry Lookahead technique computes the carry of a stage independantly of the preceding carries • The general expression for the carry can be derived as follows

First stage 39

Second stage CR, = ~ B2, + ( A2, + B2, ) Ci The carry out of the n~ stage can be found as

By· replaci ng Cn-1 , then Cn-~ then Cn-~ and so on until Cin into the equation of en, we get en independant of all the preceding carries This technique increases the hardware by comparison with the ripple technique •

2 • 2 • 4 • 2 Carry save adder

The carry save adder is especially used in adding partial products to speed up multiplication. Instead of waiting for the carry to ripple, the carry is added at a later stage. Postponement of the addition of the carries can be extended to all adder stages except the last The carries from the last stage form an n-bit operand to be added to an n-bit sum using a carry lookahead scheme This technique requires also an increase in hardware by comparison with the ripple adder technique •

In our linear phase FIR digital filter , we are looking at the minimum hardware possible with the desired sampling rate , we find that we can achieve the desired sampling rate by using only the ripple adder • 40

Chapter3 LINEAR PHASE FIR DIGITAL FILTERS The FIR digital filters can be designed to have linear phase characteristics, in addition they are always stable • 3 • 1 Proprieties of FIR digital filters An FIR causal filter can be characterized by the transfer function

N-i H(z) = L h(nT)z·11 t1=o its frequency response is given by

jwT j ~(w) N-i _j u.)i'lT H(e ) = M(W)e = L h(nT)e i1= 0

The phase response e (W) is linear , giving

8 (W) • - tw , and t is a constant •

N-i ~ h (nT) sin (~nT) (~) -1 - L-- 8 I: tan ~a.~""l------L h (nT) cos (WnT) n=o N-1.

~ 2:: h(nT)sin(wnT) i1:.c" tan (W L, ) = ~-a E h (nT) cos (WnT) .1=0 then ,

N-i L h (nT) [sin (wt) cos (WI'\T) - sin (WI'\T ) cos (1.0t U = 0 ~'::O 41 or

N-i Lh(nT)sin(wt - w~T )• 0 \1.:0

Let us solve this equation to determine the constraints the on the impulse response h(nT) for linearity of

phase

N-i /h(nT)sin(wt-LUI1T) = t'\:o

then

j 2. wt ~ _jwi'\T e L- h(nT)e = \1=0

side Let us make a change of variable in the left hand of the equation above , by letting m = N-l-n , the left hand side of the equation will be

_jwt1T j2.i.Ut N-i .jw(toI-1-I'I1)T h(nT)e = e L h [(N-l-m) TJ e \1=0

Since m is a dummy variable , we will have finally

~ N-i jw~t-(N-i)1j jWI1T 2::. h[(N-l-n) '1'] e Lh(nT)e t1=0 \1::0 42 A solution of this equation is then the set of conditions

N-i t = 2 T

h(nT) I: h [(N-l-n)'lj for 0 , n , N-l

~-1 The first equation t = T states that for ~ every value of N there is only one value of phase delay t for which linear phase can be obtained exactly. The second equation h (nT) = h (N-l-n) TJ impl ies that for the value of t , the impulse response sequence must have a special kind of symmetry • It is worthwhile examining the implications of these two equations for the separate cases where N is odd or even •

3.1.1.1 N odd When N is odd , t is an integer , which means the filter delay is an integer number of samples. The -,impulse response is symmetrical about the midpoint N-1. • Ij 2 3 • 1 • 1 • 2 N even

when N is even , t is not an integer , which means the filter delay is not an integral number of

samples • The impulse response is then synunetrical about the midpoint between the samples N-2 and 2, N 2 • The definition of a linear phase filter requires 43 the filter to have both constant group delay and constant phase delay • The group delay 1Cs of a filter is defined as

d8(w) 1 I: .. 9 dw

The phase delay 1r of a filter is defined as

In many applications, only the group delay need be constant, in which case ,the phase response is of the form

where 80 is a constant • To find the constraints on h(nT) , we use the same method as in linear phase case •

t4-i (nT) sin (LUnT) 1'1' ~ > h i1=O tan (± -r - LW) = - N-i L.h (nT) cos (k)nT) t1:o and we get the following equation :

1'1-1 j~2.t-(~-1)1) jwt\T L h[(N-l-n)~ e e = l1:o 44 The solution of this equation is then the set of conditions

t a N-! T 2 h (nT) = - h [

3 • 1 • 2 Frequency response of a linear phase FIR digital filter •

The equation h(nT) = h[(N-l-n)'!J leads to some simple expressions for the frequency response.

3 • 1 • 2 • 1 N odd N-! h(nT) is symmetric about -;r- . then

after some calculations , we get N-3 • N_4 jWT T N-l -Jw--:,T H(e = Lh(nT) + h(TT)e 2 n=o or

jwT H(e

N-i and by letting k· 2 - n we will have 45 where ao :I:

3 • 1 • 2 • 2 N even • When N is even , h (nT) is symmetric about the N-2 N jwT midpoint between and ...- , then H(e ) can be -~ 2 put on the form

N-~ jwT i..- _jwnT!t! _jwl1T H(e ) = h(nT)e + L. h(nT)e n= 0 .,.--T"

Since h (nT) = h [(N-I-n) TJ ' we get

N-2 ~N-i _joon• iT T _jw(N-i-I1)T L-h(nT) e = Lh(nT)e t1= .!i. 2 '-'=0

~nd

H-2 ~~~T ;r ! • e 2 L 2h (nT) cos [W( N2 - n) T] ~=o

Let N-i 1 k = 1 , 2 , •• , - 2 - n = k - -2 then

by letting 46

For WT = 1'1 , o independantly of {h(nT~ , the frequency response has a zero at z = -1 •

3 • 1 3 positions of the zeros of a linear phase FIR digital filter • The symmetry condition on the impulse response , imposes certain restrictions on the zeros of H(z) •

~-i - .n H (z) = 2.-h(nT) z n=o • (N-1) N-i (N-i-n) H (z) = z 2=h(nT)Z n:o

let rn = N-l-n

N-i -(N-i) H (z ) = Z L h ( (N-1-m) T) zm M:O since m is a dummy variable and h[

N-1 _(~-1) n H (z) = z 2:..h ( nT) Z n:o or

then 47

The equation above shows that H(z) and H(zi)are identical to within a delay of (N-l) samples •

The zeros of H(z) are also zeros of H{Zi) • Based on this propriety, the zeros of a linear phase

FIR digital filter have the following symmetry proprieties : i .1 a) • If Zt= a is a real zero of H(z) , then Z-t = a is also a real zero of H (z) • je~ b) • If zL = e .is a zero of H(z) , where Bt# 0 JBi and StL ..J.,.-r: T1 , then z-ii" -_ e- -- -zl is also a zero of H (z) • jet c) • If zt = rte is a zero of H(z) , where rt * 1 -jet .i i .jet ei. *0 and et *1\ , then Zt = r~ e , Zt = -;:re and -:1 1 j 9i zl = -e are also zeros of H( z) • rL Polynomials with the above proprieties are called mirror image polynomials •

As a consequence, the transfer function of a linear phase FIR digital filter can be written as a product of elementary factors as

k H (z) = TI HL (z) L:i where each Ht (z) can take one of the following three formats

.i 1 !_i HA ( z ) = (1 - az )(- crZ )

jBt -i -J9i. _i = (1 - e z) (1 e z) 48 jei, .1 ·i9.t . 1 i i8,i .1 He (z) -= (1 - r e z) (1 - r~ e z) (1 - --e z) 4 t-~ 1 .j8~ •i (1 - -e z). ri By taking rt = 1 and ei = 0 in He(Z) , we get .1 HD(Z) = 1 + z

The zero of HD(Z) lies at z = -1 •

The elemental factor HD(Z) is important because it represents a network with half-sample delay •

•1 Hn(Z) = 1 + Z

jwT• -J~-, T HD(e ). e a 2COs(~1 )

Since the linear phase FIR digital filter with even N has a transfer function of odd order (N-l) , an odd number of Hn(Z) must be cascaded with a linear phase

FIR digital filter with N even •

3 • 2 Optimum linear phase FIR low-pass digital filter with even impulse response

duration •

3 • 2 • 1 Frequency response

The frequency response of an FIR digital filter is given by :

, JwT N-i .jwnT H (e ) = .L h(nT)e n:o

If we impose the symmetry condition

h (nT) = h [(N-l-n) ~ and shift h(nT) to the left by ~ samples, we get a 49 new sequence h(nT) defined from (- ~ ) to (lr - 1) , symmetrical about the midpoint between (-1) and 0 •

AI h('11)

N -2 -i o 1 2 ~_1 .,T -,; t ~ I t I

N N h(OT) = h(-T) N ,., h(T) = h(-2T)

AI AI h(2T) :: h(-3T)

•

•

• h[(-n-1)~ N h(nT) = , n = 0 , 1 , 2 , ... 'T - 1 Since the symmetry is between (-1) and 0 , the

AI j~T frequency response H(e ) can be expressed as 1 ~-i. ~ jtAlT >- '" ~&I).,T ~ Iv _jI.lH'IT H(e = h(nT)e + ~ h(nT)e ~=_N n~o 2 50

, replace in the first summation in the right hand side n by -m-l , we get

~i '" _jl.l)",T• Lh(nT)e = h:-~ ~ ~ m being a dummy var i able and h (nT) = h D-n-l) ~ -1 I - i '. ~'" _JI.I.iI"lT ~ JwtlT jwT /.~ h(nT)e e L-h(nT)e = ...... --- 11:.. 1L '1: 0 2 The frequency response will be then

or

N jwT H(e

term This frequency response consists of a linear phase jwJ:.. and a term e Z equivalent to one half sample advance which is purely real • _ j~T If we define H(e ) as

• -Jw-'T IV Jk)T _ jWT ~ ) H(e = e 2, (e _ jwT be We see that H(e ) is purely real and can -j~~ e t. does used for design purposes , s i nee the term not affect the magnitude response of the filter • 51

The magnitude response of a typical low pass filter is as given below

j I I I I -'I o 0.5 f =wnwT

of The parameters in the standard tolerance scheme

the desired characteristic above are defined as follows bi , allowed passband deviation allowed stopband deviation °2 I edge Fp , desired passband Fs , desired stopband edge The optimal low pass linear phase FIR digital

filter can be stated as a weighted Chebyshev

approximation problem by defining : 52

Bp = {F , o " F " Fp} Bs = [F , Fs , F " O.S}

The desired frequency response of the filter is

~2'MF , F E Bp D(J ) = ~ { , F E. Bs The 'weighting function 62, j2t1F T ' F € Bp Wee ) = 1 , F € Bs

Defining G as the union of the passband and

stopband G = Bp U Bs of The optimal filter design problem becomes one ~ which finding the set {h(nT), 0' n, - I} minimizes j~n J= j2.11F _ jt,1tF Ma x , W( e ). 0 ( e ) - H ( e ) F£G The optimal linear phase FIR digital filter is the j2?fF one for which the maximum error E(e is minimized

over all F•

The set of linear inequalities implied by the

minimax problem is stated explicitly as

J;.-i ~ N i [211F(n+T~ , 1 kO" 1 - k b2, , 2 2h(nT)cos + 1\=0 for o ~ F ~ Fp

~_1 , 2:}'h (nT) cos [2if F (n++B ~ - °2 n::o for Fs F , 0.5

minimize cS2 "• 54 Jtul the maximum number of extrema of H(e , by adding to j~T this the number of extrema of E(e that are not jLVT extrema of H(e ), the total maximum number of jtwT extrema of E(e can be found. Let us then find the maximum number of extrema of jf4>T H (e ), ju>T H(e ) = Let cos (.wf) then

, t Cos (wnT) = 1)

• t Sin (wnT) = - 1) and

'wT = if (~ )1 X= C05(CUT) " _ i ~

N ~ n H (x) = x ~ 2h(nT)a(nT) (2x 1) l1=O where a(nT). is obtained by collecting like power terms of (2i' - 1)J"

#!ttl _ By letting b(nT) = 2h(nT)a(nT) , H(x) will be -}-i n H(x) = x L b ( nT) (2 x*" 1) n=o

_ j~T H{e ) can be obtained as 55 ju.>T H(e ) = H(X)! i toT: ~ COS (X) jb)T *-1 H(e = cos tto t> ~b(nT> [cOS("'T~t'! n=o _ jwT To find the extremal points, H(e ) is differentiated giving

d jtl)T jtUr jwT dL!.t (:i (e D= P (e )•Q (e where , JwT P(e

, JU)T Q(e )

c(nT) is obtained by collecting like power terms of n cos ( '-U T) • jwT Clearly ,P (e ) is zero at WT = a • J'TUl To find the zeros of Q(e ), it is useful to convert it to an ordinary polynomial in the variable y via the transformation y = COS (WT) The resulting function Q(y) is of the form ~ jl&jT -i Q (y) = Q(e = L C(nT)yn n=o jWT Q(y) is a polynomial of degree (li- - 1) , hence H(e ) 2 can have at most (~ - 1) zeros in the interval

o < LoT ~ 't1 or (.1:L.) extr emurn i n 0 ~ WT ~ 'H • 2 56 The approximation problem is being solved over a union of two disjoint frequency bands (passband and stopband) , the error function can have an extremum at each band edge , whereas these points will generally - J6.)T not be extrema of H() • The error function can then have a maximum of (JL + 2) extrema , i.e. (JL) _ j(UT ~ 2 extrema of H(e ) and two extra extrema for the passband and stopband edges •

The second theorem of PARKS and McCLELLAN for a linear phase FIR digital filter with even impulse response duration can be stated as follows :

For a filter of length N samples (the approximation is being done with ~ functions) the resulting error curve must exhibit (~ + 1) or (~ +Z) peaks • Two of the peaks are located at Fp and Fs • The point F = 0 is guaranteed to be a peak if there are

(lL + 2) peaks ,. otherwise it may or may not be a peak 2 The point F = 0.5 is never a peak • An important result of the above theorem is that

the optimal filter for N even may be an extra-ripple

filter with (~ + 2) peaks in the error curve , or an equiripple filter with (Ji- + 1) equal magnitude 2, peaks in the error function • 3. 3 Optimum linear phase FIR low pass digital

digital filter with N even and a discrete

powers-of-two coefficient space • 3 • 3 • 1 Optimal finite wordlength coefficients 57 When digital filters are implemented using special purpose hardware or simulated on a general purpose computer , each filter coefficient has to be represented by a finite number of bits. The simplest and most widely used approach to the problem is the rounding of the optimal infinite precision coefficients to its b-bit representation. However, the filters so obtained are not optimal anymore , and in most cases there exists another set of finite wordlength coefficients which gives. ·the best approximation to the desired frequency response • To find this set of coefficients , it is necesary to include the finite woralength restriction into the filter design procedure The original problem of continuous optimal Chebyshev approximation becomes a much more complex discrete optimization problem. The standard methods of optimal FIR digital filter design , namely the REMEZ algorithm and linear programming do not work when the finite wordlength is imposed • The optimal b-bit wordlength linear phase FIR digital filter with N even can be stated as follows Given : The number of bits b j~1\f The desired frequency response D(e ) '2111= and a positive weight function W(J > i both continuous on a compact subset G of (0 , T - o€ > i~'i'rF ~ and H(e > = 2h(nT) cos [2'NF (n+-r>] n=o 58

AI Find the set of b-bit coefficients h(nT) which e~ror as minimize the maximum weighted absolute defined j~TrF j2.ifF I j2,tr,: I = max.w(e ) D(e )- H(e ). F€G The inclusion of the b-bit restriction into the use of design problem formulation does not allow the the REMEZ algorithm or linear programming to solve minimax problem • to the Minimize 6, I stopband ripple, subject

constraints ~ -i 2h(nT)Cos[2t1F(n++~ , 1 + k 02, 1 - k &" ~ .2 h=o for 0 .:; F , Fp }_i , - S2, ~ ih (nT) cos I3i1'F (n++~ , 02 n=:o " for Fs ~ F ~ 0.5

A.# and h(nT) are b-bit numbers (sign included) • N Each of the b-bit coefficients h(nT) is a b-bit b binary number which can occupy one of the 2 different • values distributed between some lower and upper bound ~ ••• , _i But since it is known that l'h (nT)l 1 , n=O ,I, 2 Jt power for all non-amplifying digital filters (output lower or equal to input power) •

Using the (b - 1) bits along with the sign bit I all the upper positive bound of h(nT) is obtained when , the (b - 1) bits are ones and the sign bit is zero such that -(b-!) upper bound of h(nT) = 1 - 2 59 _(b_i) and the lower negative bound will be - (1 - 2 ) then

-(b-!) 6-i 2 (2 - 1)

Most of the integer programming computer programs

require that the discrete variables are non-negative

bounded integers • \44e should then substitute the

IV coefficients h(nT) by non-negative integer coefficients

h* (nT) •

N b-i By multiplying each coefficient h(nT) by 2 , we

get

b-i AI b_i 1.,-1 ~ (1 - 2 ) h(nT)2 "' (2 - 1)

b-i ~ b-! Adding 2 to h(nT)2 makes the upper bound as well

as the lower bound non-negative integers •

By making the substitution

* ~i[N 1 h(nT) = 2 h(nT) + ~

the lower bound of h(nT)* is 1, the upper bound of h(nT)* is 2b·-1, h(nT)*" is a non-negative integer taking b the values 1, 2 , 3 , ••• , 2 - 1 •

* N By using h(nT) instead of h(nT) , the previous

formulation problem is replaced by the following

Minimize 62 I subject to the constraints li.-1 60 2. * ~ h (nT) cos [211F (n+t~ n=o ~-1 ~ ~ (nT) cos [211F (n+-} ~ n=o for 0 ~ F " Fp

N _1 ~ ~ (nT) cos [2l1F (n++B n:o N -1 ~ h(nT) cos [211'F (n+4-U ne o for Fs ~ F ~ 0.5 it f b and h(nT) E ll,2,3, ••• ,2 - 1} The minimax problem above can now be solved using a general purpose integer programming package •

3 • 3 • 2 Powers-af-two coefficient space FIR digital filters with coefficients equal to powers-of-two are not expensive , do not involve general multiplications and are easy to implement. The integer programming becomes eminently useful when the discrete coefficient space is the the powers- of-two space • The general purpose integer linear programming packages are not suitable for designing filters with powers-of-two coefficient space , the optimization problem can not have a formulation as in the integer space • Coupling integer linear programming with a suitable branch-and-bound algorithm enables one to design filters with any discrete coefficient space • The discrete space optimization is particularly useful when there is a frequency response specification 61 with given tolerance to be met. A discrete space optimization used for the design of a linear phase FIR low pass digital filter with N = 36 , and with the following specifications : sampling frequency = 17.7 MHZ passband ripple = 0.02 stopband ripple =0.05

3-db point at 1.99 MHZ

fp = 1.77 MHZ

fs =2.54 MHZ gave the following h(nT) coefficients -5 .8 h(OT) = 2 - 2 = h(35T) -8 h(T) = 2 = h (34T) _6 -7 h (2T) = -2 -2 = h(33T) -5 -8 h(3T} = - 2 - 2 = h(32T) -5 h (4T) = - 2 = h (31T) .6 h (5T) = - 2 = h (30T) -5 h (6T) = 2 = h(29T) -4 -'1 h (7T) = 2 - 2 = h(28T) -4 h(8T) = 2 = h(27T) -6 -8 h{9T) = 2 - 2 = h(26T) -5 -7 h (lOT) • -2 - 2 = h (25T) -! -, h(11T) = -2 + 2 = h (24T) -3 -8 h(12T) = .. 2 + 2 = h (23T) -4- -, h(13T) = -2 + 2 = h(22T) -4 -5 h(14T) = 2 + 2 = h (21T) -~ -4 h(lST) = 2 + 2 = h (20T) 62 .! h(16T) = 2 = h(19T) .i -? h(17T) = 2 + 2 = h(18T) Using these h(nT) coefficients , the frequency response of the linear phase FIR low pass digital filter with N = 36 , is given by

The frequency response magnitude is

J~T H(e =

T = 56.50nsec • The plot of this frequency response is given on the following page • A FORTRAN program to plot this frequency response is given in the appendix • FREQ RESP IN, DB 4D.OD -20.00 ur-.oo 20.00 110 ..00

.. !

• 8" 64 Chapter4 VLSI NMOS hardware design of a multiplierless pipelined linear phase FIR low pass digital filter with even impulse response duration The interest in VLSI systems is due to the fact that current MOS technology allows hardware implementation of signal processors to become possible

In VLSI systems, the MOS elements must permit easy modular replication in hierchically organized networks and should ideally operate very fast in minimal area with very little power. The MOS-VLSI constraints are throughput rate, chip area, power dissipation and regularity. In our design I we use a multiplierless structure , realizing the coefficients with the smallest number of shifts and adds , to obtain a minimum chip area ,. We also use pipelining and parallel arithmetic to achieve a high throughput rate and the regularity is met by using modular cell arrays.

4 • 1 Network structures of FIR digital filters • The transfer function of an FIR digital filter is given by N-i y(Z) H (z) c = Lh{nT)Zn X(Z) n::o FIR digital filters have a variety of alternative forms of implementation • Direct form and cascade form structures are commonly used • When the transfer function is written as in the following ~ 6S -,;- .1? H ( z) = U (~Ok + ~ik Z + ~i) The filter is said to be realized in the cascade form • 4 • 1 • 1 Direct form

The direct form realization follows directly from the FIR filter input-output relationship written in the form N-i y (z) a= X (z) L.h (nT) z_n . n=o or N-i y(nT) = Lh(kT)x[(n - k)'l'J k:o A signal flow graph, obtained directly from the equation above , is as shown below

T · h~ th~N-1)lJ ~ .<±)--+- ~(nT)

This direct form structure corresponds to the most straightforward ordering of the additions and multiplications implied by the transfer function • Clearly , there are many other ways that the computations can be organized • 4 • 1 • 2 Transposed diret form 66 Based on the theory of the signal flow graphs , both the transposition of a digital circuit and the

original circuit have identical transfer functions • Specifically , "the transposed digital circuit is obtained by reversing the directions of every branch in the circuit and by exchanging the input and output terminals • The transposed direct form structure is as shown

below

.... -------fI] hli1'l-2)~ 11[(N-i)1j ___...... -______-....-.---Po...-..~- x,(hT)

or

~(n~T...... _+--______

rhllN-1Jf] ·h ~N-2)TI 4· ~ ------67 This transposed direct form structure is the so called parallel-in serial-out and is well suited for our design • 4 • 2 Multiplication by a power-of-two • We used the fixed-point binary arithmetic and the two's complement representation.

Let S be a 9-bit number including the sign bit and 151 < 1 , S can be either positive or negative • • M Let 2 be a power-of-two, where m is a non- negative integer • 4 • 2 • 1 5 positive •

-tn Multiplying S by 2 gives

-rl1 5.2

The sign bit occupies the position zero in the register

Each bit s~ occupy 1· n9 the l·~ position before multiplication will occupy after multiplication the . th (1 + m)- position. We have m positions from the left

unoccupied • If we fill out these m positions by the sign bit (zero in this case) , we will have

-m 5.2 =

noting that s~+tn = si' i • 1,2, ••• ,8

-m 5.2 68 _m Then , multiplication of a positive number S by 2 is done simply by shifting S by m places to the right and filling the positions from the left by the sign bit.

4 • 2 • 2 S negat i ve • S · S • -1 + 2:. s.t r ~-:.i ..m Multiplying 5 by 2 gives

-th The sign bit occupies the m- position , each bit occupying the i~ position before multiplication occupies after multiplication the (m + i~h position.

We have m positions from the left unoccupied • By filling these m positions'by the sign bit , we get

-m 5.2

noting that s~+m· St ' i= 1,2, ••• ,8

-m 5.2 :r:

Then , multiplication of a negative number S by imin two's complement representation is done simply by shifting S by m places to the right and filling the positions from the left by the sign bit • 69 4 • 2 • 3 S positive or negative

From the sections 4 • 2 • 1 and 4 • 2 • 2 , multiplication of a number S (positive or negative) by -m 2 in two's complement representation is done simply by shifting S by m places to the right and filling the unoccupied m positions from the left by the sign bit •

4 • 3 Pipel ining •

Pipelining is a well known hardware design technique for utilizing parallelism to increase the computation rate of a digital system. In a pipelined unit , a new task is started before the previous one is complete , this is possible since the ripple adder is a combinational circuit. A pipelined system divides the logic into stages separated by a set of latch registers

Let ~ be non-pipelined unit with total delay t i , .i that is wi th throughput t i •

Let Pm be an m-stages pipelined version of Pi ' in which each stage has the same delay ~ , and t r is the de~ay of a latch. The total delay of one stage of Pm is therefore (te + t?) , hence the maximum throughput -i of Pm is (te + tr) • The throughput of a pipelined unit is the inverse of the delay per stage, not the delay of the entire unit, hence a pipelined system has an increased throughput. As stage length is shortened , throughput increases , but as the number of stages increases , so does the number of latches necessary. There is then a trade-off between the throughput 70 and the number of latches • The transposed direct form of the FIR digital filte~ is suitable to pipelining as seen below

...... -t------

Except stageO, each other stagei represents the multiplication of the input signal by the coefficient h~~and addition of the product to the latched result of the previous stage • Our coefficients are equal to a sum or a difference of two powers-of-two, to see whether we need a pipelining for the multiplication by such a coefficient or not, we need to examine the operation speed of the pipelined linear phase FIR low pass digital filter. 4 • 4 Operation speed of the pipelined linear phase FIR low pass digital filter • Each coefficient h(nT) is expressed as a sum or a 71 difference of two powers-of-two , the multiplication by such a coefficient is realized using two shifts and one addition. Since shifing is only a matter of wiring , it takes no time to perform and the operation speed of the filter is essntially limited by the operation of addition. Our implementation uses a pipelining of the transposed direct form structure, where each stage involves a multiplication by a coefficient and one addition and since the multiplication by h(nT) needs only one addition, we have a total number of two additions per stage. The latch delay is the period of the two non-overlapping clocks ~Mand ¢s , equal to the sampling period T = 56.50nsec. In order to avoid that a stage operations overtake the following stage operations , we need to insure that

stage operations delay < T To find the delay of the operations per stage , we will assume the worst case possible, we have two additions pe~ stage, the worst case will then be two parallel adders with the maximum number of bits • Our input is a 9-bit number (including the sign bit) , the smallest -8 power-of-two number of the coefficients is 2 , the parallel adder with the maximum number of bits is the one with seventeen bits • The stage operations delay can be computed from two parallel adders as shown below 72

Let t HA = delay of an EXOR

Let t c :II: carry propagation delay through two full adders • If it was not the carry propagation delay due to the ripple adders , we would have a total stage operations delay of only 4tHA•

To find the total stage operations delay I we need then to include the carry propagation delay of the second parallel adder , then

Stage operations delay = 4 t HA + 81e Typical delays in NMOS technology are

'41A = 5. 5nsec • te -= 4. Snsec • Stage operations delay will then be Stage operations delay = 55 nsec,

Adding a delay of about 2nsec. for an inverter I we will have

Stage operations delay = GO nsec , 73

The condition STAGE OPERATIONS DELAY < T is not satisfied • Need a pipelining of the multiplication with a coefficient which will bring the number of additions per stage from two to one, as a consequence the stage is shortened and the number of latches is increased •

4 • 4 • 1 Pipelining of a multiplication by a coefficient expressed as a sum or a difference of two powers-of-two • For purpose of demonstration , let this coefficient be 9k and let the operation be addition • then

,«and ~ are neqat i ve integers. From the transposed direct form structure , we get v

w = [s£i + vet + 2~)] £i

From the equation above, we get the following signal flow graph v ) 74

Considering multiplication of v by 2 and addition of the product to sz as a new stage of the pipelined system , we need to introduce an additional latch as shown below

v

From the flow graph above , w is given by

r: -a DC - i @ ] -1 w = ~z + v(2 z + 2 ) z

As we see from the equation above, the latch added makes 2t1. and 2' as separate independant coefficients •

In order to keep always g~ as a one coefficient written as a sum or a difference of 2~ and 2~ , we need to add one more latch so that instead of having (2'" i'1 + 2') we will have i'1 (2()( + 2~) , and the signal f low graph for pipelining the multiplication by the coefficient 9 is k as given below 75

After pipelining the multiplication by a coefficient , a stage involves only one addition and

stage operations delay l& 214iA + ~ 1<: 2 or stage operations delay = 47 nsec • and adding a delay of about 2nsec. for the inverter stage operations delay = 49nsec. < 56.50nsec.

4 • 5 The structure of the FIR low pass digital filter • The structure is as mentionned in previous sections, a pipelined transposed direct form , and we use a pipelining of the multiplication by a coefficient in order to achieve a sampling frequency of 17.7 MHZ.

Due to the transposed direct form structure I when multiplying the input signal x(nT) by a negative power-of-two , the product will be negative on the assumption that x(nT) is positive, so instead of using

cC c( (5 - x ( nT) 2 ) we use (- s + x(nT)2 ) then two's

0( complement the result which will give us - (- s +x(nT)2 ) equal to (s - x (nT) 20( ) • The structure is as seen in the following page •

4. 6 The floorp1an of the structure of the 35 order linear phase FIR low pass digital filter • Each addition or substraction in the transposed direct form structure is performed using ripple full adders • The input signal is a 9-bit word including the sign bit • The coefficients are expressed as a sum or a 76 x (nT)

\I hl!Q" hLiSi) Ltr~~!~~f!f-e- __

!IN.

~~.,....--...-_...., ~---...-..;TI~~_-._~~I Hl ....--~~ t-.---.-l "---+--'

~(o!. htr)· h~)ih~' h(!iT h(~ :('l1) hl~ _ r~to ~l~~~~ 1"" !~~ I1\'1

Transposed direct form structure of the 35~ order

linear phase FIR low pass digital filter • 77 difference of two powers-of-two and they are 9-bit words including the sign bit. The multiplication by one coefficient is then realized by at most two shifts and two additions (or substractions) • The shift is done in the most simple way by appropriate river routing of the wires in the channels between the adders and the latches. We use fixed point arithmetic and the two's complement representation • All arithmetic operations in our pipelined linear phase FIR low pass digital filter as can be seen from the transposed direct form structure are in the form

0( x (nT) .2 + S• cal and as we said I x(nT).2 is obtained by appropriate wiring , the form of the arithmetic operation becomes then

0( r(nT) + S I where r(nT) = x(nT).2 It is then either an addition or a substraction depending on whether the coefficient is positif or n~gatif respectively •

a). r (nT) positif •

It is an addition and it is done using 17-bit parallel ripple adder with a carry 0 entered in the ripple adder of the least significant position •

b). r (nT) negatif. It is a substraction and it is

s r' (nT) where r' (nT) = - r (nT) and r ' (nT) is positif • 78

Here , we perform first r' (l'1lT) -S which is a substraction and it is done using 17-bit parallel

ripple adder , by inverting the 17 bits of S and

entering a carry of one in the full adder of the least

signicant position • The result is then two's

complemented giving (5 - r' (nT» .If the next r ' (nT) is also negatif, we do not twO's complement the result but we perform the substraction then we two's complement • The floorp1an of the transposed direct form structure is given in the cover pocket of the thesis • About the floorplan notations, a difference in

delay exists between £i and INV , £~ symbolizes a delay

of T, the sampling period, INV is just an inverter delay which is about 2nsec. There is also a difference between INV and INV.delay, INV means there is an inversion but INV.delay means there is no inversion • From the floorplan of the structure of this digital filter, we can determine the total number of

MOS transistors needed • we have

61*17-parallel adders giving 25,406 MOS

transistors.

17*84 latches giving 8,568 MOS transistors.

17*29 inverters giving 1,749 MOS transistors.

A total of 35,723 MOS transistors is then needed for this implementation • 79 We· can estimate the active area of this FIR digital filter chip from the layout of the pair of full adders with latches •

The layout of the pair of full adders with latches occupies an area of a 2­ 148 A *lOlA = 93425 ram = 0.10 mm The estimated area for the 17-parallel adder is a 0.10*8.5 = 0.85 mm The estimated active area of the FIR low pass digital filter will then be 2 0.85*61 = 52 mm 4 • 7 Layout of the FIR low pass digital filter

The layout~of the filter can be obtained from the layout of the pair of full adders with latches • A minimization of the length of the wires is required because- the delay in aMOS circui t depends highly on the load capacitance. We can then use cells with predefined dummy tracks, to a Llow the signals to run over the cells. The width of the channels between the adders and the latches can also be minimized by using the river routing • 80

ChapterS CONCLUSION The linear phase FIR low pass digital filters with

coefficients having a minimum number of non-zero digits

in their canonical signed digit codes can be designed to meet given specifications, by the use of discrete optimization for the determination of the coefficients

as desired • The hardware of these filters is also very much reduced, but a small increase in the number of delays is paid for by the improvement of the speed The hardware as seen from our floorplan can further be

reduced , by truncation of the 17-bit word to only a 9­

bit word , but a truncation error could affect the

specifications • Then , here a tradE~-off exists between

getting the desired specifications and paying the hardware , or saving the hardware and increasing the

tolerances of the specifications • 81

APPENDIX 82

$ c~t r--fa.cif DS ..~., L NM; B 8750 1000 4375 500; B 1000 1000 1750 500; B 1000 1000 1750 2250; B ,3750 750 4""C'; 2125; B 1250 750 625 4125; B 1000 1000 1750 4000, B 1000 1500 1750 6000; B 1000 1500 3500 5750; B 10'~O l'~OO 1750 1125C'; P- 1000 1000 4500 4000; Po 1000 750 5500 4125; B 1000 1000 6500 2250; P- 1000 1000 6500 4250; B 1000 1000 6500 5'~0; B 1000 1500 6500 6"?C:": B 1000 1000 6500 11250; B 875C' 1000 4375 11250; L NtH B 1000 1000 1750 500; B 1500 500 1750 1000; B 500 4750 750 -:1~C:"w ...... w, B 1500 500 1750 5250; B sec 4750 275() 3125; B 1000 750 1750 5875; B 1000 1000 3500 5500; B 500 4500 ·1750 8500; B 1000 1000 6500 500; B 500 5750 5500 3625; B 1500 500 6500 1000; B 1000 5750 7750 3625; B 1500 SOO 6500 6250; B 1000 500 6500 6750; B 500 500 8500 6250; B 500 3750 6500 8875; ;B 1000 1000 6500 11250; B 1000 1000 1750 "11250 ; L NP; B 1250 500 625 2250; B 1000 1000 1750 2250; B 1000 1000 6500 2250; B 1750 SOO 7875 2250; ... --- .,,-. ... .:...,,: ·B 1000 1000 175.0 4000; B 1750 500 3.125 4000; B 1000 1000 4500 4000; B 1000 1000 6500 4250; B 1750 500 7875 4500\; B 1000 750 350·0 6125; B 500 500 4250 6250; B SOC 1250 4750 5875; B 1250 50Ct 5625 5500; B 1500 2120 1750 7060; B 1500 2120 6500 7810; L NC; 0 c; r.r) C;0t., '!.'7C:" 50:" ~ 83

.,.,., :. 5 0 I~~I 50'J 1750 11::; Po 500 SCI') 450t) 4000 '0 & ..~{ 500 500 6500 4250 B 500 500 .~500 2250 B 500 500 6500 500; B 500 1000 6500 67507 B 500 500 6500 112507 L NI'; B 1250 2870 1750 7060; B 1250 2870 6500 7810; 94 lJDD 1"r:: 11250; 94 GND 1:25 500~ 9tJ. IN11 125 4125; 94 IN12 1"C: 2:250; DF [IS 3; L NMj E: 7000 1000 3500 500; B 1000 lOCO 4000 5':)0 ; B 1000 1000 1 c:.~" 2250; B 1500 750 2750 2125; B 1000 1000 4000 22507 B 1000 1000 500 6000: B 2500 750 2250 5875;: B 1000 1000 4000 5750; B 1000 1000 6500 5250; B 750 1250 6625 41251 B 1000 1500 4000 7750; B 1000 1000 6250 7000; B 750 2S()O 6 1 '".'C:: 8750;

B asoo\Jw'wI 750 4000 9625; B 1000 1000 1750 9500; B 7000 1000 3500 11250; B 1000 1000 4000 11250;' L ND; B 1000 1000 4000 500; B 1500 500 4000 1250; B 1000 6000 2750 4000; B -1500 500 4000 6750; B 1000 6000 5250 400,' ; B 1000 1000 6250 700C'; B 1000 1000 500 6000; B 1000 1000 4000 7500; B 500 2750 4000 9375; B 1000 1000 4000 11250, L NP; B 500 1750 1500 875; B 500 500 1500 -250; B 1000 1000 1500 2250;

.....--....-. • .•.lo._~ ·B 1000 ,1000 4000 2250; B 2500 500 5750 2250; B 500 1750 250 2875; B 3250 500 2125 3500; B 3750 500 1875 4500; B 1000 1000 4000 5750; B 1500 500 5250 5500; B 1000 1000 6500 5250; B 1500 2120 4000 8810; B 500 2250 1500 11125; B 1000 500 SOO 9750; B 1000 1000 1750 9500; t l>.Ir~ 84

B :;00 5C·O 'lOOO S:5'~ ; B 500 5C,j 650C 5-2~O; B 500 :.000 4000 7750; B 500 500 ~2S0 7000; B SOO 500 17S0 9500; B SOO SOO 4000 11:50; L NI; B 1~50 2870 4000 8810; 94 VDn 1~~-.., 11250; 94 GND 1:5 500; 94 IN13 1625 1375; DF ; C 2, T 0,0; C :1 T 8750,0; DS 4; L NM; B 8750 1000 43i5 500; B 1000 1000 17~O 500; B 10')0 1000 1750 2:250;

B 37~0 750 4""'tr,~-.., 2125; B 1250 750 6~tr, 4125; B 1000 1000 1750 4000; B 1000 1500 1750 6000; B 1000 1500 _3500 5750; B 1000 1000 17S'~ 11250; B 1000 1000 4~00 4000; B 1000 750 5500 412S; B 1000 1000 6S'~0 2250; B 1000 lOC'O 6500 4250;'- B 1000 1000 6500 500; B 1000 1500 6S'~0 6750; B 1000 1000 6500 11250; B 9750 1000 437S 11250; L ND; B 1000 1000 li50 ~OO; B 1500 SOO 1750 1000; B 500 :4750 750 3125; B 1500 SOO 1750 52~0; B 500 4750 2750 3125; B 1000 750 1750 5S7s; B 1000 1000 3500 S~OO; B SOO 4500 1750 8500; B 1000 1000 6500 SOC' ; B SOO 5750 S500 3625; B 1500 SOO 6500 1000; B 1000 ~7~0 7750 362S; B 1500 ~OO 6S00 6250; B 1000 500 6S00 6750; B SOO 500 ~~OO 6250; .- -' ~ "~_J._ B 500 3750 6500 8875; -'_ .. ,- _. - : B 1000 1000 6S00 11250; -.

B 1000 1000- 17S0 11250; .... ;- ... -. ~~~- L HPj .1'- .' B 12~O 500 625 2250; B 1000 1000 1750 2250; ., . - B 1000 1000 6S00 2250; -.- B 17~0 SOO 7875 2250; B 1000 1000 1750 4000; B 17S0 500 3125 4000; . B 1000 1000 4500 4000; Ie 1000 1000 650'0 4250; 9".1 1-'e"t', ~t:H', -"O-:'e" "C:r. t'. ~ 85

B 1500 2120 1750 7060; B 150'~ 2120 6500 7elOj L NC; B SOO 500 1750 500; B 500 500 1750 2250; Po 500 500 '1750 4000; Po 500 1000 1750 6000; B 500 1000 3500 5750; B 500 ,500 1750 11250; B 500 500 4500 4000; B 500 500 6500 4250; B 500 500 6500 2250; B" 500 500 6500 500; B 500 100'~ 6500 6750; B 500 500 6500 11~50; L N"'·.1. , B 1250 2870 1750 7060; B 1250 2870 6500 7810; 94 VnD 125 11250; 94 GND 125 SOO; I!F; C 4 T 15750,0; DS 5; L NM; B 4750 1000 2375 500; B 1000 1000 3750 500; B 4750 100':> 2375 11250; B 1000 1000 3'71:';" 11250; B 1000 1500 200':' 2500: B 1000 1500 3750 7250; - L ND; B 1750 500 875 625(); B 1000 1000 2000 27:50; B 1000 3~50 2000 4875; B 1000 6500 3750 4250; B 500 500 45'~O 6250; B 1000 1000 3750 500; B 500 3250 37S'~ 9125; B iooo 1000 3750 11250; Lr. NP; B 500 12250 750 6125; B 500 500 750 -500; B 1000 750 2000 2125; B 2250 500 3625 2250; B 1500 2120 3750 8310; L NC; .B 500 500 3750 SOO; B 500 1000 2000 2500; B 500 1000 3750 7250; B 500 500 3750 11250; L NIj B 1250 2870 3750 8310; 94 vnn 125 11250; 94 GNrt 125 500; 94 !NCL1 625 6125; [IF; C 5 T 24500,0; DS 6; L NM; B 4750 1 00 23 5 500; B 1000 1 00 37 0 500; ~ i~ ~~C. ~ r.r. '2~ e: ., '! ,., co: r. ~ 86

r· 1750 5C·V 875 6250; B lOOC' 1000 2000 2750; B 1000 !~50 2000 4875; Po 1000 6500 3750 4250; B 500 500 4500 62S() j B 1000 1000 3750 5'~O ; B 500 ·3250 3750 9125; B 1000 1000 3750 11250; L NPj· B 500 12250 750 6125; B 500 500 750 -500; Po 1000 7SC' 2000 2500; B 2250 500 3625 2250; B 1500 212':> 3750 8310; L NC; B 50'~ 500 3750 500; B 500 1000 2000 2500; B 500 l()OO 3750 7250; B 500 500 3750 11250; L HI; B 1250 2870 3750 8310; 94.VD!! 125 11250; 1~c; 94 GND ~ .... 500; 94 INCL2 625 6125; 94 OUTl 4625 6250; ·DF ; C 6 T 29250,0; [IS 7; L NM; B 8000 1000 4C'OO 500; B 1000 1000 1000 500; B 1000 1000 5750 500; B 1000 1000 2250 3000; B 2500 750 4000 2875; B 1000 1000 5750 3'~OO ; B 1000 1500 1000 5000; B 1000 1500 2750 5000; B 1000 1500 5750 6000; B 8000 1000 4000 11250; B 1000 1000 5750 11250; P. 1000 1000 1000 11250; L NIl;· B 1000 1000 1000 500; B 1000 4250 1000 3125; B 750 500 1875 4500; B 1000 1000 2750 4750; B 500 5500 1000 8000; B 1000 1000 1000 11250; B 1000 1000 5750 500; .. B 1500 500 5750 1000; B 1000 3500 4500 2500; B 1500 500 5750 4000; B 1000 3500 7000 2500; B 1000 ~OOO 5750 5250; B 750 500 6625 5500; B 500 1500 7250 6000; B 500 500 7750 6500; B 500 4500 5750 8500; B 1000 1000 5750 11250; L NF'; B 5500 500 2750 1750; .• "i~t" ~.'\,"'. ~"7~ "'7.'\ f\ r. ~ 87

=: lC'OO 750 275·~ 5375; B 500 500 3500 5500; B 500 1250 4000 512:;; B 375C 500 61:;5 4750; B 1500 2:'20 5750 7060; L NC; B 500 500 1000 500; B 500 500 5750 500; B 500 500 2250 3000; B 500 500 575-0 3000; B 500·1000 1000 5000; E\ 500 1000 2750 5000~ B 500 1000 5750 6000; B 500 500 1000 11250; B 500 500 5750 11250; L NI; B 1250 2870 l~OO 6060; B 1250 2870 5750 7060; 94 vnn 125 11250; 94 GND 125 500; 94 !N21 125 3000; 94 IN22 125 1750; DF ; C 7 T 0,1~500; DS 81 L NM; B 7750 1000 3875 500; B 1000 1000 3250 500; B 2500 750 1500 2125; B 1000 1000 3250 2250; B 75D 3750 625 4375; B 1000 1000 500 6750; B 1000 1000 3250 4000; B 4000 750 5750 4125; B 1000 15,00 -3250 7000; B 1000 1000 5000 6750; B 750 2000 4875 8250; B 2500 750 3250 887S; B 1000 1000 1500 9000; B 7750 1000 3875 11250; B 1000 1000 3:;50 11250; L ND; Po 1000 1000 3250 500; B 1500 500 3250 1000; B 1000 4500 2000 3000; B 1500 500 3250 5000; B 1000 4500 4500 3000; B 1000 :;000 3250 6250; B 750 500 4125 6500; B 1000 1000 5000 6750; B 500 3500 3250 9000; B 1000 1000 3250 11250; B 1000 1900 500 6750; L NF'j B 750 50~ 1625 -500; B 500 750 1000 -375; B 500 4000 1000 2000; B 1500 500 2000 3750; B 1000 1000' 3250 4000; .B 1000 1000 3250 2250; B 4000 500 5750· 2250; ~~~ ~~~ ~~~ ~~~~. 88

P. 500 100C' 1750 1 OOC'V; B 500 2:50 2250 111~5i L NC; B 5'~O 500 3250 50C; B 500 500 3250 2250; B 500 500 3250 4000; B 500 500 500 6750; B 5{)O 1000 3250 7000; B 500 500 5000 6750; B 500 500 1500 9000; B 500 500 3250 11250; L NI; B 1250 2870 3250 8060; 94 von 125 11250; 94 GND 125 500; 94 IN23 875 1500; DF ; C 8 T 8000,12500~ DS 9; L NM; B 8750 1000 4375 500; B 1000 1000 1750 500r B 1000 1000 1750 2250: B 3750 750 4125 2125; B 1:?50 750 625 4125; B 1000 1000 1750 4000; B 1000 1500 1750 6000; B 1000 1500 3500 5750; B 1000 1000 1750 11250; B 1000 1000 4500 4000; B 1000 750 5500 4125; B 1000 1000 6500 2250; B 1000 1000 6~~~ 4250; B 1000 1000 6500 500~ B 1000 1500 6500 6750; B 1000 1000 6500 11250; B 8750 1000 4375 11250; L ND; B 1000 1000 1750 500; B 1500 500 1750 1000; B 500 4750 750 3125; B 1500 500 1750 5250; B 500 4750 2750 3125; B 1000 750 1750 5875; B 1000 1000 3500 5500; B 500 4500 1750 8500; B 1000 1000 6500 500; B 500 5750 5500 3625; Po 1500 500 6500 1000; B 1000 57S0 7750 3625; B 1500 500 6500 6250; B 1000 500 6500 6750; B 500 500 8500 6250; B 500 3750 6500 8875; B 1000 1000 6500 11250; B 1000 1000 1750 11250; L NP; B l~~n 500 625 2250; B 1000 1000 1750 2250; Po 1000 1000 6500 2250; B 1750 500 7875 2250; ~ 1~n~ 1~nn 1~~~ ~n~n~ 89

B 1000 750 3500 61~5; B 500 500 4250 6250; B 500 1250 4750 5875; B 1~50 500 5625 5500; B 1500 2120 1750 7060; B 1500 2120 6500 78107 L NC; B 500 500 1750 500; B 500 500 1750 2250; B 500 500 1750 4000; B 500 1000 1750 6000; B 500 1000 3500 5750; B 500 500 1750 11250; B 500 500 4500 4000; B 500 500 6500 4250; B 500 500 6500 2250; B 500 500 6500 500; Po 500 1000 6500 6750; B 500 500 6500 11250; L NI; B 1250 2870 1750 7060; B 1~50 2870 6500 7810; 94 VDD 125 11250; 94 GND 125 500; DF ; C 9 T 15750,12500; tiS 10; L NM; P. 4750 1000 2375 500; B 1000 1000 3750 500; B 4750 1000 2375 11250; B 1000 1000 3750 11250; B 1000 15C'O 2000 25001 B 1000 1500 3750 i250; L NDj B 1750 500 875 6250; B 1000 1000 2~00 2750; B 1000 3250 2000 4875; B 1000 6500 3750 4250; B 500 500 4500 6250; B 1000 1000 3750 500r B 500 3250 3750 9125; B 1000 1000 3750 11250; L NPj B 500 12250 750 6125; B 500 500 750 -250; B 1000 750 2000 2125; B 2250 500 3625 2250~ B 1500 2120 3750 8310; L NC; B 500 500 3750 500; B 500 1000 2000 2500; B 500 1000 3750 7250; B 500 500 3750 11250; L Nlj B 1250 2870 3750 8310; 94 uno 125 11250; 94 GN!I 125 500; 94 INCLl 625 6125; DF 7 C 10 T 24500,12500; T",~ ..... 90

B 1000 000 3750 5 B 1000 500 2C'OO· 0 B 1000 500 3750 0 L NtJr O-'c:" B 175.0 500 !WI;.} 6250; B 1000 1000 2000 2750; B 1000 3250 2000 4875; B 1000 6500 3750 4250; B 500 500 4500 6250; B 1000 1000 3750 500; Po 50C 3250 ;3750 9125; B 1000 1000 3750 11250; L NP; B 500 1~250 750 6125; B 50'0 500 750 -250; B 1000 750 2000 2125; B 2250 500 3625 2250; B 1500 2120 3750 8310; L NC; B 500 500 3750 500; B 500 lOCO 2000 2500; B 500 1000 3750 7250; B 500 500 3750 11250; L NI; B 1250 2870 3750 8310; 94 vnn 125 11250; 94 GNII 125 500; 94 INCL2 625 6125; 94 OUT2 4625 6250; DF ; C 11 i 29250,12500; L NM; B 750 1000 -375 5~O; B 750 24250 -1125 12125; Po 750 1000 -375 13000; B 750 1000 34375 11250; B 750 24250 35125 12125; B 750 1000 34375 23750; E $ 91

$ cat pfa.lcs Window: -1500 35500 -750 24750 14 deF"letion 35 enhancement 38 nodes s 92

$ cat pfo.nod~s 94 1 25000 -750 94 2 29750 -75':) 94 IN13 10000 - 00; 94 GND -1500 O·, 94 \,IDD 34750 0; 94 INCLl :5000 v, 94 INCL2 29750 0;- 94 GNIi 1250 0; 94 GND 6000 0; 94 GND 12250 0; 94 GND 17000 o; 94 GND 21750 OJ 94 GNti 27750 0; 94 GND 32500 0; 94 IN12 1250 1750; 94 .IN13 9750 1750; 94 IN13 17000 1750; 94 18 26000 1750; 94 19 30750 175C' ; 94 IN12 1250 1750; 94 IN12 6000 1750; 94 IN13 1225'~ 1750; 94 IN13 17000 1750: 94 IN13 21750 1750; 94 18 26000 1750; 94 19 31750 2000; 94 27 500 2500; 94 28 7250 2500; 94 29 13500 250C'; 94- 30 16250 2500; 94 31 23000 2500; 94 18 26000 2500; 94 33 27750 2500; 94 OUTl 32500 :2500; of 0 ,,\o"'e-· 94 .L , 30750 ':'wi";' 94 INll 1250 '3500; 94 IN11 4000 3500; 94 38 15000 3500; 94 3.8 17000 3500; 94 38 19750 3500r 94 INli 1250 3500; 94 IN11 4000 3500; 94 38 17000 3500; 94 38 19750 3500; 94 IN11 6000 3750; 94 38 21750 3750; 94 47 11000 37S0; 94 27 2500 ·4250; 94 30 18250 4250; 94 38 14750 4750; 94 38 i250 4750; 94 IN23 11000 4750; 94 53 23000 4750; 94 27 3000 5000; 94 30 18750 5000; ... 1"""\ po- .~ ~ ...... ~ . 93

~~ 30 : 750 5 50; 94 38 5 50 57 0$ Q4 IN23 13500 5750; 94 53 21000 5750; 94 38 6000 6000; 94 53 21750 6000? 94 27 1000 6000; 94 30 16750 6000; 94 IN23 14500 6500~ 94 33 27750 65CO~ 94 OUTl 32500 6500; 94 38 5750 6750; 94 53 21500 6750; 94 IN23 12250 7000; 94 33 27500 7250~ 94 OUTl 32250 7250; yA IN23 12000 7750; 94 VDn 1500 8120; 94 VDn 17250 8120; 94 VDn 6250 8870; 94 VDn 22000 8870; 94 IN23 10000 9000; 74, IN23 10000 9000; 94 VDn 28000 9370; 94 VDn 32750 9370; 94 88 8750 9500; 94 VDn 12500 9~70; 94 GND 500 12500; 94 GND 5250 12500; 94 GND 10750 1Z500; 94 GND 17000 12500; 94 GND 21750 12500; 94 GND 27750 12500; ,94 GND 32500 12500; 9 4 I N2 2 0 1 4.00 0 ; 94 98 8250 14250; 94 98 17000 14250; 94 100 26000 14250; 94 101 30750 14250; 94 98 10750 14250; 94 98 17000 142507 94 98 21750 14250; 94 100 26000 14250; 94 101 30750 14250r 94 107 500 14500; 94 108 4000 145007 94 IN21 1750,15000; 94 IN21 1750 15000; 94 IN21 5250 15000; 94 112 12000 15000; 94 113 16250 15000; 94 114 23000 15000;' 94 100 26000 15000; 94 116 27750 15000; 94 101 30750 15000; 94 OUT2 32500 15000; 94 119 500 15750; 94 108 650 15750 94 IN23 10 50 160 0; q,~ T !'-!? ~: -l, '7 0 t) 1!., l\ l\ ~ 94

..)4 1:::: '?5·:'O 65·jC· ; ?4 119 5,:0 . 750~ ':;4 1 04 ~ ::5-:- 6750; ~4 113 1""""'t:"A.o,,;;,,;,;V l6i50; 94 119 3750 17'~OO ; 94 132 2~OOO 172501 94 113 18750 175':'0 ; 94 119 250 17500; 94 119 2250 17500; 94 '78 5250 17500; 94 98 5250 1775C' ; 94 11:! 17000 17750; 94 1"-:.. oJ 20250 1775C'; 94 113 18750 18250~ 94 .....1~'"..., ..,... 21000 1825C' ~ 94 .l~ ... 21750 18500y 94 98 5000 18500; 94 113 16750 18500; 94 145 10750 18500; 94 145 10750 18750; 94 145 12500 18750; 94 116 27750 19000; 94 OUT2 3250'J 19000; 94 132 21500 19250; 94 145 10500 19500; 94 \;ID!I 750 19620r 94 116 27500 19750; 94 OIIT"") 32250 19750; 94 vnn 5500 '"'...:. 620; 94 VDD 17250 0620; 94 145 9000 2 000; 94 VIID 22000 1370; 94 \.-'!:D 1100 1j 1620; 94 1)~D 28000 1870; 94 VDD 32750 1870; $' 95

$ cat pfa.sim fJrli ts: 1 . tech: nmo s d OUi2 VDD OUT2 1995 500 32500 19750 d 116 VDD 116 1995 500 27750 19750 d 145 VnD 145 1995 500 10750 19500 d 132 VDn 132 1995 SOO 21750 19~50 e INCL2 101 116 500 500 29750 18500 e INCLl 100 132 500 500 25000 18500 d 113 VnD 113 1995 500 17000 18500 d 98 von 98 1995 500 52S0 18500 e 119 145 112 500 1000 10750 18000 ~ 113 132 GND 500 500 21000 17750 d 119 vnn 119 1995 500 500 17500 e 119 98 108 500 1000 5250 17000 e IN23 132 114 500 1000 23000 16750 e IN23 113 GND 500 500 18250 16250 e IN23 112 GND 500 1000 9500 16000 e IN21 108 GND 500 1000 6500 15250 e IN21 119 -107 500 1000 500 15250 e 101 OUT2 GNI! 500 1000 32500 14500 e 100 116 GND 500 1000 27750 14500 e 98 114 GND 500 1000 23000 14500 e 98 113 GND 500 500 16250 14500 2 98 112 GND 500 1000 12000 14500 e IN22 108 GND 500 1000 4000 14000 e IN22 107 GND 500 1000 500 14000 d IN23 VDDIN23 1995 500 12250 7750 d OUTl vnn OUTl 1995 500 32500 7250 d 33 vnn 33 1995 SOO 27750 7250 d 53 vnD 53 1995 500 21750 6750 d 38 VDn 38 1995 500 6000 6750 e INCL2 19 33 500 500 29750 6000 p. INCLl 18 53 500 500 25000 6000 d 30 VnD 30 1995 500 17000 6000 d 27 vnn 27 1995 500 1250 6000 ~ 30 53 GND 500 500 21000 5250 e 38 IN23 29 500 1000 13500 5250 e 27 38 GND 500 500 5250 5250 e 38 53 31 500 1000 23000 4250 e IN11 IN23 47 500· 1000 11000 4250 e IN!l 38 28 500 1000 7250 4250 e 38 30 GND 500 500 18250 3750 e IN11 27 GND 500 50C 2500 3750 e IN12 47 GN~ 500 1000· 11000 3250 e 19 OUTl GND SOO 1000 32500 2000 e 18 33 GND 500 1000 27750 2000 e IN13 31 GND 500 1000 23000 2000 e IN13 30 GND 500 500 16250 2000 e IN13 29 GND 500 1000 13500 2000 e IN12 28 GND 500 1000 7250 2000 e IN12 27 GND 500 500 500 2000 C !N13 GNtl 55 C ~t rtII GNII 653 C 18 GND 65 C 19 GND 60 C 2i GND 87 f"'o ~ ,-. r.~.'~' ._ 96

.'" 1~3 Gr~:: :;.;:, .... ~f'" 'J ":'"c GND 1~3 C 100 3ND 65 C 101 GNrl 65 ( 108 GNI! 55 C 112 GNI! 64 C 1:3 GND 87 C 116 GNI! 83 C OUT2 GND 79 C 119 GND 84 C 132 GND 65 ~ :45 GND /0 $ 97

~** SPICE DECK created from pairfulladder.sim, tech=nmc~ H1 5 5 4 3 DNMOS L=20.0U W=5.0U M~ 6 6 4 3 DNMOS L=20.0U W=5.0U M3 / , 4 3 DNMOS L=20.0U W=5.0U M4 8 8' 4 3 DNMOS L=20.0U W=5.0U M5 6· 11 10 9 ENMOS L=5.0U W=5.0U M6 8 13 12 9 ENMOS L=5.0U W=5.0U M7 14 14 4 3 DNMOS L=20.0~ W=5.0U Me 15 15 4 ~ DNMOS L=20.0U W=5.QU M9 17 16 7 9 ENMOS L=5.0U W=10.0U M10 0 14 8 9 ENHOS L=5.0U W=5~OU M1l 16 16 4 3 DNMOS L=20.0U W=5.0U M12 18 16 15 9 ENMOS L=5.0U w=10.0U M13 20 19 8 9 ENMOS L=5.0U W=10.0U· M14 0 19 14 9· ENMOS L=5.0U W=5.0U MIS 0 19 17 9 ENMOS.L=5.0U W=10.0U M16 0 21 18 9 ENMOS L=5.0U W=10.0U M17 22 21 16 9 ENMOS L=5.0U W=10.0U MiS 0 10 5 9 ENMOS L=5.0U W=10.0U M19 0 12 6 9 ENMOS L=5.0U w=io.ou M20 0 15 20 9 ENMOS L=5.0U.W=10.0U M21 C 15 14 9 ENMOS L=5.0U W=5.0U M22 0 15 17 9 ENMOS L=5.0U W~10.0U M23 0 23 18 9 ENMOS L=5.0U W=10.0U M24 0 23 22 9 ENMOS L=5.0U w=10.0U M~~ 19 19 4 3 DNMOS L=20.0U W=5.QU M26 24 24 4 3 DNMOS L=20.0U W=5.0U M27 25 ~5 4 3 DNMOS L=20.0U W=5.0U M28 :6 26 4 3 DNMOS L=20.0U W=5.0U M29 27 27 4 3 DNMOS L=20.0U W=5.0U .H30 25 .11 28 9 ENMOS L=5.0U W=5.0U M31 26 13 29 9 ENMOS L=5.0U W=5.0U M3~ 30 30 4 ~ DNMOS L=20.0U ~=5.0U M33 31 31 4 3 DNMOS L=20.0U W=5.0U ~34 0 30 :6 9 ENMOS L~5.0U W=5.0U M35 3~ 27 19 9 ENMOS L=5.0U W=10.0U M36 0 31 27 9 ENMOS L=5.0U W=5.0U M37 33 27 26 9 ENNOS L=5.0U W=10.0U M38 35 34 19 9 ENMOS L=5.0U W=10.0U M39 36 34 27 9 ENNOS L=5.0U W=10.0U M40 0 27 30 9 ENMOS L=5.0U W=5.0U M41 0 34 31 9 ENMOS L=5.0U W=5.0U M42-0 37 35 9 ENMOS L=5.0U W=10.0U M43 0 28 24 .9 ENMOS L=5. au W=10. OU .M44 0 29 25 9 ENMOS L=5.0U W=10.0U M45 0 38 33 9 ENMOS L=5.0U W=10.0U M46 0 38 30 9 ENMOS L=5.0U W=5.0U M47 0 38 3~ 9 ENMOS L=5.0U W=10.0U M48 0 37 36 9 ENMOS L=5.0U W=10.0U M49 0 37 31 9 ENMOS L=5.0U W=5.0U eso 38 0 55.0F C51 4 0 653.0F C52 29 0 65.0F C53 28 0 60.0F C54 31 0 87.0F

'"'l::"t:" ,·f t' ,-- •._ 98

C::..O 2::- v 65.0F C61 15 C 1:3.0F Ct2 12 C' 65.0F :~63 10 0 65.0F !·~64· 18 0 55.0F ("'If:' \... 0"'; 17 0 64.0F Ci.'uO 14 0 37.0F C67 6 0 83.0F CbS 5 0 79.0F C69 16 0 84.0F CiO ..,8 0 65.0F C71 J o 76.0F $ 99

M1 t4 5 5 3 MOD2 l-20.0U WaS.OU M~ 4 6 6 3 "'002 l·~O.OU W-S.OU H3 4 7 7 :3 MOD2 l-20.0U. W-s.OU H4 4 e e :3 MOD2 l-20.0U W-S.OU Ms 10 11 6 , KODl L-:;.OU W-:;.OU "6 12 13 S 9 P10Dl l=S.OU W=S.OU M7 4 1t4 1~ :3 HOD2 l-20.0U lIIeS.OU H8 4 1S 15 3 HOD2 L-20.0U W=S.OU H9 1 16 17 9 .11001 L.-S.OU W-lO.OU HI0 8 14 0 9 HODI L=S.OU w-s.au Hl1 4 16 16 :3 HOD2 L-20.0U W=s.OU H12 15 16 18 9 HODI LaS.OU W-l0.0U Mll S 19 20 9 HODl LaS.OU W=10.0U H14 14 19 0 9 1'1001 L-S.OU W=::;.OU M1S 17 19 0 9 MOD1 L.aS.OU 1.I=10.0U 1'116 18 21 0 9 MOOl L=:;.OU W-I0.0U 1'117 16 21 .,., 9 MODI LaS.OU W=lO.OU 1118 s 10 0 9 MOOt L=:;.OU W-I0.0U 1119 6 12 0 9 MODI L=S.OU W-IO.OU 1120 20 15 0 9 HOD1'L=S.OU W=10.0U tot21 14 IS 0 9 M001 L=S.OU W-S.OU M2::! 17 1: 0 9 /'1001 L=S.OU W=10.0U 11"''7 18 23 a 9 HODl LaS.OU W-I0.0U ,.,:4 .,., 23 a 9 HOOl L=S.OU W=10.0U li:5 4 19 19 3 MOD2 L=20.0U W=S.OU H26 <4 24 24 3 /1002 L=20.0U W=S.OU 1127 4 25 25 3 HOD:! L:20.0U W=5.0U 11"0;) 26 26 3 11002 L=20.0U W=S.OU M29 4"' 27 27 :; 11002 L=20.0U W=5.0U M30 28 11 25 9 11001 L-S.OU W=:;.OU H31 29 13 26 9 HOD1 L.-S.OU W-S.OU H3:! 4 30 30 3 MOD2 La20.0U "'=S.OU H33 4 31 31 3 MOD2 L=20.0U W=S.OU t134 26 30 0 9 HODI LaS.OU W-:;.OU HZ:; 19 27 32 9 MOol L=S.OU W=10.0U t136 27 31 0 9 MODl L=S.OU W-S.OU M37 26 27 32 9 11001 L=~.OU W-I0.0U 3~ M38 19 34 9 HODI L-:;.OU 1II=10.0U <, H39 :!i 34 36 9 1'10Dl L=~.OU W=10.0U 1''1'10 30 27 C 9 1'1001 L=~.OU W-:;.OU 11-11 31 34 0 9 MOD1 L=~.OU W·~.OU #. H42 35 31 0 MODl LaS.OU WalO.OU ;J ""43 24 28 0 9 1'1001 L=S.OU Wa 10 . 0U !'14~ cs 29 0 9 1'1001 L=S.OU W-I0.0U 1145 33 38 0 9 1'10 II1 L=~.OU \Jal0.aU H46 30 38 0 9 1'1001 L-S.OU W=S.OU t14i 32 38 0 9 1'10D1 La~.OU W-1O.OU H48 36 37 0 9 MODI L.-S.OU W=-10.0U 1'149 31 37 0 9 HODI L-~.OU WaS.OU e50 38 0 O.O~~PF' eS1 ~ 0 0.6SJPF' C~:::! 29 0 O.06SPF' CS3 28 0 O.060PF' e~4 ·31 0 O.087PF' CSS 30 0 O.OSiPF' CS6 25 0 0.083PF' i(~.:: CS7 24 0 O.019PF .', CSS 21 0 0.136PF c:.;q 19 0 O.l8SPF C60 26 o 0.06SPF' C£.l 15 0 0.123PF' C62 12 0 0.06SPF' C63 10 0 0.06SPF' C64 18 0 O.O~5PF C65 11 0 0.064PF C66 1~ 0 0.OS7PF . ~ . C6' 6 0 o.oa3PF' i· C68 5 0 O.079PF I. C69 16 0 O.08t4PF' C70 S 0 0.065PF' ., C71 7 0 O.076PF' ;.:. .MODEL HODI "KOSCVTO-1.0) ~c .HODEL MOD2 NMOSCVTO--4.0) VOD 4 0 DC s VGA 34 0 DC 0 ..

VG8 37 0 DC 0 c . : VGC 3S 0 DC 0 ~ VGD 21 0 DC 0 ....•.: VGE 23 0 DC 0 VGF' 13 0 PULSECO S 2HS 2NS 2NS 20N5 56. SONS) ~. VGG 11 0 PULSECO 5 31NS 2NS :!NS :!ONS 56. SONS) .' .TRAN 1NS 113H5 ,. r .PL.OT TRAN V(5) V(7) V(2~) lao

; ..

l V(5) + V(7) ')(24 ) X TIME V(5)

(~.)------0.000.+00 2.000.+00 ••000.+00· ------...... , .... - .. ------<+)------0.000.+00 ::.000.-01 4.000.-01 ------~ - - 0.000.+00 ~.OOOe+OO ------+. X 1.000.-09 ~.OOOe+OO +. X :.000.-0' 5.000.+00 +. X 3.000.-09 ~.OOOe+OO +. X 4.~00.-09 5.000e+00 +. X ~.OOO.-O' 5.000e.00 +. X 6.000.-0' 5.000.+00 X '.000-.-0' 5.000.+00 •• X 9.000.-0' 5.000e+00 •• X '.000.-~9· 5.000e+00 ••+. X 1.000.-08 5.000.+00 X 1.100.-08 5.000..+00 ••+. X 1.~00e-08 5.000.+00 +. X 1.300.-08 ~.OOO.+OO +. X 1.~00.-08 5.000.+00 +. X 1.~00.-08 :.000.+00 +. x 1.600.-08 5.000.+00 +. X 1.700.-08 ~.OOO.+OO +. x .... 1.800.-08 5.000~+00 +• X 1.900.-08 5.000.+00 +. X ~.OOO.-08 5.000.+00 +. X :.100.-08 5.000.+00 +. X :.:"0.-08 5.000.+00 +. X :.300.-08 ~.OOO.+OO +. x 5.000.+00 +. X ;~~~::~: ~.OOO.+OO +. x :.600.-08 .5.000.+00 +. X :.700.-08 5.000••00 +. X :.800.-08 5.000.+00 +. X :."00.-08 :".000.+00 +. x 3.000.-08 5.000••00 .. X 3.100.-08 5.000e+00 +. X X 3.:00.-08 :i.OOO.+OO +. ~" ~.300.-08 5.000e+00 +. X 3.400.-08 4.900.+00 +. X 3.:00.-08 ~.55"e+OO +. .a 3.600.-08 4.053.+00 X.a 3.700.-08 3.4".+00 . a +. 3.800.-08 :.767.+00 +• 3.900.-09 :.060.+00 . .a • +. 4.000.-08 1.37'.+00 . +. ~.100.-0e· '.0'8e-01 -a * f. 4.200.-08 6.313.-01 •* ".300.-08 5.134.-01 X ••+. 4.4000-08 ...6ge.-01 x •• ...SOO.-08 ...4t23.-01 -a .. ".000.-08 4.30S.-01 X +. 4.700.-08 4t,Z36.-01 X +. ,;/ ....oo.-OS ",180.-01 X +. ".,oo.-OS ".13S.-01 X +. .. ,.OOO.-OS ~.0'7e-Ol X •• '.100.-0S 4.062.-01 . X +. .... '-...,." .,.., ...... _~ ~.200.-08 4.033.-01 .- X +. ~.300.-08 ".OOS.-Ol X +. ~.400.-08 3."\.-01 X : ~.~00.-O8 .. 3.'8~.-Ol X +. '.000.-08 3." ...-01 X +. 5.700.-08 3.'S".-01 X +. 5.800.-08 3.'83.-01 X +. ~.900.-08 3.983e-01 X 0.000.-08 3.983.-01 X +.•• 6.100.-08 3.983.-01 X +. 6.:00.-0S 3.983.-01 X +. ••300.-0S 3.983.-01 X +. 6.400.-08 3.983.-01 X +. ,.~OO.-OS 3.9S3e-01 X +. 6.000.-08 3.'83.-01 X +. '.700.-08 3.983.-01 X -.. 6.800e-08 3.983.-01 X" f. 101

H1 4 5 5 J MU~2 L-20.0U w-s.uu "2 4 6 6 3 HO~2 L-20.0U W-S.OU "3 ~ 7 7 3 110D2 L-20.0U Y-S.OU "~ ~ 8 8 3 "002 L-20.0U Y-s.OU "~ 10 11 6 '.MODl L-S.OU W-S.OU "6 12 13 8 , HOOl L-~.OU w·~.OU "7 ~ 1~ 1~ 3 11002 L-20.0U W-5.0U 118 4 15 15 3 HOD2 L-20.0U ,,·~.OU "' 7 16 17 9 110Dl L-S.OU yulO.OU 1110 S 14 0 9 HODl L-S.OU Y-S.OU H11 ~ 16 16 3 MOD2 l-20.0U W-S.OU H12· 1~ 1618 9 110Dl L-~.OU W-I0.0U 1113 8 l' 20 , HODl L-~.OU W-I0.0U 111~ 14 l' 0 9 11001 l-S.OU W-S.Ou H1S 17 l' 0 9 HODl L-S.OU W-I0.0U 1116 18 21 0 9 HODl L-S.OU W-I0.0U H17 16 21 22 , HOOl L-5.0U W-I0.0U H18 S 10 0 9 HODI L-~.OU ~~-10.0U J H19 6 12 0 , HODI L-S.OU "-10.0U H20 20 15 0 , HODI L-S.OU W-I0.0U 1121 1~ 15 0 , HOOl laS.OU W-5.0U 1122 11 IS 0 , HOOI LaS.OU W-I0.0U 1123 19 23 0 , HOOI LaS.OU W-I0.0U H24 22 23 0 , 11001 l-S.OU W-I0.0U H25 19 l' 3 "002 L-20.0U W-S.OU 1126 4 2~ 24 3 "OD2 L-20.0U W-5.0U 1127 ~ 2S 25 3 "OD2 L-20.0U W-5.0U H28 ~ 26 26 3 11002 L-20.0U w-s.OU H29 ~ 27 21 3'HOb2 l-20.0U "-5.0U HJO 28 11 25 , HO~l L-s.aU w-S.OU J 1131 29 13 26 9 HODl L-s.aU "-S.OU ' I1J2 ~ JO JO J HOD2 l-20.0U W-S.OU M33 4 31 31 3 HOD2 L-20.0U W-5.0U H3~ 26 30 0 , HODl L-S.OU W-S.Ou H3~ 19 27 32 , HODI L-5.0U W-I0.0U H36 27 31 0 , HODl L-S.OU W-S.OU- H37 26 21 33 9 HODl LaS.OY W-I0.0U 1138 19 3~ 35 , HOOl L-S.OU W-I0.0U "39 21 3~ 36 9 HODl L-5.0U W-I0.0U H~O 30 21 0 9 HODl L-S.CU W-S.OU 1141 31 34 0 9 HODI L-S.OU W-S.OU H42 35 31 0 , HODl L-s.au "-10.0U 1143 24 28 0 , HOOl L-S.OU "-10.0U 1144 2S 29 0 , HODl L-S.GU "-10.0U. 114S 33 38 0 , MODI L-~.OU W-l0.0U H46 30 38 0 9 HODl L-5.aU W-5.0U H~1 32 38 0 , MODI L-S.OU "-10.0U 11~8 36 J1 0 , HODl L-S.OU W-l0.0U 114' 31 31 0 , HODl L-5.~U "-5.0U CSO 38 0 O.OSSPF CSl ~ 0 O.6S3PF CS2 29 0 o.06spr CS3 280 O.060PF CS.a\ 31. 0 O. 087F'F C5S 30 0 O.081PF C56 2~ 0 O.08JPF CS1 2~ 0 0.079PF C58 27 0 O.lJ6PF C59 l' 0 O.18SPF C60' 26 0 O.06SF'F C61 15 0 O.123PF C62 12 0 0.06SPF C6J 10 0 0.065PF C6~ 18 0 O.OSSPF C65 11'0 0.064PF C66 14 0 0.081'F C61 6 0 O.083PF C68 5 0 0.019PF C69 16 0 Or08~PF C70 8 0 0.06SPF C11 7 0 O.016PF .MObEl HOD1 NHOS(VTO-l.0) .HODEL "002 ""OS(VTO--4.0) VOO 4 0 DC S . VOA 34 0 DC S . VGS 37 0 ~C 0 vot 38 O~OC 0 VGb 21 0 DC 0 VGE 23 0 DC 0 VGF 13 0 PUL5[

;, d _'~i.~' .. ~, .. " 'LEGEND. ; ·.)~~~~I • ,ii~~i • .: ~ '. .t U(S) ~;' .: +1 U(7) -: U(24) ( TIHE V(S) 04.000.,+00 :!.OOO.,+OO :*)------0.000.+00 ------4.000.-01 :Z .000.-01 :+)------0.000.,+00 ------.: ------,.000.+00 4.000.+00 2.000.+00 ;-)------+ • • ~.OOO.+OO +. a 0.000.+00 ' ~.OOO_+OO . +. t 1.000.-0' a 2.000.-0' ~.OOO.+OO +• 5.000.+00 +. t 3.000.-0' t 5.000.+00 +. 04.000.-0' +. t ~.OOO.-O' 5.000.+00 a ,.000.-0' . 5.000.+00 -, +. 7.000.-0' ~.OOO_+OO +• * s.ooo.-o, ~.OOO_+OO +• * , 5.000.,+00 +• t '.000.-0' t 1.000.-08 ~.000.+00 +•. I a 1.100.-08 s.ooo.+oo ,- +. a 1.200.-08 5.000_+00 +. 1.300.-08 5.000.+00 +• +. ..* 1.400.-08 5.000_+00 1.S00_-08 5.000.+00 +. • 1.600.-08 5.000_+00 +. • 1.100.-08 s.OOO.,+oo +• +. *a 1.800.-09 . S.ooo.+OO +. t 1.900.-08 5.000.,+00 a s.ooo.+oo +. 2.000.-08 t 2.100.-08 5.000.+00 i. +. 2.:00.-08 . 5.000.+00 t* 5.000.+00 i. 2.300.-08- +. a 2."00_-08 5.000.+00 2.500.-08 5.000.+00 + • • +. t 2.600,,-08 5.000.+00 t: +. t 2.700.-08 5.000.+00 5.000.,+00 +•. ---._---* 2.900.-08 ------._---- t S.OOOe+OO +. 2.900.-08 ... --"'_I"" ...... 3.000.-08 s.oou.,~ou +. a 3.100.-08 S.ooo.,+oo i. t 3.200.-08 5.000.+00 .... a 3.300.-08 5.000.+00 i. : 3.JtOO.-08 04.'00.,+00 ;; * 4.S~2.+00 + • 3.500."08 i •• 3.600.,-08 4.0Jt'.+00 + • 3.462e+00 3.700.-08 . + • . 3.800.-08 2.767e+00 * +-. 3.900.-08 2.060e+00 •• +. 4.000.-08 1.380e+00 +• 4.100.-08 9.1042.,-01 * +• 4.200.,-08 6.332e-Ol ): +. 04.300.-08 5.162.-01 * ... . 4.400.-08 04.702_-01 * . +. 04.S00.-08 •• 41'.-01 * . +. 4.600.-08 4.301.-01 * +. 4.700.-08 04.234.-01 • +. 4.800e-08 4.180.,~01 • +-. 04.'00e-08 4.1304e-Ol • i. S.OOOe-OS 4.0'&.,-01 f. S.100e-OS 04.061e-Ol • • + " 5.200e-08 04.032e-Ol • f. 5.300.-08 04.004.-01 • f. 5.400.-00 . 3. "Oe-01 • * +. s.~OO.-OS 3"85.-01 • +. ,.600e-OS 3.'84.-01 * +. 5.700.-08 3"83.-01 • f. S.SOOe-OS 3.'83e-Ol' f. s.'OO.~OB 3.'83.-01 * I • , I f. 6.000.-08 3.'S3.-01 f. 3.'S3.-01 * 6.100.-08 • ~ . 6.200.-08 3.983.-0t • 103

"1 S 5 3 "002 La20.0U W-S.OU H2 6 6 3 HOD2 La 2 0 . 0 U w-s.ou H3 7 7 3 "002 La20.0U w-S.OU "~ ~ a 8 3 "OD2 La20.0U WaS.OU "S 10 11 6 9 HOOl LaS.OU W*S.OU H6 12 13 8 9 HODl L.~.OU W*~.OU M7 ~ 1~ 1. 3 "002 La20.0U WaS.OU M8 4 15 15 3 M002 La20.0U WaS.OU M9 7 16 17 9 HODl L=S.OU W-I0.0U H10 S 14 0 9 HODl L=S.OU W=~.OU Ml1 ~ 16 16 ~ "OD2 L=20.0U WaS.OU H12 15 16 18 9 MODl LaS.OU WalO.OU H13 8 19 ZO 9 HODl LaS.OU WalO.OU M14 14 19 0 9 MODl LaS.OU W-S.OU H15 l' 19 0 9 HODl LaS.OU W-lO.OU M16 18 21 0 9 HOOl La~.OU YalO.OU H11 16 21 2~ 9 HOOl LaS.OU WalO.OU H18 S 10 0 9 HODl LaS.OU WalO.OU M19 0 12 0 9 HODl L=S.OU Wal0.0U M20 :0 15 0 9 MODl LaS.OU WalO.OU M21 14 15 0 9 HODl LaS.OU WaS.OU H~~ 17 15 0 9 MOOl LaS.OU Wal0.0U H23 18 23 0 9 HOOl LaS.OU W-IO.OU H24 ~~ 23 0 9 HOOl LaS.OU W-lO.OU H2S 4 19 19 3 H002 La20.0U WeS.OU "26 4 ~4 24 3 "002 La20.0U w=s.OU M21 4 2S 2S 3 HOD2 L-20.0U WaS.OU M2S ~ 26 26 3 "002 LaZO.OU W=S.OU H29 4 27 21 3 HOD2 LaZO.OU WaS.OU H30 29 11 2S 9 HODl LaS.OU WaS.OU M31 29 13 26 9 MODl LaS.OU WaS.OU ~2 4 30 30 3 "002 La20.0U WaS.OU M33 • 31 31 3 "OD2 La20.0U WaS.OU H34 26 30 0 9 HODl LaS.OU WaS.OU M3S 19 21 32 9 HODl LaS.OU WalO.OU M36 21 31 0 9 HODl L=S.OU WaS.OU H31 26 27 33 9 HODl LaS.OU W-lO.OU M39 19 3~ 3S 9 HODl LaS.OU Wal0.0U H39 27 34 36 9 HODl LaS.OU WalO.OU M40 30 27 0 9 HOOl LaS.OU WaS.OU K41 31 34 0 9 HODl L-S.OU W-5.0U M42 35 37 0 9 MODI laS.OU WaIO.OU H43 2~ 28 0 9 HODl L-5.0U WalO.OU H44 25 29 0 9 HOOl LsS.OU W-l0.0U H4~ 33 38 0 9 MOOl LaS.OU W-l0.0U H46 30 38 0 9 MODl L~.OU w-s.OU H47 32 38 0 9 MODl L-~.OU W-l0.0U H4S 30 37 0 9 HOOl L-5.0U WalO.OU "49 31 37 0 9 HODl LaS.OU WaS.OU CSO 38 0 O.05SPF CSl 4 0 0.6S3PF C52 29 0 O.06SPF C53 28 0 0.060Pf C54 31 0 O.oe'PF CSS 30 0 O.OS'PF CS6 2~ 0 0.OB3PF cr~ 24 0 O.O"PF CSB 27 0 O.136PF CS9 19 0 O.18SPF CoO 26 0 O.065PF Col.iS 0 O.123PF C02 12 0 O.065PF Co3 10 0 O.065Pf C04 18 0 O.055PF CoS l' 0 O.064PF Coo 14 0 O.087PF C07 6 0 O.083Pf CoS 5 0 O.079PF C69 16 0 0.oe4PF C10 S 0 O.OoSPf C11 7 0 0.O'6PF .MODEL MODl HMOS(VTO-l.O) .HODEL "002 HMOS(VTO--3.0) t VDO ~ 0 DC 5 VGA 34 0 OC S VGB 37 0 DC 5 VGC 38 0 DC 0 VGD 21 0 DC 0 VGE 23 0 OC 0 104

,*: V(S) +: V( 7) =t V(2'"

TIME V(~) <*)------2.000.+00 4.000.+00 6.000.+00 8. .. - .. .. - ~ .; c+)------1.000.-01 2.000.,-01 3.000.,-01 4. ------...... ------~.)---~------0.000.,+00 2.000.+00 4.000.+00 6. 0.000.,+00 5.000.+00 + 1.000e-09 5.000.+00 * + 2.000.-09 5.000.+00 * + 3.000e-09 5.000.+00 * + · 4.000.-09 5.000.+00 * + 5.000.-09 ~.OOO.,+OO • + 6.000.-09 5.000.,+00 * + 7.000e-09 5.000.+00 • + 8.000.-09 5.000.,+00 * + 9.000,,-09 5.000.+00 * + 1.000.,-08 5.000.,+00 * + 1.100.,-08 5.000.,+00 • + • 1.200e-08 5.000.+00 • + 1.300,,-08 5.000.. +00 • + 1.400,,-08 5.000.,+00 • + 1.500,,-08 5.000e+00 • + 1.600e-08 5.000.,+00 • + .. 1.700,,-08 5.000.,+00 • + * + 1.800.,-08 5.000e+00 * 1.900e-08 5.000.+00 • + 2.000.,-08 5.000.,+00 • + 2.100e-08 5.000.,+00 + t: 2.:!00.-OS 5.000e+00 • + 2.300.,-08 5.000.+00 * + 2.400.-08 5.000.+00 * + .•' 2.500.-08 5.000.,+00 • + 2.600e-08 5.000.,+00 * + 2.700.,-08 5.000.,+00 * + 2.800.,-08 5.000.+00 • + 2.900.-08 5.000.+00 * + 3.000e-08 5.000.,+00 * + 3.100e-08 5.000.,+00 * .. + 3.200e-08 5.000.+00 * + 3.300.,-08 ~.OOO.+OO * + * 3.400.-08 5.000.,+00 + · 3.500.-08 5.000.,+00 *• + 3.000,,-08 5.000.+00 +-.· 3.700,,-08 5.000.,+00 * + 3.800.,-08 5.000.,+00 • + 3.900e-08 5.000.+00 * + 4.000.,-08 5.000.+00 ..* + 4.100.,-08 5.000.+00 + 4.200.,-08 5.000.+00 • + 4.300.-08 5.000.+00 • + 4.400e-08 5.000.+00 "0' + .. 4.500e-08 5.000.+00 • + 4.000.-08 5.000.,+00 • + 4.700e-08 5.000.,+00 * + 4.800.-08 5.000.+00 * + 4.900e-08 5.000.+00 * + 5.000.,-08 5.000.+00 * + 5.100.,-08 5.000.+00 • + 5.200.,-08 5.000.+00 * + 5.300.-08 5.000.+00 * + 5.400.,-08 5.000.+00 • + 5.500.-08 5.000.,+00 * + 5.600.-08 5.000.,+00 * + 5.700.,-08 5.000.,+00 • + 5.800"-08 5.000.+00 • + 5.900.-08 5.000.,+00 • + 6.000.-08 s /OOOe+OO • + 6.100e-08 5.000.,+00 *• + 6.200,,-08 5.000.,+00 • + 0.300.,-08 5.000.,+00 • + 6.400e-08 5.000.+00 • + 105

- - .... -- _ --'..----~.' ..~ -...... -,

"2 6 6 3 "002 L-20.0U W-~.OU "3 7 7 3 H002 L-20.0U W-5.0U "~ ~ a 8 3 H002 L-20.0U w-s.OU "S 10 11 6 , HODl L-S.OU w-s.OU "6 12 13 8 9 HOOI L-S.OU w-s.OU "7 ~ 1~ 1~ 3 "002 L-20.0U W-5.0U "8 • 15 15 3 "002 L-20.0U W-5.0U H' 1 16 17 , HODl L-S.OU W-I0.0U H10 a 1~ 0 9 HOOl L-S.OU W-S.ou Hl1 ~ 16 16 3 H002 L-20.0U w-~.ou H12- 15 16 18 9 HODl L-~.OU W-lO.OU H13 8 19 20 9 HOOl L-S.OU W-I0.0U H1~ 1~ 19 0 9 HODl L-S.OU w-s.ou H15 17 19 0 9 HODI L-S.OU W-I0.0U H16 18 21 0 , HOOI L-S.OU W-IO.OU H17 16 21 2: , HOOl L-S.OU W-IO.OU H18 5 10 0 9 HOOl LaS.OU W-I0.0U -Hl' 6 12 0 9 HOOl L-S.OU W-IO.OU \ H20 20 1~ 0 , HOOI L-S.OU W-lO.OU . H21 1. 15 0 , HODl L-5.0U W-S.OU H22 17 15 0 9 HOOl L-~.OU-W-I0.0U H23 18 23 0 , HOOl L~5.0U W-IO.OU H2~ 22 23 0 , HODI L-S.OU W-I0.0U H25 ~ l' l' 3 H002 L-20.0U W-S.OU H26 • 2~ 2~ 3 "OD2 L-20.0U W-5.0U "27 ~ 25 25 3 "002 L-20.0U W-~.OU H28 4 26 26 3 "002 L-20.0U w-s.ou H29 4 27 27 3 H002 L-20.0U w-S.ou H30 28 11 25 9 MODI L-S.OU w-s.ou "31 29 13 26 9 HOOl L-5.0U w-S.OU "32 ~ 30 30 3 H002 L-20.0U w-s.ou "33 ~ 31 31 3 H002 L-20.0U w-s.OU H3~ 26 30 0 , HOOl L-S.OU w-s.OU H35 19 27 32 , HOOl L-S.OU W-lO.OU H36 27 31 0 , HOOl L-S.OU w-s.OU "37 26 27 33 9 HOol L-S.OU W-lO.OU H38 19 34 3S 9 HOOI LaS.OU w-lO.OU "39 27 34 36-' HOOl L-S.OU W-IO.OU ".0 30270' "001 L-S.OU w-s.ou I ".1 31 34 0 , HOOI L-S.OU w-s.OU H~2 35 37 0 , HODl L-S.OU W-IO.OU H~3 24 28 0 , HOOl LaS.OU W-IO.OU H•• 2S 2' 0 , HODl L-S.OU W-I0.0U "~S 33 38 0 , HODI L-S.OU W-IO.OU H.6 30 38 0 , HOOl L-S.OU w-s.OU ".7 32 38 0 9 HODl L-S.OU W-IO.OU H~8 30 37 0 , HODl L-S.OU W-lO.OU H.9 31 37 0 , HOOI L-S.OU WaS.OU CSO 38 0 0.OS5PF CS1 4 0 O.6S3PF C52 29 0 0.06SPF CS3 28 0 0.060PF CS~ 31 0 0.087PF CSS 30 0 O.08?PF C~6 2~ 0 0.083PF CS7 24 0 O.079PF Cs8 27 0 0.136PF CS' l' 0 O.18SPF CoO 26 0 O.06SPF C61 1S 0 O.123PF C62 12 0 O.06SPF C63 10 0 0.06SPF C6. 18 0 O.05SPF C6S 17 0 O.06.PF C66 1. 0 O.087PF C67 6 0 0.OB3PF C6B 5 0 0.07'PF C6' 16 0 0.08~P~ C10 8 0 O.06~PF \ :~~D~LOH~D~7~~~S(VTO_l.0j .' '."ODEl "OD2 H"aS(VTO·-~.O) VDD • 0 DC S VGA 3. 0 DC 5 VGB 31 0 DC' 5- VGC 38 0 DC 5 VGO 21 0 DC 0 VOE 23 0 DC 0 - 'JOF 13 0 PULSE(O 5 2NS 2NS 2NS 20NS S6.~ONS) vnr. ~ ~ f"I C"" e l:" t f"I til: "r 1 ~ e ., ",e ...~, e 'HH.fe tII:.c. _lIl';" ~ e , 106

~ f~,...... :.....-..~- ...... , _ .. __ •..4 •

* V(5) + V(7) V(~~) x TIME V(5)

~1 ~ ~ 3 "002 L=20.0U W-~.OU ~2 0 6 3 HOD2 L.20.0U W·~.OU "3 7' 3 "002 L.20.0U W-S.OU H~ ~ 8 8 3 HOD2 L·20.0U w·S.OU H~ 10 11 6 9 HODl L-~.OU W-S~OU H6 12 13 8 9 HODl L-S.OU W·S.OU "7 ~ 1~ 1~ 3 "002 L.20.0U WaS'OU H8 ~ 1~ 1~ 3 "002 L-20.0U W-S.OU H9 7 16 17 9 HODl LaS.OU W-I0.0U H10 8 1~ 0 9 HOOl Las.OU WaS.OU Hl1 ~ 16 16 3 H002 L-20.0U WaS.OU H12 1S 16 18 9 HOOl l-S.OU WalO.OU H13 8 19 20 9 HODl L-S.OU W·lO.OU H14 14 19 0 9 HOOl las.OU Was.OU "1~ 17 19 0 9 HODl l=~.OU W=10.0U H16 18 21 0 9 HOOl L.s.OU Wal0.0U H17 16 21 22 9 HOOl LaS.OU W-IO.OU HiS S 10 0 9 HOOl L=s.OU WalO.OU H19 6 12 0 9 HOOl L-S.OU WalO.OU H20 20 15 0 9 HODl L.s.OU W-lO.OU H21 1~ 15 0 9 HODl L-5.0U W-S.OU H~~ 17 15 0 9 HODl L=S.OU WalO.aU H23 18 23 0 9 HODl L-S.OU W·IO.OU "24 22 23 0 9 HOOl L.S.OU W-lO.OU H2S 4 19 19 3 HOD2 L-20.0U WaS.OU H26 4 24 24 3 H002 L-20.0U WaS.OU H27 4 25 25 3 HOD2 L-20.0U w-S.OU H28 4 26 26 3 H002 L-20.0U w=S.OU H29 ~ 27 27 3 HOD2 L-20.0U w-S.OU HJO 28 11 25 9 ~001 L=S.OU WaS.OU H31 29 13 26 9 HOOl LaS.OU WaS.OU H32 4 30 30 3 H002 L=20.0U w.S.OU H33 -4 31 31 3 HOD2 La20.0U WaS.OU H34 26 30 0 9 HOOl LaS.OU WaS.OU· H3S 19 27 32 9 HODl LaS.OU WalO.OU H36 27 31 0 9 HODl LaS.OU WaS.OU "37 26 27 33 9 HODl LaS.OU W-I0.0U H38 19 34 3S 9 HOOl L=S.OU W-lO.OU M39 27 34 36 9 HODl L-S.OU WalO.OU "40 30 27 0 9 HOOl LaS.OU WaS.OU H~l 31 3~ 0 9 HOOl L-S.OU W=S.OU H42 35 37 0 9 HOOl L.s.OU WalO.OU "43 2~ 28 0 9 HOOl LaS.OU Wa l 0 . 0U H44 2S 29 0 9 HODl L-S.OU WalO.OU H4S 33 38 0 9 HODl L-S.OU W·I0.0U H46 30 38 0 9 HODl L-S.OU WaS.OU· H47 32 38 0 9 HODl L=S.OU W=10.0U H~8 36 37 0 9 HODl Las.OU W=10.0U H~9 31 37 0 9 HODl LaS.OU WaS.OU CSO 38 0 O.O~~PF CS1 ~ 0 O.6S3PF CS2 29 0 O.065PF CS3 28 0 O.060PF C~4 31 0 O.087PF CS5 30 0 O.087F'F eS6 25 0 0.083PF ", CSi 2~ 0 O.079F'F CS8 27 0 O.136PF CS9 19 0 O.18SPF C60 26 0 0.06SPF Col lS 0 O.123PF Co2 12 0 O.06SPF C63 10 0 O.Oo5PF C6~ 18 0 O.OS5PF C6S 17 0 O.OI>4PF C66 1~ 0 O.087PF C07 I> 0 o.oa3P':'- C6S 5 0 O.079PF C09 16 0 o.oe~PF C70 8 0 O.06SPF' C71 7 0 O.076PF' .HODEL HODl NHoseVTO-l.0) .HODEL MOD2 NHOS(V10--~.O) VOD 4 0 DC S VGA 3~ 0 DC S VGB 37 0 DC 5 VGC 38 0 DC 5 vao 21 0 DC 5 VGE 23 0 DC 0 108

OLEGENO: *: V(5) + : V(7) a: V(24) X TIME V(5) (.)------0.000.+00 2.000.+00 4.000.+00 6.0< (+-)------6.000.+00 0.000.+00 5.000.+00 x * 1.000.-09 5.000.+00 x 2.000.-09 5.000.+00 x * 3.000.-09 5.000.+00 x * 4.000.-09 5.000e+00 x * 5.000.-09 5.000.+00 x * 6.000.-09 5.000.+00 x 7.000e-09 5.000.+00 x *a 8.000e-09 5.000.+00 x 9.000e-09 5.000e+00 x * 1.000e-08 5.000.+00 x * 1.100e-08 5.000.+00 x * 1.200e-08 5.000.+00 x 1.300e-08 5.000.+00 x *a 1.400.-08 5.000.+00 x 1.500e-08 5.000.+00 x *a 1.600.-08 5.000.+00 x a 1.700.-08 5.000.+00 x 1.800.-08 5.000.+00 x * 1.900.-08 5.000e+00 x *a 2.000.-08 5.000.+00 x a 2.100.-08 5.00-0.+00 x 2.200.-08 5.000.+00 x * 2.300e-08 5.000e+00 x *a 2.400e-08 5.000.+00 x 2.500e-08 5.000.+00 x * 2.600e-08 5.000.+00 .X * 2.700.-08 5.000e+00 x * 2.800e-08 5.000.+00 x * 2.900e-08 5.000.+00 x * 3.000e-08 5.000.+00 x a* 3.100.-08 5.000e+00 -x­ -~------~-_. 3.200.-08 5.000.+00 x 3.300e-08 5.000.+00 x * 3.400.-08 4.901.+00 x * 3.500.-08 4.554e+00 x * 3.600e-08 4.052e+00 x .a * 3.700e-08 3.467.+00 x 3.800.-08 2.770e+00 * x 3.900.-08 2.063e+00 .. x 4.000e-08 1.382e+00 x 4.100e-08 9.152.-01 * x 4.200.-08 6.338.-01 x 4.300e-08 5.161.-01 * x 4.400e-08 4.703e-Ol ~ x 4.S00e-08 4.419.-01 x 4.600.-08 4.301.-01 * x 4.700e-08 4.235e-Ol * x 4.800e-08 4.180e-01 x 4.900.-08 4.134.-01 * x 5.000e-08 4.091.-01 * x 5.100.-08 4.061.-01 - * x 5.200e-08 4.033.-01 x 5.300.-08 4.004.-01 * x 5.400.-08 3.991.-01 * x 5.500.-08 3.985e-01 .. * x 5.600.-08 3.984.-01 * x 5.700e-08 3.984.-01 * x 5.800.-08 3.983e-Ol * x 5.900.-08 3.983.-01 * x 6.000.-08 3.983.-01 * x 6.100.-08 3.983.-01 x 6.200.-08 3.983.-01 a* x 6.300.-08 3.983.-01 * x 6.400e-08 3.983.-01 a x 6.500.-08 3.983.-01 x 6.600e-08 3.983.-01 * x 6.700e-08 3.983.-01 *I x 109

"1 ~ ~ J hUU~ L-~O.OU W-5.0U K~ 6 6.3 HOD~ L-20.0U ,,-~.OU KJ 1 7 3 HOO~ L-20.0U w-~.OU ,. "~ ~ s a 3 "002 L-20.0U "-3.0U "5 10 11 , , MODl L-S.OU "-5.0U "6 1: 13 B , MODI L-S.OU Y-S.ou "7 ~ 'l~ 1~ 3 MOO~ L-:O.OU ",-s.OU H8 ~ 15 15 3 HOD2 L-:O.OU ~-5.0U "' 7 16 17 9 HODl L-5.0U "-10.0U H10 8 l~ 0 , HODl L-S.OU "-S.ou Hl1 ~ 16 16 3 H002 L-20.0U w-S.OU H12 15 16 18 , MODl LaS.OU W-l0.0U· "13 a l' 20 , HODl L-S.OU W-IO.OU ."1~ 1~ l' 0 9 HOOl L-S.OU w-s.OU K15 17 19 0 9 HODi L-S.OU W-lO.OU H16 18 21 0 , HODl L-S.OU W-IO.OU H17 16 21 ~~ 9 HODl LaS.OU W-10.0U H18 5 10 0 , HODl L-S.OU "-10.0U "19 , 12 0 9 HODl L-5.0U W-lO.OU "20 20 15 0 , HODl L-S.OU "-10.0U . "21 1~ 15 0 , MODl L-'.OU W-5.0U K~~ l' 15 0 , HOOl L-S.OU W-IO.OU "23 18 23 0 9 MODl L-S.OU W-I0.0U H2~ ~~ 23 0 ~ HOOl L-S.OU W-10.0U H25 ~ 19 19 3 MOD2 L-20.0U W-5.0U H26 ~ 2~ 2~ 3 MOD2 L-ZO.OU W-S.OU H~7 ~ 25 25 3 MOD2 L-20.0U "-5.0U M28 4 2~ 26 3 HOD2 L-ZO.OU W-5.0U H2' • 21 2? 3 MOD2 L-20.0U w-,.OU H30 ~8 11 25 , HODl L-5.0U "-5.0U· .H31 2' 13 26 , MOOl L-S.OU W-'.OU H32 4 30 30 3 MOD2 L-20.0U ~-S.OU "33 • 31 31 3 "002 L-20.0U "-5.0U "34 26 30 0 , HODI L-5~OU Y-5.0U "35 19 27 32 9 HODl L-S.OU W-I0.0U "36 27 31 0 , KaDl L-S.OU "-S.ou H37 2' 21 33 , HOOl L-S.OU W-IO.OU H38 19 3~ 35 , HOOl L-S.OU W-IO.OU "39 21 3~ 3' 9 MODl L-5.0U W-IO.OU "~O 30 21 0 , HODl L-S.OU W-5.0U "41' 31 34 0 , HODl L-'.OU "-S.OU "42 35 3' 0 , KODt L-'.OU "-10.0U "~3 2~ 28 0 , HODl L-S.OU Y-IO.OU ".~ 25 29 0 , HODl L-S.OU W-lO.OU "~S 33 38 0 9 HODl L-'.OU W-10~OU "~6 30 38 0 , HODl L-S.OU "-5.0U H.' 32 38 0 , HODl L-'.OU W-I0.0U "~8 3' 31 0 , HODl L-S.OU "-10.0U H~9 31 37 0,' HODl L-S.OU "-S.OU . CSO 38 0 0.OS5PF 1.~~;~_;'~.9~9~~~;~f____ ,-,., ~~..a-"" CS3 28 0 O.O'OPF CSt{ 31 0 0.08'PF C5~ 30 0 o.oe?PF CS6 2~ 0 O.083PF C~? 24 0 0.07'PF C58 21 0 O.136PF C5' l' 0 O.18~PF C60 2' 0 O.O'~PF Col 1S 0 0.123PF C.2 12 0 O.06SPF C.3 10 0 0.0.5PF C~~ 18 0 o.O~SPF' C'S 11 0 O.O'~PF C•• 14 0 0.087PF C., • 0 0.083PF c,. 5 0 0.0'.'" c., 1. 0 O.08~PF C70 8 0 o.O'~P' C71 , 0 0.076PF' .MODEL. ,.onl N"OSeVTo-t".O) .KODEL "002 HKOS(VTO--~.O) VDO 4 0 DC S . vOA 34 ° DC 5 'lOB 3' 0 DC S vse 38 0 DC S VGn 21 0 DC'S VOE 23 0 DC·S VOF ·13 0 PUL.SE(O S 2MS 2MS 2NS 20M5 S&.50NS) VGO 11 0 PULSE(~ ~ 3tNS 2HS ~NS 20N9 5~.50HSl 110

OL,£G£HD: , ~: \I(~) o( c +: V(7) t -: V(24' i X . ~ TIl'l£ \1(5) . :.000.+00 4.000....00 '.000...: (1+-)------~ 0.000."'00 '.000."'00 X i 1.000.-0' 5.000....00 X- I :.000.-0' ·5.000.... 00 X [. 3.000.-1)' $.000••00 X 4.000.-0' $.000••00 X S.OOO.-O' S.OOO.+OO X 6.000.-0' 5.000.... 00 X 7.000.-0' 5.000.+00 X 8.000.-0' 5.000.... 00 X '.000.-0' '.OOOe+OO X 1.000.-01 5.000.-+00 X 1.100.-01 $.OOOe.OO X 1.:00.-08 5.000.... 00 •X 1.JOO.-OI $.000.+00 X 1.'-00.-01 '.OOOe.OO X 1.~00.-01 S.OOO....OO X 1 ••00.-08 .5.00~."'00 X 1.700.-08 S.OOO.+OO X 1.800.-08 '.000••00 X 1.900.-0. 5.000....00 X :.000.-08 S.OOO.-+OO X ~.100.-0' S.OOO.+OO· ·X ~.200.-08 '.0"00.+00 X :.JOO.-08 '.000.+00 X· 2.400.-0. 5.000••00 X :.~OO.-O' · '.000.+00 X : ••00.-01 $.000.+00 X 2.100.-01 5.000.+00 X • :.800.-01 5.000.+00 oX • 2.'00.-08 5.000••00 X 3.000.-01 $.000.+00 X 3.100.-08 $.000.+00 X 0- 3.:00.-01 ,.000.+00 X 3.300.-08 •. _ , .000.... 00 X 3'''00.-08 5.000••00 ~, 3.:500.-08 S.OOO.+OO X 3 ••00.-01 $.000.... 00 X i' 3.700.-08 $.000.+00 X 3.800.-08 5.000."'00 X 3.900.-08 5.000.+00 X' 4.000.-08 5.000.... 00 X 4.100.-08 '5.000.+00 X • 4.:00.-0. 5.000.+00 X 4.300.-0' $.000.+00 X 4.400.-01 · ,.000.+00 1 '4.S00e-01 ,.000.+00 1 4••00.-01 ,.000.+00 .1 ...700.-01 $.000.+00 X 4.800.-08 ,.000....00 .X .4.'00.-01 5.000••00 X ,.000e-01 $.000....00 X 5.100.-01 .5.000.+00 X ...... -.-. : ... .",- '.200.-01 S.OOO.+OO 1 X 5.JOO.-OI 5.000.+00 o- ... ,.400..-01 5.000.+00 X .. $.SOOe-OI 5.000.+00 X ,.'OOe-01 5.000••00 I '.700.-01 ,.000.+00 I ... ' S.IOO.-O' 5.000e+00 X .. 5.'00.-0. 5.000.+00 . X 6.000....0. 5.000e"'00 'X 6.100e-Ot 5.000.+00 ., X '.200.-01 5.000.+00 .- X '.JOO.-OI 5.000....00 X '.400....0. 5.000.... 00 Ox ,.~OOe-OI '5. OOOe.OO.. X '.600e-01 · .s.OOOe+OO X '.700.-0' 5.000.+00 X 6.800.-08 5.000.+00 X o. 111

..±

Dept. of E'~ctrica' and Computar Engineering CHIO

oI MEN SI o:·~ H( 1 '! ) , S( 11 ) ,R ( l'J 2 )., X{'Z0 2 } , y ( 2o2 ) , 6U;: ( 5C'j0 ) ~C~OOOlO OAT~ H IO.02734375,O.0039J~25.-0.01~53125,-O.~3515&25,-~.031Z5, ?C~00020 ~. O.015025,O.03125,Q.OS46B75,O.O~25,O.OloS3125,-O.03906Z;, PC~~00030 ~ -O.lO~375,-O.12109375,-O.J546875,O.J9375,O.312:,O.50,a.625/ PC~~00040 ?1 : 3.1~1592:S54 PC~00050 F = O.\J PC~00060 00 1 I = 1,200 PCM0007Q s t i i .» 2~H(ta}~CaS(2*~!~F~O.5:::0.C5e.5) PC~OC030 ~O 2 J : 2,13 PC~~00090 ~ = (J:; 1 • 0 ) _.J • 5 PC~OOlOO S (J ) =S ( J -1 ) + ( 2:::;..1 ( 1 'j- J) :;:Ccs( 2~ PI::: F ~ .:; ~ .~ • G~ ~ 5 ) ) PC'100110 Z c~;... r!":uE PC~OOlZO ~(I)=(1/Z.~71~)~S~RT{S(la)~$(1d» PC~"'00130 Y(I)=20~~LuG10{R(!» PC~00140 x(r)=~ PC~OOlSO F=i=+O.08B5 PC~00160 1 CONTI~~UE PC~00170 N?TS=200 PC~00180 CALL PLOTS{SUF,ZO~OCtll,-l) PC~00190 CALL ?LCT{l.O,1.O,-3) , PC~OC200 CALL SC~L~(X,lO.O,Z~O,l) PCMO~ZlO CALL SCALE(V,e.O,200,1) . PC~C0220 CALL AXIS(O.OfC.Ot'~HZ·,-3,lO.O,O.O,X(N?TS+l),X(NPTS+Z)} PC~"002~O CALL AXIS(O.O,O.Ut'~RE~ RESP I~ ~3',15t3.0,90.C.Y(NPTS+l)t PC~"00240 ~ Y(NP7S+2» PCMOOZSO' CAL~ PLOT(O.O,O.O,3) PC:~00260 CALL'FL!NE(X,Y,200,1,O,O) PC~OOZ70 CALL PLOT(O.O,O.O,999) PC~OOZSO STC? PC~00290 END PCM00300 ·.2 RE18BEBCES

I • FREDRICK J-HIL1 and GERARD R.PE~IBSOI

Intreductlen t. switching the.ry and logLeal desl,n by

JOHN WILEY and SONS , INC. '98~

2 • C.MEAD and L.CONVA! • Intr.duetl•• t. VLSI syate•• readlnc aassachusset•• ADnISON-VEALI Cg80 3 V.ULBIICH !.IOLL and J.ZSaBEI , lOS VLSI ptpellned dlg~tal filters tor vl.eo appllcatlens , IEEI ICASSP , -984

4 VLSI des1gn t ••ls. referenae manual Uv/»w VLSI

COISORTIUI J .983 5 • YONG CHIIG LIM and SYDNEY R.PAIKER, FIB filter deslgn over a discrete povar8~.f-tw. c.efticlent space

IEEE ASSP , june '98'

6 • LAWIEKel R.HAirIER aDd BEllARD GO~D, theery and appllcatl.ns er d1s1tal signal preoesslBI ENGLBWOOD

CLIFFS IJ : PREITICE HALL t .975

7 • THOMAS G.HALLI. and MICHAEL J.1LYIB t p1pel1n1nc er arlth••tlc fUDcttlns , liKE .n COMPU!ERS • aUlust 4'72

8 • R.Y.PIITEI. on reut1ug tve-p.lnt nets acress 8 ehann.l in PROC. .9 DBSIGJ AUTOMATION COBJERIICE 4982 • pp 894-902 9 H.DEMAI. J.VAI GIIDEBDBUIIH and i.G05CALVES • eust•• design of hardware dig1tal fllt.rs en 1ategrated circuits 1n PROC. '982 at cust•• integrated cLrcuit cenferenee (cree) , ROCHESTER, USA.