Ohio University

VLSI NMOS hardware design of a linear phase FIR low pass digital filter A thesis presented to the faculty of the college of engineering and technology Ohio University In partial fulfillment of the requirements for the degree Master of science by Charef chabbi/ - I june,l985 OHIO UNIVERSITY LIBRARY iii ACKNOWLEDGEMENTS I would like to thank my.advisor, Dr. KOGI OGINO TANAKA for his advice and help throughout the development of this thesis. I found it an endjoyable project , and I am glad to have had this opportunity. I am also grateful to my government for supporting my advanced study in the United States • iv Contents Chapterl Introduction ----------------------1 Chapter2 The full adder --------------------3 Full adder architecture -----------3 Layout of the pair of full adders with latches ---------------------29 Simulation of the pair of full adders with latches --------------28 Carry lookahead adder ------------38 Carry save adder -----------------39 Chapter3 Linear phase FIR digital filter --40 proprieties of FIR digital filter 40 Optimum linear phase FIR low pass digital filter with even impulse response duration --------48 Optimum linear phase FIR low pass digital filter with N even and a discrete powers-oi-two coefficient space -----------------------------56 Chapter4 VLSI NMOS hardware design of a multiplierless pipelined linear phase FIR low pass digital filter with even impulse response duration ----------64 Network structures of FIR digital. filters ----------------------------64 Multiplication by a power-of-two----67 v Ptpelln1ng -~---~--.-------------~69 Operation speed ~f the p1pellned linear phase FIR lev pass d1gital f~lter ----------~-·---·-------~-~70 Structure of the FIR lev paas digital ttlt.r-~-------~-------~--~------~--75 Fl••rplan .r the structure ~f the lev pass dl,ltal filter ------------75 Chapter5 COICLUSIOI -------------------------80 APPEIDIX -.-------------~--~----------------8~ p!a.clf-----------------------------52 pfa.l.g--------·-·---------~--------94 pfa.n4des---~-----------------·-----92 pra.a1a-----------------------------95' pf•••pice-----~~--------------------97 alaulatl.n--------------------------99 resp.D.e-------~---.-.--~----------••• REFERENCES--------------------~----.t2 1 Chapterl INTRODUCTION A digital filter operates on an input-sampled signal to produce an output sampled signal by means of a computational algorithm. It can be simulated on general purpose computer or can be constructed with special purpose digital hardware. For a number of years , software implementation was the only possible mode of performing digital filtering, however the rapid development of very large scale integrated (VLSI) circuit has opened up the area of hardware implementation of digital filters. Currently , the industry can produce adders , shift registers and multipliers needed for hardware implementation of digital filters. The multiplier is the most expensive and the slowest component in digital filters, however multiplications by powers-af-two are very easy to implement in hardware and can improve the speed of the digital filter The FIR digital filters are always stable and can have a linear phase • ,There are essentially three well known classes of design techniques for linear phase FIR digital filters namely the window method, the frequency sampling method and the optimal ( in the Chebyshev sense) digital filter design methods. In the optimal design , by the use of integer linear programming with branch and bound algorithm , one can restrict the coefficient space to any discrete space • 2 We are looking to a minimum hardware and a high speed in our design of a linear phase FIR low pass digital filter. In chapter2, we discuss the full adder as being the basic building block of our digital filter , we layout a pair of full adders with latches that we simulate on the VAX 11-750, using the spice2g6 ,to check the transient response • In chapter3 , we give the conditions for the phase of the FIR digital filter to be linear, we find that the impulse response can be either symmetric or antisyrnmetric. Our FIR is a low pass I then h(nT) is symmetric. we also give the specifications to achieve in terms of tolerances • In chapter4, we adopt the transposed direct form structure of the FIR digital filter, very well suited for the pipelining , then we use also pipelining of the multiplication with a coefficient in order to achieve a sampling frequency of 17.7 MHZ with a 2.5 ~m NMOS technology • 3 Chapter2 THE FULL ADDER One of the basic building blocks of the hardwired digital filters is the full adder • A detailed discussion of the full adder architecture is then worthwhile , some other usual adders like , carry save and carry lookahead adders are rnentionned for comparison with ripple adder • 2 • 1 Full adder architecture 2 • 1 • 1 Half adder A half adder is a combinational circuit that adds two binary bits to produce a sum and a carry bit be two binary bits to be added and be sum and carry bits produced • Using Karnaugh maps, we can set down equations for St and Ct as SL is an exclusive-or of At and Bt , and a half adder circuit will be as shown below B~ V'--_---+----I--I 4 2 • 1 • 2 Implementation of the exclusive-or Using the equation above, the exclusive-or is implemented as follows Bi, 0--.--------4 and the half adder circuit will be 2 • 1 • 3 Full adder architecture A full adder is a combinational circuit that accepts one bit of each operand and an input carry to produce a sum bit and an output carry • Let An ' B.., and Cn-i be bits of each operand and 5 the input carry respectively, Let Sn and C~ be sum and output carry bits respectively • Using Karnaugh maps , we can set down equations of S\1 and C., as and the carry output en equation will be Using the two equations of Sn and C~ , we can construct a full adder from two half adders as follows we input A~ and Bn to the first half adder, the sum output of the first half adder constitutes with the carry Cn- 1 the two inputs to the second half adder to produce Sn' the carry output C~ will be obtained by ORing the carry output of the second half adder and the carry output of the first half adder • The circuit of the full adder will be then , 6 and implementing the full adder using AND and NOR gates A~ Uo--....--+---I Bno----....--......f CM o--- - - - - - - - - - ---..----1 2 • 1 • 4 Parallel adder A cascade of N full adders forms an N-bit parallel adder , as shown below The limiting speed of the parallel adder is certainly the carry propagation delay, the carry must propagate through at least two levels of logic in each full adder before C - and S~_1 can assume their final N i values • A minimization of the carry delay is then necessary , fortunately , an examination of the architecture of the full adder reveals that by taking 7 ~ instead of C~ saves one inverter delay • Then , let us find the equations of Sn+i and Crl+i in the next full adder in terms of en , since E (Ah +i e B"+1- ) .c, = ( A n+1. Bn+ 1 + en then ) St"'l+! = ( A n+ 1. Ee Bn+1.. ) .e n + ( A l1+1 Q1 Bn+i + en and the carry output Cn+i will be expressed as An+i • BYl...i To implement the next full adder, we need then first implement the exclusive-nor (XNOR) , 8 Using the two equations of Sn+i and en .... ! , the full adder wi th inputs At'\1-1. ,B.,+! and -en wi 11 have the following implementation u------o Cn+i A~1°---"'---' Bn+i &---+-----.....---. I :\ en 0------------ lID In the carry path from en to Cn+~ , we have also saved one inverter delay. Then if we allow the carry outputs C" and Cn+i to alternate , where n = 0,2,4,6,8, ••• we will save inverter delays in the carry path We saved two inverter delays in the carry path Because of the alternation of the carry outputs, the circuits of the full adders (Ah , Bn , en-i) and I I ) are different and the parallel adder will be formed by cascading a repetition of pairs of full adders • 9 The most important parameter of a parallel adder is its addition time. Considering an N-bit parallel adder , if ~ is the carry propagation time through two full adders and tHAis the delay of an exclusive-or, the N-bit parallel adder addition time is given by _ N- i I)' Ta = 2LHA + 2 "C 2 • 1 • 5 Pair of full adders with latches. Pipelining is a well known hardware design technique for utilizing parallelism to increase the computation rate of a digital system. We use pipelining in our design of FIR digital filter and we will discuss it in chapter4. In a pipeline the outputs of each stage are the inputs to the next stage, to avoid the alternative of a task overtaken by the following, the outputs of each stage should be latched • The latch circuit is designed with two non- overlapping clocked transfer transistors with an inverter between them and an inverter at the output • The circuit of the latch is the following The data at IN will appear at OUT after one clock period ( period of two non-overlapping clocks) • 10 2. 2 VLSI NMOS design of a pair of full adders with latches • 2 • 2 • 1 MOS transistor Integrated systems in MOS technology contain three levels of conducting material separated by intervening layers of insulating material. From top to bottom I the layers are metal , polysilicon and diffusion • A MOS transistor will be produced on the integrated system if a po Lys i Licori path crosses a diffusion path as shown below _____IJorain ___--~-,--__f- Gate I . , ~Source A more detailed view of the MOS transistor is given below L-J Source oxide ~+ / Channe\ ~ Land Ware the length and the width of the channel respectively • Let Vgg, vss and Vdd

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