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UCLA Electronic Theses and Dissertations UCLA UCLA Electronic Theses and Dissertations Title Applications of Formal And Semi-formal Verification on Software Testing, High-level Synthesis And Energy Internet Permalink https://escholarship.org/uc/item/6jj2b6jn Author Gao, Min Publication Date 2018 Peer reviewed|Thesis/dissertation eScholarship.org Powered by the California Digital Library University of California UNIVERSITY OF CALIFORNIA Los Angeles Applications of Formal And Semi-formal Verification on Software Testing, High-level Synthesis And Energy Internet A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Electrical And Computer Engineering by Min Gao 2018 © Copyright by Min Gao 2018 ABSTRACT OF THE DISSERTATION Applications of Formal And Semi-formal Verification on Software Testing, High-level Synthesis And Energy Internet by Min Gao Doctor of Philosophy in Electrical And Computer Engineering University of California, Los Angeles, 2018 Professor Lei He, Chair With the increasing power of computers and advances in constraint solving technologies, formal and semi-formal verification have received great attentions on many applications. Formal verification is the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property. These verification techniques have wide range of applications in real life. This dissertation describes the applications of formal and semi-formal verification in four parts. The first part of the dissertation focuses on software testing. For software testing, symbolic/concolic testing reasons about data symbolically but enumerates program paths. The existing concolic technique enumerates paths sequentially, leading to poor branch coverage in limited time. We improve concolic testing by bounded model checking. During concolic testing, we identify program regions that can be encoded by BMC on-the-fly so that program paths within these regions are checked simultaneously. We have implemented the new algorithm on top of KLEE and called the new tool Llsplat. We have compared Llsplat with KLEE using 10 programs from the Windows NT Drivers Simplified and 88 programs from the GNU Coreutils benchmark sets. With 3600 second testing time for each program, Llsplat provides on average 13% relative branch coverage improvement on all 10 programs in the Windows drivers set, and on average 16% relative branch coverage improvement on 80 out of 88 programs in the GNU Coreutils set. ii The second part of the dissertation implements symbolic/concolic testing methods onto an embedded platform. With the more extensive use and of higher demand of the embedded systems, reliability of the embedded software becomes a critical issue. Thus it is important to design a test harness that can test embedded software on the real platform or hardware in the loop framework comprehensively and systematically. We present our design prototype Codecomb. Codecomb implements symbolic/concolic execution that is able to achieve high branch coverage to generated test cases. It mainly exploits client/server architecture to achieve the isolation of testing tools and program under test such that complex computing job is performed in the server side. Experimental results show that Codecomb can detect program deficiency automatically on the embedded platform, and precisely locate errors such as buffer overflow, memory leak in a running program. The third part of the dissertation applies formal and semi-methods to high-level synthesis (HLS) for VLSI. Verifying functional equivalence of high-level synthesis with formal methods ensures the correctness of the transformation flow. Current verification work widely uses static analysis such as model checking, while a pure dynamic execution flow is missing. In this part, we propose a functional verification flow for HLS utilizing symbolic execution on both C and Verilog directly. Specifically, on behavior C level we collect program traces via symbolic execution. As for Verilog level, we first generate a circuit satisfiability modulo theory (SMT) representation. Then we propose a light-weight pure symbolic execution framework to collect Verilog’s on-the-fly time invariant version-based traces. To alleviate the scalability issue, we develop an operation abstraction method using SMT solvers to match potential C and Verilog traces. Extensive experiments on circuits from numerical computing and Chstone benchmark verify the validity and effectiveness of the flow. The last part of the dissertation investigates the applications on Energy Internet. Energy Router based system is a crucial part in the energy transmission and management under the circumstance of Energy Internet for green cities. During its design process, a sound formal verification and a performance monitoring scheme are needed to check its reliability and meaningful quantitative properties. In this chapter, we provide formal verification solutions for ER based system by proposing a continuous-time Markov chain model describing the iii architecture of ER based system. To verify real world function of the ER based system, we choose electricity trading to propose a Markov decision process model running on an ER subsystem to describe the trading behaviour. To monitor the system performance, we project the energy scheduling process in ER based system, and then implemented this scheduling process on top of cloud computing experiment tool. Finally, we perform extensive experiment evaluations to investigate the system reliability properties, quantitative properties, and scheduling behaviours. The experiment verifies the effectiveness of the proposed models and the monitoring scheme. iv The dissertation of Min Gao is approved. Todd D Millstein Sudhakar Pamarti Puneet Gupta Lei He, Committee Chair University of California, Los Angeles 2018 v To my family vi TABLE OF CONTENTS 1 Introduction :::::::::::::::::::::::::::::::::::::: 1 1.1 Motivation . .1 1.2 Original Contributions . .7 1.3 Organization . .8 2 LLSPLAT: Improving Concolic Testing by Bounded Model Checking :: 9 2.1 Introduction . .9 2.2 A Motivating Example . 11 2.3 Concolic Testing . 13 2.3.1 Program Model . 13 2.3.2 The Concolic Testing Algorithm . 13 2.4 Combining Concolic Testing with BMC . 15 2.4.1 Identifying Program Portions for BMC . 17 2.4.2 Translating Governed Regions to BMC Formulas . 19 2.4.3 Integrating BMC Formulas with Concolic Testing . 21 2.5 Experiments . 25 2.5.1 Experiment Settings . 25 2.5.2 Experimental Results . 26 2.5.3 Threats to Experiment Validity . 29 2.6 Related Work . 30 2.7 Conclusion . 32 3 Codecomb: Automated Test Case Generation And Defect Detection for Emebedded Software Based on Symbolic Execution ::::::::::::::: 34 vii 3.1 Introduction . 34 3.2 System Architecture . 36 3.2.1 Source Code Instrumentation . 37 3.2.2 Client Module . 38 3.2.3 Server Module . 38 3.3 Test Case Generation . 39 3.4 Defect Detection . 41 3.4.1 Buffer Checking . 41 3.4.2 Memory Allocation and deallocation . 43 3.5 Experimental Results . 44 3.6 Conclusion . 48 4 A Dynamic Approach to Functional Verification of High Level Synthesis 49 4.1 Introduction . 49 4.2 Preliminary . 53 4.2.1 High-level Synthesis . 53 4.2.2 Sysmbolic/Concolic Execution For Sequential Programs . 54 4.3 Verification Flow . 55 4.3.1 Verilog Trace Collection . 56 4.3.2 C and Verilog Trace Matching . 62 4.3.3 Termination of The Flow . 65 4.4 Experimental Results . 65 4.5 Conclusion And Future Work . 68 5 Probabilistic Model Checking and Scheduling Implementation of Energy Router System in Energy Internet for Green Cities ::::::::::::::: 70 viii 5.1 Introduction . 70 5.2 Preliminary . 73 5.2.1 Continuous-Time Markov Chain . 73 5.2.2 Markov Decision Process . 74 5.2.3 Energy Router Based Subsystem Architecture . 75 5.3 Architecture Modeling of The Energy Router System . 75 5.3.1 Modeling of The Multiple Energy Router System . 76 5.3.2 Modeling of Single Energy Router Based Subsystem . 77 5.4 Modeling of Energy Router Subsystem Based Electricity Trading . 80 5.4.1 Requster Modeling . 81 5.4.2 Service Provider Modeling . 82 5.5 Energy Router System Scheduling . 84 5.5.1 Implementation of ER based System Simulation . 85 5.6 Experiments and Results . 87 5.6.1 Architecture Model Properties . 87 5.6.2 Electricity Trading Model Properties . 90 5.6.3 Scheduling Behaviour of ER Based System . 91 5.7 Conclusion and Future Work . 92 6 Summary ::::::::::::::::::::::::::::::::::::::: 94 .1 Preliminaries . 97 .2 Proofs . 97 .2.1 Properties of Effective Dominance Sets and Governors . 97 .2.2 Properties of the BMC Generation Algorithm . 99 References ::::::::::::::::::::::::::::::::::::::::: 104 ix LIST OF FIGURES 2.1 Program Model . 13 2.2 An Example . 19 2.3 Branch coverage imporvement on the GNU Coreutils. Each bar denotes a bench- mark under test. Y-axis represents relative branch coverage improvement. 28 3.1 Codecomb architecture . 36 3.2 Run time comparison between CodeComb and Auto+Valgrind . 47 4.1 High-level synthesis functional verification flow . 55 4.2 A Verilog SMT description . 57 4.3 An example of operation abstraction . 63 5.1 ER system in energy Internet for green cities . 71 5.2 Architecture of single ER-based subsystem . 76 5.3 Multiple-ER system failure probability . 87 5.4 Single-ER based subsystem failure probability . 88 5.5 Single-ER based subsystem communication count . 88 5.6 Minimum cost for the requester to get the required amount of services . 88 5.7 Maximum loss for the provider to provide the required amount of services . 89 5.8 Average total revenue and average total line loss for ER based system . 89 .1 Topological ordering of the governed region . 100 .2 An execution from the governor gov to a destination d .............. 100 .3 Topological ordering of the governed region . 100 x LIST OF TABLES 2.1 Edge formulas and block formulas . 21 2.2 Branch coverage comparison between Llsplat and KLEE on the Windows NT Drivers Simplified . 27 2.3 Branch coverage comparison between Llsplat and KLEE and the number of encoded governed regions on 10 randomly selected benchmarks from the GNU Coreutils .
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