Pcbs for Computing Density from Big Bang to the Automobile

Total Page:16

File Type:pdf, Size:1020Kb

Pcbs for Computing Density from Big Bang to the Automobile AltiumLive 2017: PCBs for Computing Density From Big Bang to the Automobile Andreas Doering IBM Research – Zurich Laboratory 1 Agenda 1 The DOME project 2 Motivation for Microservers 3 Boards 4 Insights 5 Outlook 2 * IDC HPC technology excellence award, ISC17 3 DOME ppp Astron, IBM, Dutch gvt •4 Ronald P. Luijten / July 2017 SKA (Square Kilometer Array) to measure Big Bang Start of nucleosynthesi End of Big Protons Inflatio s through nucleo- Modern Bang created n fusion synthesis Universe 0 10-32s 10-6s 0.01s 3min 380’000 years 13.8 Billion years Picture source: NZZ march 2014 •5 SKA: What is it? ~0.5M Antennae .07GHz-0.45GHz. ~0.5M Antennae .5GHz-1.7GHz. 1. 109 samples/second * .5M antennae: .5 1015 samples/sec. 2. 3.5 109 samples/second * .5M antennae: 1.7 1015 samples/sec. ~3000 Dishes 3. 2 1010 samples/second * 3K antennae: 6.1013 samples/sec 3GHz-10GHz. Sum = 2 1015 samples/second @ 86400 seconds/day: 170 1018 (Exa) samples/day. Assume 10-12x reduction @antenna: 14 Exabytes/day (minimum). Top 500: Sum=123 PFlops. 2GFlops/watt. 100x Flops of Sum! ~ 7GWh •6 CSP SDP ~ 1 PB/Day. 330 disks/day ~ 10 Pb/s ? ? 120’000 disks/yr 86’400 sec/day 14 ExaByte/day Top-500 Supercomputing(11/2013)…. 0.3Watt/Gflop/s Too hard Today’s industry focus is 1 Eflop @ 20MW. (2018) ( 0.02 Gflop/s) Most recent data from SKA: CSP….max. power 7.5MW SDP….max. power 1 MW Latest need for SKA – 4 Exaflop (SKA1 - Mid) Too easy (for us) 1.2GW…80MW Factor 80-1200 Moore’s law multiple breakthroughs needed •7 © 2016 IBM Corporation Dome Project: Research Streams… Sustainable Data & (Green) Nanophotonics Streaming …plus Computing an open …are mapped to research projects: user System Analysis platforUser m:platform Algorithms & Machines - Student projects - Events - Research Computing Transport Storage Collaboratio n - Microservers - Nanophotonics - Access Patterns - Accelerators - Real-Time Communicatio ns - New Algorithms 33M€ 5-year Research Project: 76 IBM PY (32 in NL); 50 ASTRON PY •8 Definitions • “Microserver” = The server class of the mobile era • “Microserver” = SoC + DRAM + Flash + Power • “Microserver” = Backplane + not-enclosed modules 9 Motivation • Silicon scaling limits, Energy for computation vs. on-chip- communication vs. off-chip communication • Use of large SMP-servers by partitioning, docker, etc.: Cache Coherency not fully used • Emergence of powerful embedded processor cores, in particular ARM • Premise given through Aquasar cooling work enabled DOME funding 10 Table of PCBs Length Width Thickness Module Name Iterations Layers Holes Components Nets Backdrilling Material Tool [mm] [mm] [mm] P5020/P5040 processor 3 139.7 55.5 1.28 10 3242 1007 539 no ISOLA-400 A Big Baseboard 1 220 160 1.28 10 491 175 154 no ISOLA-400 A Power Converter 2 139 56.5 1.63 8 737 440 231 no FR-4 A mSATA on DIMM 2 139.7 55.5 1.24 4 341 69 67 no FR-4 A 8p1 backplane 2 300 200 2.7 18 3582 565 1326 no FR-4+ A Testboard for switch power converter 1 160 220 1.6 8 888 259 134 no FR-4 A Switch Mothercard >1 139.7 57.8 3.6 28 3311 837 730 yes A Switch Daughtercard 1 139.7 57.8 1.8 10 423 213 160 no FR-4 A Mini baseboard 2 160 100 1.2 6 851 376 241 no FR-4 A Bracket for DIMM connector on Minibaseboard 2 154 32 1.2 6 116 2 98 no FR-4 A Bracket for SPD08 connector on Minibaseboard 1 C T4240 processor 3+1 139.7 63 1.6 16 1316 820 Panasonic C mSATA on SPD08 3 139.7 62.5 1.6 6 1014 79 105 no FR-4 A M2 carrier 2 139.7 61.6 1.6 6 1091 130 131 A Auxiliary power converter 1 61 56 1.6 4 478 74 30 no FR-4 A PCIe Extender no FR-4 A LS2088 Processor module 1? 139.7 62.5 1.6 14 1037 714 no Panasonic R1577/1570 C USB HUB Module 2 139.7 61.5 1.57 8 1162 557 387 no FR-4 A BB2 backplane 2 520 200 3.15 22 12598 1076 3820 7 Runs Panasonic Megtron 6 A FR-4, Panasonic Interposer card 1 139.7 80 1.57 8 897 76 132 4 Runs A Megtron 6N FMKU2595 FPGA 2 139.7 63 1.57 14 7442 881 914 no Panasonic Megtron 6 A A= Altium Designer, C = Cadence 11 System Overview 8x40Gb Ethernet 10G Ethernet storage node Switch 8/32/128 Power compute nodes converter P5020/P5040 2/4 cores [email protected], 16GByte DDR3, 2xXAUI,4x1GbE, 2xSATAv1 8 x mSATA or T4240 24 cores [email protected], 24GByte DDR3, 4x10GbE, 2x1Gb, 2xM2 2x SATAv2, PCIe-2.0 x8 LS2088 8xARMv8@2GHz, 32GByte DDR4, 6x10GbE, PCIe, 2xSATA FMKU2595 FPGA 330KLUTs, 4x10GbE, 4xGbE,2xSATA 12 Backplane connectors DIMM socket with removed latches for generation 1 3M’s SPD08 in various lengths For generation 2 3 segments of Molex Impact 210 contacts (70 diff pairs) Xtreme Poweredge for power converter (both) 13 System today Backplane for • 32 compute nodes, • 8 populated • 1 Switch node, • 1 Management node • 2 Storage nodes • Water cooled 14 View from above QSFP cages Water In/Out 10 GbE Switch Server nodes Storage node Cooling Rails Power node 15 System Q4 2017 Two backplanes, total 64 compute Nodes, e.g. 1536 cores, 1536 GB DRAM 64 SSDs 16 Gallery of (some) Boards 17 Power Converter • Master thesis project: • Student did high-level design (e.g. selection of backplane connector), component selection, and schematic entry. Layout was completed by regular engineer: First version worked, • 1 iteration to improve stability, protection Challenges: High current on top/bottom and SMD packages, location of connectors, and tight IC/L/C-converter triangle, conflict ofhigh profile Ls and hot ICs that must be covered by cool plate 18 40A per contact finger, allowing different type of C/L 19 Switch Module Left: Main Switch PCB 130mm x 55mm Right: Switch with mounted daughter card 20 Pin Assignment • Pin Assignment has to suit back plane and switch module design • Both are challenging (Back plane has more space, but many more wires) • Reduce crossing on both boards • XAUI has low requirements on length balancing • 1st Iteration: • Let the CAD tool choose the pinout on both boards independently • Find out the critical spots • Use python script to build systematic pinout that circumvents these 21 PCB Layer Stack Press-Fit Connector on this side Total PCB thickness 6 inner signal layers, impedance controlled 3.6mm with shielding ground layers Length of connector in-between pins 1.2mm Original Assumption, that board space across “through-hole” 4 high-current connector cannot be power supply used, was wrong. lanes Need backdrilling ASIC on this side 22 PCB routing Routing between connector pins with 1 signal pair This narrow strip (1cm wide) is one critical part. 23 FPGA Node PCI- and/or Network-Attached 2 Channels DDR4 (e.g. 16GByte) Xilinx® Kintex® UltraScale 6 x 10 GBE, PCIe3 x8, 2 x SATA3 Status: In bringup 24 FPGA Node – Layout Concept Flyby control signals on 3 Layers, P2P data signals mainly on 1 layer HighSpeed IO on 2 inner layers 25 Cooling Combination of passive cooling on decapped chip, using vapor chambers and hot- water 26 Insights • Main source of error: transfer from data sheet into tool • Second source of error: Harness interface (swapping P/N on diff pairs, clock/data on I2C) • Third source of error: voltage levels of pins (e.g. enable of power converter) • Why is there no electronic transfer of component data to designers? Exception: TI (e.g. https://webench.ti.com/cad/) Why is there no standard format? There was an initiative XMLEDA, etc. • DRC could do more, if symbols provided the information (e.g. P/N property, clock, etc.) • Conversion from one tool to another is a кошмар Hired Elgris and still 5 working days turned into 2 months 27 Acknowledgements This work is the results of many people • Ronald Luijten (Lead Architect/Technical Lead), Francois Abel (Switch, FPGA. and BB2-lead), Beat Weiss (Core Engineering), Matteo Cossale (Cooling), Stephan Paredes (Coooling), and others: IBM ZRL/CH • Peter v. Ackeren,, Ed Swarthout, Dac Pham : Freescale/NXP • Yvonne Chan, IBM Toronto • Gijs Schonderbeek, Sieds Damstra, Albert-Jan Boobstra: ASTRON/NL • Several students and interns • And many more remain unnamed…. Companies: NXP; IBM; TransferDSW – NL, Strukton/NL, Roneda/BE, AT&S/AT, Supercomputing Systems/CH, Miromico/CH Dutch Gvt for DOME grant 28 Outlook • Still work to be done, HW testing, SW, redesign of some boards for bugs or low production yield, cost reduction of some components • Commercially available through startup ILA Microservers • First customer bought 15 T4240 modules • Buildup of two systems for ASTRON and ZRL (with enclosure, etc.) • GPU node • Target markets: • Data center • Scientific computing (SKA) • Embedded (vehicles, robots, IoT Edge server) 29 Backup System Management • Every node is a USB device • Cypress PSoC controller implements module-level management • Serial console • Power Sequencing • Current and Temperature Monitoring • JTAG • etc. • Python process on host allows access of all hosts • Implements IPMI • Interacts with Switch, FPGA tools, etc. 31 QorlQ T4240 Communication Processor 32 32-way carrier network topology FM6000 switch T4240 module 32 way carrier 32x 10 GbE internal connectivity from switch 8 x 40GbE external connectivity (QSFP+) Green links optionally connect to other 32way carrier Ronald P. Luijten / July 2017 33 33 Thanks for your Attention! Questions?.
Recommended publications
  • The Case for Radio Astronomy
    A Sustainable approach to large ICT Science based infrastructures; the case for Radio Astronomy Domingos Barbosa #1, João Paulo Barraca#&, Albert-Jan Boonstra*, Rui Aguiar#&, ,Arnold van Ardenne *£, Juande de Santander-Vela §,, Lourdes Verdes-Montenegro§ # Instituto de Telecomunicações, Campus Universitário de Santiago, 3810-193 Aveiro, Portugal 1 [email protected] & Universidade de Aveiro, Campus Universitário de Santiago, 3810-193 Aveiro, Portugal * ASTRON, P.O. Box 2, 7990 AA Dwingeloo, The Netherlands £Chalmers University of Technology, Gothenburg, Sweden §Instituto de Astrofísica de Andalucia (IAA-CSIC) Glorieta de la Astronomía s/n, E-18008, Granada, Spain Abstract—Large sensor-based infrastructures for radio energy, and develop low carbon emission technologies, to be astronomy will be among the most intensive data-driven projects adopted as part of a future Strategic Energy Technology Plan. in the world, facing very high power demands. The Radio astronomy projects will be among the most data-intense geographically wide distribution of these infrastructures and and power hungry projects. Recent experiences with Square their associated processing High Performance Computing (HPC) Kilometer Array (SKA) [1] precursors and pathfinders like facilities require Green Information and Communications Technologies (ICT): a combination is needed of low power ASKAP, MeerKAT and LOFAR reveal that an important part computing, power and byte efficient data storage, local data of the life cycle cost of these large-scale radio astronomy services, Smart Grid power management, and inclusion of projects will be power consumption [6],[7]. As an example, a Renewable Energies. Here we outline the major characteristics 30-meter radio telescope requires approximately 50 kW and innovation approaches to address power efficiency and long- during operation (about 1GWh for a typical 6h VLBI - term power sustainability for radio astronomy projects, focusing observation experiment) enough to power a small village, on Green ICT for science.
    [Show full text]
  • This Does NOT Imply Low Performance! the SKA, Upon Completion in Ca
    IBM / ASTRON DOME Project High-Performance, Energy-Efficient Microserver Andreas Doering, Francois Abel, Matteo Cossale, Stephan Paredes, Ronald Luijten The DOME Project µServer ASTRON, The Netherlands Institute for Radio Astronomy, and IBM collaborate Integration of an entire server node motherboard* into a single microchip except DRAM, in the DOME project to research extremely fast, but low-power exascale NOR-boot flash and power conversion logic. computer systems targeted for the international Square Kilometre Array (SKA). This does NOT imply low performance! The SKA, upon completion in ca. 2024, will be the world’s largest and most sensitive radio telescope. * no graphics It will be used to explore evolving galaxies, dark matter and even the very origins of the universe – the Big Bang – dating back more than 13 billion years. The SKA is expected to generate roughly 14 exabytes of raw data per day. In the DOME Project, the scientists investigate new technologies that will be required to read, store and analyze that data. 139 x 55 mm2 245 mm DOME µServer Motivation & Objectives 305 mm • Create the world’s highest-density 64-bit µ-server drawer – Useful to evaluate both SKA radio-astronomy and IBM future business – Platform for business analytics appliance pre-product research Compute node board Interfaces: – High energy efficiency / very low cost • USB (management) – Commodity components, HW + SW standards-based SKA (Square Kilometre Array) to measure Big Bang • 4 x 10 GbE – Leverage “free computing” paradigm • 2 x SATA – Enhance with
    [Show full text]
  • Energy-Efficient Data Transfers in Radio Astronomy with Software UDP RDMA Third Workshop on Innovating the Network for Data-Intensive Science, INDIS16
    Energy-Efficient Data Transfers in Radio Astronomy with Software UDP RDMA Third Workshop on Innovating the Network for Data-Intensive Science, INDIS16 Przemek Lenkiewicz, Researcher@IBM Netherlands Bernard Metzler, Researcher@IBM Zurich Research Lab Chris Broekema, Researcher@ASTRON Netherlands Institute for RadioAstronomy Table of contents/Agenda template Radio-astronomy & The Square Kilometre Array Data Transport in Radio Astronomy Our Solution and Experiments Conclusions and Future Work The DOME project Netherlands Zürich Research Lab 2 ©2015 IBM Corporation 13 November 2016 Radio astronomy & The Square Kilometre Array A brief introduction Astronomy §Lenses, mirrors, sensors §Array of antennas and/or dishes §Light §Radio frequencies §Picture of object §Map of radio sources Gran Telescopio CANARIAS Low-Frequency Array (LOFAR) The M33 Galaxy The M81 Galaxy 4 ©2015 IBM Corporation 13 November 2016 The Square Kilometre Array 5 ©2015 IBM Corporation 13 November 2016 Radio astronomy data transport SKA telescope data flow 7 ©2015 IBM Corporation 13 November 2016 SKA Phase 1 in numbers (italics are derived and/or speculative) SKA1 MID SKA1 LOW Location Karoo, South Africa Western Australia Number of receivers 197 (133 SKA + 64 MeerKAT) 131.072 (512 st x 256 el) Receiver diameter 15 m (13,5 m MeerKAT) 35 m (station) Maximum baseline 150 km 65 km Frequency channels 65.536 65.536 SDP input bandwidth 3,1 Tbps 3,1 Tbps Req’d Compute capacity* 20-72 PFLOPS 16-41,5 PFLOPS Archive growth rate 10 – 100 Gbps (50yr life) 25 – 100 Gbps (50yr life) SDP
    [Show full text]
  • Inventec DCS6072QS OCP Hardware Specification
    Inventec DCS6072QS ToR/Leaf Switch Specification Revision History Revision Date Author Description .01 3/27/2015 Alex Johnstone Initial Release .02 5/28/2015 Alex Johnstone Incorporated Engineering feedback. First version submitted to the OCP. Author: Alex Johnstone Contents Revision History .............................................................................................................................. 2 Contents ........................................................................................................................................... 3 Licenses ........................................................................................................................................... 5 1.1 License .......................................................................................................................... 6 Scope ................................................................................................................................................ 7 Overview .......................................................................................................................................... 7 Physical Overview ........................................................................................................................... 8 1.2 Dimensions.................................................................................................................... 8 1.3 Top View......................................................................................................................
    [Show full text]
  • SKA, DOME & ASTRON Project
    SKA, DOME & ASTRON project - µServer Ronald P. Luijten – Data Motion Architect [email protected] IBM Research - Zurich 16 July 2015 DISCLAIMER: This presentation is entirely Ronald’s view and not necessarily that of IBM. COMPUTE is FREE – DATA is NOT Ronald P. Luijten – Data Motion Architect [email protected] IBM Research - Zurich 16 July 2015 DISCLAIMER: This presentation is entirely Ronald’s view and not necessarily that of IBM. DOME: • ppp Astron, IBM, Dutch gvt • 20MEur funding over 5 years • Started feb 2012 Ronald P. Luijten – BDEC @ ISC15 - 16Jul15 3 SKA (Square Kilometer Array) to measure Big Bang Start of Big Protons nucleosynthesis End of nucleo- Bang Inflation created through fusion synthesis Modern Universe 0 10 -32 s 10 -6s 0.01s 3min 380’000 years 13.8 Billion years Picture source: NZZ march 2014 © 2012 IBM Corporation Ronald P. Luijten – BDEC @ ISC15 - 16Jul15 4 CSP SDP ~ 1 PB/Day. 330 disks/day ~ 10 Pb/s ?? ? 120’000 disks/yr 86’400 sec/day 15 ExaByte/day Top-500 Supercomputing(11/2013)…. 0.3Watt/Gflop/s Too hard Today’s industry focus is 1 Eflop @ 20MW. (2018) ( 0.02 Gflop/s) Most recent data from SKA: CSP….max. power 7.5MW SDP….max. power 1 MW Latest need for SKA – 4 Exaflop (SKA1 - Mid) Too easy (for us) 1.2GW…80MW Factor 80-1200 Moore’s law multiple breakthroughs needed ©© 20142012 IBMIBM CorporationCorporation Ronald P. Luijten – BDEC @ ISC15 - 16Jul15 5 •IBM at IBMCeBIT 2013 –/ Rethink ASTRON your business DOME project DOMETechnology Project: roadmap 5 development Years, 33M Euro •Sustainable •User (Green) Computing •Nanophotonics •Data & Streaming Platform •System Analysis -Student projects -Events •Algorithms & Machines -Research Collaboration •Computing •Transport •Storage -Microservers -Nanophotonics -Access Patterns -Accelerators -Real Time Communications -Compressive Sampling •6 •©•© 20132012 IBMIBM CorporationCorporation •6 Ronald P.
    [Show full text]
  • On Large-Scale System Performance Analysis and Software Characterization
    Research Collection Doctoral Thesis On Large-Scale System Performance Analysis and Software Characterization Author(s): Anghel, Andreea-Simona Publication Date: 2017 Permanent Link: https://doi.org/10.3929/ethz-b-000212482 Rights / License: In Copyright - Non-Commercial Use Permitted This page was generated automatically upon download from the ETH Zurich Research Collection. For more information please consult the Terms of use. ETH Library DISS. ETH NO. 24524 ON LARGE-SCALE SYSTEM PERFORMANCE ANALYSIS AND SOFTWARE CHARACTERIZATION A thesis submitted to attain the degree of DOCTOR OF SCIENCES of ETH ZURICH (Dr. sc. ETH Zurich) presented by ANDREEA-SIMONA ANGHEL Ing. Sys. Com. Dipl. EPF born on 19.08.1986 citizen of Romania accepted on the recommendation of Prof. Dr. Lothar Thiele, examiner Prof. Dr. Anton Gunzinger, co-examiner Dr. Gero Dittmann, co-examiner 2017 A dissertation submitted to ETH Zurich for the degree of Doctor of Sciences DISS. ETH No. 24524 Prof. Dr. Lothar Thiele, examiner Prof. Dr. Anton Gunzinger, co-examiner Dr. Gero Dittmann, co-examiner Examination date: July 26th, 2017. This work was conducted in the context of the joint ASTRON and IBM DOME project and was funded by the Dutch Ministry of Economische Zaken, and the Province of Drenthe. IBM, Blue Gene, and POWER8 are trademarks of International Business Machines Corporation, registered in many jurisdictions worldwide. Intel, Xeon and Xeon Phi are trademarks of Intel Corporation in the U.S. and other countries. Other product or service names may be trademarks or service marks of IBM or other companies. To my beloved husband and family Acknowledgements Doing a PhD has been a great experience for me during which I had the chance to learn how to conduct high-quality research, how to write good scientific publications, how to collaborate in an effective manner with engineers and researchers worldwide and to meet some extraordi- nary intelligent people.
    [Show full text]
  • Dome Project DOME Project Subjects
    Dome Project DOME Project Subjects Introduction DOME project Expectations before start of project Challenges The engineering part Results Lessons learned Currently running projects Benefits for Transfer Q & A Introduction Henk de Jonge CTO at Transfer DSW (Formerly DsignWorx) since 2010 Started on the Dome project in 2012 Project Management for the various DOME projects: Processor Module Processor Baseboard Module Switch Power Test Module Switch Module Daughterboard Switch Module Motherboard Introduction Transfer Design Automation Solutions PCB ASIC/FPGA System Design Consulting Services EDA Integration Library management Educational Services Tool based Methodology Engineering services Design Automation Solutions • Altium Unified Electronic Devel. Solution • JTAG Technologies JTAG Design for test • BoardPerfect EDA Autorouter • SpaceClaim Smart 3D tool for engineers • Simplified Solutions 3D component models • Desktop EDA 3D (IDF) interface to AD DOME Project SKA (Square Kilometer Array) Big Bang Big Data Bilateral The Netherlands Switzerland South Africa Australia United Kingdom Italy … DOME DOME User Platform DOME Project - LOFAR LOFAR project (Low Frequency Array) Low frequency -> High wavelength -> Large scaled antenna’s Astron (Dwingeloo Dr.) Antenna’s LOFAR Imaging DOME Project -SKA SKA (Square Kilometer Array) Project South Africa Australia Beamforming DOME Project – Big Bang Big Bang DOME Project – Big Data Big Data - SKA project Big Bang 2014 – 15 petaflops Exascale computing 2024 – 15 exaflops Source: Wikipedia, the free encyclopedia
    [Show full text]
  • The IBM-DOME 64Bit Μserver Demonstrator: Findings, Status and Outlook Ronald P
    The IBM-DOME 64bit µServer Demonstrator: Findings, Status And Outlook Ronald P. Luijten – Data Motion Architect [email protected] IBM Research - Zurich 8 April 2014 DISCLAIMER: This presentation is entirely Ronald’s view and not necessarily that of IBM. Compute is free – data is not Ronald P. Luijten – Data Motion Architect [email protected] IBM Research - Zurich 8 April 2014 DISCLAIMER: This presentation is entirely Ronald’s view and not necessarily that of IBM. Definition µServer: The integration of an entire server node motherboard * into a single microchip except DRAM, Nor-boot flash and power conversion logic. 133mmx55mm 245mm 305mm * no graphics Ronald P. Luijten – HPC User Forum April 2014 •3 SKA (Square Kilometer Array) to measure Big Bang Start of End of Big Protons nucleosynthesis Inflation nucleosynthesis Bang created through fusion Modern Universe 0 10 -32 s 10 -6s 0.01s 3min 380’000 years 13.8 Billion years © 2012 IBM Corporation Ronald P. Luijten – HPC User Forum April 2014 •4 SKA: Largest Radio-astronomy antenna Big data on Steroids Up to 2 Million+ Antenna’s What does this mean? © 2012 IBM Corporation Ronald P. Luijten – HPC User Forum April 2014 •5 Prelim. Spec. SKA, R.T. Schilizzi et al. 2007 / Chr. Broekema Central Signal Proc Science Data Proc ?? ~ 10 Pb/s ~ 1 PB/Day. 86’400 sec/day ? 10..14 ExaByte/day Ronald P. Luijten – HPC User Forum April 2014 •6 CSP SDP ~ 1 PB/Day. 330 disks/day ~ 10 Pb/s ?? ? 120’000 disks/yr 86’400 sec/day 10..14 ExaByte/day Top-500 Supercomputing(11/2013)….
    [Show full text]
  • Technology Benchmark Report (D-GEX, Mid-Term)
    Ref. Ares(2017)2229414 - 30/04/2017 ASTERICS - H2020 - 653477 Technology benchmark report – D- GEX ASTERICS GA DELIVERABLE: D3.8 Document identifier: ASTERICS-D3.8-final.docx Date: 30-04-2017 Work Package: WP3 OBELICS Lead Partner: INAF Document Status: Report Dissemination level: Public www.asterics2020.eu/documents/ Document Link: ASTERICS-D3.8.pdf Abstract The document shows results in benchmarking different computing technologies and architectures for astrophysical data analysis, focusing on performances in execution time COPYRIGHT NOTICE 1 and power consumption. Experiments have been conducted in the mainframes of ASTRI project (INAF) and DOME (ASTRON). Both groups have designed systems targeting the requirements of low power consumption, thus realising sort of datacenter in a box; the ASTRI team focused mainly on software (ASciSoft) and algorithms, to be run on embedded boards (Nvidia Jetson, ARM + Nvidia GPU processors) attached on ground telescopes, while ASTRON team investigating on hardware integration. Testing have been conducted giving expected results, while leaving room for improvements, both in hardware selection and integration and in software development. ASTERICS - 653477 © Members of the ASTERICS collaboration PUBLIC COPYRIGHT NOTICE 2 I. COPYRIGHT NOTICE Copyright © Members of the ASTERICS Collaboration, 2015. See www.asterics2020.eu for details of the ASTERICS project and the collaboration. ASTERICS (Astronomy ESFRI & Research Infrastructure Cluster) is a project funded by the European Commission as a Research and Innovation Actions (RIA) within the H2020 Framework Programme. ASTERICS began in May 2015 and will run for 4 years. This work is licensed under the Creative Commons Attribution- Noncommercial 3.0 License. To view a copy of this license, visit http://creativecommons.org/licenses/by-nc/3.0/ or send a letter to Creative Commons, 171 Second Street, Suite 300, San Francisco, California, 94105, and USA.
    [Show full text]
  • The IBM-Astron DOME Energy Efficient Microserver: Status, Plans and Demo Ronald P
    The IBM-Astron DOME energy efficient microserver: status, plans and demo Ronald P. Luijten – Data Motion Architect [email protected] IBM Research - Zurich 26 May 2015 DISCLAIMER: This presentation is entirely Ronald’s view and not necessarily that of IBM. COMPUTE is FREE – DATA is NOT Ronald P. Luijten – Data Motion Architect [email protected] IBM Research - Zurich 26 May 2015 DISCLAIMER: This presentation is entirely Ronald’s view and not necessarily that of IBM. IBM Research - Zurich: From Atoms to Big Data Analytics © 2015 International Business Machines Corporation •3 The World is Our Lab World's largest information More than 3,000 IBM invested technology research scientists and $6B on R&D in organization engineers 2014 Africa India T.J Watson Zurich China Austin Ireland Haifa Tokyo Almaden Brazil Australia © 2015 International Business Machines Corporation IBM Research - Zurich - Established in 1956 - 45+ different nationalities - Open Collaboration: - Framework Programme7: 277 projects engaged, 68 funded, 1,900 partners - Horizon2020: 52 applications, 341 partners - Two Nobel Prizes (1986 and 1987) - Binnig and Rohrer Nanotechnology Centre opened in 2011 (Public Private Partnership with ETH Zürich and EMPA) © 2015 International Business Machines Corporation Scientific Departments Big Data Cognitive Computing & Computational Sciences: next generation cognitive systems and technologies, big data and secure information Analytics management, HPC and computational sciences Industry and Cloud Solutions: transforming industries through
    [Show full text]
  • Eindhoven University of Technology MASTER Power Modeling and Analysis of Exascale Systems Poddar, S
    Eindhoven University of Technology MASTER Power modeling and analysis of exascale systems Poddar, S. Award date: 2016 Link to publication Disclaimer This document contains a student thesis (bachelor's or master's), as authored by a student at Eindhoven University of Technology. Student theses are made available in the TU/e repository upon obtaining the required degree. The grade received is not published on the document as presented in the repository. The required complexity or quality of research of student theses may vary by program, and the required minimum study period may vary in duration. General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain Department of Mathematics and Computer Science Groene Loper 5, 5612 AZ Eindhoven P.O. Box 513, 5600 MB Eindhoven The Netherlands Series Title: Master graduation thesis, Embedded Systems Power modeling and analysis of Commissioned by Professor: exascale systems prof.dr. H. (Henk) Corporaal Group / Chair: Electronic Systems Date of final presentation: by August 15, 2016 Date of publishing: Author: Sandeep Poddar August 31, 2016 Student id: 0926459 Report number: (Optional for groups) Internal supervisors: prof.dr. H. (Henk) Corporaal External supervisors: ir.
    [Show full text]
  • DOME Microserver: Performance Evaluation of Suitable Processors R
    DOME Microserver: Performance Evaluation of suitable processors R. Clauberg and R.P. Luijten THE DOME MICROSERVER PROJECT WANTS TO IMPLEMENT A HIGH DENSITY HIGH ENERGY EFFICIENCY MICROSERVER FOR THE PLANNED SQUARE KILOMETER ARRAY RADIO TELESCOPE. THE PRESENT ARTICLE DESCRIBES THE PERFORMANCE EVALUATION OF SUITABLE PROCESSORS FOR THIS PROJECT. SPECIAL EMPHASIS IS ON THE ABILITY TO PROCESS WORKLOADS RANGING FROM SIMPLE WEB-SERVER TYPE TO COMPLEX CLUSTER TYPES WITH HIGH ENERGY EFFICIENCY. ……The DOME project [1] is a collaboration between IBM and ASTRON, the Netherlands Institute for Radio Astronomy, to develop a computing solution to the exascale requirements for data processing of the international “Square Kilometer Array” radio telescope. One sub-project is the development of low cost low energy consumption microservers for processing the huge amount of data generated every day. To achieve these goals we are developing a high density microserver enabled by a water cooling system [2] and a highly modular system to cover different classes of workloads [2] [3]. The system is built of node cards and baseboards. Node cards cover compute nodes, accelerator nodes, storage nodes, and switching nodes. Baseboards offer different interconnect fabrics for different classes of workloads at different cost levels. Figure 1 shows a block diagram of the microserver system. To achieve our low energy consumption goal we are looking specifically at system on a chip (SOC), multi-core processor solutions. SOCs reduce energy expensive inter-chip signaling and multi-core processors offer increased energy efficiency by running multiple cores at low frequency instead of one core at high frequency. However, the need to handle commercial applications requires processors with a 64-bit operating system.
    [Show full text]