INDEPENDENT RESEARCH Semiconductors 16th January 2018 Heading to another record year for equipment makers Semiconductors
ams BUY FV CHF82 This note is the opportunity for an in-depth analysis of the various Bloomberg AMS SW Reuters AMS.S technological developments unfolding in the semi-conductor industry Price CHF93.08 High/Low 109/31.05 Market cap. CHF7,858m Enterprise Val CHF8,506m and their impact on the players. We focus in particular on the equipment PE (2017e) 83.0x EV/EBIT (2017e) NS producers who, while often in the chipmakers’ shadow, are pioneers in
ASM INTL BUY EUR71 some innovative technologies. In our view, the current context of more Bloomberg ASML NA Reuters ASML.AS complex innovation places some equipment producers in an Price EUR57.98 High/Low 62.27/43.61 Market Cap. EUR3,612m Enterprise Val EUR2,684m unprecedented position to add value and reinforce pricing power. PE (2017e) 18.8x EV/EBIT (2017e) 24.7x Capital intensity is reaching a new record level for the industry. The ASML BUY FV EUR180 vs. 175 substantial wave of investment in 2017 seems to confirm that, following that Bloomberg ASML NA Reuters ASML.AS Price EUR149.35 High/Low 158.45/107.75 of mobile and the smartphone, the industry is embarking on a new era of Market Cap. EUR64,439m Enterprise Val EUR64,374m PE (2017e) 33.2x EV/EBIT (2017e) 28.1x artificial intelligence. Concretely, there is a plethora of underlying trends at work in terms of both technological architectures and industry hierarchies BE SEMICONDUCTOR BUY EUR91 Bloomberg BESI NA Reuters BESI.AS which are changing to respond to the new application needs and the Price EUR76.65 High/Low 76.65/33.28 difficulties surrounding innovation in the sector. We see the equipment Market Cap. EUR3 069m Enterprise Val EUR2 908m PE (2017e) 17,6x EV/EBIT (2017e) 13,6x manufacturers as best placed to benefit from these changes.
DIALOG SEMICONDUCTOR NEUTRAL FV EUR28 ASMI – Aligned with the industry road map. We see ASMI as enjoying Bloomberg DLG GR Reuters DLGS.DE Price EUR25.25 High/Low 51.264/22.214 a leadership position in ALD tools and, in this respect, the group should Market Cap. EUR1,929m Enterprise Val EUR1,174m benefit from the penetration of the 3D NAND technologies and the arrival PE (2017e) 9.4x EV/EBIT (2017e) 5.9x of 7nm. In view of this positive trend and the upside potential of 23% INFINEON BUY FV EUR26.3 Bloomberg IFX GY Reuters IFXGn.DE generated by our FV of EUR71, we are initiating coverage of the stock with Price EUR24.12 High/Low 25.28/16.295 a Buy recommendation. Market Cap. EUR27,408m Enterprise Val EUR26,298m PE (2017e) 24.5x EV/EBIT (2017e) 22.3x Besi – Buy what the industry needs. With a 75% market share in the MELEXIS SELL FV EUR55 FOWLP technologies and 50% of the installed base of TCB/TSV systems, Bloomberg MELE BB Reuters MLXS.BR Price EUR89.9 High/Low 89.9/68.5 in our view Besi looks to be the big winner in the accelerated adoption of Market Cap. EUR3,632m Enterprise Val EUR3,584m Advanced Packaging in the back-end. In addition to this expertise, the PE (2017e) 32.5x EV/EBIT (2017e) 27.9x company is positioned in sectors where advanced semi-conductor SOITEC BUY FV EUR70 components are seeing growth, like computing, automotive and mobile. In Bloomberg SOI FP Reuters SOIT.PA Price EUR66.8 High/Low 70.73/29 view of this positive momentum and the upside potential of 19% generated Market Cap. EUR2,095m Enterprise Val EUR2,029m PE (2017e) 55.1x EV/EBIT (2017e) 37.9x by our FV of 91 EUR, we adopt a Buy recommendation.
STMICROELECTRONICS BUY FV EUR21.9 ASML – Boosted by EUV start. Our conviction that ASML will benefit Bloomberg STM FP Reuters STM.FR from the increased adoption of EUV by the Tier 1s and the growth of the Price EUR19.99 High/Low 21.225/10.705 Market Cap. EUR18,213m Enterprise Val EUR17,884m Chinese players remains intact. We have updated our FV from EUR175 to PE (2017e) 21.3x EV/EBIT (2017e) 19.4x EUR180 and maintain our Buy recommendation. u-blox NEUTRAL FV CHF185 Bloomberg UBXN SW Reuters UBXN.S Price CHF211.6 High/Low 220.5/164.7 Market Cap. CHF1,472m Enterprise Val CHF1,365m Analyst: Analyst: PE (2017e) 29.1x EV/EBIT (2017e) 21.5x Dorian Terral Frédéric Yoboué 33(0) 1.56.68.75.92 33(0) 1 56 68 75 54 [email protected] [email protected]
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Table of contents Executive Summary ...... 3 1. Demystifying the industry ...... 5 1.1. Equipment manufacturers are promoters of growth ...... 5 1.2. Mapping ...... 6 2. Front-End: Moore’s law is dead, long live Moore’s law ...... 8 2.1. Not without difficulty, the race for scaling continues ...... 10 2.2. 7nm EUV: a shared objective, two strategies ...... 13 2.3. For want of nodes, architectures are proliferating ...... 17 2.3.1. A paradigm shift is currently under way ...... 17 2.3.2. Bridging the gap with a return to the 22nm ...... 19 2.3.3. The return of SOI for digital chips ...... 20 2.4. In Memory, three strategies are being deployed ...... 23 2.4.1. DRAM ...... 23 2.4.2. NAND ...... 25 2.5. In Analog, materials are the next big thing ...... 27 2.6. An environment favourable to the equipment manufacturers ...... 29 2.6.1. Logic – fewer players, more spending ...... 29 2.6.2. Memory – undersized production capacity...... 30 2.6.3. The focus on differentiating manufacturing technologies offers some players opportunities...... 31 2.6.4. China, national security is prompting the country to invest ...... 32 2.6.5. Spending on equipment setting new records...... 34 3. Back-End: Advanced Packaging is transforming the whole industry ...... 36 Technology basics – Traditional chip packaging process ...... 37 3.1. Wafer Level Packaging, a key packaging technology ...... 38 3.1.1. TSV and WLP, or when packaging is inspired by the Front-End ...... 38 3.1.2. At TSMC, FOWLP is used as a growth driver ...... 39 3.1.3. No shortage of FOWLP development ideas ...... 42 3.2. 3D integration is the new holy grail ...... 43 3.2.1. The first assemblies: board, modules, SoCs and other SiPs ...... 43 3.2.2. A first wave of innovation is visible with 2.5D modules ...... 44 3.2.3. 3D, the packaging of the future ...... 44 Industry insight – aveni depicts a need for innovation in manufacturing methods ...... 47 3.3. Ramifications: fading frontiers ...... 49 3.3.1. The cards have been reshuffled for the foundries, IDMs and OSATs ...... 49 3.3.2. The equipment manufacturers forced to choose sides ...... 50 4. Investment opportunities remain ...... 53 4.1. There is currently no premium on the equipment manufacturers ...... 53 4.2. Change in the momentum scoring system used to define Beta ...... 54 ASM International Fair Value EUR71 BUY Coverage initiated ...... 59 Supported by a changing industry ...... 59 ASML Fair Value EUR180 vs. EUR175 BUY-Top Picks ...... 89 Ideally positioned to capture the growth ...... 89 BE Semiconductor (Besi) Fair Value EUR91 BUY Coverage initiated ...... 91 Buy what industry needs! ...... 91 Bryan Garnier stock rating system ...... 119
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Executive Summary Moore’s law now seems to For the past few decades, technological development has been driven by Moore’s law although this have definitively slowed. effect now seems to have definitively slowed. This deceleration is owing to the ever-more and increasingly complex technological constraints on production, amplified by a growing and exacting requirement for high-performance electronic components. Furthermore, the ubiquity of electronics in our everyday lives is naturally leading to wider diversity in demand, and satisfying this while further reducing costs and improving component performance is impossible without major changes in architecture, materials and component encapsulation processes.
After years of investment sustained mainly by innovation in mobile, we are embracing a new era driven by artificial intelligence. The ramifications and implications of the development of artificial intelligence are multiple, and the advances made in this area are vital to the development of autonomous cars, and to the smart assistance, facial recognition and augmented reality functions increasingly offered on mobiles, connected objects and other applications.
All these afore-mentioned new applications require data centers in which the substantial mass of data is stored and most of the processing is carried out. The emergence of applications requiring artificial intelligence is such that we are seeing technological changes to servers at all levels: 1/ in chips, the processing power requirement is exploding and traditional CPUs are being replaced by GPUs or specialised chips like ASICs and FPGAs, 2/ the memory requirement is also seeing exponential growth with architecture problems in terms of both chip design and packaging and, lastly 3/ demand for analogue components is growing with the proliferation of sensors, particularly optical.
Admittedly, artificial intelligence is not the industry’s only catalyst, but this important theme, at the cross roads between several industries is, in our view, symptomatic of the major technological changes unfolding across the sector, particularly on advanced nodes, and helps to inform our understanding of component demand.
Front-end and back-end Upstream of all these technological changes, the front-end and back-end equipment manufacturers are equipment manufacturers working alongside the chipmakers to develop new architectures, production technologies and are pioneers in advanced encapsulation (or packaging) methods capable of meeting the need for high levels of performance and technologies. alleviating the difficulties with miniaturisation.
In the Front-End, the innovation momentum is slowing but capital intensity continues to increase. Although the number of IDMs and foundries able to afford leading-edge manufacturing facilities continues to decline, we note the 1/ ongoing growth in production capacity, for both new and old technologies, 2/ creation of intermediate technology nodes offering a compromise between cost and performance, and 3/ development of new architectures to circumvent the physical barriers linked to increasingly fine-tuned etching. All of the above factors provide a solid growth foundation for the equipment manufacturers best placed to help the fabs.
In the Back-End, the transformation under way is equally powerful and the growth opportunities greater still. Hitherto deemed to be a low-value-added activity, assembly and encapsulation currently offers solutions enabling the industry’s innovation rate to be maintained. Regrouped under the Advanced Packaging label, these new encapsulation technologies are becoming increasingly popular owing to the complexity of innovation in the industry’s advanced nodes and herald a new round of investment in new tools adapted to this technology, thereby creating a substantial new market for some equipment manufacturers.
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Although complex, we are convinced that this transformation offers opportunities for component manufacturers, and particularly equipment manufacturers. We have decided to initiate coverage of two new companies, ASM International and Besi, both exposed to the investment growth dynamic particularly in advanced nodes, each situated at the opposite end of the chain (front- end and back-end respectively), and both of which could benefit from this context.
ASM International
We are initiating coverage of ASM International (ASMI) with a Buy recommendation and a FV of EUR71. ASMI enjoys a leadership position in ALD tools, and we see the following short-term catalysts: 1/ another year of capex growth in the semiconductor industry, 2/ the penetration of the 3D NAND technologies and the arrival of 7nm which should benefit ALD and Epitaxy equipment, and 3/ an improving profile with the withdrawal from the back-end activities. Nevertheless, ASMI’s shares are trading on 2018e P/E of 14.9x, i.e. a discount of 16% compared to industry average of 17.8x.
BE Semiconductor
We are initiating coverage of Besi with a Buy recommendation and a FV of EUR91 (+19%). The company has a leadership position in Advanced Packaging equipment, and should benefit from the current context which is favourable to back-end technologies. After an excellent set of results for the first nine months of 2017, the company should be supported in the short term by positive expectations regarding both industry spending on equipment and the growth dynamic in the various end markets. These drivers of outperformance seem not to be fully priced in the current consensus.
ASML
Early in 2018, the success of EUV systems is no longer in doubt and all eyes are now on ASML’s ability, and that of its suppliers, to ramp up production of these new generation tools. The group is thus in a comfortable situation with an order book equipping all the EUV fabs through to the end of 2018e. With a buoyant context and a 2018 which should continue to see strong growth, we maintain our Buy recommendation and adjust our FV from EUR175 to EUR180.
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1. Demystifying the industry 1.1. Equipment manufacturers are promoters of growth For more than 40 years, the semiconductor industry has succeeded in maintaining an average annual growth rate of over 9%. This is explained by the penetration of technology into everyday lives and our ever-increasing dependence upon it. There have been a succession of underlying trends, the main ones being the adoption of personal computing and the development of the internet followed by the advent of mobile and, in particular, the smartphone. Currently it is the Internet of Things, Artificial Intelligence and Big Data which are giving us a glimpse of tomorrow’s world. Unlike many sectors, each new trend is added to its predecessors rather than replacing them. Consequently, although trends may succeed one another, electronic device production continues to grow.
Fig. 1: New waves of incremental innovation, leading to new technological challenges and creating new opportunities
Capital intensity increasing in logic, memory, and display
More semiconductor content in electronics
Value shifting to technology and electronics
Source: Gartner; Applied Materials; Bryan, Garnier & Co ests.
Within the semiconductor industry, the equipment manufacturers are at the heart of innovation and are benefiting as much as chipmakers from the move up-market applying for the past few decades.
In this report we position the different players within the industry, highlight the catalysts responsible for growth in the next few years and rank the companies most likely to benefit.
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1.2. Mapping Step Holistic Inspection Diagnostic/ USD5.7bn planarization Technology (LPT) Linear Processing Processing Linear Planarization (CMP) Planarization Chemical-Mechanical Chemical-Mechanical Chemical-Mechnanical Chemical-Mechnanical USD3.6bn Process Implant (Ion) Doping (Gas)Doping Thermal Annealing Diffusion/Ion implant (CVD) (PVD) (ALD) (MBE) Epitaxy Deposition / USD10.5bn Physical Vap. Dep. Dep. Vap. Physical Dep. Layer Atomic Electro-Chem. Dep. Electro-Chem. Chemical Vap. Dep. Dep. Vap. Chemical Molecular B. Epitaxy Epitaxy B. Molecular Rapid Thermal Proc. Dry Wet Strip & Clean FRONT-END [ USD42bn ] Multiple iterations USD12.3bn Etching Plasma Etch Plasma Reactive Ion Etching Ion Reactive EUV DUV Photolithography USD9.8bn Photoresist Spin-coating Sand CARTOGRAPHIE DES EQUIPEMENTIERS SEMI-CONDUCTEURS (1/2) SEMI-CONDUCTEURS EQUIPEMENTIERS DES CARTOGRAPHIE Engaving WithEngaving Laser Mask Manufacturing Mask Fusing High Purity High Fusing Silica WAFER MANUFACTURER WAFER Machine Czochralski Growth Czochralski Wafer Gringing Edge Wafer Manufacturing Bryan Garnier coverage STEPS MAKERS EQUIPMENT EQUIPMENT MARKET SIZE TECHNOLOGIES Source: Company Data; VLSI; Bryan, Garnier & ests. Co list. Garnier Bryan, VLSI; a non-exhaustive Data; Company Source: represents table This written. was document this date the at capitalisation market according their to order in bottom to top a decreasing ranked normally are listed, if Companies, Disclaimers:
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USD4.4bn Die Inspection Die Wafer Inspection Package Inspection Package Back-End Metrology Metrology & Inspection TEST [ USD4.4bn ] USD4.4bn TEST [ Lithography USD0.2bn Back-End Lithography AP Plating USD0.03bn BACK-END [ USD8.8bn ] USD8.8bn [ BACK-END Dicing Mounting Blade Dicing Dicing Laser USD1.2bn Plasma Dicing Plasma Backside Grinding Backside Package Singulation Package ASSEMBLY [ USD4.4bn ] USD4.4bn [ ASSEMBLY Packaging USD0.8bn Molding & Sealing Finishing &Finishing Marking Package Inspection Package TSV] Bonding Die Attach Die Wire Bond USD2.1bn Advanced Packaging Advanced MAPPING THE INDUSTRY - SEMICONDUCTOR EQUIPMENT MANUFACTURERS (2/2) [Flip Chip, fan-in Chip, [Flip WLP, FOWLP, Bryan Garnier coverage STEPS STEPS / SOLUTIONS STEPS EQUIPMENT MAKERS EQUIPMENT MARKET SIZE Source: Company Data; VLSI; Bryan, Garnier & ests. Co list. Garnier Bryan, VLSI; a non-exhaustive Data; Company Source: represents table This written. was document this date the at capitalisation market according their to order in bottom to top a decreasing ranked normally are listed, if Companies, Disclaimers:
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2. Front-End: Moore’s law is dead, long live Moore’s law The numerous upheavals taking place within the industry reduce our visibility on the opportunities currently offered to the equipment manufacturers.
To date, the technological changes in the semiconductor industry have unfolded at a frantic pace giving rise to a new technology node (an array of manufacturing techniques) roughly every 18 to 24 months. These have been made possible by the strong growth in consumer products like smartphones.
However, this frenetic race to miniaturisation and power defined by Moore’s law inevitably seems to be tending to become asymptotic and for several years we have been witnessing a slowdown in the rate of innovation due to the growing difficulty in developing ever-finer-tuned scaling technologies.
At the same time, these additional efforts are leading to a rise in chip manufacturing costs and a slowdown in the adoption of new technologies across the industry.
While this situation is by no means recent, we believe that it has become more pronounced of late. Even if the quest for increasingly reduction in scaling continues, its deceleration has given birth to two distinct new innovation trends:
The development of new transistor architectures. This involves new transistor construction techniques enabling them to, either 1/ tolerate a new phase in size reduction, and/or 2/ respond more effectively to the multiplication of application areas for which various optimisations are required, and unaddressed by the creation of new nodes.
The creation of intermediate nodes. These are created to respond in an optimal manner to the performance needs of a high proportion of integrated circuit designers while resolving issues surrounding the relentless rise in transition costs they are facing (exponential growth in design and manufacturing costs).
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Fig. 2: Trend in manufacturing costs associated with technological leaps
5 4.01 4
2.82 -68% 3 1.94 +21% 2 1.55 1.28 1.42 1.31 1 Cost per (in 100M gate USD)
0 90nm 65nm 40nm 28nm 20nm 16/14nm 10nm
Source: International Business Strategies Inc.
Within this context, the equipment manufacturers are thus having to contend with different development waves to which they need to adapt. In addition to the creation of new factories to meet the growing demand for electronic components, one of the major factors in the health of the equipment manufacturers had hitherto been the steady succession of technology nodes. Other factors must now also be considered to evaluate the opportunities for the equipment manufacturers. Their industrial expertise (level of the production chain at which their equipment operates) is increasingly important when it comes to discerning the underlying dynamic for individual equipment manufacturers.
To add another layer of complexity to this picture, we are seeing the emergence of new classifications which no longer respond to actual changes in transistor size (synonymous with new nodes) but to the use of new architectures such as finFET and SOI. This trend in response to a commercial imperative makes it more difficult to compare products between equipment manufacturers.
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2.1. Not without difficulty, the race for scaling continues In recent years, companies like TSMC, Samsung and GlobalFoundries have fought to maintain their leadership positions within the ultra-competitive foundries market. This war has intensified to such an extent that even Intel, the historic king of the sector, has allowed itself to be overtaken.
Fig. 3: Fewer and fewer players can afford leading-edge fabs
Number of Players with a leading edge fab
25 Mitsubishi Sanyo Rohm ON Hitachi Atmel ADI 18 Sharp Sharp Cypress Cypress Sony Sony Infineon Infineon 13 13 TI TI TI TI Toshiba Toshiba Toshiba Toshiba Freescale Freescale Freescale Freescale SMIC SMIC SMIC SMIC Even the kin g Renesas Renesas Renesas Renesas Intel is laggin g Fujitsu Fujitsu Fujitsu Fujitsu 8 behind in the node race ! Panasonic Panasonic Panasonic Panasonic Panasonic UMC UMC UMC UMC UMC STM STM STM STM STM 5 IBM IBM IBM IBM IBM IBM 4 AMD AMD GloFo GloFo GloFo GloFo GloFo 3 Samsung Samsung Samsung Samsung Samsung Samsung Samsung Samsung TSMC TSMC TSMC TSMC TSMC TSMC TSMC TSMC Intel Intel Intel Intel Intel Intel Intel Intel 2002-2003 2006-2008 2008-2012 2010-2012 2012-2014 2014-2015 2016-2017 2004-2006 (90nm) (130nm) (65nm) (45/40nm) (32/28nm) (22/20nm) (16/14nm) (10nm)
Source: Bryan, Garnier & Co.
Whereas the costs of migrating to a new node are growing exponentially, being a first mover in the new manufacturing technologies is also increasingly important. The first player to offer a new node has more chance of dominating this new market and ensuring that its equipment is profitable. In the last twenty years, amongst the foundries, TSMC has been one of the best at this game. However, Samsung continues to put up a good fight as seen recently with its 14nm LPP/LPC technology. For its part, GlobalFoundries is lagging slightly on the 14nm although the former AMD fab is boasting an aggressive road map for the next few years.
Last March, TSMC and Samsung announced the launch of 10nm mass production, with the latter even communicating that 70,000 wafers of 10nm FinFET (10LPE; an early version) had already been produced. At Samsung, 10nm manufacturing had already started back in September 2016 but we expect the number of designs for 10nm to have remained limited to date as February 2017 was the real launch month for 10nm with the arrival of the Samsung Galaxy S8. Compared with 14LPP production which had, until that point, been Samsung’s leading-edge process node, the 10LPE technology enables a c.30%
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Semiconductors reduction in energy consumption and chip size, factors that are particularly important for smartphone manufacturers. Nonetheless, this new 10nm manufacturing process is seen as particularly resource-intensive since it uses up to three lithography/etch stages (called Litho-Etch Litho- Etch Litho-Etch and LE3) for the critical layers.
In November 2017, Samsung also announced the mass production of the second generation of the 10nm known as 10LPP (previously unveiled in March 2017), which will enable developers of chip to reduce power consumption or increase performance compared to the first generation 10nm (10LPE). Based on the road map of the previous nodes, we expect the launch of third and fourth versions, known respectively as 10LPC and 10LPU, which should further improve the PPA (performance, power, area) characteristics.
Fig. 4: Really launched in 2017, Samsung’s 10nm has numerous advantages versus the 14nm
GloFo Samsung
7nm DUV 14LPP 10LPE 10LPE 10LPP 10LPU 8LPP vs 14LPP vs 28LPP vs 14LPE vs 14LPE vs 10LPE vs 10LPE vs 10LPP
Power >60% 60% 40% 30% ~15% unknown 10%
Performance >30% 40% 27% >10% ~10% unknown unknown
Area Reduction >50% 50% 30% 30% none unknown 10%
Source: Samsung
At TSMC, we estimate that 10nm production began in May 2017 with the launch of two new iPad generations and their dedicated processor, the Apple A10X Fusion. In the Taiwanese company, the first 10nm production generation is dubbed CLN10FF. However, the real production ramp-up started in the 2017 second half with the arrival of the new A11 iPhone processors feeding the iPhone 8 and X.
TSMC expects 10nm to contribute around 10% of its total sales in respect of fiscal year 2017. Via its GigaFabs 12 and 15 fabs, the Taiwanese company hopes to deliver more than 400,000 10nm wafers in 2017. Compared with TSMC’s 16nm technology, the new 10nm generation should enable a-more-than 50% reduction in chip size, a 20% improvement in performance and a 40% reduction in energy consumption. For the moment, there is no question of a multiplication of 10nm generations at TSMC. The group should rather focus on the very rapid development of 7nm production.
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Fig. 5: At TSMC, the 10nm offers a 20% performance uplift vs the 16nm
TSMC
16FF+ 16FF+ 10FF 7FF 7FF vs 28HPM vs 20SOC vs 16FF+ vs 16FF+ vs 10FF
Power 70% 60% 40% 60% <40%
Performance 65% 40% 20% 30% unknown
Area Reduction ~50% none >50% 70% >37%
Source: TSMC
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2.2. 7nm EUV: a shared objective, two strategies In a relatively unprecedented fashion, the foundries have different visions regarding the production of a new node. We are seeing very different timelines and strategies for setting up 7nm EUV production, the industry’s common medium-term objective.
On one side, there is Samsung who has decided to launch 7nm production only once the EUV equipment is ready for mass production. In the other camp, TSMC and GlobalFoundries have opted to invest in the development of 7nm DUV production and to deploy this as rapidly as possible then, in a second stage, to adopt the EUV technology as soon as it is available.
As of the date this note was written, we understand that TSMC is only just entering risk production, the group having been entrusted with several chip designs for testing. If all goes well, volume production is expected to start during the second quarter of 2018 and we should see the first consumer devices equipped with 7nm chips as of the 2018 second half. Compared with TSMC’s 16nm, this 7nm production node should enable a 70% reduction in chip size (at a constant number of transistors), a 60% reduction in energy consumption and a 30% increase in frequency.
TSMC’s second 7nm generation should thus arrive once the EUV tools have been deemed sufficiently high performance for mass production. At this stage, the Taiwanese foundry’s customers who are looking to use this production technology will need to embark on a new development phase to adapt some of their chip design layers to more aggressive design rules. However, this additional development investment should be offset by production cost savings thanks to the deployment of EUV tools which reduce the number of manufacturing stages.
Fig. 6: EUV delivers lower cost for complex patterning
Source : ASML
TSMC plans to launch EUV production testing as of the second quarter of 2018, meaning that volume production is likely to begin during the 2019 second half.
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Fig. 7: The 7nm EUV will be 10% more efficient than the 7nm DUV at TSMC
TSMC
7FF 7FF 7FF EUV 5FF EUV vs 16FF+ vs 10FF vs 7FF vs 7FF EUV
Power 60% <40% 10% lower
Performance 30% unknown lower higher
Area Reduction 70% >37% ~10-15-20% tangible
HVM Start ~Q2 2018 - ~H2 2019 ~H2 2020
Source: TSMC
In summary, the 7nm node should mark the EUV’s real commercial launch. This is the contrarian scenario we had argued back in 2015 when ASML maintained that the introduction of the EUV would take place in 10nm and the detractors were predicting the failure of the EUV. While slip-ups are still possible, we should see the first EUV chips on the market as of 2019. And as outlined previously, Samsung should be the first real user of EUV lithography for mass production.
This strategy does, nonetheless, involve some risks for Samsung. With risk production launched in the second half of 2018, mass production in 7nm EUV should begin as of the second half of 2019. To avoid being outpaced by its competitor TSMC, and for fear of lagging behind on EUV development, Samsung recently introduced two new intermediate nodes, the 8nm and the 6nm. In our view, the first is the most important. This intermediate node should enter mass production during the 2019 first half, i.e. shortly after the launch of TSMC’s 7nm DUV. We understand that this 8LPP at Samsung constitutes more of a development of the 10nm than a bona fide new technology node (i.e. the definition of an intermediate node). While Samsung is maintaining a low profile on this 8LPP, the group has nonetheless stipulated that it will use a DUV technology for its production.
At GlobalFoundries, the 10nm is out of the question. The foundry is already focusing on the 7nm, known as the 7nm Leading Performance (7LP), whose production launch is planned as of the second quarter of 2018 for ramp-up during the 2018 second half. Compared with the GF 14nm (whose R&D comes from Samsung), the 7LP should enable a 40% improvement in performance while further reducing chip size. Like TSMC, GlobalFoundries is preparing to launch 7nm production without EUV, prior to adopting the latter once it becomes available, i.e. probably in 2019. To plan for this, the group has also announced that it should receive two EUV tools from ASML during H2 2017. Given the delivery schedule announced during ASML’s Q3 results, we expect these tools has been delivered to GF during the Q4.
At Intel, the situation is less clear. The company is already falling behind on the 10nm whose launch is planned in early 2018 with its ‘Cannon Lake’ generation of processors, and the global number one (reportedly outpaced by Samsung this year thanks to the boost in memory sales) has yet to announce the exact timeline for the adoption of a 7nm manufacturing technology. On the other hand, the processor manufacturer has already announced that it will follow this with the launch of a new generation dubbed ‘Ice Lake’, still in 10nm.
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At this stage, Intel remains a fervent supporter of the EUV technology but has yet to announce a launch date. We understand that the processor manufacturer is seeking above all to make sure that the yields are satisfactory. In addition, Intel’s 10nm manufacturing process is delivering good results, a situation which does not encourage the semiconductor giant to be an early adopter of the EUV technology at any cost.
Fig. 8: The 7nm and EUV do not figure in Intel’s current road map
Source: Intel
To conclude, to arrive at the 7nm, there are currently as many strategies as players.
Fig. 9: Wrap up: as many strategies as players to arrive at the 7nm node
2017 2018 2019 2020 2016 2021 H1 H2 H1 H2 H1 H2 H1 H2
GlobalFoundries 14LPP 7nm DUV 7nm with EUV
14nm 14nm++ 10nm+ Intel 14nm+ 10nm 10nm++ 14LPP 8LPP Samsung 10LPE 10LPP 7LPP 6nm 14LPC 10LPU
SMIC 28nm 14nm in development
CLN16FF+ CLN10FF CLN7FF CLN12FFC/ TSMC CLN7FF+ 5nm CLN16FFC CLN16FFC CLN12FFC CLN12ULP
UMC 28nm 14nm no data
Source: Bryan, Garnier & Co ests.
In our view, the most advanced technology nodes like the 10nm, 7nm and 5nm in development, will continue to be mainly supported by sales of the advanced processors used in consumer devices like smartphones, computers, consoles and servers, as well as by fast-growing artificial intelligence applications.
Thus, the slowdown we are seeing in smartphone sales (+13.1% CAGR13-16 vs. +3.6% CAGR16-19e) could be offset by 1/ an increase in the value of the components per telephone, 2/ the development of
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connected cars, 3/ the Internet of Things, and 4/ data centres, all having artificial intelligence and mass storage (on flash memory) for their points in common as technological leverage. IDC also expects average cognitive system/artificial intelligence growth of 55.1% over the next three years to USD47bn (vs USD8.0bn in 2016).
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2.3. For want of nodes, architectures are proliferating While the fact that Intel does not rank amongst the industry leaders for innovation marks a break with the past, we also note a paradigm shift for production as a whole. Although the aforementioned players continue to invest billions of dollars in leading edge fabs, we are witnessing backsliding initiatives concerning production technologies. The aim being to meet the needs of a part of the industry which is primarily focusing on price and not performance.
This also involves a break with past models, reflecting major changes in the conception of technological innovation at the level of the nodes and their financial considerations suggested by Moore’s law.
Whereas production of 10nm is booming in 2017 and the industry leaders are now looking at the deployment of 7nm production (or even 5nm), it is interesting to note that ≥40nm still exceeds 50% of global production.
These older nodes remain very much in use for diverse applications, notably for the production of semiconductors like power components, image sensors and chips bound for the Internet of Things.
Fig. 10: ≥40nm production remains predominant, even at the foundries
70. 0
60. 0
50. 0
40. 0
30. 0
20. 0
Foundry market USD) billions (in market Foundry 10. 0
0.0 2015 2016 2017 2018 2019 2020
≥0.25µm 0.18/0.15µm 0.13µm 90nm 65nm 45/40nm 28nm 22/20nm 16/14nm 10nm 7nm ≤5nm
Source: International Business Strategies Inc.
2.3.1. A paradigm shift is currently under way For many years, the semiconductor industry based the bulk of its industrial development on the migration from one technology node to another. In addition to the gains in performance contributed by the new nodes, the scale of the leaps was such that the reduction in transistor size led to a significant decline in transistor manufacturing costs per wafer (more transistors/capacitors per wafer). This fall in manufacturing cost was then a key factor in the rapid adoption of new technologies.
Currently, the transition to nodes below 28nm requires more complex research and development which takes longer and is more expensive, for both chip design and manufacturing. In short, the fabs are having to contend with:
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An explosion in design costs: Gartner estimates the cost associated with the migration from 10nm to 7nm for the chipmakers at around USD271m, i.e. 3.4 times the cost of moving from 16/14nm to 10nm, and 9 times that of the preceding leap from the 28nm to the 16/14nm.
Fig. 11: Development costs of the advanced nodes
$271m
x 2.3
x 1.5 $120m
x 2.7 $80m
$30m
28nm 16nm/14nm 10nm 7nm
Source: Gartner; Bryan, Garnier & Co ests.
Ever-higher manufacturing costs: below 28nm, the increasing complexity of the manufacturing techniques required to achieve reduction in scaling has led to an increase in manufacturing costs. Transistors manufactured in 10nm are thus around 20% more expensive than a transistor in 28nm (Fig 2).
In an environment where innovation takes longer and is more expensive, and where many players continue to use old technologies, the leading foundries are being forced to revisit their strategies to create still more value. To respond to the imbalance between performance needs and increased manufacturing costs below 28nm, we are seeing innovation directed at the creation of intermediate nodes and the accelerated development of alternative architectures like FD-SOI.
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Fig. 12: Different applications, differents stages, a sweet-spot for the industry
Performance driven transitions; high volume chips only
Industry sweet spot
Performance & costs driven transitions
Source: TSMC; Bryan Garnier & Co ests.
Thus, while innovation focused solely on transistor miniaturisation no longer meets the needs of a part of the industry, some players have spotted an opportunity. Firstly, given the fact that many players do not require the performance uplifts offered by the new nodes and, secondly, because there is a diversification move under way in complex applications with the growth in connected objects, autonomous car systems and artificial intelligence in data centres, which are showing specific optimisation needs.
A better response to this application diversification can be found in the differentiation/segmentation of innovation through technological architectures. These new architectures enable the improved segmentation of chip designers’ needs in terms of energy consumption, space and performance, all at prices adapted to their financial situation.
In addition to bringing better targeting of innovation, since they are compatible with several generations of nodes, these industrial processes can be applied to a wider spectrum of customers. They also require a lower level of foundry reorganisation than that involved in the transition from one node to another.
2.3.2. Bridging the gap with a return to the 22nm We are currently seeing a common trend amongst the three leading foundries involving a focus on technology nodes dating back several years, aimed at capturing a Tier-2/Tier-3 customer base. With ever-higher development and manufacturing costs due to increasingly downscaling, part of the industry has embarked on a quest for an alternative solution.
After the commercialisation of the 16/14nm and the 10nm, the ‘back-pedaling’ to the 22/20nm is thus seeking to fill a commercial vacuum created by the latent need for a so-called ‘intermediate’ node in response to chipmaker appetite for greater efficiency, associated with a more affordable level of investment compared with the 16/14nm and 10nm.
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Furthermore, the interest of the 22/20nm lies in its compatibility with the planar geometries used until now, i.e. the 28nm and earlier. This enables the integrated design circuits to be fairly-effortlessly adapted to a new, more-advanced form of production, while maintaining R&D expenses at an acceptable level. The IP libraries are thus more numerous and time-to-market can be kept to a minimum.
Amongst the major foundries, GlobalFoundries and Samsung offer chip manufacturing in 22nm and 18nm FD-SOI respectively, and TSMC plans to add production using a bulk planar structure to its catalogue. Intel has opted for FinFET solutions which prioritise low energy consumption but require more radical design adaptation since this form of manufacturing implies the adoption of a three- dimensional architecture. Each of these foundries will thus potentially be exposed to different markets.
2.3.3. The return of SOI for digital chips The Silicon On Insulator (SOI) technology, known especially through the SOI wafer manufacturer, Soitec (Buy, FV EUR70), enables an improvement in transistor performance thanks to a thin insulating layer (i.e. substrate) applied directly on the wafer. This technology mainly targets digital chips and radio-frequency chipsets (RF).
SOI production of 300mm (for digital) enjoyed its heyday when it enabled AMD to win market share from Intel during the early 2000s, reaching a market share of 50% in 2006. During this period, SOI for digital was mostly seen as a more expensive technology than traditional manufacturing but one that enabled enhanced performance. It then went into a long decline linked to 1/ decelerating momentum for AMD relative to Intel, and 2/ the absence of a growth relay since few players aside from AMD, IBM and Microsoft (for the Kinect on the Xbox 360) launched SOI production lines for digital chips. These days SOI 200mm wafers nonetheless remain widely used in the manufacturing of chips destined for connectivity (nearly 100% of RF systems use components produced on 200mm SOI wafers) and we are seeing renewed interest in 300mm SOI wafers with FD-SOI, replacing the historic PD-SOI.
Amongst Soitec’s customers, the most well-known are GlobalFoundries, Samsung and STMicroelectronics (Buy, FV EUR21.9). FD-SOI production is often compared to bulk CMOS FinFET although these two technologies address different markets and are not direct competitors.
finFET for applications that are resource-hungry in terms of processing power. finFET’s 3D structure is optimal for managing the conductivity of the electric current, making it the technology par excellence for applications banking on computing performance. However, the performance gain delivered and the cost incurred in the transition to FinFET mean that it is not suitable for all applications.
SOI is targeting the other (numerous) applications. FinFET currently addresses a fairly limited customer typology even if it is responsible for some high-volume orders. These days, most chips remain manufactured on ≥28nm nodes (Section 2.3, Fig. 10) and FD-SOI is targeting just this kind of chip: chip designers prioritising a good balance between reduced energy consumption and enhanced transistor performance without necessarily requiring the level of performance delivered by FinFET. For example, the advantages coming from the SOI technology are positive for the development of connected objects which are accomplishing ever-more-complex tasks with a relatively small format and battery. The construction of SOI wafers also makes them very appropriate for increasing the reliability of chips bound for automotives. These are two market segments which are particularly fast-growing currently.
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A cheaper solution. SOI wafers reduce the complexity of the manufacturing process and increase the production yield compared with the FinFET technology. GlobalFoundries’ 22nm FD-SOI process (22FDX) requires 38 layers of lithography, i.e. 30-40% fewer than the 16/14nm FinFET process (c.60 stages of lithography), like 12FDX compared with 10nm finFET. Furthermore, since FD-SOI is a planar manufacturing process, it doesn’t require revising the entire chip design but only its partial adaptation.
A highly versatile technology. The interposition of a thin layer of silicon oxide (buried oxide) between the outer layer (channel) and the silicon substrate increases the electrical intensity thresholds tolerated by the transistor compared to bulk silicon. Thus, depending on the stimulation potentially realised on the reverse of the wafer via reverse body biasing and forward body biasing, it is possible, respectively, to either regulate leakage (reduce consumption) or enhance chip performance (to the detriment of energy consumption).
Fig. 13: Design of a FD-SOI transistor
Body Biasing
Source : Soitec
An optimised solution for connectivity applications. 3D structures like FinFET suffer from parasitic resistance and capacitance (RC) which limits the performance of connectivity applications (bluetooth, wifi, cell phones, etc.). It is thus very difficult, or even impossible, to produce an application processor, the memory and an RF module on the same die. This type of design is, however, perfectly credible in planar structure such as SOI.
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Fig. 14: GlobalFounderies offers a wide range of applications based on Soitec’s SOI technology
Source: GlobalFoundries
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2.4. In Memory, three strategies are being deployed In the memory segment, we are also witnessing a major upheaval in manufacturing technologies. On one side stands DRAM memory production which is suffering, with a slight delay, from the same ills as logic chip manufacturing. On the other side, the Flash NAND memory manufacturers have adopted an innovative strategy and have temporarily managed to get around the problem of horizontal density (transistor downscaling) by developing 3D memory architectures. In the two cases, and unlike the Logic players, the visibility on the road maps of the various memory producers remains very limited.
2.4.1. DRAM Few world players are currently capable of producing DRAM memory. Amongst the leaders are Samsung, Micron (including Elpida) and SK Hynix.
Fig. 15: A handful of players share the DRAM market
21%
29%
46%
1Q14 2Q14 3Q14 4Q14 2014 1Q15 2Q15 3Q15 4Q15 2015 1Q16 2Q16 3Q16 4Q16 2016 1Q17 2Q17 3Q17
Samsung SK Hynix Micron Group Others
Source : DRAMeXchange
Amongst these three players, Samsung is currently the leader in terms of the adoption of new production technologies. The group launched production of 1x nm DRAM chips (18nm equivalent) as of the end of 2016. Its 1x DRAM memory manufacturing should not be running at full speed. By 20 December 2017, Samsung has even announced that 1y nm DRAM memory production (16/15nm equivalent) has started.
At SK Hynix and Micron, the most advanced DRAM memory (DDR4/LPDDR4/ LPDDR4X/GDDR5/GDDR5X/HBM2) is produced using 20/21nm respectively. The launch of 1x DRAM memory has have taken place during Q4 2017 for the former, and should take place during the first quarter of 2018 for the latter. Nanya is bringing up the rear, having launched its 20nm production only very recently.
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Fig. 16: Summarised road maps of the leading DRAM players
2013 2014 2015 2016 2017 2018
H1 H2 H1 H2 H1 H2 H1 H2 H1 H2 H1 H2
46/35nm 25nm 20nm 18nm 16/15nm Samsung (DDR3) (DDR3/DDR4) (DDR4/LPDDR4/LPDDR4E/GDDR5/HBM2) (1x) (1y)
42/30nm 25nm 20nm Micron 1x nm (DDR3/DDR4) (DDR3/DDR4) (DDR4/LPDDR4/GDDR5/GDDR5X)
29nm 25nm 14LPP 21nm 18nm SK Hynix 1y nm (DDR2/DDR3/HBM1) (DDR3/DDR4/LPDDR4) 14LPC (DDR4/LPDDR4/LPDDR4X/GDDR5/HBM2) (1x)
Nanya windbond 50/42nm 42/30nm (DDR3/DDR4/LPDDR4) 20nm
Source: Tech Insights; Bryan, Garnier & Co ests.
2016 proved a particularly difficult year for the DRAM equipment manufacturers. Several players like Applied Materials and ASM International noted investment in DRAM at a very low level, having seen a double-digit decline, and equipment orders for the development of 1x DRAM were postponed.
In 2017, a significant uptick in demand has forced memory designers to invest more and IC Insights forecasts an increase in capex to USD13 billion (+53% yoy) and USD19 billion (+33% yoy) for DRAM and NAND respectively. The strong growth recorded for DRAM versus flash memory (NAND) needs to be seen within the context of a very low comparison base for the former and, inversely, rapid 2016 growth in excess of 20% for the latter. Most DRAM capex for 2017 is coming from the upgrading and conversion of the installed base and not from increased manufacturing capacity. Only SK Hynix has announced a 3% to 5% expansion in it DRAM production capacity in 2017 with a new fab at Wuxi in China which delivery took place during the fourth quarter of 2017. At the same time, the company also stipulated that the upgrading of the production chains had not been sufficient to satisfy demand.
The memory players have thus widely prioritised NAND memory to the detriment of DRAM in their factory expansion plans. We explain this phenomenon by the strong demand for 3D NAND on which all the players have been lagging behing relative to Samsung. According to DRAMeXchange, 3D- NAND memory should represent up to 50% of NAND memory in 2017, and 70% in 2018.
In conclusion, the challenges facing the equipment manufacturers are similar to those in the Logic segment, namely, the ongoing quest for increasingly reduction in geometries with, however, a certain lag relative to the Logic segment. In our view, the significant dichotomy between supply and demand in DRAM, and the addition of capacity at SK Hynix in 2017 are likely to encourage its competitors to follow suit as of 2018 to protect their market share. The equipment manufacturers should thus benefit more from this than in 2017, and the best placed are likely to be those present in the multi-patterning required for 1x DRAM development.
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2.4.2. NAND As for DRAM memory, the NAND memory market is controlled by a handful of players.
Fig. 17: Three players share nearly three-quarters of the NAND memory market
10% 12%
17%
18%
37%
1Q14 2Q14 3Q14 4Q14 2Q15 3Q15 4Q15 1Q16 2Q16 3Q16 4Q16 1Q17 2Q17 3Q17
Samsung Toshiba WDC Micron SK Hynix Intel
Source : DRAMeXchange
In this market segment, the adoption of 16nm or even 14nm production began as of 2014. However, the players are now facing insurmountable obstacles in terms of increased horizontal density (shrinking transistors’ size). They have thus opted for memory production by layer. Since 2015 we have thus witnessed the rapid emergence of NAND memory production in 32 layers, followed by 48, 64 and even 72 layers, while Samsung, Micron and Toshiba have just launched 64-layer production. For its part, SK Hynix plans the launch of 72-layer production during the fourth quarter of 2017.
Here the innovation challenges are no longer those of fine-tuned etching but rather the players’ ability to upgrade their production lines enabling an increase in the vertical density of NAND memory chips. The next stage consists of deploying 96-layer production, with a launch widely expected in 2018.
For the equipment manufacturers, the priority is thus to meet the need for a very specific type of manufacturing which consists of stacking (deposition) and etching each of these layers with the highest- possible level of precision. It will be the players capable of supplying high-precision deposition tools which stand to benefit the most from this trend, i.e. the manufacturers of Metal-Organic Chemical Vapor Deposition (MOCVD), Plasma-Enhanced CVD (PECVD) and Atomic Layer Deposition (ALD) tools. The largest being Applied Materials, Tokyo Electron, ASM International, Veeco and Lam Research (see introductive Section “Mapping” for more details).
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Fig. 18: Very similar stacked structures at all the players
Source: Tech insights
Furthermore, NAND memory is also currently being penalised by a dearth of production capacity. This shortage has existed since the end of 2016 and is leading to soaring memory chip prices. All the players have thus launched plans to build new fabs.
For example, we note that SK Hynix plans to increase the production capacity of its M14 fab and build a new fab for NAND memory at Cheongju in South Korea. Chinese company YMTC plans to invest USD24bn in building three fabs specialised in 3D NAND, the first to come on line during 2018 with a capacity of 300,000 wafers. Samsung, the leader with a market share of more than 35%, plans to expand the production capacity of its 3D V-NAND fab open since 2014 in Xian in northern China with a budgeted spend of USD7bn over the next three years. Note that, following the sale of its memory activities to a consortium led by Bain Capital, the future of Toshiba’s 3D NAND Fab 6 manufacturing facility foreseen for 2019 is very uncertain.
Fig. 19: Summarised road maps of the leading NAND players
2014 2015 2016 2017 2018 2019 2020 H1 H2 H1 H2 H1 H2 H1 H2
2D NAND
Samsung 19nm 16nm 14nm
Toshiba 19nm-Y 15nm_1st 15nm_2nd Western Digital Micron Intel 16nm im Flash Tech
SK Hynix 16nm 14nm 12nm
3D NAND
Samsung 32L 48L 64L 92L 128L
Toshiba 48L 64L 96L 128L Western Digital Micron Intel 32L 64L (Gen2) 96L (Gen3) 128L im Flash Tech
SK Hynix 36L (V2) 48L (V3) 72L (V4) 96L (V5) 128L
Source : Tech insights
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2.5. In Analog, materials are the next big thing In some circumstances, silicon-based technologies are reaching their performance limits, particularly in applications operating in hostile environments or extreme conditions, and for Analog components. This is why we see the industry gradually turning to new substrates like gallium nitride (GaN) and silicium carbide (SiC) which improve the performance of some types of components, and notably power semiconductors.
In power applications, the characteristics and performance of semiconductors are measured as a function of the electric voltage (or the power expressed in watts), the commutation frequency in hertz and the temperature they can withstand. And yet these limits are soon reached for transistors on silicon like power MOSFETs and IGBTs, and the reduction in transistor size is no longer likely to suffice to optimise performance. It is thus vital to turn to other types of substrata like GaN and SiC which enable an improvement in component performance in return for a higher cost of manufacturing.
Transistors on silicon like power MOSFETs and IGBTs have limited physical properties. The power MOSFET is used for applications requiring a voltage of between 10V and 500V, and can go up to 900V in its super-junction version. The IGBT can withstand voltages of between 400V and 10kV. But, more importantly, these technologies on silicon have a bandwidth of around 1.1eV, a parametre which determines the degree of conductivity and, consequently, the level of dispersal of the heat generated by the system (note that the heat generated by the electric circuit is synonymous with energy leakage).
On this point, GaN and SiC are two alloys with wider bandwidth of, respectively, 3.4eV and 3.3eV. Thanks to this property, components produced on GaN and SiC will give off much less heat and deliver a higher level of performance. GaN and SiC can withstand voltages of between 30V and 600V for the first and 600 and 10kV for the second.
Fig. 20: Positioning of the different technologies in 2023
Source: Yole Développement
It is for this reason that we see market opportunities in automotives and industry. The components used in these segments operate at high power levels and the management of the heat they disperse becomes a major issue. According to research from Yole Développement, the Power IC market is likely
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to represent USD27 billion in 2016 and should grow by 4.0% in 2017e followed by 7.0% in 2018e (16- 20 CAGR of 4.4%), driven mainly by the automotive (CAGR16-20 c. 12%), industrial (16-20 CAGR c.9%), and communications (16-20 CAGR c. 5%) segments.
Fig. 21: Trend in the Power Devices market
4.4% CAGR 16-20 30. 0
20. 0
10. 0
0.0 2016 2017 2018 2019 2020
Discr et es Power modules Power IC
Source: Yole Développement; Bryan, Garnier & Co ests.
There is an obvious and major arbitrage to be made between substrate cost and performance. The recent progressive move towards 300mm wafers in silicon for power components (notably at Infineon) accentuates the price differentials and applies a serious brake to the penetration of SiC and GaN which are still realised on 100mm and 150mm wafers. Nonetheless, changing needs and notably the adoption of electric motors for vehicles is leading to a growing interest in new power component manufacturing technologies. Until now, GaN and SiC wafers had been considered too expensive and component manufacturing using GaN and SiC had de facto been reserved for military and special applications. With the emergence of electric vehicles whose motors are battery powered, the need to optimise energy efficiency increases and the potential market is now sizeable.
Currently, GaN remains a niche technology with around 52,000 wafers manufactured annually and a market value that we estimate at USD55 million. With annual growth potentially set to average 10% over the next three to five years, GaN is likely to gain market shares on MOSFET (USD 6.1 billion, 16- 22 CAGR c. 3.4%) in mass market and high-added-value applications, however the cost of GaN continues to hold back its development. In our view, the companies which could benefit from the development of GaN over the long term are Infineon, STMicroelectronics, Texas Instruments, ON Semiconductor, the specialised division of Cree, Wolfspeed and even Dialog which has begun to collect samples of new products in GaN.
Inversely, silicium carbide is already justifying its use in very-high-electric-voltage and heat disperal environments like the automotive and wider industrial segments. SiC sales (USD246 million in 2016) are likely to increase more rapidly than those of IGBT (USD3.4 billion in 2016) with growth averaging a respective 28% and 10% between 2016 and 2020. Moreover, Infineon, STMicroelectronics and ON Semiconductor (via the acquisition of Fairchild) already offer SiC-based power components. The first and last are already well referenced in industrial applications (notably alternating and direct current converters for photovoltaic panels), while ST is blazing its own trail in automotive, a particularly attractive market.
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2.6. An environment favourable to the equipment manufacturers While the industry is currently moving in several directions, this trend is not unfolding at the expense of the equipment manufacturers – quite the reverse. The increased complexity of manufacturing is leading to an ever-greater dependence on the innovation realised by the equipment manufacturers. Thus, between a 28nm and 7nm fab, the capital intensity practically doubles. This trend also holds true in memory production, in both NAND and DRAM, but at different magnitudes of, respectively, +60% and +38%.
Fig. 22: Capital intensity is increasing for all forms of production
Device type Node Migration Capital Intensity Increase NAND Planar to 3D (64 layer) 60% DRAM 25nm to 16/14nm 38% Logic Foundry 28nm to 7nm 87%
Source: Applied Materials; Bryan, Garnier & Co ests.
Building a 7nm fab with capacity of 100,000 wafers per month thus currently requires investment of USD18 billion versus ‘only’ USD9 billion for a fab with similar capacity using 28nm.
Fig. 23: Capital intensity by type of manufacturing (for a new fab with capacity of 100k wafers per month)
Device type Capital Intensity (100k wspm greenfield) in USDbn 28nm 9 7nm 18 1y DRAM 6 3D NAND (64L) 6
Source: Applied Materials; Bryan, Garnier & Co ests.
2.6.1. Logic – fewer players, more spending The ongoing battle between the industry leaders, i.e. TSMC, Samsung, GlobalFoundries and Intel, remains supportive for the equipment manufacturers. It is mainly driven by demand from the large order givers, i.e. Apple, Qualcomm (subject to a hostile bid from Broadcom), MediaTek, AMD, Nvidia and other fabless Tier 1s for the foundries, and by competition from AMD and the manufacturers of ARM processors for Intel.
This is underpinning significant momentum within the four industry leaders. While risks have emerged as to demand for ageing nodes like the 16/14nm and soon the 10nm, we note that the latter remain very much in use despite the introduction of new geometries. As before, this form of manufacturing remains sought after by Tier 2/3 fabs who cannot afford state-of-the-art production (due to a lack of volume and pricing power) but who nonetheless have a substantial appetitite for performance.
Given the panel of players who continue to invest in advanced manufacturing and their solidity, in our view the reduction in the number of players capable of affording leading edge production has now reached its end. All now appear to have attained sufficient critical mass to enable them to pursue the race towards the future new technologies. And although Intel may currently be lagging, in our view it should rapidly catch up with a more-efficient architecture and, potentially, a more rapid migration to 5nm than its peers.
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Thus, in the logic segment, we expect the level of capex to fluctuate around its current levels. With the number of players in this segment stabilising, the market growth for the equipment manufacturers comes mainly from the need for more efficient, and thus more expensive, devices.
2.6.2. Memory – undersized production capacity In terms of production, 2017 was characterised by a sharp imbalance between the supply and demand of DRAM and NAND memories which was reflected in soaring memory prices estimated at +77% and +38% respectively (source IC Insights) for the year. We see several factors behind this phenomenon.
The first being a boom in memory applications – The booming demand is explained by 1/ the adoption of the flash memory disk (SSD) in datacentres and personal computers, and 2/ the ongoing increase in storage capacity and DRAM memory embedded in smartphones.
Slower migration towards the new technologies – In our view the industry is facing innovative difficulties owing to the limits encountered in transistor miniaturisation. We have seen, firstly, low DRAM bit growth in recent years and, secondly, the NAND producers, except Samsung, have been having problems with their transition to 3D NAND.
Investment in new production capacity has remained limited in recent years with the situation only now becoming unblocked. To increase the production of memory applications, new fabs are currently being built but the latter are unlikely to come on line before 2019. We expect an increase in equipment orders towards the end of 2017, and in 2018 on the back of the replacement of current equipment and procurement for new fabs.
According to IC Insights, 24% of the investment in equipment in 2017e, i.e. USD19.4 billion, is likely to be destined for NAND flash memory. The growth in equipment investments for NAND and DRAM is estimated at 57% in 2017 compared with 2016. Samsung plans to open two new fabs, of which one specialised in DRAM in Pyeongtaek, South Korea, and the second in V-NAND (3D structure) production. The other main players in the sector, like SK Hynix, Micron and Toshiba, are also planning to open new fabs.
In the memory segment, the main driver of equipment demand should thus be the growth in manufacturing capacity and not the technology shift itself.
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2.6.3. The focus on differentiating manufacturing technologies offers some players opportunities If one thing remains true for the sector, it is that the semiconductor market is seeing steady growth (average annual growth of 9% over more than 40 years). Component demand is even more significant, imposing an automatic and quasi-permanent constraint on manufacturing.
The various manufacturers are doing battle in R&D to maximise the yield on their fabs before taking any decisions regarding extensions and, eventually, launching plans to build new fabs. There are thus two ways to engineer a significant improvement in chip manufacturing capacity: 1/ R&D investment in manufacturing processes to improve the production yield, and 2/ investment in new production tools. We have already seen that the Logic segment is currently focusing on new technologies whereas the memory segment needs to build new fabs.
For the equipment manufacturers, these two factors are well known and widely anticipated. However, we also note that 1/ the increasing complexity involved in maintaining the rate of change in the industry, 2/ the paradigm shift bringing old production technologies back into focus, and 3/ the development of new materials are all impacting the equipment manufacturer universe.
We don’t, however, believe that the change is synonymous with danger for most of the equipment manufacturers. More specifically, we see this environment as positive for the development of:
EUV developed by ASML. Our estimates show EUV equipment sales approaching USD6 billion in 2020 compared with c. USD400 million currently, i.e. a quasi-doubling in the market every year. However, this should not prevent the company from continuing to generate sales from DUV equipment, given the slowdown in the adoption of new nodes and the still-widespread use of old technologies.
Etching tools for memory. Deposition and etching are estimated to represent 60% of equipment expenditure in 3D NAND versus 34% for 1x nm NAND. It is worth noting that, according to Gartner, nearly two-thirds of the growth in capex for the semiconductor industry should be linked to flash memory between 2015 and 2019. This is likely to benefit the etch and deposition equipment leaders, namely Tokyo Electron, Applied Materials, Lam Research and Veeco.
Precision deposition tools like Atomic Layer Deposition (ALD). We estimate ALD equipment sales of approaching USD1.5 billion in 2020 versus around USD700 million in 2016, i.e. average growth of 21% over the period. This growth should be driven by 1/continuing shrinkage in transistor size in logic chips then DRAM memory chips, leading to additional manufacturing complexity, and 2/ the adoption of 3D architecture in NAND storage memory. The equipment manufacturers active in this segment are ASM International, Tokyo Electron, Lam Research, Wonik IPS, Jusung and Aixtron.
Deposition tools. As for ALD, we expect CVD techniques to benefit from 1/ the growing complexity of logic chips, leading to a multiplication in the number of layers (a chip designed in 10nm can number up to 60 layers, while a chip designed in 28 nm numbers only around twenty), and 2/ the growth in 3D NAND chips which favours deposition tools. Since CVD tools are used in stages similar to those involving ALD, the main players are broadly the same, i.e. Tokyo Electron, Applied Materials, ASM International, Veeco, Lam Research, Hitachi Kokusai and Jusung.
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2.6.4. China, national security is prompting the country to invest For quite some time, numerous industry leaders have maintained a watching brief on China. Firstly, because this is a very substantial market, and whose growth is expected to be strong in the next few years. Secondly, because it has hitherto been a potential location for developing new fabs.
Furthermore, China is currently executing a massive development plan for its semiconductor industry which offers both new opportunities and potential new threats for Western, Korean and Taiwanese companies. Since the Chinese government is keen to reduce its trade deficit and is not comfortable with the idea of being technologically dependent on other countries, it has granted a group of public investors an investment capacity of more than USD150bn (to invest by 2025).
In total, several hundred local companies are going to benefit from help with their investments, i.e. in the form of subsidies, joint-ventures with a local state-owned entity, and direct investments.
The Chinese government is not partisan and is happy to join forces with foreigners to accelerate the growth in its local semiconductor industry (and hence repatriate the expertise of the different partners). It is within this context that players like GlobalFoundries, Intel, Samsung, SK Hynix, TSMC and UMC have recently launched fab construction programmes.
The impact on the geographical breakdown of fab construction is nonetheless already apparent since the country is now number one, far outstripping the USA.
Fig. 24: China, the number one for fab construction through to 2019
15
10
5
0 China Americas Taiwan SE Asia Eur ope & Mideast Japan Korea
2017 2018 2019 2020
Source: SEMI (November 2016)
In total, we have identified 26 projects, in various stages of advancement, to build fabs in China between now and 2020. Note, however, that there is a significant risk that some of these projects do not come to fruition. This is explained by the administrative complexity in the country which has led to delays in the past.
If all the projects see daylight, Chinese production capacity would be multiplied by five or six-fold. Currently, Chinese production capacity stands at c.400,000 wafers per month (wpm). Even with a relatively low success rate standing at two in three of the projects announced, production capacity in China should surpass 1.4 million wpm in 2020.
For the equipment manufacturers, this is a godsend. During its Q2 2017 telephone conference, ASML considered that, as things currently stand, it would be reasonable to assume that the opportunity created
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Semiconductors by these fab construction projects could be worth USD3.5 billion for the group (EUR3 billion). Applied Materials should begin to benefit in 2018.
Lastly, in this environment of massive growth, note that the bulk of the projects concentrate on Memory production (c.60%) and the manufacturing of Logic chips (c.40%) but there are no plans for a fab destined for the production of Analog chips. There is thus little prospect of competition for the European players whose Analog expertise remains dominant (STMicroelectronics, Infineon, NXP, X- Fab, etc.).
In addition, few of these fabs will produce advanced production technology chips (i.e. <14nm). This means that most chips will be produced using the 28nm and above technologies. Thus, KLA-Tencor has reiterated that growth in demand for reconditioned equipment is expected to equal that of new, old-generation equipment. The only exception currently is TSMC, where there are plans to build a fab destined for chip manufacturing using 16nm FinFET.
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2.6.5. Spending on equipment setting new records In 2017, investment in equipping semiconductor fabs is expected to reach a new record. Halfway through the year, SEMI, the association regrouping multiple equipment manufacturers which complies and publishes annual forecasts, forecasted 23% growth in 2017 versus 2016, to around USD49.6bn. This figure compares with the 17.9% growth expected by Gartner.
Fig. 25: 38% growth in 2017 with 2018 also to see rapid growth
Region 2016e 2017e 2018e Americas 4374 5419 7742 Growth (%) -13% +21% +43% China 6857 7548 12387 Growth (%) 43% +17% +64% Europe & Mideast 2233 3871 4258 Growth (%) 6% +78% +10% Japan 4466 6000 6194 Growth (%) -17% +30% +3% Korea 8353 20903 19935 Growth (%) 3% +172% -5% SE Asia 2664 1355 1935 Growth (%) 147% -62% +43% Taiwan 11532 11613 10258 Growth (%) 21% -5% -12% Total 40.479 56710 62710 Growth (%) 12% +38% +11%
Source: SEMI – World Fab Forecast Report, January 2018
In September, SEMI significantly upgraded its assumptions for 2017 and the agency’s latest forecasts point to growth of 38% in 2017 to some USD56.7 billion. This should see the industry set a new record in terms of spending on equipment since the previous record set in 2011 is expected to be comfortably surpassed.
Fig. 26: An unprecedented level of investment
70 180%
60 140%
50 100% 40 60%
USDbn 30 20%
20 Percentagechange Fab equipment spending equipment Fab 10 -20%
0 -60% 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018
Source: SEMI (January 2018)
For 2018, the SEMI market research, which is more recent than that of Gartner, foresees a 11% increase in investment compared with 9% for the latter.
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Semiconductors
In 2017, no fewer than 20 new fabs should be completed (10 are still being built, 10 are being equipped). For 2018, around 21 additional fabs are expected to see the light of day and come on stream (15 are already being built with construction to start shortly on a further six).
Fig. 27: 20 new fabs in 2017, with a further 21 planned for 2018
Probability 2017 2018 2019 2020 Description
40% 1 unconfirmed
50% 2 2 unconfirmed
55% 1 planned
60% 6 3 planned
65% 1 announced
70% 5 2 3 announced
80% 9 13 1 in construction
85% 1 2 in construction
90% 10 equiping
Sum 20 21 12 9 62
Source: SEMI
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Semiconductors
3. Back-End: Advanced Packaging is transforming the whole industry While in NAND memory the industry has managed to get around the slowing growth in horizontal density (shrinking transistor size, i.e. Moore’s law) via the adoption of a 3D architecture, unfortunately the latter cannot be adapted to logic chips and DRAM. Thus, while horizontal density struggles to grow in these types of chips and technological changes in Front-End are decelerating, we note that the current leaders are starting to pay more attention to Back-End (BE, or BEoL for Back-End of Line).
In traditional manufacturing, the BE is responsible for the singulation or dicing stages of chips in the wafer, for packaging and for connecting the silicon to the components’ external connection system (Ball Grid Array, Lead Frame, etc.), as well as for wafer testing of the integrated circuits. However, the growing complexity of the structures of system-in-package (SiP) is adding to the interconnect issues between the chips themselves. We have thus seen the emergence of new packaging methods, known as Advanced Packaging, like 2.5D packaging, 3D and Wafer Level Chip Scale Packaging (WLCSP), of both the Fan-in and Fan-out (FOWLP) types.
Fig. 28: Roadmap of packaging solutions
1970s 1980s 1990s 2000s 2010s
Quad flat Dual-in-line Small System in Wafer-level 2.5-D 3-D Quad flat Leadless Pin-grid Ball-grid no-leads Chip-scale Package on package outline array package package integrated integrated package package chip carrier array package package package circuits circuits
Source: McKinsey ; Bryan, Garnier & Co ests.
FE vs. BE investments Historically, in the semiconductor industry, assembly and packaging (Back-End) was deemed to be a (USDbn) low-added-value and low-margin activity, explaining why it is rarely mentioned by chipmakers. In
40. 0 addition, Back-End equipment costs continue to rank very low down the scale of total costs for
30. 0 semiconductor manufacturers (c.5%). However, we now have every reason to believe that, in future,
20. 0 growth in Back-End equipment could be stronger than that of Front-End.
10. 0
0.0 Front-end Back-end Source: Gartner
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Technology basics – Traditional chip packaging process Packaging is one of the final stages in the creation of a chip, just after the efficiency test known as wafer testing, and comprises the techniques used to encapsulate one or several functions (logic, memory, analogue/RF) in a box which will then be connected to the printed circuit to protect against external manipulation and impurities like dust or oxidation.
There are several die packaging/connection techniques, of which the simplest is wire bonding (see the following diagram). Firstly, the dies formed on the wafer are separated (stage 2) and individually mounted on a metal frame known as the leadframe (stage 3). The connections between the chip and the metal structure are made thanks to very fine wire bonding, and everything is encapsulated in a plastic or epoxy box, then incorporated into the printed circuit.
Wire Bonding
Source: Clive Maxfield’s books; Bryan, Garnier & Co.
The performance of a type of packaging mainly depends on the size of its envelope around the die, and the density and quality of the connections it is able to establish with the substrate. Compared with other more-advanced methods, the limitations of wire bonding lie in 1/ the number of connections it is possible to establish on the die periphery, 2/ the calibre of the filaments which will impact both the transmission time for the electrical signal and the size of the final packaging.
Having reached the limits of wire bonding, the flip-chip ball grid array (BGA) technique is now the one most commonly used. The flip-chip not only establishes its connections with the substrate starting solely from the die extremities but also uses the latter’s whole surface. This increases the connection density and enables a reduction in packaging size to the so- called CSP (chip-scale packaging). The size of CSP packaging is close to that of the integrated circuit, i.e. a volume below or equal to 1.2x that of the die.
Flip-Chip
Source: IC Knowledge.
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Semiconductors
3.1. Wafer Level Packaging, a key packaging technology
3.1.1. TSV and WLP, or when packaging is inspired by the Front-End To continue to satisfy the demand for more-efficient, diverse and cheaper components, some major changes have taken place at Front-End level in terms of architecture and materials. However, the development of new packaging processes is now required. Since 2015, we have thus witnessed the emergence of a packaging process known as Wafer Level Packaging (WLP) in combination with Through Silicon Via (TSV).
The TSV consists of creating microscopic interconnects within the silicon itself. This technique is replacing more traditional wire bonding methods and enables a direct interconnect between the dies, or from the dies to the substrate.
For its part, WLP is a packaging technology consisting of beginning the encapsulation phases at the level of the wafer unlike traditional packaging techniques which begin encapsulation once the dies have been separated from the wafer.
Since the WLP process enables the production of chips for which the final packaging size is virtually identical to that of the die (Chip-Scale Packaging), this is a packaging methodology which is highly sought after by the manufacturers of smartphones and other electronic devices where each square millimeter is at a premium. For example, the first-generation iPhone embedded two chips packaged in WLP while the 2016 iPhone 7 has 14. At this stage, there is no reason to believe that the number of WLP components embedded in the iPhone 8 and iPhone X won’t be higher than on the iPhone 7. Unfortunately, the X ray analyses enabling this to be confirmed are not yet available.
Fig. 29: Significant increase in WLP packaging on the 2016 iPhone 7
Source: Techsearch
There are currently two types of WLP process, Fan In Wafer Level Packaging (also called Wafer Level Chip Scale Packaging, WLCSP) and Fan Out Wafer Level Packaging (FOWLP).
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3.1.2. At TSMC, FOWLP is used as a growth driver FOWLP enables the issues surrounding size differences between the interconnects to be resolved at the level of the silicon and the PCB (electronic board). This method uses a wafer deconstruction process during which the functional dies of the principal wafer are separated (dicing), repositioned on a new wafer then coated with epoxy. This carrier wafer has been pre-produced to play an interface role between the die’s fine connections on one side and the wider connections of the OCB on the other. This method thus enables the multiplication of the number of interconnects and I/Os (inputs and outputs) of a chip even if transistors are getting smaller.
Fan-Out WLP preserves most of the benefits of Fan-In WLP (WLCSP) since this technique enables 1/ a reduction in the final size of the chips (notably density in the case of FOWLP), 2/ no substrate use, thereby making the interconnects more effective since they are shorter, 3/an improvement in the compatibility of the chips produced with SiP-type packaging, and 4/a reduction in thermal resistance and improved dispersal. On the other hand, it offers a solution to one of the issues with Fan-In WLCSP, i.e. the limited number of interconnects, which takes place at the expense of a reduction in chip size. In WLCSP, this limit is naturally imposed by the number of interconnects that it is possible to position on the die knowing that the minimum size of each interconnect is limited by the PCB capacities. FOWLP thus enables this problem to be circumvented by using a carrier wafer enabling the routing of the interconnects.
Since it responds to the very concrete needs of 1/a reduction in chip size, 2/an improvement in chip performance, and 3/an increase in the number of functions managed by the chips (number of inputs/outputs), FOWLP-type advanced packaging is currently enjoying strong growth. Furthermore, 2016 was a pivotal year concerning the adoption of FOWLP, and the projections are still very ambitious. According to Yole Développement, the FOWLP chip packaging market could represent 4.8 million wafers in 2020e versus only 1.0 million in 2016, i.e. average growth of 47.9% over three years.
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On the smartphone, one of the segments in which fan out packaging is already widely used, the number of chips likely to use this packaging method in the future remains substantial.
Fig. 30: Mobile still offers opportunities for FOWLP
Source: Yole Développement
Moreover, TSMC has clearly understood this and has identified this market as one of the fastest- growing. Again, according to Yole Développement, the FOWLP market should see strong growth over the next few years, moving from a value of USD450m in 2016 to around USD2.4bn by 2020.
There are several reasons for this. In addition to the increasingly-massive adoption in smartphones which constitutes the heart of the fan-out market and mainly involves single-die applications (base band, power management, RF transceivers, etc.), a new generation of FOWLP, with still-higher levels of performance, will underpin this growth. This is in response to the needs of the high-density-type (HD) chips we have seen emerging with the Apple’s processors.
Fig. 31: Fan-out market revenue
2500 Other players entering the market 2000 +25% CAGR 1500 Apple & TSMC start collaboration in HD FO 1000 FO Revenue (in millions USD)
500
0 2014 2015 2016 2017e 2018e 2019e 2020e 2021e
"Core" F O High-density FO
Source: Yole Développement
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Semiconductors
Thanks to its expertise in the HD FOWLP process developed for Apple, TSMC is the uncontested leader in this technology. Compared with traditional FOWLP, HD enables a significant expansion in the number of interconnects for each chip - a particularly important criterion for telephone manufacturers. HD FOWLP supports applications feeding very advanced processors and next- generation memories. In 2016, TSMC was the pioneer in this field with its InFO (integrated fan-out) technology which made its debut in the A10 processor on the iPhone 7 launched in 2016. In value terms - TSMC is carving out the lion’s share with a 60% market share knowing that its cooperation with Apple continues with the A11 – this segment should increase by 55% in 2017e. The growth is expected to be maintained in 2018e, taking the total value of the FOWLP market to USD1.4bn, i.e. a substantial opportunity.
In addition to chipmakers for smartphones, automotive component manufacturers are also showing significant interest in FOWLP. Moreover, it is worth remembering that the FOWLP technology was developed by Infineon in 2012 for its packaging requirements on components destined for cars. One of the main automotive uses is ADAS radar systems (autonomous driving).
Given the growing importance of this packaging technology, Infineon has opted for the licensing route, explaining why a number of OSATs (Outsourced Semiconductor Assembly and Test), the players whose industrial expertise focuses solely on Back-End, did not find themselves totally outpaced despite TSMC’s spectacular arrival. To our knowledge, the FOWLP supplied by OSATs like JCET/STATs CHinPAC, ASE and Amkor account for some 40% of the total FOWLP market.
This is just one example of the transformations taking place within the industry. Advanced Packaging regroups the production technologies at the frontier between Front-End and Back-End. Thus, these two types of players dedicated to subcontracting but traditionally focused on two very different types of manufacturing now find themselves competing with one another.
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3.1.3. No shortage of FOWLP development ideas While, from a commercial perspective, FOWLP is only just getting started we note that, at technological level, the R&D teams in the foundries and OSATs are working flat out to maintain their leadership. Amongst the notable FOWLP developments to come are:
Fan-out Package on Package FOPLP: This development will enable a reduction in production costs. Rather than using a traditional 300mm-diametre wafer as the carrier wafer, FOPLP consists of repositioning the dies on silicon panels whose size can reach 600x600mm (cf. left-hand diagram showing a 300mm wafer in gold versus a 600x600mm panel in green). Nonetheless, the adoption of panels requires the adaptation of all the packaging tools. To our knowledge, there are currently only a few players to have shown an interest: A*Star, ASM Pacific, Fraunhofer and ITRI in collaboration with Amkor, ASE, Nepes, Powertech, Samsung and STATS ChipPAC on the OSAT side. For their part, only Intel and TSMC are engaged in R&D. However, given the current changes in R&D programmes, it seems unlikely that the FOPLP technology will be available for mass production before a few years. Source: STATS ChipPAC, Rudolph
FOPoP: To further improve the integration of the different chip elements, we know that TSMC is already working on the fan out package on package (FOPoP) technology. This FOWLP derivative enables the foundry to superimpose several dies like the applications processor and DRAM memory. This technology competes with Amkor’s Through Molded Via (TMV) technology which had Fan-out Package on Package hitherto offered the best compromise. With FOPoP, however, TSMC is able to offer superior performance levers. A first generation of this technology (given the commercial name inFO-PoP by TSMC) has already been in use for the past year for the Apple A10 processors on the iPhone 7 and, more recently, for the Apple A11 on the iPhone 8/X. In reality, it involves the stacking of an FOWLP-packaged processor and a DRAM memory chip linked by interconnects (Through-inFO Source: TSMC vias, or TIV technology) specially created within the processor’s packaging. With this technology, TSMC and Apple achieve a 30% reduction in the size of their chips. This method is also cheaper since it enables the avoidance of several stages.
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Semiconductors
3.2. 3D integration is the new holy grail In addition to the performance benefits and the reduction in chip unit size, the new packaging techniques also enable an improvement in module assembly methods. The assembly of several chips within a same module is not new but the technological development making this possible means that this practice is increasingly vital for the industry.
3.2.1. The first assemblies: board, modules, SoCs and other SiPs One of the traditional ways of creating a complex electronic system had consisted of producing the different types of chips separately then inter-linking them via a circuit board. Thus, each element of the system, such as the computing processor, maintenance processor, memory and MoDem, were individually packaged then soldered to the mother board to constitute the system. In this way, every component was produced using the most advanced manufacturing technique available for the individual component category.
Fig. 32: Set up of a traditional board
Source: Clive Maxfield’s books; Bryan, Garnier & Co.
However, in this configuration, there was no optimisation of the system’s final size. Had we continued to use this technology, today’s smartphones would resemble large office computers. Furthermore, since the interconnects between the chips were not direct, the connectivity and performance were not optimal. An improved version of these systems, known as the MCM for multi-chip module, regrouped the different digital chips (processor and memory) within a single packaging such that the performances of the interconnects were slightly improved.
The System-on-Chip (SoC) technology subsequently emerged. In this configuration, all the functions are implemented on a same die, interconnect performance is perfect and energy consumption is optimised to the maximum. Unfortunately, creating this kind of system is very complex and expensive. In addition, the regular implementation of analogue chips and RFs such MoDems, require disadvantageous production choices to be made for the adjacent Logic chips. To alleviate this problem, some manufacturers have developed so-called System-in-Package (SiP) systems, largely resembling MCMs but deriving benefits from improved individual packaging. Digital chips are thus produced on a same die, as are Analog chips and RFs, before being assembled in a single module.
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Fig. 33: Structure of a SiP
Source: Clive Maxfield’s books; Bryan, Garnier & Co.
3.2.2. A first wave of innovation is visible with 2.5D modules In the previous technologies, all the dies had been positioned next to each other, i.e. in 2D. And, although SiPs were relatively functional and efficient, the growing needs for connection points for each die rapidly ran into the physical capacity limitations of the SiP substrate. We thus witnessed the emergence of silicon interposers between the dies and the substrate. These silicon interposers were composed of Through Silicon Via (TSV) connections whose sole aim was to overcome the problems surrounding the proliferation of connection points and routing.
Fig. 34: 2.5D packing overcomes the interconnect limitations
Source: Clive Maxfield’s books; Bryan, Garnier & Co.
3.2.3. 3D, the packaging of the future Unfortunately, 2.5D techniques cannot solve the problems surrounding system size in that the dies remain juxtaposed. We thus arrive at 3D packaging, where the dies are superimposed. Here too there are several methods: either the dies are superimposed and positioned back to back (but this is limited to two superimposed dies) or, in the more advanced method, the lower dies embed TSV interconnects aligned with those of the dies positioned on top.
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Fig. 35: 3D packaging, currently the most efficient technology
Source: Clive Maxfield’s books; Bryan, Garnier & Co.
These production methods are currently the most advanced and supplement the technologies outlined earlier, namely Flip Chip and Wafer Level Packaging. They enable complex arrangements with a very large number of dies, each produced using the Front-End technology the most adapted to their individual functions. Furthermore, interconnect performance is optimal and energy consumption is reduced to a minimum. We estimate that systems using Advanced Packaging can reach levels of performance some two to three times higher than that of a traditional system, with a 30% to 40% reduction in size.
Fig. 36: At present limited to high-end applications
Source: McKinsey; Bryan, Garnier & Co.
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As with WLP, the adoption of these new packaging techniques raises identity issues for the foundries and OSATs. In effect, 3D packaging is closely linked to the use and benefits of WLP. Additionally, as with FOWLP, this technology requires the use of a pre-prepared carrier wafer to create the interconnects and other TSVs. This is why the two areas of industrial expertise partially overlap and again compete with each other in 2.5D and 3D packaging.
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Industry insight – aveni depicts a need for innovation in manufacturing methods
aveni has developed an innovative approach to metallization for semiconductor, MEMS, advanced packaging, and related applications. aveni’s processes— Electrografting and Chemicalgrafting—rely on molecular engineering to grow metallization films molecule by molecule.
aveni’s management accepted to share its view on recent industry evolution, advance packaging solutions and the solution which aveni has developed to handle upcoming challenges.
“Smaller, faster, cheaper” are buzzwords used to describe the integrated circuits (ICs, or “chips”) within the electronic devices that are ubiquitous in our everyday lives. But as ICs evolve, conventional chip-making methods present significant challenges as Moore’s Law marches toward obsolescence. Chip makers cannot simply continue to decrease IC dimensions to near nothingness (on the scale of angstroms) and still produce functional devices. This has forced designers to adopt novel architectures, which includes moving from the horizontal into the vertical dimension by stacking chips, one on top of another, which has been recently adopted in advanced packaging.
An illustration of vertically stacked memory and logic die, Stacked chips require vertical electrical connected with TSVs interconnections between each chip of the stack. These interconnections use metal, such as copper (Cu), to create fine wiring to transmit the electrical current. Through silicon via (TSV) is an interconnect method that creates high density electrical connections between vertically-stacked chips for several high- performance applications, such as CMOS image sensors, high-bandwidth memory (HBM) and graphics processing units (GPU) (see Figure on the left). The TSV is a Courtesy AMD cylindrically-shaped hole in which one chip is connected to another chip by using metal.
Advanced TSVs can be eight or more times taller than they are wide (i.e., they have an aspect ratio of ≥8:1). The interconnect wiring is composed of multiple layers. Thin diffusion barrier and Cu seed layers of TSVs require conformal deposition (Conformal deposition of 100% exists if the deposited film thickness on vertical features equals the film thickness deposited on flat surfaces.) throughout the feature, before the vias are filled with Cu, using a water-based electroplating solution. Unlike the conformal deposition required for diffusion barrier and seed layers, the Cu fill step requires bottom-up filling for best device performance.
Conventional dry deposition methods for the barrier and seed layers, such as physical and chemical vapor deposition (PVD and CVD), are challenged by shrinking geometries and aspect ratios of 8:1 and greater. The vapor-phase reactant atoms formed during PVD and CVD, cannot easily travel to the bottom of the micron-scale diameter vias to create the metal film layers. This transport limitation leads very slow deposition rates, but more significantly, it causes more film to deposit at the top of narrow features than at the bottom. This causes the vias to close off during the subsequent Cu fill step and create voids, which degrade electrical performance of the device.
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The advantages of Electrografting™, the wet metal deposition technology developed by aveni®, have become apparent as wiring widths shrink and the use of stacked chips grows. Electrografting (eG) does not have the issues of limited reactant transport and higher cost of CVD and PVD for TSV. aveni’s eG technology is used in conjunction with industry- standard electroplating equipment. eG builds up molecular structures to create superior-quality conformal metal layers. eG is ideal for high aspect ratio TSVs, and has demonstrated capability for aspect ratios up to 40:1.
Logic devices, such as microprocessors that are the brains in a computer or smartphone, use up to 12 layers of copper to create wiring within the device. The features for the first four wiring layers are narrower than the remaining layers, and can be under 30 nanometers wide, which is less than one-thirtieth the width of an average human hair. The process is known as dual damascene, and like TSV, has deposition steps for diffusion barrier, Cu seed layer, and Cu fill.
The effect of copper fill chemistries on discontinuous PVD The barrier and seed layers use conventional copper seed in advanced damascene features dry methods (CVD and PVD) for dual damascene. However, as mentioned for TSV, they have limitations. PVD reached the end of its useful lifetime for Cu seed over 10 years ago, because it can no longer deposit a continuous layer. The breaks in the layer are troublesome, because the conventional acidic solutions used for subsequent Cu fill can penetrate through breaks in the discontinuous seed layer, and chemically attack the barrier underneath. When the barrier is attacked, it leads to sidewall voids (see Figure on the left) and reduced device yield, which affects the chip maker’s bottom Source: aveni line. aveni's alkaline Sao™ chemistries are superior to conventional acidic Cu fill solutions, and maintain the integrity of the barrier layer, even with discontinuous Cu seed, to provide increased yield and device performance.
It is critical that Cu filling begins at the bottom of the features and continues upward, to prevent seams and keyhole voids from forming at the centre of the features during fill, and compromising device yield. aveni Sao solutions were specifically developed for bottom-up Cu filling, and use precise manipulation of chemistries to inhibit deposition the open areas in favour of the narrow trenches and vias.
As the industry progresses, devices will continue to evolve and shrink while they become ever more complex and move into the vertical dimension. This will necessitate constant innovation on the part of chemical suppliers and equipment manufacturers to meet changing device requirements. aveni continues to deliver leading-edge capability with metallization solutions to meet the needs of the evolving market.
Bruno Morel, CEO Frédéric Raynal, PhD, CTO and VP Engineering Karen Reinhardt, Strategic and Technical Marketing Director Judy La Cara, Marketing Director
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3.3. Ramifications: fading frontiers
3.3.1. The cards have been reshuffled for the foundries, IDMs and OSATs Advanced Packaging requires a significant level of investment and greater integration between the Front-End and Back-End. This partly explains the lead established by the IDMs and foundries relative to the OSATs (Outsourced Semiconductor Assembly and Test). While the OSATs are currently reporting volumes, these are mainly being generated with the first generations of Advanced Packaging which do not offer the same levels of integration and performance as the next generations developed by TSMC, Samsung and Intel.
Fig. 37: Leaders in Advanced Packaging in 2016
Intel Others 12.4% 33.0% SPIL 11.6%
JCET/STATS ChipPAC 7.8% ASE 7.7% Amkor 6.4% TSMC ChipBond Samsung 6.6% 7.5% 7.0% In million wafers, 300mm eq
Source: Yole Développement; Bryan, Garnier & Co ests.
In view of their critical mass giving them higher margins and a better financial position, compared with the OSATs the leading IDMs and foundries are pioneers in the new technologies. Furthermore, it is easier for a player with a Front-End capability to integrate the equipment required for Advanced Packaging than the inverse. Many phases in Advanced Packaging (creation of interposers and TSV) are effectively realised in Front-End lines and are assimilated with fairly basic Front-End phases. For an IDM or foundry, it thus involves extending FE lines towards an already-perfectly-mastered area of expertise. On the other hand, for an OSAT, it involves a move up market and the acquisition of new technology.
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Fig. 38: A non-natural move for the foundries and OSATs
Source: Yole Développement
This does not mean that the OSATs are not going to benefit from the value creation offered by Advanced Packaging. We do, however, expect them to remain focused on ‘trailing edge’ (as opposed to leading-edge, or next-generation Advanced Packaging) and less-advanced Advanced Packaging. This should nonetheless represent the bulk of the market in volume terms and thus enable these players to generate additional revenues.
Thus, while in recent years OSAT growth has been stoked by 1/ IDMs disposing of less-advanced or non-strategic technologies, 2/ demand growth that could not be satisfied by the IDMs, we see Advanced Packaging progressively acting as an additional growth lever.
It is, however, important to bear in mind that the OSAT market is atomised and thus intensely competitive, leading to pricing pressure of some 2% to 5% per year. The quest for an improvement in profitability and critical mass to be able to invest more is driving a market consolidation.
Fig. 39: Net margins of the TOP 25 OSATs
Source: Yole Développement
3.3.2. The equipment manufacturers forced to choose sides We expect demand for Advanced Packaging equipment to accelerate. In our view, the traditional packaging market is not particularly buoyant currently and has a weak growth outlook. We believe that the slowdown in innovation and inflation in transition costs being witnessed on the most advanced
50
Semiconductors nodes are bolstering the value-added offered by the new packaging technologies which are now demonstrating an ability to differentiate akin to that of transistor reduction for the foundries.
Fig. 40: Assembly Equipment Market: USD4.4bn
Wire Bonding
22% 30% Die Attach
Advanced Packaging
1% Plating 28% 20% Other Assembly
Source: VLSI; Bryan, Garnier & Co ests.
Since it combines a response to cost practices and the ability to improve performance, we are seeing the gradual adoption of Advanced Packaging in a natural move which should be followed by the whole industry. Firstly, we expect the growing demand of logic and memory components in data centres, and the proliferation of optical modules integrated in small-scale objects (drones, connected devices and smartphones), and of automotive, to drive the growth in Advanced Packaging.
Currently, Advanced Packaging represents a volume of 27 million wafers (in 300mm equivalent). In 2017e, we should see volume growth of around 9.7%, and 7.8% on average over three years to 37 million in 2020e. The penetration of Advanced Packaging as a percentage of total wafer market volume should thus increase from 34.2% in 2016 to 38.9% in 2020e. On the sub-contractor side, whether foundries or OSATs, we expect Advanced Packaging market growth to average 6%-7% over the next five years, versus 3%-4% for the total packaging market, and 4%-5% for semiconductors.
Fig. 41: Advanced Packaging market
40 40%
TSV 30 35% FOWLP FIWLP 20 30% Fli p chi p AP penetration M wafers, Eq. 300mm wafers, M 10 25%
0 20% 2014 2015 2016 2017e 2018e 2019e 2020e 2021e
Source: VLSI; Bryan, Garnier & Co ests.
This growth in the volumes of wafers bound for Advanced Packaging should benefit the sales of the equipment manufacturers whose growth we forecast at 11.8% in 2017e to USD4.1bn. Within this market, it is tools for the Fan-Out WLP process which should capture the biggest share of this growth.
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While investment in FOWLP production tools represented only USD140m in 2016, Yole expects the annual growth in this segment to exceed 40%, to USD700m in 2021.
Fig. 42: FOWLP, a major catalyst for the equipment manufacturers
800
600
400 (in millions USD) 200 FOWLP equipment market equipment FOWLP
0 2015 2016 2017 2018 2019 2020 2021
Sputter Lithography Pick and place Coati ng Debonding Molding
Source : Yole Développement (Aprill 2017)
While Advance Packaging as a whole represents a major opportunity for the equipment manufacturers, we expect the latter to benefit from this growth to a greater or lesser extent as a function of their positioning. We have already mentioned the performance differential that the foundries were capable of achieving relative to the OSATs. We have also mentioned the additional difficulty faced by the OSATs in deploying this type of production. We thus expect foundry demand for more advanced and thus more expensive tools to be higher than that of the OSATs.
Given the additional resources of the foundries and IDMs compared with the OSATs, we see those equipment manufacturers mainly focusing on high-performance equipment to benefit from greater growth momentum. Amongst the latter, we would point to BE Semiconductor which is one of the few Back-End equipment manufacturers to 1/ offer tools enabling the development of Advanced Packaging lines, and 2/concentrate on the high-end.
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4. Investment opportunities remain 4.1. There is currently no premium on the equipment manufacturers The exceptional growth enjoyed by the industry in 2017 was welcomed by the market, with the sample of 13 equipment companies we have setup to track the industry benefiting from an average share price increase of 69%.
Fig. 43: Average share price rise of 69% for the equipment manufacturers in 2017
AIXTRON (XET) 256.75% BE SEMICONDUCTOR 120.54% TOKYO ELECTRON 84.70% LAM RESEARCH 74.09% TERADYNE 64.84% APPLIED MATS. 58.41% KULICKE & SOFFA INDS. 52.57% ASML HOLDING 35.59% KLA TENCOR 33.54% ASM PACIFIC TECH. 32.56% ASM INTERNATIONAL 31.49% CANON 27.47% NIKON 24.93%
0% 50% 100% 150% 200% 250% 300%
Source: Thomson Reuters IBES; Bryan, Garnier & Co ests.
For all that, valuation ratios remained relatively stable over the year and even deteriorated as the year unfolded in that the sample was trading at an average P/E (12m fwd) of 17.3x in early 2017 whereas it this multiple currently stands at 16.4x. This is why, despite the strong share price performances posted by most of our companies in 2017, we are convinced that investment opportunities remain.
Fig. 44: The equipment manufacturers are trading at their historic average levels
19.0x 18.5x 18.0x 17.5x 17.0x 16.5x 16.0x 15.5x 12m fwd P/E ratio 15.0x 14.5x 14.0x juil.-14 juil.-15 juil.-16 juil.-17 mai-14 mai-15 mai-16 mai-17 nov.-14 nov.-15 nov.-16 nov.-17 janv.-14 janv.-15 janv.-16 janv.-17 sept.-14 sept.-15 sept.-16 sept.-17 mars-14 mars-15 mars-16 mars-17
Source: Thomson Reuters IBES; Bryan, Garnier & Co ests.
The growth enjoyed in 2017 by a number of the equipment manufacturers was so strong that valuation ratios had returned to their normative levels at the end of 2017.
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While, for 2018, the industry growth is likely to be slightly weaker than during 2017, the semi-conductor equipment manufacturers should continue to see strong growth.
We are thus initiating coverage of two European equipment manufacturers, ASM International and BE Semiconductor. Although both are equipment manufacturers, these two groups do not compete head on in that ASM International focuses on the development of deposition reactors and thus addresses Front-End fabs while Besi is specialised in the sale of packaging equipment, i.e. the Back-End.
In both cases, we see these players as positioned to benefit from the growth in the industry by offering solutions to the growing technical complexity outlined above.
4.2. Change in the momentum scoring system used to define Beta This report is an opportunity to modify the scoring of the momentum factors used in our methodology to define Beta following the change in our methodology for defining Beta implemented in July 2017 (see our report Switching to a multi-dimensional prospective beta).
As mentioned above, the industry growth was particularly strong for the equipment manufacturers in 2017. This was explained, notably, by substantial levels of equipment demand from memory producers, themselves exposed to a shortage in production capacity.
Should this trend continue in 2018, we would expect it to be less strong. Hence we apply a rating of 4 (out of 5) compared with 5 previously.
This modification in scoring affects only the equipment manufacturers, i.e. ASMI, ASML, and Besi.
Fig. 45: Momentum score
Category Related Company Market Segment Rating Automotive 3 Application momentum Industry 4 ams, Dialog, Melexis, Used for Semiconductor Smartphone 4 Infineon, Soitec, manufacturers and Wafer Computing 3 STMicroelectronics, u-blox manufacturers Consumer 2 Average 3.2 Memory makers 4 Manufacturing momentum Logic IDMs 4 ASMI, ASML, BE Semiconductor Used for Equipment manufacturers Logic Foundries 4 Average 4.0
Source: Bryan, Garnier & Co ests.
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Fig. 46: Weighting of the exposure used to define Beta
ASMI ASML BESI Memory Makers Memory Makers Memory Makers
40% 33% 33%
30% 30% 33% 33% 33% 33%
Logic Logic Logic Logic Logic Logic Foundries IDMs Foundries IDMs Foundries IDMs
Source: Bryan, Garnier & Co ests.
Fig. 47: Quality score used to define Beta by company
ASMI ASML BESI Product specific success 3 5 3 Restructuring and M&A risks 3 5 4 Historical earning surprise 3 4 4 Customer diversification 2 3 5 Financial strength 5 3 5 Forex resistance 3 4 3 Market Capitalisation 1 5 1 Quality Score 2.9 4.1 3.6 Source: Bryan, Garnier & Co ests.
Fig. 48: Definition of the Betas for the equipment manufacturers
ASMI ASML BESI (a) - Quality score 2.9 4.1 3.6 (b) - Momentum score 4.0 4.0 4.0 (c) = avg(a,b) - Company score 3.4 4.1 3.8 (d) = 1/(c/3) - Company factor 0.88 0.7 0.8 (e) - Anchor Beta 1.27 1.27 1.27 (f) = (d*e) - Adjusted Beta 1.11 0.94 1.01 Source: Bryan, Garnier & Co ests.
The Beta used for the ASML valuation thus moves from 0.90 to 0.94 and the new WACC comes out at 8.2% versus the 7.9% previously used.
Lastly, for ASMI and Besi, our methodology derives betas of 1.11 and 1.01 respectively, i.e. WACCs of 9.0% and 8.7%.
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Summary of our coverage
Company name Currency Mkt Cap Price Reco. FV (Upside) 2018e P/E 2018e EV/EBIT 2018e EV/Sales ROCE PEG
ams CHF 7,858 93.1 BUY 82 (-11.9%) 20.5x 22.2x 5.5x 9.4% 1.1x
ASM INTERNATIONAL EUR 3,612 58.0 BUY 71 (+23%) 14.9x 22.8x 3.6x 9.1% 1.3x
ASML EUR 64,439 149.4 BUY 180 (+21%) 24.8x 20.8x 6.2x 23.4% 1.1x
BE SEMICONDUCTOR EUR 3,069 76.7 BUY 91 (+19%) 15.4x 11.8x 4.4x 85.1% 1.9x
DIALOG SEMICONDUCTOR EUR 1,929 25.3 NEUTRAL 28 (+10.9%) 7.7x 4.5x 0.8x 49.8% -0.7x
INFINEON EUR 27408 24.1 BUY 26.3 (+9.0%) 24.5x 22.3x 3.4x 17.1% 2.3x
MELEXIS EUR 3,632 89.90 SELL 55 (-38.8%) 30.4x 25.8x 6.4x 45.3% 4.1x
SOITEC EUR 2,095 66.80 BUY 70 (+4.8%) 33.7x 23.9x 4.6x 27.2% 1.1x
STMICROELECTRONICS EUR 18,213 19.99 BUY 21.9 (+9.6%) 21.1x 17.6x 2.3x 19.5% 1.5x
u-blox CHF 1,472 211.60 NEUTRAL 185 (-12.6%) 24.5x 18.3x 2.8x 23.2% 1.6x
Source: Bryan, Garnier & Co ests.
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INDEPENDENT RESEARCH ASM International 16th January 2018 Supported by a changing industry TMT Fair Value EUR71 (price EUR57.98) BUY Coverage initiated
Bloomberg ASM NA We are initiating coverage of ASM International (ASMI) with a Buy Reuters ASMI.AS recommendation and a FV of EUR71 (+23%). ASMI enjoys a leadership 12-month High / Low (EUR) 62.3 / 43.6 position in ALD tools, and we see the following short-term catalysts: 1/ Market capitalisation (EURm) 3,612 Enterprise Value (BG estimates EURm) 2,684 another year of capex growth in the semiconductor industry, 2/ the Avg. 6m daily volume ('000 shares) 228.6 penetration of the 3D NAND technologies and the arrival of 7nm which Free Float 100% should benefit ALD and Epitaxy equipment, and 3/ an improving 3y EPS CAGR 15.3% Gearing (12/16) -19% profile with the withdrawal from the back-end activities. Nevertheless, Dividend yields (12/17e) 1.18% ASMI’s shares are trading on 2018e P/E of 14.9x, i.e. a discount of 16% compared to industry average of 17.8x. YE December 12/16 12/17e 12/18e 12/19e Revenue (EURm) 597.93 724.87 790.91 785.38 EBITA EURm) 82.2 108.7 125.0 126.4 The need for ALD is increasing as the industry reduces transistors’ scale. Op.Margin (%) 13.8 15.0 15.8 16.1 At memory application level, the sector players are currently accelerating Diluted EPS (EUR) 2.67 3.08 3.90 4.10 EV/Sales 5.41x 3.70x 3.60x 3.81x their investment in 3D structures with greater dependence on the EV/EBITDA 24.1x 16.9x 15.1x 16.0x deposition techniques provided by ALD. We expect the sales growth in EV/EBITA 39.3x 24.7x 22.8x 23.7x this segment (50%+ of total revenue) to at least equal that of the ALD P/E 21.7x 18.8x 14.9x 14.1x ROCE 4.9 9.4 9.1 8.4 market over the next three years, i.e. average annual growth of 20%.
ASMI is benefiting from positive momentum in epitaxy. Epitaxy sales 61.0 are gaining popularity outside the historic circle composed of the Analog 56.0 players. The recent improvements to its Intrepid systems have attracted 51.0 the interest of Logic players, and are considerably expanding the 46.0 addressable market from USD100m to c. EUR600m. However, a close 41.0 watch needs to be kept on ASMI’s margins which have been negatively 36.0 impacted by the development of these new products. 31.0 15/07/16 15/10/16 15/01/17 15/04/17 15/07/17 15/10/17 15/01/18 ASM INTERNATIONAL SXX EUROPE 600 TECHNOLOGY An improving stock market profile. In 2017, the group’s management embarked on significant dilution of its equity investment in the back-end via its former ASMPT subsidiary whose market capitalisation accounted for 50% of ASMI’s own market capitalisation at the end of the Q1. The sale of 14% of its holding enabled the group to generate proceeds of EUR695 million, of which a substantial portion should be returned to shareholders while the rest should give the company sufficient financial headroom to maintain and reinforce its competitive advantage in the core front-end business.
Analyst: Analyst: Doiran Terral Frédéric Yoboué 33(0) 1.56.68.75.92 33(0) 1 56 68 75 54 [email protected] [email protected]
r r ASM International
Simplified Profit & Loss Account (EURm) 31/12/14 31/12/15 31/12/16 31/12/17e 31/12/18e 31/12/19e 31/12/20e Revenues 546 670 598 725 791 785 833 Change (%) -10.9% 22.7% -10.7% 21.2% 9.1% -0.7% 6.1% Adjusted EBITDA 112 165 134 158 188 188 199 Adjusted EBIT 90.5 111 82.2 109 125 126 136 EBIT 90.5 111 82.2 109 125 126 136 Change (%) 124% 22.7% -26.0% 32.2% 15.0% 1.2% 7.4% Financial results 64.3 40.9 55.5 293 102 104 119 Pre-Tax profits 155 152 138 402 227 231 254 Tax (17.6) 5.4 (2.3) (8.3) (20.4) (23.1) (25.4) Net profit 137 157 135 394 207 208 229 Adjusted net profit 98.7 141 164 187 227 225 239 Change (%) 415% 43.1% 16.1% 13.8% 21.5% -0.9% 6.4% Cash Flow Statement (EURm) Depreciation & amortisation 21.2 54.4 51.8 49.8 63.3 61.3 63.3 Change in working capital 9.3 8.4 (68.7) (68.5) 7.6 7.2 (11.2) Operating cash flows 110 175 80.6 88.0 157 167 162 Capex, net (31.8) (70.6) (60.1) (77.6) (77.5) (72.3) (75.0) Free Cash flow 78.6 104 20.5 10.4 79.8 94.4 86.9 Acquisition, net 0.0 (0.90) 0.0 691 0.0 0.0 0.0 Financial investments, net 0.0 42.9 22.1 51.5 18.3 18.2 19.3 Dividends (31.8) (37.2) (42.7) (41.5) (54.3) (57.6) (54.1) Issuance (repurchase) of own shares (24.6) (67.8) (82.3) (163) (197) (200) (200) Issuance (repayment) of debt (1.4) 0.0 (0.81) (0.13) 0.0 0.0 0.0 Other 52.6 19.8 14.5 1.7 (7.0) (7.0) (7.0) Net debt (386) (447) (378) (928) (768) (616) (461) Balance Sheet (EURm) Tangible fixed assets 79.2 91.8 95.0 106 120 131 143 Intangibles assets & goodwill 16.1 92.8 111 119 126 133 140 Investments 1,092 1,181 1,236 700 783 869 969 Company description Deferred tax assets 1.8 11.6 13.9 12.1 12.1 12.1 12.1 Other non-current assets 20.4 29.0 41.4 37.4 37.4 37.4 37.4 ASM International is a Dutch Cash & equivalents 386 447 378 928 768 616 461 company which focuses on the Inventories 123 114 112 157 150 144 149 manufacturing of atomic layer Current assets 108 110 160 155 184 187 199 deposition (ALD), chemical vapour Total assets 1,827 2,076 2,148 2,214 2,181 2,130 2,111 Shareholders' equity 1,690 1,948 2,016 2,058 2,013 1,963 1,938 deposition (CVD), epitaxy and vertical Provisions 0.0 9.0 5.8 6.2 6.2 6.2 6.2 furnaces (VFs). Today, the group Deferred tax liabilities 0.0 11.3 13.1 13.1 13.1 13.1 13.1 benefits from a strong momentum on Current liabilities 135 106 112 136 147 146 152 ALD and epitaxy tools. The group L & ST Debt 1.8 1.2 1.4 1.1 1.1 1.1 1.1 also holds a 25% stake in ASM Pacific Total Liabilities 1,827 2,076 2,148 2,214 2,181 2,130 2,111 Capital employed 1,306 1,503 1,639 1,131 1,246 1,348 1,478 Technology, a Back-End tool maker Ratios based in Hong-Kong. Gross margin 43.07 44.13 44.24 42.01 42.80 43.80 44.10 Adjusted operating margin 16.59 16.59 13.75 15.00 15.80 16.10 16.30 Tax rate 11.34 (3.52) 1.66 2.06 9.00 10.00 10.00 Adjusted Net margin 18.09 21.08 27.41 25.74 28.66 28.60 28.69 ROE (after tax) 8.12 8.07 6.72 19.14 10.26 10.58 11.82 ROCE (after tax) 6.14 7.65 4.93 9.42 9.13 8.44 8.27 Gearing (22.82) (22.94) (18.76) (45.11) (38.16) (31.39) (23.80) Pay out ratio 23.18 23.63 31.50 10.53 26.27 27.73 23.64 Number of shares, diluted 64.30 62.93 61.29 60.55 58.17 54.74 51.30 Data per Share (EUR) EPS 2.14 2.50 2.21 6.50 3.55 3.79 4.46 Restated EPS 1.53 2.24 2.67 3.08 3.90 4.10 4.66 % change 414% 46.2% 19.2% 15.2% 26.4% 5.3% 13.6% BVPS 26.29 30.96 32.89 33.98 34.61 35.86 37.78 Operating cash flows 1.72 2.78 1.31 1.45 2.70 3.04 3.16 FCF 1.22 1.66 0.33 0.17 1.37 1.72 1.69 Net dividend 0.50 0.59 0.70 0.68 0.93 1.05 1.06
Source: Company Data; Bryan, Garnier & Co ests.
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Table of contents
1. Investment Case ...... 62 2. Snapshot of the group ...... 63 3. Customers still increasingly big spenders, but where are we on ALD? ...... 64 3.1. ALD, a vital tool for advanced nodes ...... 64 3.2. A niche market within the equipment market ...... 66 3.2.1. Current applications ...... 67 3.2.2. Future applications ...... 70 4. Strong momentum for the group’s other activities ...... 72 4.1. Epitaxy is currently taking off ...... 72 4.2. De facto, a positive outlook for the Services and Maintenance activity? ...... 73 4.3. On the other hand, PECVD and vertical furnaces remain stable ...... 73 5. 2017 has been a record year for spending but will the same hold good for 2018? ...... 74 5.1. A problem of scale ...... 74 6. ASM Pacific Technology ...... 76 6.1. A back-end activity which has been deconsolidated but remains high profile ...... 76 6.2. The highlighting of a valuation issue ...... 76 6.3. A strategic shareholding according to the management ...... 77 6.4. Positive initiatives to be pursued? ...... 78 7. Our central scenario ...... 79 7.1. A top line scenario driven by ALD ...... 79 7.2. Towards an upwards revision in the consensus ...... 80 7.3. A balance sheet which remains solid ...... 82 7.4. Increased shareholder returns ...... 83 8. Valuation ...... 84 8.1. A DCF at EUR69 per share ...... 84 8.2. A SOP at EUR74 per share ...... 86 8.3. Re-rating potential ...... 87 Bryan Garnier stock rating system...... 89
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1. Investment Case
The reason for writing now Developing the forthcoming generations of chip manufacturing processes is looking increasingly complex given the growing physical limitations to be circumvented in fine-tuned etching below 7nm. ASM International is one of the rare equipment manufacturers with the ability to develop tools capable of pursuing this race for performance. The group has notably developed Atomic Layer Deposition tools which should drive sales momentum over the next few years.
Valuation Our Fair Value of EUR71 is the average of a sum of the parts (FV EUR74) and a DCF (FV EUR69 with a WACC of 9.0%). Based on our estimates, the stock is trading at a 2018e P/E of 14.9x and a PEG of 1.3x.
Catalysts The ASM International share price should react to the following: 1/ the momentum in ALD equipment sales which is expected to accelerate in the coming financial years; 2/ the investment dynamic of the leading players and ASMI customers like IDMs/Logic Foundries and memory producers; 3/ the powerful Back-End dynamic to be found in ASMI through ASMPT.
Difference from consensus In our view, the consensus remains too cautious on the group’s 2018e growth and is not factoring in the ongoing share buyback programme. While the industry is set for another year of growth, the consensus is expecting a xx% decline. We are forecasting a 2016/2020e EPS CAGR of 15%. For the 2018e/2019e financial years (the only ones for which the consensus is available), our estimates stand an average of 4% above those of the consensus.
Risks to our investment case Our forecasts are mostly underpinned by industry capex plans which have already been announced or are expected, and may be subject to both upside and downside volatility depending on the economic backdrop. The ASM International investment case is also based on the growth of its market segments and on the penetration of the ALD and epitaxy technologies. Lastly, we expect 2018 investment in capex to be particularly exposed to memory applications, the deployment of advanced production in 7nm/5nm at the large foundries and to Chinese spending.
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2. Snapshot of the group ASM International is a Dutch company which focuses on the manufacturing of atomic layer deposition (ALD), chemical vapour deposition (CVD), epitaxy and vertical furnaces (VFs). Although the group has developed tools for batch processing and single wafer tools, the bulk of sales is generated with the latter, ASMI has also developed deposition tools using several reactors (up to eight), combining the precision of single wafer tools with the level of performance achieved with batch processing.
Fig. 1: Snapshot of the group
ALD systems Vertical Furnaces PECVD systems Epitaxy systems
(BG ests.) % of sales
CAGR 2015/2017e: +15.5% CAGR 2015/2017e: -1.5% CAGR 2015/2017e: +2.0% CAGR 2015/2017e: +27.1%
200 150 75 150 100 50 momentum 100 50 50 25 (BG ests.) 0 0 0
Revenue FY15 FY16 FY17e FY15 FY16 FY17e FY15 FY16 FY17e
- Pulsar XP - Intrepid XP - Advance A412 Plus - Emerald XP - Dragon XP8 - Epsilon 3200 - Advance A400 - Eagle XP8 - Epsilon 3200 Plus Key products
- Any logic foundry such as TSMC, GlobalFoundries or Smasung - Any IDM such as Intel, STMicroelectronics and Infineon - Any memory maker such as Micron, Samsung, SK Hynix and Toshiba (examples) Key consumers
- Transistor shrink (7nm/5nm) - New fab programmes - New fab programmes - New fab programmes - 3D NAND development - 3D NAND development Key catalysts
- Development of alternative methodologies - Foundry/IDM/Memory maker - Foundry/IDM/Memory - Foundry/IDM/Memory maker - Foundry/IDM/Memory capex maker capex capex Strong maker capex sensitivity to
Source: Company Data; Bryan, Garnier & Co ests.
Furthermore, the group generates a proportion of its sales (which we estimate at approaching 23%/25%) from maintenance services and training.
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3. Customers still increasingly big spenders, but where are we on ALD? 3.1. ALD, a vital tool for advanced nodes ALD stands for Atomic Layer Deposition. This is a thin film deposition process and is one of the key techniques used in chip production for the successive deposition of isolation films and conductors on a wafer.
ALD is a technique derived from traditional chemical vapor deposition (CVD) which is one of the deposition methods most currently used in semi-conductor manufacturing. In CVD, several precursors in the gas phase are injected into a reactor heated to a very high temperature and containing a wafer. These precursors are going to inter-react on the surface of the wafer and create a fine layer of material.
For example, the injection of dichlosilane into the reactor will form a layer of silicon oxide (SiO2), an insulator. For the deposition of some chemical compounds like phosphosilicate glass (used for interconnects), the temperature inside the reactor can reach 1,100°C. Since these temperatures are particularly high, they can alter the wafer (and notably the metal layers already created during previous stages), which is why this production technique has been improved thanks to the prior formation of a plasma (gas + electrical discharge) within the reactor. This enables the characteristics of the CVD deposition to be preserved while reducing the temperature of the chamber. This technique is known as Plasma Enhanced CVD (PECVD).
Fig. 2: Plasma Enhanced Chemical Vapour Deposition (PECVD)
Source : Lam Research
With increasingly fine- (PE)CVD is thus a process that is extensively used in electronic component manufacturing. However, tuned etching, controlling with continuing reduction in scaling, controlling and maintaining the quality standard of and maintaining the deposition have become major priorities. Controlling the thickness of the film formed on the surface quality standard of of the wafer depends on two factors, 1/ the quantities of gas injected into the reactor and 2/ the deposition have become major priorities exposure time.
To improve the deposition quality, the various stages of chemical reactions have been separated so that they can be managed individually – this is ALD. A first stage consists of injecting into the reactor a very precise quantity of a single percursor (e.g. Si in a gas state) which is absorbed by
the exposed surfaces of the wafer. A very precise quantity of a second gas/plasma (e.g. O2) is then
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injected into the reactor and, on contact with the areas of the wafer exposed to the first gas, will trigger
a process to create a very fine layer of material (in our example, a layer of silicon oxide (SiO2).
Fig. 3: Atomic layer deposition process (ALD)
Source : Lam Research
Unlike CVD, ALD has the huge advantage of only deposing a single atomic layer at a time, but especially of being self-regulating. Control over deposition and thus the latter’s uniformity is perfect, and all the more so in that ALD is effective on substrate presenting a very high aspect ratio (cavities, raised areas) which is notably the case for wafers in the production process.
Fig. 4: ALD enables a higher quality, more uniform standard of deposition
Source: Lam Research
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3.2. A niche market within the equipment market Deposition speed In actual fact, this deposition process is currently used for a growing number of applications including constitutes ALD’s main in the production of advanced Logic (CPU, GPU, ASIC, ASSP, FPGA, etc.) and Memory (DRAM, drawback: 1nm/min NAND, MRAM, etc.) chips. However, it has one major drawback: deposition speed. Although a versus 100nm/min for CVD reactor is capable of propogating films at a speed of over 100nm per minute, ALD systems are CVD limited to a deposition rate of under 1nm per minute.
Fig. 5: Comparaison with the other deposition techniques
Source : Fraunhofer
This means that the ALD market is relatively limited. While the total semiconductor deposition market was worth USD10.5bn in 2016, we estimate that the ALD segment represented only USD700m. This is a market which saw very decent growth between 2012 and 2015, only to collapse in 2016 owing to the massive investment in DRAM memory capacity by the memory players and the transition to Flash NAND memory production in 3D.
This air pocket, which negatively impacted ASMI in 2016, is now behind us. Although the use of ALD single wafers (such as those from ASM International) had not been particularly competitive for the production of the first generations of Flash NAND in 3D memory chips, it is becoming increasingly attractive with the multiplication of layers. Relative to the batch ALD system, single wafers effectively offer much greater precision which is useful as of 64 layers.
Average annual growth of Furthermore, ALD is increasingly used in the manufacturing of advanced logic chips. By 2020 the 20% to USD1.5 billion in ALD market could thus exceed USD1.5 billion, i.e. an average annual growth rate of more than 2020 20%. This is therefore a market segment which is growing more rapidly than the deposition systems market as a whole.
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3.2.1. Current applications The following are amongst the applications which make most sense.
FinFET: Once transistors’ size had passed the 20nm threshold, manufacturers were forced to ALD for FinFET adopt a new transistor architecture developed by Intel known as FinFET. This is a 3D transistor geometry, aimed at increasing control over the current transiting via the ever-smaller transistors.
This architecture does nonetheless raise some additional issues relative to traditional planar construction. Chemical vapour deposition techniques rapidly suffer from a lack of conformity on complex forms of substrate (cf. Fig. 3). In other words, the areas of the wafer which are reached more easily are rapidly covered with a thick film of material whereas the less accessible areas are either not coated with the film or have a layer of film which is too fine.
. In this context, the use of ALD systems is rapidly becoming necessary. Nevertheless, note that in Source : Lam Research the example of a chip produced in 10nm FinFET in 2017, only three or four of some forty stages are really produced in 10nm. Thus, the need for ALD tools is limited to the most advanced forms of production (currently at TSMC, Intel, Samsung and GlobalFoundries) and only for a few stages. However, the forthcoming node technologies (5nm and 3nm) are likely to require a more complex level of transistor architecture (Gate All Around, or GAA) and potentially lead to demand for ALD tools.
Fig. 6: ALD will become increasingly critical
Source: Applied Materials ; Bryan, Garnier & Co.
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ALD for 3D NAND 3D NAND: Although the horizontal density of memory chips is increasingly difficult to improve, flash memory (NAND) manufacturers have opted for a new stacking architecture, thereby increasing the vertical density. These next-generation chips (the volume production launch effectively took place in early 2015 and is still ramping up in 2017, cf. sector report part 2.4.2) thus originate from a succession of conducting and insulating deposition layers, interlinked by interconnects.
Unlike traditional NAND chips whose storage cell uplift was solely dependent on the development of lithography, 3D memory chips depend rather on innovative etching and deposition techniques. In the production phases, a much higher level of precision and . Source : Lam Research uniformity is thus increasingly important. Especially owing to the fact that the aspect ratio of a 3D NAND die can be very high since 3D NAND chips can number up to 96 layers (at present).
Fig. 7: ALD is a vital technology for NAND 3D production
Contact: ALD Metal Fill
Wordline: ALD Metal Fill Channel: ALD High aspect ratio etch
Source: ElectroIQ; Bryan, Garnier & Co.
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ALD for SAxP Self-Aligned Patterning: While the lithography technologies have struggled to evolve (EUV production should be launched as of 2018 after more than 20 years in development), one of the techniques enabling transistors downscaling with the current tools is double lithography. In other words, a first half of the circuit is exposed then revealed, then these stages are repeated a second time for the second half of the circuit. This is known as double-patterning or LELE (Litho Etch Litho Etch).
The problem is to achieve the perfect alignment of the two masks without which the chip will not function. To alleviate this issue, another method has been developed known as Self-Aligned Double Patterning (SADP). This method consists of exposing the wafer (lithography) to create . Source : Lam Research spacers which will subsequently serve as supports since they will be coated in a highly precise deposition stage (in ALD), the thickness of this deposition ultimately determining the size of the finished transistors. The following stage consists of removing the top of the spacers and their coating, then removing the spacers to leave only the vertical depositions. This will form the frame for the future transistor gates.
Fig. 8: SADP unfavourable to lithography equipment, favourable to ALD
Source : ITRS ; Bryan, Garnier & Co.
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3.2.2. Future applications Logic
The ongoing miniaturisation of transistors is favourable to ALD. Although lithography technologies continue to evolve and ASML is managing to constantly develop the EUV technology, transitor architecture now needs to be revisited.
Since 20nm, more manufacturers have adopted the FinFET technology. This technology is more complex than the planar technology used until now and the development of each node is leading to increased transistor architecture complexity.
As we know it today, the FinFET architecture is unlikely to suffice to maintain full control over the transistors in the forthcoming nodes. Some advanced manufacturers, like TSMC, GlobalFondries, Intel and Samsung, are thus already working on the next architecture to adopt. The initial work points to a nanotube-based architecture, known as the Gate-All-Around.
Fig. 9: The Gata-All-Around (GAA) architecture is positive for ALD
Source: Ecole Polytechnique Fédérale de Lausanne
Beyond 2020, the roadmap remains highly uncertain but a consensus does nonetheless exist in the industry and points to the adoption of 5nm between 2021 and 2023. It is at this point that the new architecture could be adopted. In effect, beyond 7nm, transistors suffer from a quantum confinement effect.
Beyond 7nm, ALD use The first demonstrations made to date show that ALD use is required. Firstly, because the size of the will be obligatory. This is transistors requires an ever-more precise deposition. Secondly, because one of the development avenues already the case for next- consists of using III-V materials, whose deposition is only possible in ALD. generation logic and memory chips. It is nonetheless important to note that, in 5nm, the development cost of a chip could amount to more than USD500m. This compares with a USD270m development cost for the design of a 7nm chip, which is itself nine times higher than the development of a chip in 28nm. This production is thus
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ASM International likely to be reserved to applications with high volumes or significant added value. Amongst the latter, we might mention all the artificial intelligence applications and those involved in autonomous vehicles.
Beyond 5nm, the visibility is even lower. We know that Intel, SMC, Samsung and GlobalFoundies are working on the matter but we have yet to gain a precise vision on the technologies that have been adopted.
For the manufacturers of ALD systems, the potential customers should thus remain identical to those using the most advanced 7nm systems. However, the use of ALD will become increasingly critical. It is no longer a case of using ALD only for patterning but also for transistor construction.
Memory
For the producers of NAND memory, the required increase in vertical density should raise new challenges. We might reasonably expect that, on the assumption that the industry will adopt a 3D NAND memory manufacturing technology in 128 layers, the precision required to realise the interconnects will continue to increase.
We thus don’t expect any downturn in demand for ALD tools on the part of memory producers. Note, however, that the memory segment is one of the most volatile. The visibility on volumes through to 2020 remains very low and numerous factors could lead all the memory producers to suddenly stop expanding their production capacity (cf. sector report part 2.6.2). This could have an immediate positive impact on the sales of single wafer ALD tools.
For the producers of DRAM memory, the miniaturisation trend closely resembles that of the logic chip producers. Given the numerous programmes for DRAM plant construction (cf. sector report part 2.6.4), 2018 should be a growth year for this segment.
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4. Strong momentum for the group’s other activities The group generates half its sales from ALD tools. There is nonetheless considerable growth momentum within ASM International driven by other types of equipment and services.
4.1. Epitaxy is currently taking off Epitaxy is a technique used to grow thin layers measuring several nanometers in density and enabling an improvement in the technical characteristics of a specific part of the wafer. There are several technologies: 1/ molecular beam epitaxy (MBE), 2/ liquid phase epitaxy (LPE), 3/ and vapour phase epitaxy (VPE). ASM International is focusing on VPE with its range of Intrepid tools.
Historically, ASM International’s epitaxy customers were players specialised in power components (Infineon, STMicroelectronics, NXP, ON Semiconductor, etc.). The total epitaxy market represents approximately USD600m annually, with the segment in which ASM International is positioned only USD100m.
Nonetheless, during 2017, we noted Increasing interest from increasing interest on the part of logic chip producers in ASM the logic chip producers International’s epitaxy tools. In digital, the increasingly massive use of ultra-shallow junction in ASMI’s epitaxy tools architecture and high-k dielectrics enabling an increase in chip performance and the avoidance of any negative effects from leakage current is leading to a relentless rise in demand for epitaxy precision tools. Similarly, the use of epitaxy methods to form the transistor source and drain is more and more widespread.
Thanks to recent upgrades to these Intrepid systems, ASM International managed to win a major contract during the 2017 first half and we have reason to believe that it concerns TSMC. This is a large-scale contract which should lead to additional orders. The result is a doubling in epitaxy system sales during 2017e.
We believe that ASMI will now be able to leverage this contract to open other doors. We know that the group is in the process of working with Tier 1 fabs to develop its tools in line with their needs.
Although this activity is still minor for the group, the strong growth momentum should be reflected in overall 2017e and 2018e growth. Note, however, that by entering the Tier 1 digital market, ASM International is now competing with the historic leaders like Applied Materials. On the other hand, we don’t expect new players in this market, knowing that it is a segment with high barriers to entry.
In the coming years, the epitaxy market should also benefit from growing momentum in the power components market, notably with silicon carbide (SiC) and gallium nitride (GaN) effervescence.
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4.2. De facto, a positive outlook for the Services and Maintenance activity? We estimate that the sales generated in services are approaching 25% of the group’s total sales, i.e. around EUR170m a year.
This is a usual level for semiconductor equipment manufacturers. This portion of revenue is generally very qualitative since it generates 1/recurring sales, 2/margins that are higher than average for the group.
While ASM International does not disclose the level of margin for services, the ASML example is instructive. In 2016, ASML generated EUR2.2bn of sales in services and options (i.e. around 30% of the group’s total sales), with a gross margin of more than 50%, i.e. 500 basis points above the average for the group.
However, the above example corresponds to lithography tools. These are highly complex tools which cost between 10 and 20 times the price of an ASM International’s ALD tool, hence customers are very interested in the development options offered by ASML. This thus enables lithography specialists to apply higher margins for their services. Additionally, ASML service offering include software with a particularly high margin level.
That is the reason why, we believe that within the framework of an ASM International, the difference in margin between the services activity and the sale of tools remains limited. In that it is very attuned to the installed base, this activity should nonetheless automatically be reinforced over time.
4.3. On the other hand, PECVD and vertical furnaces remain stable The group also markets two other types of system: PECVD systems and Vertical Furnaces. On our estimates, PECVD systems and VFs account for a respective c. 20% and 15% of the group’s total sales.
In terms of VFs, the group primarily focuses on historical customers and mainly those specialised in Analog. We thus do not see any particular negative or positive trends and expect the business to remain relatively stable over the next four years.
We expect a similar trend for PECVD tools as ASM International is not a leader in this field and mainly plays a role of dual-source supplier here.
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5. 2017 has been a record year for spending but will the same hold good for 2018? Demand for ALD equipment is not necessarily growing at the same rate for the whole semi-conductor fab equipment market.
To understand the demand dynamic, we first need to understand how these production tools are used. ALD systems are more precise but also considerably slower. Thus they are mainly used for the production of DRAM and NAND memory, and for advanced logic chips.
In 2016, we noted a shift in the allocation of DRAM production capacity. Some resources were effectively transferred to NAND memory production, a market segment whose capacity had been constrained owing to a change in production process with the adoption of 3D NAND.
5.1. A problem of scale ASM International is not the only player to produce deposition tools. Amongst ASM International’a major competitors can be found the giant Applied Materials, Tokyo Electron, and Lam Research. There is also a multitude of smaller players like Jusung (a Korean company very close to the Korean memory producers), Aixtron and Veeco, the latter having reinforced its business with the acquisition of UltraTech (cf. our Mapping the Industry in the introduction).
Being a manufacturer of systems dedicated to semiconductor production is not easy. Firstly, you need to invest massively in R&D to produce tools at the technological leading edge. Then comes the issue of critical mass since players like TSMC who can invest up to USD15bn in the construction of a plant want to be sure that their suppliers are viable over the long term. This is especially true in that the choice of supplier is critical since chipmakers avoid having a multitude of tools with different brands. This complicates the training of operators, the compatibility of different pieces of equipment, tool maintenance and any eventual relationships involving R&D cooperation that may be forged with the equipment manufacturers.
To evaluate this scale criterion, many factors are taken into account including sales volumes, balance sheet solidity, production capacity and any eventual partnerships.
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Fig. 10: ASMI, smaller than most of equipment makers
Peers Market Capitalization (USDm) 2017 Sales (USDm) 2017 Net Debt (USDm) APPLIED MATS. 47,426 14,537 -1,972 ASML HOLDING 63,943 10,377 -184 LAM RESEARCH 25,929 8,014 -3,348 TOKYO ELECTRON 24,940 7,091 -2,796 NIKON 6,734 6,641 -1,605 KLA TENCOR 14,011 3,480 -86 ASM PACIFIC TECH. 4,836 2,228 -190 TERADYNE 7,239 2,096 -1,260 ASM INTERNATIONAL 3,631 878 -546 KULICKE & SOFFA INDS. 1,470 809 -592 BE SEMICONDUCTOR 2,920 707 -251 AIXTRON (XET) 1,430 280 -268
Source: Company Data; Bryan, Garnier & Co ests.
Amongst the semiconductor equipment manufacturers, ASM International is thus relatively small. Nonetheless, within a deposition equipment market valued at USD10.5bn, ALD accounts for just 10%. Within this context, chipmakers are more inclined to choose a supplier based on the quality of its technology rather than for its size. However, they may be inclined to force a modest-sized supplier to secure major partnerships to ensure maintenance service supply continuity and/or new equipment whatever happens.
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6. ASM Pacific Technology 6.1. A back-end activity which has been deconsolidated but remains high profile Since the incorporation of the company in 1964, ASM International’s consolidation scope has regularly changed. In addition to the creation of a JV with Philips in 1984 dedicated to lithography, which subsequently gave birth to an autonomous group currently valued at more than EUR64bn, ASML (Buy, FV EUR180), ASM International also created ASM Asia in 1975 (following the acquisition of Fico Toolings in 1974). This Hong Kong-based branch specialising in back-end equipment (chip packaging) was to be listed for trading in 1988 and renamed ASM Pacific Technology (ASMPT).
Until 2013, ASM International still held 52% of the capital of ASM Pacific Technology (ASMPT). On 15 March 2013, ASMI decided to sell a block (c. 12% of the ASMPT share capital) via an over- the-counter transaction, thereby reducing its shareholding to 39.19%, and also leading to the deconsolidation of the group’s back-end operations (currently included in the financial results of the P&L).
6.2. The highlighting of a valuation issue In April 2017, ASMI decided to reduce its shareholding in ASMPT to 34.29%. Then, in November 2017, ASMI decided to further reduce its shareholding in ASMPT to 25.22%. Given ASMPT’s current valuation, the market value of this shareholding is now close to EUR1bn. This needs to be seen within the perspective of an ASMI market capitalisation of EUR3.3bn.
Fig. 11: Equity value to Entreprise value
3500 3000 928 28% -1 2500 0% 11 2000 3,335 1,240 37% 1500
Value (in EUR) 1000 500 1,157 35% 0 ASMI maket Net Cash Provision Financial Market Value EV of ASM As a % of ASMI cap. Assets of ASMPT International market cap.
Source: Thomson Bryan, Garnier & Co ests.
If the ‘why’ can clearly be explained, so can the timing. Last April, at the time of the first announcement, the stock had risen by 89% since 1 January 2016 and by 40% since 1 January 2017. By way of comparison, the performance of the ASMI share price was +52%/+29% over these same periods. Between January 2016 and November 2017, the performance of ASMI share price and ASM PT share price were +67% and +93% respectively.
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Fig. 12: ASMI vs ASMPT since 1 January 2016
199.0 179.0 159.0 139.0 119.0 99.0
Share Price (base 100 100 Share Price (baseindex) 79.0 01/2016 02/2016 03/2016 04/2016 05/2016 06/2016 07/2016 08/2016 09/2016 10/2016 11/2016 12/2016 01/2017 02/2017 03/2017 04/2017 05/2017 06/2017 07/2017 08/2017 09/2017 10/2017 11/2017 12/2017 ASM INTERNATIONAL ASM PACIFIC TECH.
Source: Thomson Bryan, Garnier & Co ests.
It is also worth mentioning the fact that some ASMI shareholders, and notably Eminence Capital which then held approaching 10% of ASMI, had published an open letter a few days earlier to force the ASMI management to evaluate and propose to the forthcoming AGM (22 May 2017) a total exit from the ASMPT share capital (enabling the generation of 40% more value for shareholders according to Eminence).
6.3. A strategic shareholding according to the management The maintenance of the shareholding in ASM Pacific Technology has often been raised in the past and remains a thorny issue. According to the management, the main reason for continuing to hold an equity interest in ASMPT is that it is a way of maintaining a scale of business which inspires confidence with potential customers. We validate this explanation, especially because we regularly meet companies that are impacted by their relative small size. In our view, the stake in ASMPT also offers an indirect diversification which offers a degree of security in the event of a downturn and it allows small synergies thanks to co-development, hence slightly reducing R&D expenses.
Of the above, we find the last the most convincing. The semi-conductor industry effectively has some highly specific practices when it comes to procurement. As outlined above, a number of factors are taken into account including the level of sales generated, balance sheet solidity and production capacity. And while we are convinced that ASM International on a stand-alone basis nonetheless disposes of a respectable size enabling it to survive the screening processes of most industry players, some Tier 1s may set demanding thresholds for ASMI alone which may could the relationships at risk were there to be a deterioration in one of these criteria.
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6.4. Positive initiatives to be pursued? The apparent determination of the ASMI management to maintain a substantial equity interest in ASMPT has not prevented it from diluting its shareholding in the Hong Kong based company by a total of c. 14% during 2017. On two occasions, ASMI has reduced its exposure to the back-end activities: a first sale of 5% taking the holding to 34% in April 2017, followed by a reduction to 25% this November. These two profit-taking transactions raised a respective EUR245m and EUR450m for the company, to be seen in perspective with cash of EUR379m at the end of the 2017 first quarter.
Following the receipt of the EUR245m in April, the company announced a plan to buy-back shares amounting to EUR250m, versus EUR100m for the previous buy-back programme, to be respected through to November 2018. Thereafter, ASMI also commited to distribute a portion of the EUR450m to shareholders in its November press release. With our EBITDA forecasts of around EUR158m in 2017e and EUR188m in 2018e, and estimated capex of around EUR73/78 million annually, we believe that this significant increase in cash gives the group more flexibility to both satisfy shareholders via buy back programmes and dividends distribution, while maintaining a comfortable mattress to invest and maintain/increase its competitive advantage on ALD and epitaxy equipment.
We welcome the recent initiatives from the company which has embarked on reducing its exposure to the back-end activities since this operation provides 1/ improved visibility on the core business for shareholders since, in April 2017, the front-end activities were implicitly valued at EUR1.5 billion, i.e. a scant 33% of the company’s market capital (fig. 10); and 2/ greater flexibility to increase shareholder return through additional share buyback programmes.
These initiatives have enabled the group to boost the valuation of its Front-End activity by nearly 38%. While this activity is currently trading at around 10.6x the operating profit (12m fwd), it had been valued at only 7.6x on the day the spin-off was announced back in April 2017.
The current exposure to ASMPT seems more reasonable with some potential positive outputs in 2018e. The back-end was still valued at one third of the company’s market value at end November, which is a significant improvement compared with the 50%+ contribution at the beginning of the year. At present we belive that the maintenance of a certain level of shareholding and control in the back-end activities could be beneficial over the medium term since 1/ the group maintains a size sufficent to address all levels of customer and does not find itself below the minimum thresholds of the Tier 1s, 2/ the Back-End environment is particularly buoyant, and 3/ ASMPT has a dominant position in the sector, thereby boosting the scale effect and reinforcing the momentum effect. ASMPT is effectively the back-end number one and the company is well positioned to capture the current investment cycle which looks set to continue during 2018, particularly in CIS applications and the penetration of advanced packaging technologies (however, on this last theme, we have a marked preference for Besi on which we are initiating coverage with a Buy recommendation in parallel with this note). We thus believe that, while a complete exit from ASMP might be seen as beneficial or even vital by some shareholders, it could also prove damaging for ASM International’s growth over the longer term, and thus for certain historic shareholders.
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7. Our central scenario 7.1. A top line scenario driven by ALD 2017 was marked by strong growth in memory chip sales within the semi-conductor sector. Behind this trend was a supply-demand imbalance: a significant increase in demand from mobile, automotive and computing applications, at a time when the supply side had reached its maximum production capacity and was experiencing difficulties with migrating to the 3D NAND structures. All the players thus began an investment round to upgrade the installed base and open new fabs with, for some, capex plans running through to 2020 (see sector note section 2.6.5).
Given the increase in etching layers which require more precision than can be achieved with wafer batches (or multi-wafer equipment) or/and other technologies, we thus expect an automatic increase to ALD equipment sales, and notably for the single wafer ALD tools sold by ASMI. Over the medium/long term, the transition to memory chips with 96 or more layers will require more single- wafer ALD tools, thereby underpinning our confidence in the strong long-term growth for this equipment. Note that ASMI has not benefited that much from the growth in DRAM memory where there is less need for ALD tools, and especially where, in 2017, the fabs have preferred to upgrade their installed bases rather than purchase new equipment, having prioritised the development of 3D NAND memory. We should see an improved contribution from DRAM products to equipment sales as of 2018 with the opening of new plants and developing existing fabs at Samsung, Micron and SK Hynix.
Nonetheless, the number one customers for ASMI’s ALD equipment should remain the logic chip foundries where the company boasts strong positioning and increasing penetration in different types of application. The sales momentum in this segment should be underpinned by the use of FinFET in advanced nodes, and the progressive transition to 10nm and 7nm.
Finally, our forecasts show the sales contribution from ALD equipment remaining above 35% in 2018, and average growth of 17% between 2016 and 2020e, in line with the growth in this market based on VLSI’s projections.
While we expect weak or even zero growth in the sales of vertical furnaces and PECVD equipment through 2020e (despite we expect a strong growth by 2018e thanks to a opportunistic win at a Tier 1 customer for 3D NAND), the company is investing more in the sale of epitaxy equipment which is benefiting from a growing interest from foundries specialising in digital applications. This market should represent a USD600m to USD700m opportunity, and extend well beyond the circle of the group’s historic customers whose market potential was limited to some USD100m.
We expect a growth of In the first three quarters of 2017, ASMI total sales grew by 25.0% and we expect sequential growth of 9% in 2018e, and average about 4% during the fourth quarter, i.e. +8% in Q4 relative to the previous year. The scenario described growth of 9% between previously points to a growth of 9% in 2018e, and average growth of 9% between 2016 and 2020e. 2016 and 2020e
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7.2. Towards an upwards revision in the consensus Despite the fact that ASMI is a fixed cost businesss and we are forecasting average annual sales growth of c.9% between 2016 and 2020e, our model has a broadly stable gross margin over the period. In our view, the increasingly high proportion of new products, particularly in expitaxy and PECVD, is going to hold back gross margin growth. The epitaxy market is currently dominated by Applied Materials, however the foundries are encouraging competition between their potential suppliers and, in our view, this is one of the reasons for ASMI’s recent epitaxy tool growth with the logic players. Furthermore, in our view, ASMI’s entry into these new markets is also helped by a concession on margins. The company’s management admitted to putting the emphasis on the good just-in-time execution of orders from its new customer (who appears to be very important in the sector and who we believe to be TSMC). The group thus hopes to first convince by banking on an uplift in volumes and market share, ahead of a normalisation in margins after several quarters.
Furthermore, we have adopted a cautious approach concerning the OPEX trend. We see the development of ALD and expitaxy tools leading to a temporary acceleration in operating expenses as a percentage of sales. This is why, for 2018e/2019e/2020e, our model has OPEX growing at a faster rate than sales. However, this negative effect is counterbalanced by an OPEX rise of only 7% in 2017e versus an expected 21% growth in sales for this same financial year. This also explains the 15% average annual growth in operating profit between 2016 and 2020e versus sales growth averaging 9% over the same period.
In total, we are forecasting a 2016/2020e EPS CAGR of 15%. For the 2018e/2019e financial years (the only years for which a consensus is available), our estimates are on average 4% above those of the consensus. We consequently expect an upwards revision to the consensus in the coming months.
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Fig. 13: P&L – Average EPS growth of 15% in 2016/2020e
[in EURm] / FYE 31/12 2016 1Q17 2Q17 3Q17 4Q17 2017e 2018e 2019e 2020e CAGR 16/20e Sales 598 144 202 185 193 725 791 785 833 8.7% Seq. growth -11% -16% 40% -8% 4% 21% 9% -1% 6% Gross profit 265 62.9 88.2 74.1 79.4 305 339 344 367 Gross margin 44% 44% 44% 40% 41% 42% 43% 44% 44% SG&A -88 -23 -25 -26 -26 -100 -106 -110 -119 % of sales -15% -16% -12% -14% -13% -14% -13% -14% -14% R&D -91 -25 -25 -22 -23 -95 -108 -108 -112 % of sales -15% -17% -12% -12% -12% -13% -14% -14% -14% Other -3 0 0 0 0 -1 0 0 0 % of sales -1% 0% 0% 0% 0% 0% 0% 0% 0% EBIT 82 15 38 26 30 109 125 126 136 13.4% Operating margin 14% 10% 19% 8% 16% 15% 16% 16% 16% EBITDA 134 27 51 37 43 158 188 188 199 10.4% Operating margin 22% 18% 25% 20% 23% 22% 24% 24% 24% Net financial interests 2 0 0 0 0 0 0 0 0 % of sales 0% 0% 0% 0% 0% 0% 0% 0% 0% Foreign currency effects 13 -7 -11 -8 0 -25 0 0 0 % of sales 2% -5% -5% -4% 0% -4% 0% 0% 0% Results from investments 68 35 115 32 160 343 122 121 129 % of sales 7% 21% 53% 14% 80% 44% 13% 13% 14% Income Tax -2 -1 -2 -3 -2 -8 -20 -23 -25 Income tax rate -2% -4% -2% -5% -1% -2% -9% -10% -10% Adj Net Profit 164 41 56 48 42 187 227 225 239 9.9% Net margin 27% 29% 28% 26% 22% 26% 29% 29% 29% Dil. EPS 135 36 132 42 184 394 207 208 229 14.0% EPS seq. growth 19% -39% 36% -17% -10% 15% 26% 5% 14%
Source: Bryan, Garnier & Co ests.
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7.3. A balance sheet which remains solid Our model outlined above implies a return to the levels of free cash flow generated in 2014 and 2015. This follows two years of FCF held back by a decline in 2016 sales and a higher working capital requirement in 2016 and 2017e.
Fig. 14: Return to a level of FCF approaching EUR80m as of 2018e
120.0 100.0 80.0 60.0 40.0
FCF (in EURm) 20.0
FY13 FY14 FY15 FY16 FY17e FY18e FY19e FY20e
Source: Company, Garnier & Co ests.
Nonetheless, the sizeable shareholder returns also outlined in the following section are leading to a gradual reworking of the group’s cash. Since this phenomenon is under control, in our view it does not constitute a reason for concern.
At the end of the 2016 financial year, the group had net cash of EUR378m. This net cash should end the 2017 financial year at close to EUR930m. We subsequently forecast net cash of EUR460m at the end of 2020e, including more than EUR762m returned to shareholders during the 2018e/2019e/2020e financial years.
Fig. 15: A balance sheet which remains solid despite aggressive shareholder return initiatives
[in EURm] 2016 2017e 2018e 2019e 2020e Inventories 112 157 150 144 149 Accounts receivable 137 134 163 166 178 Cash and cash equivalents 378 928 768 616 461 Other 23 21 21 21 21 Total current assets 651 1240 1102 947 810 Property, plant, & equipment 95 106 120 131 143 Goodwill 11 11 11 11 11 Investment in associates 1236 700 783 869 969 Other 156 157 164 171 178 Total non-current assets 1498 974 1079 1183 1301 Total assets 2148 2214 2181 2130 2111 Accounts payable 61 75 87 86 92 Accrued expenses and other 49 57 57 57 57 payables Other 8 10 10 10 10 Current liabilities 118 142 153 153 159 Deferred tax liabilities 13 13 13 13 13 Pension liabilities 1 1 1 1 1 Other 0 0 0 0 0 Non-current liabilities 15 14 14 14 14 Shareholders' equity 2016 2058 2013 1963 1938 Total liabilities and Equity 2148 2214 2181 2130 2111
Source: Bryan, Garnier & Co ests.
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7.4. Increased shareholder returns By reducing its shareholding on two occasions this year, by 5% (EUR245m) in April and by 9% (EUR450m) in November, the group has generated EUR695m of additional cash. While the first disposal had given rise to a EUR250m buyback programme, significantly higher than the EUR100m in the previous programme, we expect a substantial revision in the payout policy for shareholders following the second disposal. We expect buybacks amounting to around EUR170m during 2017 versus EUR97 million in 2016, and are forecasting around EUR200m thereafter.
Additionally, over the last three years, the group has on average paid out 30% of its earnings in the form of dividends with average annual growth of 11.9% (or 9.2% in absolute value). In view of the exceptional financial results in 2017, we are forecasting a decline in the payout rate to around 10%, representing a 30% increase in the reported dividend per share to EUR0.91 versus EUR0.70 in 2016. Our model shows cash of EUR934 million at the end of 2017, and EUR627 million at the end of 2018.
Fig. 16: Cash generation remains substantial…
[in EURm] 2016 1Q17 2Q17 3Q17 4Q17e 2017e 2018e 2019e 2020e EBITDA 134 27 51 37 43 158 188 188 199 Change in WCR -56 14 -51 8 -9 -38 -10 2 -12 Other 3 -7 -14 -9 -2 -33 -20 -23 -25 Cash flow from operating activities 81 33 -14 36 33 88 157 167 162 Capex -60 -14 -26 -18 -20 -78 -78 -72 -75 Free Cash Flow 20 19 -41 19 13 10 80 94 87 Acquisitions 0 0 246 0 446 691 0 0 0 Other 22 0 18 18 15 51 11 11 12 Cash flow used for investing -38 -14 237 1 441 665 -66 -61 -63 activities Purchase of treasury shares -97 -30 -40 -33 -71 -174 -197 -200 -200 Proceeds from issuance of shares 15 7 3 0 0 10 0 0 0 Dividends -43 0 -41 0 0 -41 -54 -58 -54 Other -1 0 0 0 0 0 0 0 0 Cash flow from financing activities -126 -24 -78 -32 -71 -205 -251 -258 -254 Total Cash flow -83 -4 145 5 403 548 -160 -152 -155 CTA (Cumulative translation adj.) 14 5 -1 -2 0 2 0 0 0 Net increase in cash -69 1 144 2 403 550 -160 -152 -155 Cash at beginning of period 447 378 379 523 525 378 928 768 616 Cash at end of period 378 379 523 525 928 928 768 616 461
Source: Bryan, Garnier & Co ests.
Fig. 17: … enabling an increase in shareholder returns
300.0 251.1 257.5 253.9 250.0 215.0 54 57 54 200.0 139.7 41 150.0 116.2 43 100.0 61.2 37 197 200 200 31.5 174 50.0 32 79 97 0.0 32 29 FY13 FY14 FY15 FY16 FY17e FY18e FY19e FY20e Shareholder returns (in EURm) Share buyback programmes Dividends
Source: Thomson Bryan, Garnier & Co ests.
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8. Valuation Our ASM International valuation comes from an equally-weighted average of a DCF and a sum of the parts (SOP).
Hence our Fair Value of EUR71, offering 23% upside potential relative to current share price levels. In view of the growth and the elements outlined above, we are adopting a Buy recommendation on the stock.
Fig. 18: Overview of our valuation methods
Method Weight FV (in EUR) Upside DCF 50% 69 20% SOP 50% 74 28% Average valuation 100% 71 23%
Source: Bryan, Garnier & Co.
8.1. A DCF at EUR69 per share Our DCF-derived valuation is based on the following assumptions:
Our base case scenario which includes estimates out to 2020e. As for the other semi- conductor players under our coverage, we apply a cyclical growth model to the normalised period (from 2021e to 2027e). We use a growth rate of 4.9% (equivalent to the average growth rate over the last five years) at the beginning of the normalised period, i.e. 2019e, which seems to us more representative of the coming years. We then apply a straight-line reduction to this growth rate through to 2027e to converge with our terminal growth of 2.0%. Over the 2018/27e period, this scenario results in average growth of 4.1%.
We apply an average operating margin of 16.9% over the 2021/27e period, i.e. 10bps above the average margin in our 2018e/2020e scenario.
A WCR close to 23.0% of sales over the whole period, i.e. the group’s historic level of WCR expressed as a percentage of sales.
Investment fluctuating around 8.0% of sales over the whole period.
A tax rate of close to 10% corresponding to the normative tax rate of ASM International. The group benefits from a low tax rate thanks to fiscal optimisation made possible by the group’s international operations.
A WACC of 9.0%. We apply a beta of 1.1x derived from our multi-dimensional prospective beta calculation methodology (see our note Switching to a multi-dimensional prospective beta), a risk-free rate of 1.6% and a market risk premium of 7.0%.
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Fig. 19: A WACC of 9.0%
WACC European risk-free interest rate 1.6% Equity risk premium 7.0% Beta 1.2 Return expected on equity 10.0% Interest rate on debt 2.5% Market Capitalization (EURm) 2,169 Net debt on 31/03/15 (EURm) -59 Entreprise value (EURm) 2,111 WACC 10.0%
Source: Bryan, Garnier & Co. ests.
Fig. 20: DCF, a FV at EUR69, i.e. upside potential of 20% in EURm (FYE 31/12) 2018e 2019e 2020e 2021e 2022e 2023e 2024e 2025e 2026e 2027e Revenues 791 785 833 877 920 960 997 1,031 1,062 1,088 Change (%) 9.1% -0.7% 6.1% 5.3% 4.8% 4.4% 3.9% 3.4% 2.9% 2.5% Adjusted EBIT 125 126 136 140 147 155 162 169 176 182 Adjusted operating margin 15.8% 16.1% 16.3% 16.0% 16.0% 16.1% 16.3% 16.4% 16.6% 16.7% Tax -20 -23 -25 -27 -15 -15 -16 -17 -18 -18 Tax rate 9.0% 10.0% 10.0% 10.0% 10.0% 10.0% 10.0% 10.0% 10.0% 10.0% Net Operating income after tax 105 103 110 114 132 139 146 152 158 164 Capex, net -78 -72 -75 -77 -74 -77 -80 -82 -85 -87 As a % of sales 9.8% 9.2% 9.0% 8.8% 8.0% 8.0% 8.0% 8.0% 8.0% 8.0% Depreciation & amortisation 63 61 63 67 74 77 80 82 85 87 As a % of sales 8.0% 7.8% 7.6% 7.6% 8.0% 8.0% 8.0% 8.0% 8.0% 8.0% WCR 180 178 190 201 211 220 228 236 243 249 As a % of sales 22.8% 22.7% 22.8% 22.9% 22.9% 22.9% 22.9% 22.9% 22.9% 22.9% Change in working capital 8 7 -11 -10 -10 -9 -9 -8 -7 -6 Free cash flows 98 100 88 93 123 130 138 145 151 158 Discounted free cash flows 97 90 73 71 86 84 81 78 75 72
Total discounted FCF - 2018e-2027e 806 Discounted Terminal value - 2028e+ 1,006
Enterprise value 1,812 WACC
+ Fair value of associates 1230 [in EUR] 8.0% 8.5% 9.0% 9.5% 10.0%
+ Fair value of financial assets 11 15% 72 69 67 65 63
- Provision (incl. pension plan) 1 16% 73 71 68 66 64 - Net debt on 31/12/2017 -928 17% 75 72 69 67 65
Equity value 3,981 18% 76 73 71 68 66 Op. margin Nbr of diluted shares (m) 58.174 19% 78 75 72 69 67
Valuation per share (EUR) 69 Upside vs. current share price 20% Source: Bryan, Garnier & Co.
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8.2. A SOP at EUR74 per share To take into account the ASM International stake in ASM Pacific Technologies, and to value ASMI’s Front-End business as accurately as possible, we use a valuation based on a Sum of the Parts.
This valuation method is based on the use of peer group multiples to value the ASMI core business. We used a sample of ten semi-conductor equipment manufacturers, which points to average 2018e EV/Sales and EV/Operating profit multiples of 3.3x and 13.4x respectively.
Fig. 21: List of peers used
Company EV/Sales 2018e EV/EBIT 2018e ASML HOLDING 6.0x 21.9x APPLIED MATS. 3.3x 11.4x TOKYO ELECTRON 2.1x n.m. LAM RESEARCH 2.8x 9.7x KLA TENCOR 4.2x 10.9x TERADYNE 3.1x 12.3x NIKON 0.9x 14.9x BE SEMICONDUCTOR 4.3x 13.0x KULICKE & SOFFA INDS. 2.0x 13.0x AIXTRON (XET) 4.5x n.m. Average 3.3x 13.4x
Source: Thomson Reuters I.B.E.S.; Bryan, Garnier & Co ests.
Fig. 22: A Sum of the Parts valuation at EUR74
(A) EV of Front-End business 2018e Revenues 791 Average Peers EV/Sales ratio 3.3x Front-end Valuation 2,628 EBIT 124.96 Average Peers EV/EBIT ratio 13.4x Front-end Valuation 1,674 Net debt on 31/12/17 (EURm) -928 Average valuation of Front-end business (EURm) 3,079 Average valuation of Front-end business (EUR/sh) 53 (B) Net Debt + Restatement ASM PT market capitalisation (HKDm) 45,286 ASM PT market capitalisation (EURm) 4,917 Stake of ASM International in ASM PT 25% Current value of ASM Intl's stake (EURm) 1,240 Current value of ASM Intl's stake (EUR/sh) 21 (A)+(B) Valuation of ASM International Average valuation of Front-end business (EUR/sh) 53 Current value of ASM Intl's stake (EUR/sh) 21 Valuation of ASM International (in EUR/sh) 74 Upside vs. current share price 28%
Source: Bryan, Garnier & Co ests.
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8.3. Re-rating potential To arrive at the intrinsic ratios currently applied by the market to the ASM International business, we used a reverse SOP methodology. To this end, we took the current ASM International share price, then deducted the market value of ASM Pacific, thus deriving respective intrinsic 2018e EV/Sales and EV/Operating profit ratios of 1.5x and 9.6x, i.e. a discount of 54% and 28% to the peer group average.
Fig. 23: Intrinsic EV/Sales and EV/EBIT ratios of 1.5x and 9.6x respectively
2018e 2017e (A) Current share price of ASM International 58 51 ASM PT market capitalisation (HKDm) 45,286 44,469 ASM PT market capitalisation (EURm) 4,917 4,828 Stake of ASM International in ASM PT 25% 39% Current value of ASM Intl's stake (EURm) 1,240 1,902 (B) Current value of ASM Intl's stake (EUR/sh) 21 33 (A)-(B) Intrinsic value of the Front End business (in EUR/sh) 37 18 Intrinsic value of the Front End business (in EURm) 1,205 677 Net debt on 31/12/17 (EURm) -928 -379 Revenues 791 725 Intrinsic EV/Sales ratio 1.5x 0.9x EBIT 125 109 Intrinsic EV/EBIT ratio 9.6x 6.2x
Source: Bryan, Garnier & Co ests.
The valuation ratios for ASM International’s core business thus point to an average re-rating potential of about 40% based on the average valuation ratios for the sector.
Note that this exercise, carried out using the data available on the day before the announcement of the sale of a block in ASM PT last April, derives respective intrinsic EV/Sales and EV/Operating profit ratios of 0.9x and 6.1x. The re-rating of the Front-End activity hoped for by the management and shareholders has effectively taken place but is clearly not yet complete.
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Intentionally left blank
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INDEPENDENT RESEARCH ASML 16th January 2018 Ideally positioned to capture the growth TMT Fair Value EUR180 vs. EUR175 (price EUR149.35) BUY-Top Picks
Bloomberg ASML NA Early in 2018, the success of EUV systems is no longer in doubt and all Reuters ASML.AS eyes are now on ASML’s ability, and that of its suppliers, to ramp up 12-month High / Low (EUR) 158.5 / 107.8 production of these new generation tools. The group is thus in a Market capitalisation (EURm) 64,439 Enterprise Value (BG estimates EURm) 64,374 comfortable situation with an order book equipping all the EUV fabs Avg. 6m daily volume ('000 shares) 1,150 through to the end of 2018e. With a buoyant context and a 2018 which Free Float 58.6% should continue to see strong growth, we maintain our Buy 3y EPS CAGR 26.8% Gearing (12/16) -8% recommendation and adjust our FV from EUR175 to EUR180. Dividend yields (12/17e) 0.80%
Visibility continues to improve on EUV. While this technology has YE December 12/16 12/17e 12/18e 12/19e taken a while to prove its viability, this is no longer an issue. The Group Revenue (EURm) 6,795 8,616 10,025 10,624 EBITA EURm) 1,658 2,294 3,007 3,428 has managed to supply its three large customers, i.e. Intel, Samsung and Op.Margin (%) 24.4 26.6 30.0 32.3 TSMC, with tools that are sufficiently high-performance to justify the Diluted EPS (EUR) 3.44 4.50 6.02 7.02 EV/Sales 9.38x 7.47x 6.34x 5.86x EUR110m unit price demanded by ASML. And with the ongoing race for EV/EBITDA 31.6x 23.8x 18.5x 16.1x efficiency and ever-finer etching, these players are increasingly inclined to EV/EBITA 38.4x 28.1x 21.1x 18.2x up their levels of capex so as not to fall behind. 2018 should be the year in P/E 43.4x 33.2x 24.8x 21.3x ROCE 15.9 18.8 23.8 26.6 which EUV finally enters production, something which should further
increase the whose industry’s interest in this technology. We expect a 138.4 gradual increase in EUV systems sales to 48 units in 2020e, i.e. the 128.4 maximum capacity of ASML’s EUV plant.
118.4 108.4 China and the memory producers are also increasingly big spenders. 98.4 As shown in our sector note, the total investment spend for fabs continues 88.4 to grow and should reach another record-year by 2018. We thus have no 78.4 reason to anticipate a fall in DUV system revenues. Our model has sales 68.4 21/01/16 21/04/16 21/07/16 21/10/16 21/01/17 21/04/17 21/07/17 of EUR10.0bn in 2018e and EUR12.1bn by 2020e. Overall, the strong ASML HOLDING SXX EUROPE 600 momentum leads us to lift our estimates by 4% on average over the next three years.
We maintain our Buy recommendation. Following the change to our industry scoring methodology, ASML’s beta is negatively impacted. Nevertheless, this update is counterbalanced by the upwards adjustment to our estimates. Our new FV is thus EUR180 (vs. EUR175).
Analyst: Analyst: Doiran Terral Frédéric Yoboué 33(0) 1.56.68.75.92 33(0) 1 56 68 75 54 [email protected] [email protected]
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Simplified Profit & Loss Account (EURm) 31/12/14 31/12/15 31/12/16 31/12/17e 31/12/18e 31/12/19e 31/12/20e Revenues 5,856 6,287 6,795 8,616 10,025 10,624 12,151 Change (%) 11.6% 7.4% 8.1% 26.8% 16.3% 6.0% 14.4% Gross profit 2,596 2,896 3,045 3,869 4,762 5,174 6,501 Adjusted EBITDA 1,547 1,864 2,018 2,707 3,432 3,873 5,109 Adjusted EBIT 1,282 1,565 1,658 2,294 3,007 3,428 4,654 EBIT 1,282 1,565 1,658 2,294 3,007 3,428 4,654 Change (%) 22.4% 22.1% 5.9% 38.4% 31.1% 14.0% 35.7% Financial results (8.6) (16.5) 33.7 (47.4) (55.1) (26.6) (24.3) Pre-Tax profits 1,274 1,549 1,691 2,246 2,952 3,402 4,630 Tax (77.0) (161) (220) (302) (384) (442) (625) Net profit 1,197 1,387 1,472 1,944 2,568 2,960 4,005 Adjusted net profit 1,197 1,387 1,472 1,944 2,568 2,960 4,005 Change (%) 17.8% 15.9% 6.1% 32.1% 32.1% 15.2% 35.3% Depreciation & amortisation Change in working capital (607) 17.4 0.0 (961) (428) (182) (464) Operating cash flows 1,025 2,026 1,666 1,551 2,565 3,222 3,995 Capex, net (361) (545) (2,988) (343) (451) (478) (486) Free Cash flow 664 1,481 (1,323) 1,208 2,114 2,744 3,509 Financial investments, net 345 (615) (200) 550 0.0 0.0 0.0 Dividends (268) (302) (446) (517) (589) (669) (760) Issuance of shares 39.7 33.2 583 37.6 0.0 0.0 0.0 Issuance (repayment) of debt (4.1) (3.6) 2,226 (242) 0.0 0.0 0.0 Other (696) (561) (399) (381) (750) (750) (800) Net debt (1,600) (2,279) (737) (64.9) (840) (2,165) (4,114) Tangible fixed assets Intangibles assets & goodwill 3,526 3,814 6,809 6,348 6,343 6,338 6,333 Deferred tax assets 188 162 34.9 25.5 25.5 25.5 25.5 Other non-current assets 55.3 124 117 264 264 264 264 Cash & equivalents 2,754 3,409 4,057 3,309 4,084 5,409 7,358 Company description Current assets 4,232 4,166 4,501 4,883 5,670 6,004 6,857 Total assets 12,204 13,295 17,206 17,416 19,004 20,696 23,529 ASML is an equipment maker Shareholders' equity 7,513 8,389 9,820 10,600 11,830 13,370 15,815 specialised in lithographic tools for the Provisions 6.0 4.9 22.3 23.0 23.0 23.0 23.0 semiconductors industry. In a growing Deferred tax liabilities 276 263 599 522 522 522 522 lithography market, the group has Current liabilities 3,256 3,509 3,445 3,027 3,385 3,537 3,925 L & ST Debt 1,154 1,130 3,320 3,244 3,244 3,244 3,244 managed to increase its market share Total Liabilities 12,204 13,295 17,206 17,416 19,004 20,696 23,529 over the years, from 30% in 2000 to Capital employed 5,912 6,110 9,083 10,535 10,990 11,205 11,701 80% at present. ASML is the only Ratios group to have invested in the EUV Gross margin 44.33 46.06 44.81 44.90 47.50 48.70 53.50 technology, enabling a further Operating margin 21.90 24.89 24.40 26.62 30.00 32.27 38.30 reduction in the size of transistors Tax rate 6.05 10.42 12.98 13.46 13.00 13.00 13.50 Net margin 20.43 22.06 21.66 22.56 25.62 27.86 32.96 making up chip components and ROE (after tax) 15.93 16.54 14.99 18.34 21.71 22.14 25.32 solving the cost equation facing the ROCE (after tax) 20.38 22.95 15.88 18.84 23.81 26.62 34.41 semiconductors industry. As an Gearing (21.30) (27.17) (7.51) (0.61) (7.10) (16.19) (26.01) equipment maker, the group is Pay out ratio 22.28 21.73 30.36 26.53 22.82 22.51 18.89 Number of shares, diluted 440 433 428 432 427 422 416 dependent on investments by semiconductors manufacturers Data per Share (EUR) EPS 2.74 3.22 3.46 4.52 6.05 7.05 9.66 including Intel, Samsung, TSMC, Restated EPS 2.72 3.21 3.44 4.50 6.02 7.02 9.62 SMIC, SK Hynix, Micron… % change 16.2% 17.8% 7.3% 30.8% 33.7% 16.6% 37.1% BVPS 17.09 19.39 22.96 24.55 27.72 31.70 37.98 Operating cash flows 2.33 4.68 3.90 3.59 6.01 7.64 9.59 FCF 1.51 3.42 (3.09) 2.80 4.95 6.51 8.43 Net dividend 0.61 0.70 1.05 1.20 1.38 1.59 1.83
Source: Company Data; Bryan, Garnier & Co ests.
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INDEPENDENT RESEARCH BE Semiconductor (Besi) 16th January 2018 Buy what industry needs! TMT Fair Value EUR91 (price EUR76.65) BUY Coverage initiated
Bloomberg BESI NA We are initiating coverage of Besi with a Buy recommendation and a Reuters BESI.AS FV of EUR91 (+19%). The company has a leadership position in 12-month High / Low (EUR) 76.7 / 33.3 Advanced Packaging equipment, and should benefit from the current Market capitalisation (EURm) 3,069 Enterprise Value (BG estimates EURm) 2,908 context which is favourable to back-end technologies. After an Avg. 6m daily volume ('000 shares) 187.8 excellent set of results for the first nine months of 2017, the company Free Float 100% should be supported in the short term by positive expectations 3y EPS CAGR 41.8% Gearing (12/16) -41% regarding both industry spending on equipment and the growth Dividend yields (12/17e) 2.09% dynamic in the various end markets. These drivers of outperformance seem not to be fully priced in the current consensus. YE December 12/16 12/17e 12/18e 12/19e Revenue (EURm) 375.38 596.89 653.60 669.94 A context highlighting Besi’s expertise. The progressive adoption of EBITA EURm) 75.2 214.5 242.5 233.1 nodes below 20nm, and the complexity encountered with miniaturisation Op.Margin (%) 20.0 35.9 37.1 34.8 Diluted EPS (EUR) 1.70 4.37 4.98 4.84 technologies are casting a positive light on the back-end players who are EV/Sales 7.80x 4.87x 4.37x 4.20x developing advanced solutions. With a strategy focused on high-end tools, EV/EBITDA 32.6x 12.8x 10.9x 11.1x Besi represented an average 80% of its main IDM customers’ backlogs for EV/EBITA 38.9x 13.6x 11.8x 12.1x P/E 45.2x 17.6x 15.4x 15.8x die attach equipment at the end of the 2017 Q3, and should thus benefit ROCE 37.7 84.8 85.1 78.0 from the favourable context to affirm its competitive advantage in Advanced Packaging equipment which contributed 30% of its 2016 93.1 revenue. 83.1
73.1 The 63.1 Artificial intelligence will be a significant growth driver. proliferation of connected objects and democratisation of artificial 53.1 intelligence applications is leading to in-depth changes in the technological 43.1 architecture of data centers whose processing power requirement and 33.1 demand for memory chips with substantial bandwidth is accelerating. 23.1 15/07/16 15/10/16 15/01/17 15/04/17 15/07/17 15/10/17 15/01/18 BE SEMICONDUCTOR SXX EUROPE 600 TECHNOLOGY These changes are increasing the use of the fan-out (+107% yoy in 2018e) and TCB/TSV (+67%e) technologies where Besi holds a respective 75% market share and 50% of the installed base.
Opportunities to seize in China. In 2014, Besi launched a geographical diversification plan focused on the Asian continent to benefit from, amongst other things, the Chinese government’s USD161bn of investment in semiconductors through to 2025. Despite a brand image which still needs to be established in the region, this development represents a real growth opportunity for the group.
Analyst: Analyst: Doiran Terral Frédéric Yoboué 33(0) 1.56.68.75.92 33(0) 1 56 68 75 54 [email protected] [email protected]
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Simplified Profit & Loss Account 31/12/20e 31/12/14 31/12/15 31/12/16 31/12/17e 31/12/18e 31/12/19e (EURm) Revenues 379 349 375 597 654 670 772 Change (%) 48.6% -7.8% 7.5% 59.0% 9.5% 2.5% 15.2% Adjusted EBITDA 82.1 73.0 89.8 228 262 253 296 Adjusted EBIT 72.1 57.9 75.2 214 242 233 272 EBIT 72.1 57.9 75.2 214 242 233 272 Change (%) 282% -19.7% 29.8% 185% 13.1% -3.9% 16.8% Financial results (0.74) (0.79) (1.6) (8.9) (6.5) (6.7) (7.7) Pre-Tax profits 71.3 57.1 73.6 206 236 226 265 Tax (0.20) (8.1) (8.3) (28.1) (35.4) (34.0) (39.7) Net profit 71.1 49.0 65.3 178 201 192 225 Adjusted net profit 71.1 49.0 65.3 178 201 192 225 Change (%) 341% -31.2% 33.4% 172% 13.0% -4.0% 16.9% Cash Flow Statement (EURm) Depreciation & amortisation 10.0 15.1 14.6 13.4 19.6 20.1 23.1 Change in working capital (10.9) 16.8 3.9 (53.4) (17.4) (5.0) (31.3) Operating cash flows 72.9 86.5 98.7 169 203 208 217 Capex, net (15.8) (9.8) (11.2) (11.2) (19.6) (20.1) (23.1) Free Cash flow 57.1 76.7 87.5 157 183 187 194 Acquisition, net 0.0 0.0 0.0 0.0 0.0 0.0 0.0 Financial investments, net 0.0 0.08 (80.0) (25.0) 0.0 0.0 0.0 Dividends 0.0 (56.9) (45.4) (65.3) (93.4) (105) (101) Issuance (repurchase) of own shares 1.1 (3.5) (22.0) (24.5) (32.0) (36.0) (36.0) Issuance (repayment) of debt (1.6) 4.2 127 (6.0) 0.0 0.0 0.0 Other (29.0) 3.2 (42.6) (17.2) (5.3) (1.5) (9.5) Net debt (93.1) (117) (141) (160) (213) (257) (304) Balance Sheet (EURm) Tangible fixed assets 27.2 26.7 27.0 22.9 11.2 (0.90) (14.8) Intangibles assets & goodwill 84.8 85.9 83.7 81.9 93.6 106 120 Investments 0.0 0.0 0.0 0.0 0.0 0.0 0.0 Company description Deferred tax assets 21.7 18.5 14.3 9.7 9.7 9.7 9.7 BE Semiconductor Industries (Besi) is Other non-current assets 1.7 2.7 2.5 2.5 2.5 2.5 2.5 developing and manufacturing Cash & equivalents 135 158 305 340 398 444 501 semiconductor assembly equipment Inventories 69.4 53.9 55.1 70.9 77.6 79.6 91.6 targeting Back-end of Line (BEoL) Current assets 104 87.1 100 179 195 200 228 Total assets 444 433 588 707 788 840 938 production. It operates through three Shareholders' equity 329 332 345 427 508 566 662 segments: Die Attach, Packaging and Provisions 0.0 0.0 0.0 0.0 0.0 0.0 0.0 Plating. It develops assembly Deferred tax liabilities 6.0 6.2 6.7 4.7 (1.8) (8.5) (16.3) processes and equipment for Current liabilities 92.3 73.0 99.1 144 149 151 160 L & ST Debt 17.4 21.4 137 132 132 132 132 leadframe, substrate and wafer level Total Liabilities 444 433 588 707 788 840 938 packaging applications in a range of Capital employed 211 196 177 218 242 254 293 end user markets, including Ratios electronics, computer, automotive, Gross margin 43.78 48.81 51.01 57.28 57.60 55.50 55.00 industrial and solar energy. Adjusted operating margin 19.03 16.58 20.02 35.93 37.10 34.80 35.30 Tax rate 0.27 14.27 11.23 13.65 15.00 15.00 15.00 Adjusted Net margin 18.78 14.02 17.39 29.74 30.69 28.73 29.16 ROE (after tax) 21.63 14.74 18.92 41.61 39.45 34.00 33.99 ROCE (after tax) 34.08 25.36 37.71 84.84 85.08 78.02 79.03 Gearing (28.33) (35.20) (40.86) (37.59) (41.86) (45.45) (46.00) Pay out ratio 0.0 116 69.51 36.77 46.58 54.75 44.91 Number of shares, diluted 37.98 38.50 38.51 40.68 40.26 39.79 39.32 Data per Share (EUR) EPS 1.87 1.27 1.70 4.37 4.98 4.84 5.72 Restated EPS 1.87 1.27 1.70 4.37 4.98 4.84 5.72 % change 335% -31.9% 33.3% 157% 14.1% -2.9% 18.3% BVPS 8.66 8.63 8.96 10.49 12.63 14.23 16.83 Operating cash flows 1.92 2.25 2.56 4.15 5.04 5.22 5.52 FCF 1.50 1.99 2.27 3.87 4.55 4.71 4.93 Net dividend 0.0 1.48 1.18 1.61 2.32 2.65 2.57
Source: Company Data; Bryan, Garnier & Co ests.
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Table of contents
1. Investment Case ...... 94
2. The back-end is the new front-end ...... 95 2.1. A context favourable to Advanced Packaging ...... 95 2.2. A particular focus on FOWLP ...... 97
3. Besi is well positioned to capture the market growth ...... 100 3.1. Snapshot ...... 100 3.2. A specialist in advanced packaging ...... 101 3.3. Strong positioning in the automotive industry ...... 102 3.4. Artificial intelligence is acclerating cloud computing and the need for memory . 104 3.5. Mobile components gaining in complexity ...... 106
4. A big winner in advanced packaging ...... 109 4.1. A premium strategy in the assembly industry ...... 109 4.2. China: a dual challenge for Besi ...... 111
5. Our central scenario ...... 113 5.1. A second year of growth to come ...... 113 5.2. A favorable context for margin expansion ...... 114 5.3. Strong cash generation opens perspective for transformational transaction ...... 115
6. A significant upside potential ...... 116 6.1. We have a Buy recommendation ...... 116 6.2. A DCF at EUR92 per share ...... 116 6.3. Peer comparison of EUR89 ...... 118
Bryan Garnier stock rating system...... 119
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1. Investment Case
The reason for writing now Our sector review published in parallel with this note outlines the technological challenges the industry players are facing in terms of innovation. This context puts back-end solutions in the sweetspot and the industry has embarked on a significant investment phase which looks set to continue in 2018. Given its expertise and positioning focused on advanced equipment, Besi seems to be the main beneficiary of this environment.
Valuation Our EUR91 Fair Value stems from the average between a peer comparison (FV EUR89) and a DCF valuation (FV EUR92 with WACC of 8.7%). On the basis of our estimates, the share is trading on 2018e P/E of 15.4x and PEG of 1.9x.
Catalysts The Besi share price should react to the following: 1/ the penetration of Advanced Packaging applications which is likely to depend on the adoption of advanced nodes; 2/ investment growth by the leading players and Besi’s customers in memory, computing and automotive, like Micron, Samsung, Intel and Infineon; 3/ the trend towards concentration and the health of the OSATs in China, accompanied by the Chinese government’s investment plans, particularly in complex applications.
Difference from consensus Our sector note attempts an in-depth review of the major challenges in the semiconductor sector over the short and medium term, at both financial and technical level. As we write, we believe that the consensus is not factoring in (or only partially) 1/ a second year of investment growth driven by memory, and 2/ gains in market share for Besi whose advanced applications should benefit from a powerful growth dynamic in data centers and the automotive industry.
Risks to our investment case Our forecasts mostly depend on sector capex plans that have been announced or are anticipated, and may be subject to volatility on both the upside and downside depending on the economic backdrop. The Besi investment case is also based on the growth momentum in its market segments and the penetration of Advanced Packaging technologies. Lastly, we believe that the investment in capex in 2018 will be particularly exposed to memory applications and Chinese spending.
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2. The back-end is the new front-end 2.1. A context favourable to Advanced Packaging In the semiconductor industry value chain, the front-end players are responsible for developing the technologies used in transistor manufacturing, and the back-end players supply the component assembly tools along with the appropriate testing tools.
The front-end has benefited more from overall capex growth since this part of the chain contributed more added value to the technological change compared with the back-end which, while necessary, was less disruptive in terms of differentiation and innovation. According to Gartner, investment in the front-end grew by 5.5% on average between 2014 and 2016, and represented 80% of total equipment spending in 2016, versus a 3.8% decline in back-end investment.
However, momentum now seems to be shifting towards the back-end thanks, in part, to Advanced Packaging. After the frantic technological developments in miniaturisation dictated by Moore’s law, pronouncing the emergence of a new technology node every 18 to 24 months, we are currently seeing a slowdown in miniaturisation. This slowdown is being manifested in longer and more costly development of front-end technologies for an equivalent improvement in performance and, by domino effect, slower adoption of these technologies hy the industry (cf. Sector Note Part 2.1).
These constraints, which are mainly being seen on advanced nodes below 20nm, are casting a positive light on back-end technologies and investment in this equipment should represent 23% of total spending in 2017. In addition to the transfer of a portion of front-end investment towards the back- end, this growth cycle should be underpinned by 1/ the progressive adoption of advanced nodes which require more Advanced Packaging solutions to take benefits of scaling and further improve performance of the chip, 2/ initiatives from the Chinese government which could inject nearly USD161bn into semiconductor-related infrastructure through to 2025, and 3/ a capex uptick in some sectors like automotive, computing and memory.
In the back-end, spending on assembly equipment, in which Besi is involved, thus progressed by 12.5% in 2016 and should grow by a respective 23.1% and 4.1% in 2017 and 2018, according to the latest estimates from research company VLSI. This is much faster than overall spending for which growth is estimated by Gartner at 10.2% and -0.5% in 2017 and 2018 respectively.
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Fig. 1: 16-21e sales CAGR of 7.9% for assembly equipment
6000
5000
4000
3000
2000
Assembly market (USDm) 1000
2016 2017e 2018e 2019e 2020e 2021e
Source: VLSI (October 2017)
In back-end equipment, investment in advanced packaging tools should grow more rapidly. These technologies enable a considerable reduction in the size of the envelope that encapsulates and protects the dies, and the creation of interconnects and assembly structures which optimise performance and energy consumption.
Fig. 2: Advanced packaging applications are becoming increasingly popular
50 42%
40% 40 TSV 38% 30 FOWLP 36% FIWLP 20 Fli p chi p 34% AP penetration M wafers, Eq. 300mm wafers, M 10 32%
0 30% 2016 2017e 2018e 2019e 2020e 2021e
Source: VLSI (January 2017)
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2.2. A particular focus on FOWLP FOWLP is an advanced packaging technology which enables a reduction in semi-conductor size and enhanced performance. One of the characteristics of this technology, notably in comparison with the BGA flip-chip, is the absence of advanced substrates between the interconnects at the level of the silicon and the PCB. This means a thinner chip and a gain in design flexibility, together with an improved electrical and thermal performance resulting from shorter interconnects.
Fig. 3: Apple’s A10 chip is thinner with nearly 60%* more performance
Source: Yole; *Geekbench
In view of the manufacturing complexity and a higher profitability threshold, the sales volume of applications based on FOWLP packaging is currently limited to applications with space and efficiency issues. This is particularly the case for the Analogue chips (RF, audio, bluetooth, etc.) used in mobiles, connected objects and the automotive industry.
In these activities, Besi has good commercial relationships with major IDMs and OSATs like Infineon (95% of the die attach backlog in 2017 YTD), STMicroelectronics (80%), SPIL (60%), JCET/STATS ChipPAC (80%), ASE (60%), and Amkor (75%) (Fig. 10). Besi should benefit from the growth in the FOWLP overall market which is estimated at a respective 52% and 88% in 2017 and 2018, to reach USD209 million and USD394 million, according to research company Yole Développement.
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Fig. 4: Numerous Besi customers are involved in advanced packaging
Intel Others 12.4% 33.0% SPIL 11.6%
JCET/STATS ChipPAC 7.8% ASE 7.7% Amkor 6.4% TSMC ChipBond 6.6% Samsung 7.5% 7.0% In million wafers, 300mm eq
Source: Yole (June 2017)
There are several FOWLP technologies, for example the eWLB (embedded Wafer Level Ball Grid Array), RCP (Redistributed Chip Packaging), M-series, and inFO (integrated FO). However, only the eWLB and inFO technologies represent a significant proportion of the market. eWLB was initially developed by Infineon, STATS ChipPAC and STMicroelectronics, and now represents the quasi- totality of core-FO production (applications with low-density transistors and/or a limited number of inputs/outputs).
InFO is a TSMC technology which arrived in 2016 to equip all iPhone and iPad’s AXX series processor as of today. It currently represents the first and only FOWLP technology designed for high-density applications. In view of the substantial volumes ordered by Apple and a pricing effect which is above the core-FO applications, inFO is expected to represent around 42% of the FOWLP market in 2017.
Fig. 5: FOWLP market growth (in USD million)
2500
2000
1500 High-density FO
1000 "Core" F O
500
0 2014 2015 2016 2017e 2018e 2019e 2020e 2021e
Source: Yole (August 2017)
The performance plaudits for the A10 and A11 processors manufactured by TSMC are prompting Samsung and Qualcomm to develop similar technologies. We thus see TSMC’s rival foundries, first Samsung followed by certain OSATs, investing in FOWLP equipment to capture market share in high-density applications.
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Furthermore, we know that Samsung’s electronic component division, Samsung Electro-Mechanics Co. (SEMCO) stepped up investment in R&D as of 2016 aimed at the development of FO-Panel Level Packing (FOPLP). The companies ASE and Nepes are also said to be amongst those to be developing the future generations of FOPLP technology.
As its name indicates, FOPLP uses rectangular panels as the carrier replacing the traditional wafers. Source: Besi With dimensions of up to 600x600mm, these panels can provide a much larger surface on which to position the dies (see the sector note section 3.1.3), and thus reduce the production costs of the FO technologies.
Fan-out represents a major priority for numerous players, who have been working to make this type of production more accessible. Within this context, FOPLP is an attractive alternative however, unlike traditional wafers, the panels suffer from a lack of standardisation and come in several formats. This is a major drawback in terms of the adoption of this technology since the absence of norms reduces the equipment compatibility to a limited number of chipmakers, something which is likely to result in an automatic and significant increase in manufacturing costs.
Fig. 6: Several sizes of panel in development
Commercial Companies Panel Size Production date Amkor Not disclosed Still in R&D 300mm x 300mm ASE/Deca 2018/2019 and/or 600mm x 600mm Nepes 650mm x 700mm Late 2017 Powertech 370mm x 470mm (LCD) Not disclosed Samsung 600mm x 720mm (LCD) Not disclosed Samsung 730mm x 920mm (LCD) Not disclosed Samsung 400mm x 500mm (LCD) Not disclosed SPIL 370mm x 470mm (LCD) Not disclosed STATS ChipPAC Not disclosed Still in R&D TSMC Not disclosed Not disclosed Unimicron Not disclosed Not disclosed Source: Company data; SemiEngineering; Bryan, Garnier & Co ests.
Samsung is likely to be working on two panel sizes and two FOPLP technologies. A first technology dubbed ePLP for small-dies with multi-die to be delivered during the second half of 2018 and a second technology known as PLP-m for more sophisticated applications which is expected to follow later.
Besi is involved in the development of these tools in partnership with Samsung, TSMC and Hynix, but does not foresee any contribution to sales in the short term.
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3. Besi is well positioned to capture the market growth 3.1. Snapshot Die Attach Equipment Packaging Equipment Plating Equipment
5% 20%
75% % of sales
momentum Revenue & margins
- Die Bonding (2100xP, 2100 sD, 2009 SSI,…) - AMS-i (Leadframe, MEMS, Sensors) - Multi Module Attach (2200 evo, 2200 evo hS...) - AMS-W/LM (Substrate) - Flip Chip (8800 Chameo, 8800 TCB, 8800 FC, - FML (Wafer, Panel) - Plating (Leadframe, Solar, Film & Foil, Battery) 2100 FC,…) - FCL (X, P, X/P) - Die Sorting (WTT, TTR) - FSL (Singulation, Sorting) Key products - Die Lid Attach (DLA)
Single chip, multi chip, multi module, flip chip, Conventional, ultra thin and wafer level molding, Tin, copper and precious metal plating systems TCB and eWLB die bonding systems and die trim and form and singulation systems. and related process chemicals. sorting systems. Key applications
- ASM Pacific Technology - Towa - Hitachi - Hanmi - ClassOne Technologies - Shinkawa - ASM Pacific Technology - Toray Key competitors
- ASE - ASE - ASE
- Amkor - Amkor - Amkor - Cowell/Foxconn - Cowell/Foxconn - Cowell/Foxconn - Infineon - Infineon - Infineon - JCET/STATS - JCET/STATS - JCET/STATS - NXP - NXP - NXP (examples) - Qorvo - Qorvo - Qorvo Key consumers - STMicroelectronics - STMicroelectronics - STMicroelectronics
-IDMs and Foundries capex -IDMs and Foundries capex - Advanced packaging penetration - Advanced packaging penetration - Solar market development - Automotive and computing markets - Automotive and computing markets - China's investments plan - China's investments plan Key catalysts
Source: Company Data; Bryan, Garnier & Co ests.
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3.2. A specialist in advanced packaging Besi is an equipment manufacturer specialised in the development of tools destined for the back-end. These tools are sold to IDMs’ fabs and to back-end specialised sub-contractors (OSATs for Outsourced Assembly and Test) responsible for the manufacturing of electronic components. For several years, the company has built up expertise in the equipment required for complex and high- performance applications.
The company has a diversified portfolio of equipment, classified under three categories:
Plating equipment (5% of 2016 sales) is mainly designed to protect the substate from physical alterations, improve conductivity and reinforce the resistance to heat emission. It is in this segment that Besi has the largest market share. The company is currently developing a copper plating for solar applications. Besi expects the efficiency of this technology to be better than that of the silver plating used until now, and the company could benefit from a positive trend in line with the penetration of photovoltaic solutions.
The Die Attach (70% of 2016 sales) and Packaging (25%) products sold by Besi cover the main back-end assembly processes like leadframe, wire bonding, flip chip and wafer level packaging (WLP) bonding systems. The Advanced Packaging technologies used in the flip chip or WLP processes like the TCB (Thermal Conductive Bonding), TSV (Through Silicon Via) and FOWLP (eWLB and inFO) technologies saw a substantial round of investment by the foundries in 2016 and contributed around 30% of Besi’s sales in the same year. Besi’s systems represent around 50% of the TCB/TSV systems in circulation with signficant penetration in memory and GPU applications, and a market share of some 75% in FOWLP.
Fig. 7: Besi’s product portfolio
Source: Company Data
Besi’s main competitor is ASM Pacific Technology (ASMPT), the global leader in back-end equipment with an assembly market share of around 25% and sales of USD931 million (50% of consolidated revenues) in 2016. The company is number one in the CIS applications (CMOS Imaging Sensors) used in smartphones, and has a strong position in the technologies used in LED screens and the automotive
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industry. Like Besi, ASMPT is positioned on Advanced Packaging solutions like the flip chip, TCB and FOWLP.
While, in 2016, ASMPT benefited from a favourable trend notably thanks to the sale of solutions for LED sensors where Besi is not present, in 2017 Besi’s sales are being underpinned by an acceleration in the sales of Advanced Packaging applications, and favourable strategic positioning in the automotive industry and datacenters.
Fig. 8: Besi has significantly outperformed its peers in the last two quarters
80.0%
60.0%
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20.0%
0.0% YoY revenue growth -20. 0%
-40. 0% 4Q 2015 1Q 2016 2Q 2016 3Q 2016 4Q 2016 1Q 2017 2Q 2017 3Q 2017 Calendar period
ASMPT (Back-end segment, USDm) Be si (US Dm ) K&S (USDm)
Source: Company Data; Bryan, Garnier & Co ests.
The expected development of technologies in the automotive industry and computing (via data centers), which represent a respective 18% and 24% of Besi’s sales, encourage us to believe that this outperformance could continue in the coming quarters.
3.3. Strong positioning in the automotive industry According to WSTS, the market for semiconductors in automotive should post growth of 12% in 2017, followed by an average of +10% between 2016 and 2019. The vehicle fleets in production are moving in the electrical and autonomous/assisted driving paradigm, and integrate far more complex functions which require more electronic components than previously. Soon, nearly 80% of innovation in the automotive sector should be driven by semiconductors components, according to numerous industry experts.
The complexity of the screen, connectivity features, GPS and radar applications incoporated in today’s vehicles require a progressive migration to advanced technologies in order to reduce component size, introduce more components and functionalities, and improve the performance of chips.
The functionalities contributed by these new technologies are becoming pertinent marketing arguments extoling the driving experience, comfort and safety, while the differentiation between manufacturers increasingly involves embedded electronics. The penetration of image sensors could also be driven by regulatory changes in favour of better road safety. For example, the United States is expected to make a rear camera mandatory in all vehicles manufactured from May 2018.
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Fig. 9: Multiple cameras in some vehicle models
Source: Company data; Bryan, Garnier & Co ests.
Image sensors for ADAS (Advanced Driving Assistance Systems) systems are becoming more accessible and we are witnessing an acceleration in the adoption of RADAR and LIDAR technologies. These advanced driver assistance chip technologies are manufactured by players like Infineon, NXP and Bosch, and require the advanced packaging technologies that Besi is able to supply.
Via its high-end positioning, Besi has long maintained commercial relationships with many of the leading IDMs and captures a significant market share of their backlogs in both die attach and packaging.
Fig. 10: Substantial market shares with major players
100% 100%
80% 80%
60% 60%
40% 40%
20% 20% Share of clients' die attach orders attach die clients' of Share 0% orders packaging cleints' of Share 0% ST Micro Infineon NXP Bosch ST Micro Infineon NXP
FY15 FY16 FY 17e FY15 FY16 FY 17e
Source: Company Data; Bryan, Garnier & Co ests.
In 2016, Besi generated 18% of its sales with the automotive industry, i.e. around EUR68m. In 2017, the company has benefited from a positive investment round by the foundries and IDMs specialised in automotive and, given the figures for the first three quarters and the Q4 guidance, we expect the company to generate at least EUR110m in this segment (or 18% of 2017e total sales), i.e. year-on-year growth of 62% in 2017.
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3.4. Artificial intelligence is accelerating cloud computing and the need for memory Cloud computing is another powerful catalyst – The high demand for storage in data centers is in response to multiple needs 1/ limited local storage faced with the exponential growth in data usage, 2/ increased flexibility for the management and deployment of business services, 3/ the need to collect, aggregate, index and analyse a massive amount of data for various needs, all leveraging artificial intelligence algorithms. One just needs to look at cloud services revenue from Amazon’s AWS and Microsoft’s Azure, which grew 42% over the first three months of 2017 for AWS and 99% from June 2016 to June 2017 for Azure.
Increasingly sophisticated needs – This massive transfer of data to existing data centers has rapidly called into question their architectures which were no longer suited to the requirements. In addition to the need to adopt more advanced nodes like the 10nm currently and the 7nm in the months to come (cf. sector report part 2.2), there has been an in-depth change in the type of components used.
Until now, Intel had enjoyed a virtual monopoly in cloud computing thanks to its CPU (Central Processing Unit) expertise. However, with Moore’s law reaching its limits, the innovation in transistors’ size, which has long supported the hegemony of CPU processors for resource-hungry applications, is no longer providing an adequate improvement in performance and energy management, prompting the chipmakers to turn to chip designs that are more adapted to the challenges involved in big data and artificial intelligence.
These reasons partly explain the unprecedented success of the GPU (Graphic Processor Unit) chips from Nvidia, the latter having hitherto been known for its graphic processors dedicated to video games. After years of research and development, the US company has developed GPUs specially manufactured for artificial intelligence tasks. Some of Nvidia’s graphic chips have up to more than 3,500 processing cores to compute data while an Intel CPU chip numbers only up to 28. Other integrated circuits are also being brought to the fore by artificial intelligence like ASICs (Application Specific Integrated Circuits) and FPGAs (Field-Programmable Gate Arrays) which bring greater design flexibility.
Fig. 11: Nvidia is surfing on the back of data center development
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0 Jun-14 Sep-14 Dec-14 Mar -15 Jun-15 Sep-15 Dec-15 Mar -16 Jun-16 Sep-16 Dec-16 Mar -17 Jun-17 Sep-17
Stock price (Base 100) Datacenter r ev enue (Base 100)
Source: Company Data; Reuters Knowledge; Bryan, Garnier & Co ests.
Memory component demand seeing strong growth in 2017 – The substantial increase in memory component prices in 2017 is the result of an acute supply-demand inbalance. According to the Yole
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The insatiable need for memory in smartphones and data centers is fed by 1/ an increase in volume of smartphones and connected objects, 2/ a ever-more complex, diverse and varied quantity of information navigating between devices and servers to power intelligent personnal assistants, or automatic image/photo processing, applications that use massive articifial intelligence ressources.
On the memory supply side, the players had been lagging on investment since they were suffering from a highly competitive environment and difficulties in migrating to the more advanced nodes requiring the involvement of 3D structures. The latter have recently decided to invest in upgrading the installed base and the construction of new plants. IC Insights estimates show memory-linked equipment spending reaching USD42bn in 2017, growth of 84%.
What will be the impact on a player like Besi? – 24% of Besi’s equipment sales come from computing and c. 15% of the company’s sales are exposed to memory components. The technological changes outlined above in Logic applications and Memory in data centers are going to increase the use of the BGA flip-chip, WLCSP, FOWLP and TCB/TSV technical processes. Besi’s expertise in this premium equipment (the company has a market share of c. 75% in FOWLP and 50% of the TCB/TSV equipment installed base) and its close commercial relationships with companies like Micron, Samsung, and Intel underpin our view that the company should benefit to the full from the growth momentum in data centers and artificial intelligence.
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3.5. Mobile components gaining in complexity A segment which remains dynamic – the four main pillars of smartphone innovation, i.e. the processor, camera, screen and memory, justify the annual device upgrades by most manufacturers. The semiconductor market growth in mobiles is estimated to 5% CAGR over the next three years, supported by: 1/ penetration of smartphones in mobile which should reach 77% in 2020 (vs. 74% in 2016) thanks to average annual volume growth of 3%, 2/ increase in the value of components which are more and more complex, 3/ proliferation of the components used in smartphones which contribute to additional features.
Proliferation of cameras in smartphones - In 2016, Huawei and LG were the first to market smartphones with dual-rear cameras followed by the iPhone 7 Plus in the third quarter of the same year. The increased share of the large format in the Apple smartphone mix compared with previous generations shows the attraction of this function to consumers, to such a point that the iPhone 8 Plus is likely to sell better than the smaller model according to numerous surveys. Since Apple frequently plays the role of industry pioneer, we are already seeing the massive adoption of these modules in high- end smartphones and, to our knowledge, only Google with its Pixel 2 has not opted for this functionality (but rather opted in favor of more photo processing through software and artificial intelligence). The Yole Développement institute estimates that one in five smartphones will be equipped with dual- cameras by 2020 versus around 5% currently.
3D imaging is another major catalyst – Apple unveiled facial recognition with its iPhone X via a 3D sensor module known as TrueDepth. This module adds three sensors to the front of the phone: an infrared camera, an infrared light and a projector using more than 30,000 dots. We believe that the infrared camera is supplied by STMicroelectronics (Buy, FV EUR21.9) and is based on Soitec (Buy, FV EUR70)’s SOI technology.
Fig. 12: TrueDepth on the Apple iPhone
Source: Apple website
IC Insights is forecasting average growth in CMOS image sensors of 8.7% to USD15.9 billion, of which 11.5% in volume, between 2016 and 2021.
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Fig. 13: Growth in CMOS image sensors
$15.9 16. 0 8.0
12. 0 6.0 $10.0 $10.5
8.0 4.0
4.0 2.0
0.0 0.0 2015 2016 2017 2018 2019 2020 2021
Sales (USDbn) Units (in billions)
Source : IC Insights
Besi equipment is compatible with 70% of mobile components – CIS (CMOS Imaging) sensors have been amongst the first applications to use advanced packaging solutions like WLP (Wafer Level Packaging) and TSV (Through Silicon Via). The multiplication of their uses is thus a positive factor for the sales of Besi equipment. Furthermore, these components are not the only ones to be driving the higher penetration of assembly applications. Many Analog and RF components in smartphones are already manufactured with Advanced Packaging processes like eWLB and we see their presence continuing to increase considering the need to reduce the size of each component to make room for new ones, and the importance given to performance.
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Fig. 14: The new complexity of smartphones is increasing Besi’s addressable market
Source: Company Data
In conclusion, we see Besi as being well positioned to capture a significant portion of the forthcoming back-end investment. Advanced packaging technologies should grow more rapidly in 2018 with estimated wafer production of 32 million (300mm eq.) (+9%), composed of flip-chip (+6%), fan- in WLP (+6%), fan-out WLP (+53%) and TSV/TCB (+33%), compared with 56 million wafers (+5%) for the remaining assembly solutions, according to VLSI. In our view, Besi’s competitors are not as well positioned, in terms of both technology - particularly FOWLP and TSV/TCB - and the end-markets which should be the fastest-growing in the short term.
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4. A big winner in advanced packaging 4.1. A premium strategy in the assembly industry Adopting a premium strategy – Besi has no plans to grow its market share significantly in the assembly segment (c. 14% in 2016) since the company is focusing on high-value-added equipment which addresses a minority of the foundries. This ultra premium strategy is being deployed in all these business segments without exception, from die bonding (c. 70% of 2016 sales), to packaging (c. 25%), and plating (c. 5%). Besi offers technical support and upgrades throughout the life of its products (services supplied contributed 15% of sales in 2016 with an operating margin of more than 60%).
Fig. 15: Besi is gaining market share in 2017
30.0%
20.0%
15.1% 10.0% 13.2% 14.2% 11.6% 12.3% 11.6%
Assembly market share market Assembly 8.7%
0.0% 2012 2013 2014 2015 2016 H1 2017 9m 2017 Calendar period
AS MPT Besi K&S
Source: Company Data; VLSI; Bryan, Garnier & Co ests.
One proof of the quality of the equipment supplied by Besi is its presence, often very dominant, within numerous major IDMs in their respective markets. For example, at the end of Q3 2017, Besi’s Die Attach products represented 80%, 95%, and 90% of the respective order books of STMicro, Infineon, and NXP (Fig. 10). This finding is all the more conclusive in that, on average, Besi sells its equipment at prices some 25% to 40% higher than those of ASM Pacific Technologies (ASMPT), its closest competitor.
A focalisation strategy enabling Besi to consolidate its competitive advantage – Besi focuses its expertise on equipment which is mostly destined for the back-end of the assembly segment in the manufacturing of high-end semiconductor components. In our view, this strategy diffentiates the company from its competitors and constitutes a clear competitive advantage. The company can concentrate its R&D resources on a same category of tools, thereby maintaining its technological leadership.
For example, ASMPT’s back-end operations represent only 50% of its total sales, with a high proportion of traditional wire bonding technologies. K&S has accelerated its entry into advanced technologies via two acquisitions, Assembléon in 2015 and Liteq in 2017, whose success will depend on the quality of execution and integration. These issues do not apply at Besi and, while the company previously benefited less from the growth in the more traditional technologies than its peers (Fig. 16), the strategy of focalisation should now bear fruit with the aceclerating penetration of Advanced Packaging.
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Fig. 16: Marked outperformance relative to its peers
60% 40%
30% 40%
20% Gross margin 20% Operating profit Operating 10%
0% 0% 2012 2013 2014 2015 2016 H1 2017 9m 2017 2012 2013 2014 2015 2016 H1 2017 9m 2017 Calendar period Calendar period
ASMPT (Back-end segment) Besi K&S ASMPT (Back-end segment) Besi K&S
Source: Company Data; Bryan, Garnier & Co ests.
A growing proportion of IDMs in Besi’s sales – Historically, IDMs and sub-contractors (OSATs) represented a broadly-equivalent proportion of Besi’s total sales. With the current technological changes which are requiring more investment, this mix has shifted towards IDMs who have a higher investment capability. In 2017, the IDMs represented close to 70% of Besi’s orders and the consequences are very concrete for the company’s gross margin which increased from 51.0% over FY 2016 to 57.4% in the first nine months of 2017. It is worth pointing out that there is no difference in the prices applied between the IDMs and OSATs. The correlation between Besi’s gross margin and the share of IDMs is owing to the fact that the latter tend to invest in next-generation equipment and thus there is a higher ASP.
However, it is worth mentioning that leading OSATs do not want to be lagged to far behind and we see an increasing number of M&As in this segment in order to better compete with OSATs. This consolidation trend also means that we should also see OSATs’ investment in Advanced Packaging follow suit in a near future.
Fig. 17: The growing proportion of orders from IDMs illustrates the increased penetration of advanced packaging equipment
76% 69%
60% 60%
51% 51%
2013 2014 2015 2016 H1 2017 9m 2017
Source: Company Data
A potential big winner in Advanced Packaging penetration – Besi’s focalisation strategy gives the company ideal positioning within the current context of increasingly complex innovation in the semi- conductor industry. In our view, the penetration of advanced packaging technologies like FOWLP and TCB/TSV, in which Besi has substantial market shares, should increase with the strong demand for
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NAND and DRAM memory, the proliferation of autonomous and electric vehicles and the intensive use of artificial intelligence which will accelerate the progressive transition to sub-20nm nodes.
4.2. China: a dual challenge for Besi Besi is mainly exposed to European and American innovation – These two continents are pioneers in the new technologies, notably in mobile and automotive, and are thus the main customers for the high-end equipment sold by Besi (note that Besi registeres its equipment sales according to customers’ fabs locations mainly based in Asia). This rational explains the company’s relatively weak geographical footprint with Chinese companies.
The group is however stepping up its geographical diversification – In the past few years, Besi has engaged in diversification efforts and has progressively transferred its production, component supply sources and some of its research and development to the Asian continent to benefit from lower operating costs. The company is killing two birds with one stone since this move is not aimed solely at improving margins but also getting closer to the infrastucture of its customers and considerably reducing the time between the placing of orders and delivery, while impoving inventory management.
Favourable timing – This expansion in Besi’s production capacity happens to coincide with the Chinese government’s five-year plan to double investment in semi-conductor manufacturing infrastructure via a USD150bn investment fund. (see sector report part 2.6.4). The company could also benefit from the concentration move currently being seen amongst the OSATs who are looking to stay in the innnovation race.
Fig. 18: 61% of additional investment in China in 2018e
2017e Semiconductor Equipment - USD49.4bn (+19.9% yoy) 2018e Semiconductor Equipment - USD53.2bn (+7.7% yoy)
Taiwan 20% Taiwan China China 26% 14% Europe 21% 7%
SEA/RoW Europe Japan 6% 8% SEA/RoW 11% 6% Japan North 10% America Korea North 10% Korea America 26% 25% 10%
Source: WSTS (July 2017)
Concretely, for example, in 2014 the company decided to open a part of its Die Bonding production lines in Beshan, China, specifically destined for the local Chinese market. This type of move could also see the Die Bonding systems produced at Besi APac (Malaysia) being specifically adapted to demand from local Chinese customers.
Beneficial effects on the top line and margins – Firstly, Besi’s low profile brand image with Chinese companies has already been the subject of some concrete improvements. Besi Leshan’s production quadrupled in 2016 to 139 units versus 33 in 2015, and this has been reflected in the group’s mix in which 30% of total sales were generated in China during 2016 versus 20% in 2014. Secondly, moving Besi’s plants closer to its customers in the region is improving its operational efficiency. For example,
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the timeline between the placing of orders and delivery of some equipment to Chinese customers has been reduced by at least four weeks in comparison with the eight to ten weeks four years ago.
We nonetheless remain prudent – Despite the opportunities potentially offered by the geographical diversification initiated by Besi, we remain prudent as to the results at least in the short term. In our view, Besi’s competitors could benefit more from the Chinese growth dynamic given their higher capacity locally, closer commercial relationships and more appropriate positioning on the traditional technologies. Even on high-end applications and advanced packaging, Besi’s competitive advantage based on the quality of its equipment seems undermined by the more aggressive pricing policy in China. To win market shares, the company could be forced to make concessions on its gross margin.
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5. Our central scenario 5.1. Another year of growth to come 2017 and 2018 should set new records in terms of investment for the semi-conductor market. The latest research from IC Insights (November 2017) forecasts growth of 35% in capex spending to USD90.8 billion in 2017. This forecast has been revised up by 15ppts relative to the research house’s previous figures released in August and compares with the 10.2% growth forecast by Gartner in July 2017. In our view, the IC Insights figures seem closer to reality since these data are more recent and include the recent investment plans, notably the one from Samsung in memory. IC Insights expects Samsung to double its investment to USD26.0 billion versus USD11.3 billion in 2016 to perpetuate its lead, and should thus represent a little under 30% of the industry’s investment.
Sales of assembly and packaging equipment have benefited from this growth dynamic as seen in the VLSI figures which forecast growth of 23.1% for the segment, and the results from the leaders, ASMPT, K&S, and Besi, who reported total revenue up by 31.1% (based on USD) for the first nine months of 2017.
2018 is likely to be another year of growth for the equipment manufacturers, again driven by capex spending on memory and the assembly and packing segment should not be left out with growth expected to be 4.7% according to the October 2017 data from VLSI. At the date of publication of this report, this growth forecast seems already very cautious. In fact, the first feedbacks we get about the dynamics of this part of the business leads us to rather expect a high single digit growth.
Within this context, we expect Besi to be well positioned to gain market share and post a year of growth approaching 10% in 2018e. In addition to the market growth, the company should benefit from the complexity of applications in memory, computing and automotive, and its technological leaderhip in advanced packaging applications. With sales growth of 55.7% over the first nine months to EUR439.5 million, we estimate Besi’s market share at 13.4%, versus 10.4% in 2016. We expect a further market share gain of 70bps in 2018, to 14.1%, representing sales growth of 9.5%. We are forecasting average sales growth of 9% between 2017e and 2020e, a scenario that seems cautious when compared with 13.8% on average achieved between 2013 and 2016.
Beyond 2018e, visibility remains limited so far. Thus, we adopt a soft growth scenario that corresponds to a cooling-down equipment demand following the two years 2017/2018 of strong growth. For Besi, we model a turnover of EUR670m, i.e. 2.5% above 2018e.
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5.2. A favorable context for margin expansion The growth expected in 2018e should enable the group to maintain its margins above 57%, compared with the 58.7% recorded in the Q3 2017 and 57.3% expected over the full year 2017e based on our estimates. We forecast a gross margin slightly below the 2017 highs given the company’s geographical diversification towards China which should slightly weigh on the product mix and equipment selling prices.
Given the rapid growth in sales growth expected for 2017e, EBIT margin is expected to increase due to lower OPEX acceleration. Thus, we anticipate an EBIT margin of 35.9% for 2017e, this compares with an EBIT margin of 20.0% in 2016 (and 35.8% over the first 9 months of 2017). We then expect OPEX growth of 5% on FY18e and 3.5% FY19e. With top-line growth of 9.5% and 2.5% for FY18e/FY19e respectively, it means that the group is expected to generate 90bps of additional EBIT margin in 2018e related to a lower growth of OPEX compared to turnover, then a reverse phenomenon in 2019e. We model a decrease of 20bps of EBIT margin in 2019e linked to the faster evolution of OPEX than turnover, so the EBIT margin 2019e stands at 34.8% or 2.3ppts below 2018e. We maintain a margin level close to 35% over the remainder of our scenario.
Overall, our scenario derives an EPS CAGR of 36% between 2016 and 2020e.
Fig. 19: P&L – Average EPS growth of 36% over 2016/2020e
[in EURm] / FYE 31/12 2016 1Q17 2Q17 3Q17 4Q17e 2017e 2018e 2019e 2020e CAGR 16/20e Sales 375 110 170 159 157 597 654 670 772 19.7% Seq. growth 7% 18% 54% -6% -1% 59% 10% 2% 15% Gross profit 191 61.4 97.4 93.6 89.5 342 376 372 424 Gross margin 51% 56% 57% 59% 57% 57% 58% e 55% R&D -36 -8 -9 -9 -10 -36 -40 -39 -44 % of sales -10% -8% -5% -6% -6% -6% -6% -6% -6% G&A -80 -22 -25 -21 -23 -92 -94 -100 -108 % of sales -21% -20% -15% -13% -15% -15% -14% -15% -14% EBIT 75 31 63 63 57 214 242 233 272 38.0% Operating margin 20% 28% 37% 40% 36% 36% 37% 35% 35% EBITDA 90 34 67 66 61 228 262 253 296 34.7% Operating margin 24% 31% 39% 42% 39% 38% 40% 38% 38% Financial result -2 -2 -3 -2 -2 -9 -7 -7 -8 % of sales 0% -2% -2% -1% -1% -1% -1% -1% -1% Income Tax -8 -5 -8 -8 -7 -28 -35 -34 -40 Income tax rate -11% -16% -14% -13% -13% -14% -15% -15% -15% Net Profit 65 24 52 53 48 178 201 192 225 36.2% Net margin 17% 22% 31% 33% 30% 30% 31% 29% 29% Dil. EPS 1.70 0.60 1.29 1.30 1.18 4.37 4.99 4.85 5.74 35.6% EPS seq. growth 33% 39% 117% 1% -9% 157% 14% -3% 18%
Source: Bryan, Garnier & Co ests.
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5.3. Strong cash generation opens perspective for transformational transaction With capex spending that we estimate at around 3% of annual sales (in line with the group’s historic average between 2014 and 2016), and a strategy of higher share buy backs then in preveious years, the group should continue to grow its available cash. Besi should have enough headroom to reinforce this investment if required and distribute more cash to shareholders. At the end of 2020e, we anticipate a gross cash position close to EUR450m.
Fig. 20: Robust cash generation
[in EURm] 2016 2017e 2018e 2019e 2020e CAGR 16/20e EBITDA 90 228 262 253 296 Change in WCR 4 -53 -17 -5 -31 Other 0 -6 -42 -41 -47 Cash flow from operating activities 99 169 203 208 217 Capex -11 -11 -20 -20 -23 Free Cash Flow 88 157 183 187 194 Other 0 25 0 0 0 Cash flow used for investing activities -11 14 -20 -20 -23 Proceeds/Repayment of LT & ST debt 123 -2 0 0 0 Dividends -45 -65 -93 -105 -101 Proceeds from issuance of shares -22 -25 -32 -36 -36 Other -76 -29 0 0 0 Cash flow from financing activities -21 -121 -125 -141 -137 Total Cash flow 67 62 58 46 57 Exchange rate effects 0 -2 0 0 0 Net increase in cash 0 60 58 46 57 Cash at beginning of period 158 225 260 318 364 Cash at end of period 225 285 318 364 421 17.0%
Source: Bryan, Garnier & Co ests.
Additionally, note that our scenario leads to FY20e net cash position of more than EUR300m, i.e. a comfortable pocket allowing transformational deals if required. In Europe, several small equipment manufacturers could be reconciled to the image of Amicra or Süss Microtec, a German group of 355 million EUR capitalization specializing in equipment Back-End.
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6. A significant upside potential 6.1. We have a Buy recommendation Our Fair Value of EUR91 Our Fair Value of EUR91 stems from an equi-weighted average between a DCF valuation and stems from an equi- peer comparison. In view of the share's significant upside of 19% and previously described positive weighted average between momentum, we have adopted a Neutral recommendation on the share. a DCF valuation and peer comparison and points to Fig. 21: Overview of our valuation methods an upside potential of 19% Method Weight FV (in EUR) Upside Peer group 50% 89 16% DCF 50% 92 21% Average valuation 100% 91 19%
Source: Bryan, Garnier & Co. 6.2. A DCF at EUR92 per share Our DCF-derived valuation is based on the following assumptions.
Our central scenario includes meaningful estimates out to 2020e. As for the other semi- conductor players under our coverage, we apply a cyclical growth model to the meaningful period (from 2018e to 2021e). For the second year of our meaningful period, we have applied the average growth of 9.0% recorded between 2011 and 2017e since the latter includes an equivalent number of up and down cycles for Besi. To this growth rate we then apply a straight-line reduction in the growth over the normalised period from 2021e to 2027e to reach our terminal growth rate of 2.0% in 2028e. We obtain average growth of 6.2% over the normalised period while our overall scenario derives growth of 7.5% between 2017e and 2028e.
We apply an average operating margin of 33.9% over the 2018e/27e period, then a straight- line reduction in this level of margin to reach our long-term margin of 28%, reflecting a slowdown in technological innovation.
A WCR at approaching 23.0% of sales over the whole period, i.e. slightly below the historic level given the lower growth.
Capex equaling 3.0% of sales in 2018e throughout the period, i.e. in line with its historic level.
A tax rate of 15%. The normative tax rate in the Netherlands is 25% however Besi realises most of its activity in the Asis Pacific (78% of 2016 sales) and the United States (22% of 2016 sales), explaining a lower effective tax rate.
A WACC of 8.7%. We apply a beta of 1.01x which follows the adoption of our new multi- dimensional prospective beta (Switching to a multi-dimensional prospective beta),, a risk-free rate of 1.6% and an equity risk premium of 7.0%.
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Fig. 22: A WACC of 8.7%
WACC European risk-free interest rate 1.6% Equity risk premium 7.0% Beta 1.0 Return expected on equity 8.7% Interest rate on debt 2.0% Market Capitalization (EURm) 2,582 Net debt on 31/12/17e (EURm) -160 Entreprise value (EURm) 2,422 WACC 8.7%
Source: Bryan, Garnier & Co. ests.
Fig. 23: DCF, a FV at EUR92, i.e. potential upside of 21%
in EURm (FYE 31/12) 2018e 2019e 2020e 2021e 2022e 2023e 2024e 2025e 2026e 2027e Revenues 654 670 772 853 933 1,009 1,079 1,141 1,191 1,230 Change (%) 9.5% 2.5% 15.2% 10.6% 9.4% 8.1% 6.9% 5.7% 4.5% 3.2% Adjusted EBIT 242 233 272 301 329 346 358 367 371 370 Adjusted operating margin 37.1% 34.8% 35.3% 35.3% 35.3% 34.3% 33.2% 32.2% 31.1% 30.1% Tax -35 -34 -40 -44 -49 -52 -54 -55 -56 -55 Tax rate 15.0% 15.0% 15.0% 15.0% 15.0% 15.0% 15.0% 15.0% 15.0% 15.0% Net Operating income after tax 207 199 233 257 280 294 305 312 315 314 Capex, net -20 -20 -23 -26 -28 -30 -32 -34 -36 -37 As a % of sales 3.0% 3.0% 3.0% 3.0% 3.0% 3.0% 3.0% 3.0% 3.0% 3.0% Depreciation & amortisation 20 20 23 26 28 30 32 34 36 37 As a % of sales 3.0% 3.0% 3.0% 3.0% 3.0% 3.0% 3.0% 3.0% 3.0% 3.0% WCR 140 145 176 201 220 238 255 269 281 290 As a % of sales 21.4% 21.6% 22.8% 23.6% 23.6% 23.6% 23.6% 23.6% 23.6% 23.6% Change in working capital -17 -5 -31 -25 -19 -18 -16 -14 -12 -9 Free cash flows 190 194 201 232 261 276 288 297 303 305 Discounted free cash flows 176 166 158 168 174 169 162 154 144 134
Total discounted FCF - 2018e-2027e 1,604 Discounted Terminal value - 2028e+ 1,911
Enterprise value 3,515 WACC
+ Fair value of financial assets 49 [in EUR] 7.7% 8.2% 8.7% 9.2% 9.7%
- Net debt on 31/12/2017 -160 26% 103 95 88 83 78
Equity value 3,724 27% 106 97 90 84 79
Nbr of diluted shares (m) 40.292 28% 108 100 92 86 81
29% 111 102 94 88 82 Valuation per share (EUR) 92 Op. margin
Upside vs. current share price 21% 30% 113 104 96 90 84
Source: Bryan, Garnier & Co ests.
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6.3. Peer comparison of EUR89 For our peer comparison of Besi, we have created a sample including only semiconductor equipment makers. As such, they are exposed to similar customers and market dynamics. We have taken the average of two multiples: FY18e EV/EBIT and FY18e P/E. The margins of Besi's comparables are particularly disparate (KLA Tencor 38%, Nikon 7%), which is why we do not use EV/Sales multiples for valuation purpose.
Fig. 24: Breakdown of our sample of peers
Company name Market Cap (in USDm) 2018e EBIT margin 2018e EV/EBIT 2018e P/E ASML HOLDING 64,439 27% 21.9x 26.8x APPLIED MATS. 46,485 29% 11.4x 13.3x LAM RESEARCH 25,134 29% 9.7x 12.9x TOKYO ELECTRON 26,601 17% n.m. 17.4x KLA TENCOR 13,859 38% 10.9x 15.0x TERADYNE 7,203 25% 12.3x 18.9x NIKON 6,639 7% 14.9x 26.3x ASM PACIFIC TECH. 4,757 19% 12.3x 16.6x ASM INTERNATIONAL 3,612 17% 19.7x 16.0x KULICKE & SOFFA INDS. 1,438 15% 13.0x 14.9x Peers Average 22% 14.0x 17.8x BE Semiconductor 3,408 37% 10.8x 15.4x Premium (discount) -23% -14%
Sources: Thomson Reuters I.B.E.S.; Bryan, Garnier & Co. ests.
Comparison of peer multiples points to a valuation for Besi of EUR89, or upside of 16%.
Fig. 25: Peer comparison: FV of EUR89 or upside potential of 16%
Multiple Peer average Implied Besi valuation (in EUR) 2018e EV/EBIT 14.0x 89 2018e P/E 17.8x 89 Average 89 Upside vs. current share price 16%
Source: Bryan, Garnier & Co. ests.
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Bryan Garnier stock rating system For the purposes of this Report, the Bryan Garnier stock rating system is defined as follows: Stock rating Positive opinion for a stock where we expect a favourable performance in absolute terms over a period of 6 months from the publication of a BUY recommendation. This opinion is based not only on the FV (the potential upside based on valuation), but also takes into account a number of elements that could include a SWOT analysis, momentum, technical aspects or the sector backdrop. Every subsequent published update on the stock will feature an introduction outlining the key reasons behind the opinion. Opinion recommending not to trade in a stock short-term, neither as a BUYER or a SELLER, due to a specific set of factors. This view is intended to NEUTRAL be temporary. It may reflect different situations, but in particular those where a fair value shows no significant potential or where an upcoming binary event constitutes a high-risk that is difficult to quantify. Every subsequent published update on the stock will feature an introduction outlining the key reasons behind the opinion. Negative opinion for a stock where we expect an unfavourable performance in absolute terms over a period of 6 months from the publication of a SELL recommendation. This opinion is based not only on the FV (the potential downside based on valuation), but also takes into account a number of elements that could include a SWOT analysis, momentum, technical aspects or the sector backdrop. Every subsequent published update on the stock will feature an introduction outlining the key reasons behind the opinion. Distribution of stock ratings
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