CHARACTERIZATION of SUB-90 Nm GATE LENGTH RF MOSFETS USING LARGE SIGNAL NETWORK ANALYZER

CHARACTERIZATION OF SUB-90 nm GATE LENGTH RF MOSFETS USING LARGE SIGNAL NETWORK ANALYZER

A Thesis

Presented in Partial Fulﬁllment of the Requirements for the Degree Master of Science in the

Graduate School of The Ohio State University

Venkatesh Balasubramanian, B.E. Electrical and Electronics

* * * * *

The Ohio State University

2009

Master’s Examination Committee: Approved by

Prof. Patrick Roblin, Adviser Prof. Mohammed Ismail Adviser Prof. Wu Lu Graduate Program in Electrical and Computer Engineering c Copyright by

Venkatesh Balasubramanian

2009 ABSTRACT

This thesis presents a methodology to characterize sub 90 nm gate length RF

MOSFETs used for PA applications. First, MATLAB and ADS are used to ﬁt the

gate and the drain pads’ parameters with the small signal S-parameters measured over

a range of frequencies. Then, test beds for Class A and Class B Power Ampliﬁers in

Common Source (CS) and Common Gate (CG) conﬁguration are designed in ADS to compare the simulation results with the measured data from the Large Signal

Network Analyzer (LSNA). CG conﬁguration based Power Ampliﬁers are further studied to test the device symmetry by injecting signals from both the source as

well as the drain side. Realizing that over 50 % of the output admittance can be

accounted by the substrate network, a scheme is developed to study the substrate of the device using LSNA as all the previous models proposed in the literature are

based on small signal measurements. Signals are injected at low frequency (600

MHz) and high frequency (4 Ghz) to account for all possible components and a1,

a2, b1 and b2 parameters are measured using LSNA. The eﬀect of harmonics on the

device performance was studied to ﬁnd the optimum number of harmonics beyond

which there was no appreciable variation in the performance by introducing ﬁgure

of merits. Finally, pulsed-IV/RF measurements were simulated in ADS for class B

operation to validate the experimental test beds involving LSNA.

ii This is dedicated to my family and friends

iii ACKNOWLEDGMENTS

It is with great pleasure and honor that I am writing this section of the thesis.

I will try my best to include all the people who have aided me towards this thesis, both academically as well as personally.

I would like to sincerely thank Prof. Patrick Roblin for being my adviser during my M.S. studies. The various brainstorming sessions with him have been immensely beneﬁcial towards the successful completion of this thesis. Moreover, He has been a great role model for me as a researcher and teacher.

I would also like to thank Dr. Mohammed Ismail and Dr. Wu Lu for being a part of my defense committee. They helped me by clearly my doubts while compiling this thesis. They have, indeed, been of great support to me.

It is with great pleasure I thank the various visiting scholars like Dr. Dominique

Chaillot, Prof. Hyo Dal Park, Prof. Young Gi Kim and Dr. Fabien De Groote. These acquaintanceships will forever be treasured.

I would like to mention my gratitude towards all the staﬀ members, both at technical as well as management level. I thank the members of SITE for prompt attention towards all the computer related problems that I had encountered.

I would like to thank Mrs. Gloria Torrini-Roblin for organizing wonderful group parties which brought the group even more closer as a family.

iv I am very fortunate to have excellent lab members who have been my pillars of support during this study. A special mention here is necessary to acknowledge Dr.

Seok Joo Doo who has been a great source of inspiration for making great strides in

research. This research work would not have been possible without his experimental

work and constant mentoring. I will forever cherish our association. My sincere thanks

to Inwon Suh for being like a family member than just a friend. Our brainstorming

sessions have immensely beneﬁted both of us towards our research. This section will

be incomplete if I don’t mention Dr. Jong Soo Lee who accompanied me at late

nights when I was running simulations. In fact, I would like to thank all the Korean

students in the Electrical and Computer Department for sharing great times with me

and treating me as one among them. I thank Hong Tang for the excellent friendship

we shared. I would also like to mention Xian Cui, Yang Xi, Young Seo Ko, Shashank

Mutha, Ji Woo Kim and Chieh Kai Yang for supporting me towards this research.

I would like to thank Rich Taylor and Krishnanshu Dandu from Texas Instru-

ments for the ﬁnancial support towards this research. The quartering meetings were

of immense help towards this research as well as towards building my professional

character. Particularly, the meeting in Dallas was an excellent opportunity to get an

insight of professional life beyond academics.

I would like to express my gratitude to my close friends like Anisha Ramesh, Balaji

Kumar, Indira Seshadri, Sriram Sivaramakrishnan, Sughosh Rao, Sriram Sridharan,

Rahul Subramanian and Joseph Chandraraj. Also, my thanks to the members of

ISKCON who always supported me spiritually. They have always been like a family

to me.

v Finally, my sincerely thanks to my family members for all their love and support.

The endless Skype chatting sessions always bridged the mental distance between us, if not the physical one. Their constant encouragement was quintessential towards making this a memorable time of my life.

vi VITA

May 5, 1984 ...... Born - Chennai, India

June 30, 2006 ...... B.E. First Class with Distinction Electrical and Electronics Engg., Anna University, Chennai, India April 2007 - March 2008 ...... Graduate Research Associate, Non Linear RF laboratory, The Ohio State University.

PUBLICATIONS

Research Publications

S. J. Doo, P. Roblin, V. Balasubramanian, R. Taylor, K. Dandu, G. H. Jessen, and R. Rojas, “Adaptive second harmonic active load for pulsed-IV/RF class-B operation”. ARFTG 70th Conf., Tempe, AZ, Nov. 2007.

FIELDS OF STUDY

Major Field: Electrical and Computer Engineering

Studies in RF circuit design and device modeling: Prof. Patrick Roblin

vii TABLE OF CONTENTS

Page

Abstract ...... ii

Dedication ...... iii

Acknowledgments ...... iv

Vita ...... vii

List of Tables ...... xi

List of Figures ...... xii

Chapters:

1. Introduction ...... 1

1.1 Motivation ...... 1 1.2 Thesis Outline ...... 3

2. Trends in Device Modeling ...... 5

2.1 Introduction ...... 5 2.2 BSIM4 MOSFET Model ...... 6 2.3 RF Device Modeling ...... 7 2.3.1 Introduction ...... 7 2.3.2 Equivalent Circuit Representation of RF MOSFET . . . . . 8 2.4 RF modeling in BSIM4 ...... 9

viii 3. Pad Modeling ...... 12

3.1 Introduction ...... 12 3.2 Extrinsic Networks ...... 12 3.2.1 Experimental Method ...... 12 3.2.2 Network Topologies ...... 14 3.3 Analytical Analysis of Pad networks ...... 14 3.3.1 OPEN configuration ...... 15 3.3.2 SHORT configuration ...... 17 3.3.3 THRU configuration ...... 17 3.4 ADS Implementation ...... 19 3.4.1 Description ...... 19 3.4.2 Results ...... 20 3.5 Conclusion ...... 20

4. Characterization of Class A and Class B Power Ampliﬁers ...... 23

4.1 Introduction ...... 23 4.2 Large Signal Network Analyzer ...... 24 4.3 Class A Configuration ...... 26 4.3.1 DC-IV Characteristics ...... 26 4.3.2 Common Source Configuration ...... 26 4.3.3 Common Gate Configuration ...... 32 4.4 Class B Configuration ...... 36 4.4.1 Experimental Setup ...... 36 4.4.2 ADS Implementation ...... 37 4.5 Conclusion ...... 39

5. Detail Analysis of the Harmonics on the Device Performance ...... 40

5.1 Introduction ...... 40 5.2 Mathematical Analysis of Harmonics ...... 41 5.3 Figure of Merits ...... 42 5.4 Analysis of Class A Power Ampliﬁer in Saturation Mode ...... 43 5.5 Analysis of Class B ampliﬁer ...... 48 5.6 Conclusion ...... 49

6. Veriﬁcation of Device Symmetry ...... 50

6.1 Introduction ...... 50 6.2 Experimental Setup ...... 51 6.3 ADS Implementation ...... 52

ix 6.4 Comparison of measured and simulated results ...... 52 6.5 Conclusion ...... 60

7. Substrate Extraction ...... 61

7.1 Introduction ...... 61 7.2 Experimental Setup ...... 61 7.3 ADS Implementation ...... 63 7.4 Comparison of measured and simulated results ...... 63 7.5 Conclusion ...... 68

8. Envelope Simulations for Pulsed IV/RF Excitations ...... 69

8.1 Introduction ...... 69 8.2 Envelope Simulations in ADS ...... 69 8.3 ADS Implementation ...... 70 8.4 Results ...... 70 8.5 Conclusion ...... 71

9. Conclusion and Future Work ...... 74

Bibliography ...... 76

x LIST OF TABLES

Table Page

3.1 Comparison of the extracted parameters using ADS and MATLAB . 22

4.1 Source and Drain Extrinsic Parameters ...... 34

5.1 Figure of merits for class A operation in saturation mode ...... 45

5.2 Figure of merits for reconstructed waveforms from 4 harmonics for Class A operation in saturation mode ...... 46

5.3 Figure of merits for Ids plot for DUT and strong model for Class A operation in saturation mode ...... 47

5.4 Figure of merits for class B operation ...... 49

6.1 Input signal schemes for testing device symmetry ...... 52

7.1 Input signal schemes for performing substrate extraction ...... 62

xi LIST OF FIGURES

Figure Page

2.1 Diﬀerent MOSFET models in BSIM4 based on source-drain resistance: (a) Basic intrinsic model; (b) Symmetric source-drain series resistance (rdsMod = 0); (c) Asymmetric external source-drain resistance model (rdsMod = 1) (Adapted from [11]) ...... 7

2.2 Equivalent circuit representation of RF MOSFET (Adapted from [11]) 9

2.3 Diﬀerent RF MOSFET models in BSIM4 based on gate resistance: (a) Basic intrinsic model (rgateMod = 0); (b) Model with constant gate electrode resistance (rgateMod = 1); (c) Model with both constant and bias-dependent gate resistance (rgateMod = 2); (d) Model with two additional nodes for the gate resistance components (Adapted from [11]) ...... 10

2.4 Five-resistance substrate network in BSIM4 (Adapted from [11]) . . 11

3.1 Complete RF MOSFET model with the gate and drain manifolds, the extrinsic component shell and the intrinsic transistor...... 13

3.2 Equivalent networks for Extrinsic components: (a) the capacitors represent the bond-pad capacitances, (b) the capacitors represent capacitance causing geometries in the MOSFET like gate-feed to source-feed crossovers...... 15

3.3 Extrinsic networks: (a) gate extrinsic network, (b) drain extrinsic network...... 16

3.4 OPEN conﬁguration of the gate-drain extrinsic network...... 16

3.5 SHORT conﬁguration of the gate-drain extrinsic network...... 17

xii 3.6 THRU conﬁguration of the gate-drain extrinsic network...... 18

3.7 ADS Circuit Implementation ...... 19

3.8 Smith Charts in ADS showing the parametric extraction ...... 21

4.1 Output current response for: (a) Class A, (b) Class B ...... 24

4.2 Diﬀerent topologies of Ampliﬁers ...... 25

4.3 DC-IV characteristics of the DUT ...... 27

4.4 ADS schematic for Class A saturation mode ...... 27

4.5 Current and Voltage plots for Class A PA operating in the saturation region ...... 28

4.6 Ids vs Vgs and Ids vs Vds loadlines for the Class A Power Ampliﬁer operating in the saturation region ...... 29

4.7 Current and voltage plots for Class A Power Ampliﬁer operating in the Linear region ...... 30

4.8 Ids vs Vgs and Ids vs Vds loadlines for the Class A Power Ampliﬁer operating in the linear region ...... 31

4.9 Test Bench for analyzing Class A Power Ampliﬁers in Common Gate Conﬁguration ...... 32

4.10 DC-IV characteristics of the DUT in the Common Gate conﬁguration 33

4.11 ADS schematic for Common Gate Class A Power ampliﬁer ...... 34

4.12 Current and Voltage waveforms for Class A ampliﬁer operating in Com- mon Gate Conﬁguration ...... 35

4.13 Input and Output loadlines for Class A ampliﬁer operating in Common Gate Conﬁguration ...... 36

xiii 4.14 Schematic for the experimental set-up for the characterization of the Class B Power Ampliﬁer ...... 37

4.15 Current and Voltage waveforms for Class B ampliﬁer operating in Com- mon Source Conﬁguration ...... 38

4.16 Input and Output loadlines for Class B ampliﬁer operating in Common Source Conﬁguration ...... 39

5.1 Graphical analysis to determine the optimum number of harmonics for Class A operation ...... 44

5.2 Comparison of the reconstructed Ids for Class A saturation mode . . 46

5.3 Comparison of the reconstructed Ids for DUT and strong model in saturation mode ...... 47

5.4 Graphical analysis to determine the optimum number of harmonics for Class B operation ...... 48

6.1 Experimental Setup to determine the device symmetry ...... 51

6.2 ADS setup for testing device symmetry ...... 53

6.3 Current and voltage plots for case A at 4 GHz ...... 54

6.4 Current and voltage plots for case B at 4 GHz ...... 55

6.5 Current and voltage plots for case C at 4 GHz ...... 56

6.6 Current and voltage plots for case A at 600 MHz ...... 57

6.7 Current and voltage plots for case B at 600 MHz ...... 58

6.8 Current and voltage plots for case C at 600 MHz ...... 59

7.1 Experimental Setup to perform substrate extraction ...... 62

7.2 ADS setup for performing substrate extraction ...... 63

xiv 7.3 Injected (a) and reﬂected (b) waveforms for case 3 with vin = −0.3 V at 600 MHz ...... 64

7.4 Current and voltage waveforms for case 3 with vin = −0.3 V at 600 MHz 65

7.5 Injected (a) and reﬂected (b) waveforms for case 3 with vin = −1 V at 600 MHz ...... 66

7.6 Current and voltage waveforms for case 3 with vin = −1 V at 600 MHz 67

8.1 Pulsed RF- IV simulation setup in ADS ...... 71

8.2 Comparison of the DC-IV/CW-RF load-lines between the measurement and ADS circuit envelope simulation ...... 72

8.3 Comparison of the pulsed-IV/RF load-lines between the measurement and ADS circuit envelope simulation ...... 73

xv CHAPTER 1

INTRODUCTION

1.1 Motivation

Over the past decade, tremendous growth has been seen in the research of Analog and RF circuits. This has been boosted by the advancements made in the device processing technology as well as the demand from the industry to integrate them with the digital circuitry. As the industry keeps on increasing the packing density of the chips to fulﬁll the Moore’s law [1], it is becoming even harder for the RF and

Analog engineers to rub their shoulders with those of their digital counterparts. This is greatly attributed to the various short channel eﬀects that arise due to scaling [2].

The biggest problem with the short channel devices is that the approximations made in the case of long channel devices are no longer valid. This leads to various effects which are generally ignored in the long channel length modeling. One of the contributing factors is the difficulty in the scaling of threshold voltage, VT H which is limited by the channel length, temperature, process and the drain voltage induced capacitance [3]. Furthermore, large gate-source voltages Vgs induce higher electric field between the gate and the channel, limiting the channel area for the charge carriers, leading to increasing charge scattering, thus lowering mobility [4]. Consequently, this

1 degradation aﬀects the device transconductance. Another concerning issue is the

voltage saturation which is prominent at lower channel length due to higher vertical

electric ﬁeld. This leads to reduction in the saturation current and impairs the device

performance even further. [3]. High lateral electric ﬁelds owing due to increasing

drain-source voltage also lead to increase in the kinetic energy of the carriers, referred

to as hot carriers [5]. These carriers account for impact ionization which induces

drain-substrate current and at very high ﬁelds, even gate current. Another issue is

the Vds dependence of the output impedance, ro. With the inclusion of the channel

length modulation eﬀect, ro is given by:

1 + λVds ro = (1.1) λID

Eqn. 1.1 suggests a linear relationship between ro and Vds. But, as the latter

increases, impact ionization eﬀect becomes more prominent which increases the drain

current, thus reducing ro [2]. This variation leads to nonlinear eﬀects in many circuit

applications.

Hence, Analog and RF device modeling at shorter gate lengths oﬀers many ob- stacles to bridge the gap between the simulated and measured device characteristics.

Engineers have constantly been working on improving the fidelity of the device models. The initial efforts, appropriately called as Level 1, 2 and 3, incorporated the higher order effects and provided acceptable performance for gate lengths in the order of µm. But these models were generated based on the various physical equations that determine the MOSFET operation. Unfortunately, these efforts fell short as the device scaling became more prominent. This led to the development of BSIM (Berke- ley Short-channel IGFET model) models, designed by the BSIM research group at

2 University of California, Berkeley. Empirical parameters were introduced to increase the accuracy of the models. Currently BSIM3, BSIM4 and BSIMSOI are the various models oﬀered. Chapter 2 will touch upon the BSIM models in detail.

Most of the research in the MOSFET device modeling is directed towards digital

and low-frequency analog circuit applications focusing on the DC ID, conductances

and intrinsic capacitances up to the baseband frequency (20 KHz). As a result, these

models fall short when they are used for RF (GHz) applications as the extrinsic

parasitics become equally important as the intrinsic ones. Therefore, it becomes

essential to account for high frequency behaviour of both intrinsic as well as the

extrinsic parameters to increase the ﬁdelity of the RF circuit simulations.

Furthermore, at high frequencies, the substrate also inﬂuences the device perfor-

mance. It has been found out that 50 % of the output admittance can be accounted

by the substrate. This becomes a matter of great concern in the design of high fre-

quency power ampliﬁers at shorter gate length technologies. Traditionally, a lumped

RC circuit was assumed as the network and the parameters were extracted by ﬁtting

using the small signal S-parameters measured via VNA [6].

1.2 Thesis Outline

Chapter 2 will introduce BSIM models in detail followed by a discussion on the

trends on RF device modeling. Here, the inclusion of gate resistance and the substrate

network will be enunciated.

In chapter 3, a methodology is introduced on the extraction of the gate and

the drain pads by ﬁtting the parameters with the small signal S-parameters data

obtained from ICCAP. First, the various impedance equations for OPEN, SHORT

3 and THRU conﬁgurations are introduced followed by extraction using MATLAB.

Next, schematics for these conﬁgurations are generated on ADS and the optimization is performed. A comparison is made between the extracted parameter using MATLAB and ADS.

In chapter 4, testbeds for the characterization of Class A and Class B PAs in both common-source (CS) and common-gate (CG) conﬁgurations are presented. The simulated data from ADS is compared with the measured data using a Large Signal

Network Analyzer.

The eﬀect of harmonics on the device performance is studied in chapter 5. Here,

ﬁgure of merits are introduced to determine the optimum number of harmonics beyond which there is no considerable variation in the device characteristics.

CG conﬁguration is further investigated in chapter 6 to study the device symmetry.

Here, the input signals are injected into the source as well as the drain side to analyze the source and the drain current. This is repeated for diﬀerent values of Vgs to study the impact of gate-source voltage on the device symmetry.

Chapter 7 is dedicated to the study of substrate extraction of the RF MOSFET using LSNA. First, the characterization scheme is introduced. Next, the currents and voltages produced by the existing substrate network are compared with the measured data from LSNA.

Chapter 8 presents a novel scheme of using envelope simulations rather than the usual harmonic balance simulations to perform Pulse RF-IV measurements for RF characterization in ADS.

Finally, chapter 9 concludes this work by drawing inferences and providing sug- gestions for future work.

4 CHAPTER 2

TRENDS IN DEVICE MODELING

2.1 Introduction

Ever since MOSFET was invented, many attempts have been made to study the physical effects and model them accurately. While the earlier attempts accounted for the physical effects only, the researchers from the BSIM research lab took an entirely different direction by introducing empirical parameters. This allowed the representation of the dimensions dependence of various parameters using simple equations. A

general equation of a given parameter [2] is as follows:

αP βP γP P = Po + + + (2.1) Leff Weff Leff × Weff

where Po is the value of the parameter for longer dimensions while αP , βP and γP are

the ﬁtting parameters.

While this trend was followed by the BSIM1 and BSIM2 models, they fell short

as the devices were shrunk to greater extent. Consequently, BSIM3 and BSIM4

included both these empirical equations and equations incorporating physical eﬀects.

Currently, BSIM3, BSIM4 and BSIM SOI are available.

5 2.2 BSIM4 MOSFET Model

BSIM3, released in 1996, is a physics based, deep sub-micron MOSFET model for

design of digital and analog circuits. Its features include a single I − V expression to describe I and COUT characteristics from sub-threshold to strong inversion as well as

the linear to the saturation operation regions and a new capacitance model for short

and narrow geometry devices [7]. Unfortunately, as the engineers started exploring

RF applications, BSIM3 was unable to address the physical eﬀects. As a result,

BSIM4 model [8] was developed which extends BSIM3 into the frontiers of sub-100

nm regime for RF applications as well as the usage of advanced process technologies

such as non-uniform substrate doping.

BSIM4 accounts for the ﬁnite charge-layer thickness [9] which occurs when the gate

oxide is very thin (< 3nm) in both the DC and the capacitance model by accepting the

electrical gate oxide thickness, physical gate oxide thickness and their diﬀerence [10].

Two additional ﬁtting parameters XL and XW are introduced to incorporate the

channel length and width oﬀsets due to the processing factors such as etching and

mask. BSIM4 also introduces an asymmetric source-drain resistance model which

allows the bias dependent resistances at the source and the drain to be diﬀerent

and that they are physically connected between the external and the internal source-

drain nodes. A parameter is also included in the BSIM4 model named rdsMod to

select diﬀerent source-drain resistance models. Fig. 2.1 represents the basic MOSFET

model with no series source-drain resistance. When rdsMod = 0, symmetric source-

drain resistance model from the BSIM3v3 is used, as shown in Fig. 2.1(b), and when

rdsMod = 1, the external asymmetric source-drain resistance model is selected, as

shown in Fig. 2.1(c).

6 D D D R + R (v) 0.5 Rds d0 d Di Di

G G G

Si Si R + R (v) 0.5 Rds s0 s S S S (a) (b) (c)

Figure 2.1: Diﬀerent MOSFET models in BSIM4 based on source-drain resistance: (a) Basic intrinsic model; (b) Symmetric source-drain series resistance (rdsMod = 0); (c) Asymmetric external source-drain resistance model (rdsMod = 1) (Adapted from [11])

2.3 RF Device Modeling

2.3.1 Introduction

Due to advancements in the sub-100nm regime of CMOS process technology it has been easier to achieve higher transit frequencies fT and lower noise ﬁgures, which is conducive for RF device modeling. It is very important to develop accurate device models to accurately predict device performance. As devices operate in the giga-

hertz range, it is essential to determine the extrinsic components. Gate resistance

RG should be considered in RF device modeling as its contributes to the thermal

noise which signiﬁcantly aﬀects the input admittance at gigahertz range [11] and in-

creases the noise ﬁgure of the transistor. Furthermore, gate resistance also decreases

the fmax of the device. Substrate coupling eﬀects through the drain and source

7 junctions along with the substrate network contribute to the output admittance. In

fact, the substrate network contributes up to 50% of the total output admittance [6].

Consequently, a MOSFET model without the substrate network cannot predict the

frequency dependence of the output admittance of the device.

2.3.2 Equivalent Circuit Representation of RF MOSFET

A four terminal equivalent representation of RF MOSFET [11] with the extrinsic components is shown in Fig. 2.2. The resistive components include the gate resistance RG, the series source resistance RS, the series drain resistance RD and the substrate resistances RSB, RDB and RDSB. The capacitive components include the gate-source overlap capacitance CGS, gate-drain overlap capacitance CGD, gate-bulk overlap capacitance CGB and the source-drain capacitance CDS. The diode compo-

nents include the source-bulk junction diode DSB and the drain-bulk junction diode

DDB. A detailed analysis of the internal and external components has been done

in [11].

A number of models have been proposed for the substrate network. The simpler

networks include one-resistance [12] and two-resistance [13] models. As they include

lesser parameters, they are easier to analysis and perform parametric extraction.

However, as the operating frequency increases well into the GHz range, they tend to

be less accurate. The four-resistor and ﬁve-resistor [14] networks are more accurate

and are valid for higher frequencies, but their analysis and parametric extraction

of the components is very complex. The three-resistor network model [15] is fairly

accurate up to 10 GHz frequency and oﬀers a simpler analysis and parametric analysis.

Section 2.4 throws light on the RF device modeling parameters in BSIM4.

8 G

RG B S D B

CGS CGD

C CSB R DB S RDS RD DSB DDB CGB

RDSB

RSB RDB CDS

Figure 2.2: Equivalent circuit representation of RF MOSFET (Adapted from [11])

2.4 RF modeling in BSIM4

One of the most important features of BSIM4 is the inclusion of the RF model [11].

This model includes the gate electrode resistance (bias-independent) and intrinsic- input resistance (bias-dependent). The latter is considered as a ﬁrst-order Non Quasi-

Static (NQS) model. Diﬀerent gate resistance models can be selected by assigning desired values to a model parameter rgateMod. When rgateMod = 0, no gate resistance is included in the simulation. As a result, the basic MOSFET model is used, as shown in Fig. 2.3(a). When rgateMod = 1, a resistor with constant gate resistance Rgeltd is introduced [11] as indicated by the Fig. 2.3(b). Fig. 2.3(c) shows the condition when rgateMod = 2 with the inclusion of an intrinsic-input model with variable resistance Rii. The total gate resistance in this case is the sum of the gate electrode resistance and the bias dependent intrinsic-input resistance. When

9 rgateMod = 3, additional node is added for the intrinsic-input gate resistance model as shown in Fig. 2.3(d). This allows the AC current through the overlap capacitance

to be parallel to the current component through the Rii unlike the case in Fig. 2.3 where it passed through Rii.

G G

Rgeltd

S D S D

(a) (b)

Rgeltd

Rgeltd + Rii Cgso Rii Cgdo

S D S D

Figure 2.3: Diﬀerent RF MOSFET models in BSIM4 based on gate resistance: (a) Basic intrinsic model (rgateMod = 0); (b) Model with constant gate electrode resistance (rgateMod = 1); (c) Model with both constant and bias-dependent gate resistance (rgateMod = 2); (d) Model with two additional nodes for the gate resistance components (Adapted from [11])

BSIM4 also oﬀers a built-in substrate resistance network which accounts for the signal coupling through the substrate at high frequencies. This is selected by the

10 parameter rbodyMod. When rbodyMod = 0, then the classic MOSFET model model shown in Fig. 2.3 is used. When rbodyMod = 1, then a ﬁve-resistance substrate model shown in Fig. 2.4 is introduced.

IDS

Iii+ IGIDL RBPS RBPD sbNode dbNode bNodePrime

RBSB RBPS RBDB

bNode

Figure 2.4: Five-resistance substrate network in BSIM4 (Adapted from [11])

11 CHAPTER 3

PAD MODELING

3.1 Introduction

A complete schematic of a RF MOSFET includes intrinsic, extrinsic and the bond- wires [16]. Fig. 3.1 shows the complete electric model of a RF transistor including the bonding pads and manifolds, resistive and reactive extrinsic components, the intrinsic transistor model and a thermal sub-network used for developing electro- thermal model.

This chapter will focus on the parametric extraction of the extrinsic networks for gate and drain.

3.2 Extrinsic Networks

3.2.1 Experimental Method

The extrinsic network extraction methods are based on cold-FET method [17].

The device is biased with the Vds set to zero volts. In this condition, there is no electric ﬁeld in the channel of the FET. As a result, the electrons are in the ohmic regime and are called as ‘cold’ electrons. Moreover, in this condition, the small-signal equivalent circuit model is eﬀectively shorted out, placing the device in a passive

12 Gate Drain manifold/Bond−pad manifold/Bond−pad Intrinsic model

Gate extrinsic network Drain extrinsic network

Source extrinsic network

Extrinsic shell

Thermal sub−network

Figure 3.1: Complete RF MOSFET model with the gate and drain manifolds, the extrinsic component shell and the intrinsic transistor.

13 condition. The gate of the device is then biased in order to put the transistor into

either cut-oﬀ or conducting modes, in which the intrinsic small-signal equivalent net-

work is furthered simpliﬁed to identify and measure the extrinsic shell components.

The extrinsic parameters are extracted using direct methods from single-frequency

S-parameter measurements, or by optimization over a range of frequencies for open,

short and thru conﬁgurations. Powerful device modeling softwares like ICCAP can

be further used for data acquisition.

3.2.2 Network Topologies

There are two common network arrangements [16] which are adopted for the extrinsic networks. While the device geometry determines the choice of the network, the network shown in Fig. 3.2(a) is usually chosen due to reduced number of math-

ematical matrix inversions in the de-embedding of the extrinsic shell. The extrinsic

capacitance component represents the bond-pad capacitance of the small test FETs.

On the contrary, the capacitor in the network shown in the Fig. 3.2(b) represents

other signiﬁcant capacitive components including gate-feed to source-feed crossovers.

In this work, a modiﬁed version of the former network is used to represent the extrinsic

network.

3.3 Analytical Analysis of Pad networks

A modiﬁed version of Fig. 3.2 is employed in this work. Fig. 3.3(a) represents the

gate extrinsic network and Fig. 3.3(b) represents the drain extrinsic network. Here,

the source extrinsic network is not taken into consideration. In order to perform the

parametric extraction, the networks must be analyzed for OPEN, SHORT and THRU

conﬁgurations. The S-parameters of these networks in the three conﬁgurations are

14 L Lx Rx x Rx

Cpx Cpx

(a) (b)

Figure 3.2: Equivalent networks for Extrinsic components: (a) the capacitors represent the bond-pad capacitances, (b) the capacitors represent capacitance causing geometries in the MOSFET like gate-feed to source-feed crossovers.

measured for a range of frequencies from 500 MHz to 40 GHz and saved in touchstone

format. In order to implement these networks in MATLAB, it is essential to calcu-

late the Z-parameters for these conﬁgurations before proceeding towards parametric

extraction.

3.3.1 OPEN conﬁguration

In the OPEN conﬁguration, the two networks are terminated with inﬁnite resis-

tance. Fig. 3.4 shows the resulting network. The Z-parameters for this network are

calculated below

1 Z11 = + R10 (3.1) jωC10

1 Z22 = + R20 (3.2) jωC20

Z12 = Z21 = 0 (3.3)

15 R12 R22

R11 P1 P2 P1 P2 L L20 R21 C C10 10 20

R R10 20

(a) (b)

Figure 3.3: Extrinsic networks: (a) gate extrinsic network, (b) drain extrinsic network.

P1 P2

C10 C20

R10 R20

Figure 3.4: OPEN conﬁguration of the gate-drain extrinsic network.

16 R 12 R22

P1 P2 R L L R C10 11 10 20 21 C20

R10 R20

Figure 3.5: SHORT conﬁguration of the gate-drain extrinsic network.

3.3.2 SHORT conﬁguration

In the SHORT conﬁguration, the two ports of each network are connected with one another resulting in zero impedance between them. Fig. 3.5 shows the resulting network. The Z-parameters for this network are calculated below:

1 1 −1 1 − 1 1 −1 − Z11 = + R10 + R11 + + (3.4) " jωC10 R12 jωL10 #

1 1 −1 1 − 1 1 −1 − Z22 = + R20 + R21 + + (3.5) " jωC20 R22 jωL20 #

Z12 = Z21 = 0 (3.6)

3.3.3 THRU conﬁguration

In the THRU conﬁguration, the networks are directly connected to one another.

Fig. 3.6 shows the resulting network. The Z-parameters for this network are calculated

below:

17 R 12 R22

R11 P1 P2 L L R C10 10 20 21 C20

R10 R20

Figure 3.6: THRU conﬁguration of the gate-drain extrinsic network.

1 1 − Z11 = + R10 jωC " 10 1 −1 1 1 −1 1 1 −1 1 − + R11 + + + R21 + + + + R20 R12 jωL10 R22 jωL20 jωC20 # (3.7)

1 1 − Z22 = + R20 jωC " 20 1 −1 1 1 −1 1 1 −1 1 − + R11 + + + R21 + + + + R10 R12 jωL10 R22 jωL20 jωC10 # (3.8)

Z12 = Z21 =

1 R 1 R jωC10 + 10 jωC20 + 20 −1 −1 1 1 1 1 1 1 jωC20 + R20 + jωC20 + R20 + R11 + R12 + jωL10 + R22 + R22 + jωL20 (3.9)

18 SCHEMATIC

IMPORTED MEASURED DATA OPTIMIZATION ALGORITHMS

Figure 3.7: ADS Circuit Implementation

3.4 ADS Implementation

3.4.1 Description

Fig. 3.7 shows the circuit implementation in ADS for optimization. In order to

import the measured data in ADS, the DataAccessComponent item is used. Here,

the S-parameters are assigned to a simple 2-port network. This has been marked as

‘IMPORTED MEASURED DATA’.

The section marked as ‘SCHEMATIC’ shows the circuit implementation when

the gate and drain extrinsic networks are in THRU conﬁguration. In order to per-

form ﬁtting, optimization expressions have been formulated. These are indicated by

19 ‘OPTIMIZATION ALGORITHMS’. In order to achieve perfect fit, the difference between the S-parameters of the two networks must converge towards zero. As a result, the difference between both the magnitude and the phase of the S-parameters are minimized as shown in Eqn. 3.10 and 3.11

abs((mag(S[i, j])) − (mag(S[p, q]))) (3.10)

abs((phase(S[i, j])) − (phase(S[p, q]))), (3.11)

where (i,j) and (p,q) correspond to the ports 1 and 2 of the schematic and the imported network respectively.

3.4.2 Results

The parametric extraction of the S parameters plotted in Smith Charts using ADS is shown in Fig. 3.8.

In order to verify the results obtained using ADS, least square approximation is used in MATLAB to facilitate parametric extractions on networks implemented using the Z parameter equations derived in section 3.3. Table 3.1 summarizes the extracted parameters using ADS and MATLAB. It can be seen that the extracted values are quite similar.

3.5 Conclusion

In this chapter, diﬀerent topologies used for extrinsic networks were explained.

This was followed by the analytical analysis of the OPEN, SHORT and THRU con-

ﬁgurations of the gate and drain extrinsic networks employed in this work. The measured data was ﬁtted into the resulting networks using ADS and MATLAB where excellent matching was obtained between the values of the extracted parameters.

20 Figure 3.8: Smith Charts in ADS showing the parametric extraction

21 PARAMETER ADS MATLAB R10 ( Ω) 10.5 10.6 C10 (fF) 31.0 31.7 R11 ( Ω) 0.97 0.95 R12 ( Ω) 790.1 792.0 L10 (pH) 53.9 53.6 R20 ( Ω) 11.0 11.4 C20 (fF) 30.0 30.7 R21 ( Ω) 0.89 0.80 R22 ( Ω) 795.1 797.0 L20 (pH) 31.9 31.7

Table 3.1: Comparison of the extracted parameters using ADS and MATLAB

22 CHAPTER 4

CHARACTERIZATION OF CLASS A AND CLASS B POWER AMPLIFIERS

4.1 Introduction

Power Ampliﬁers are designed to deliver the maximum power output for a given selection of active device [18]. They are further divided into class A, AB, B, C, D and

E based on the conduction angle of the input signal through the amplifying device.

Generally, Class A, AB, B and C are used for Analog circuits while Class E and

F are used for switching circuits. In Class A mode, the active transistor works in

the linear range all the time as the conduction angle is 360o or 2π radians. Even

though the ampliﬁers works in the linear mode, the power eﬃciency is very poor. As

a result, Class A ampliﬁers are generally used for low-power applications. In Class B

mode, the active transistor works in the linear range half of the time and is ideally

turned oﬀ for the remaining duration. As a result, the conduction angle is 180o or

π radians. In order to achieve complete conduction for the complete cycle, another

ampliﬁer operating in Class B mode is used which remains active during the negative

sinusoid. This leads to higher eﬃciency than Class A, but adds nonlinear distortion

to the output waveform. Moreover, the transistor saturation ﬂattens the peaks of the

23 iac

Idc

iac

(a) (b)

Figure 4.1: Output current response for: (a) Class A, (b) Class B

output sinusoid. The output current response for Class A and Class B is shown in

Fig. 4.1

Ampliﬁers can also be divided into three main topologies namely Common Source,

Common Gate and Common Drain depending on the input and the output terminals [2]. These topologies are shown in Fig. 4.2. In this work, only the ﬁrst two topologies will be investigated.

4.2 Large Signal Network Analyzer

Under realistic large-signal operating condition, small-signal network analysis is insuﬃcient to characterize a Device Under Test (DUT) due to the non-linear behavior of the DUT.The Non Linear RF Laboratory at the Ohio State University has acquired a Large Signal Network Analyzer (LSNA) in Spring 2004 under an AFOSR equipment grant [19].

LSNA can be used to conduct vectorial characterization of the non-linear response of RF systems to periodic signals. This is due to its unique ability of facilitating measurements of both the phase and the amplitude of periodic RF signals of both the

24 COMMON GATE COMMON DRAIN

VDD VDD

RD ID VOUT M

VIN ID

VOUT VBIAS M RL

V IN COMMON SOURCE

VDD

VOUT

VIN M

Figure 4.2: Diﬀerent topologies of Ampliﬁers

fundamental as well as the harmonics up to 20 GHz [20]. In addition, the frequency range can be upgraded up to 50 GHz. During this work, the data acquisition in LSNA was limited to 20 GHz. The acquired voltage and current waveforms of the DUT at the predetermined reference planes and operated under certain bias condition can be easily converted into the incident and reﬂected waveforms.

The OSU LSNA measurement system [21] consists of a test set, sampling converter, signal generator, power meter and harmonic reference(HPR) module. The test set separates the incident and the reﬂected waves at the measurement ports 1

25 and 2. The resulting four channels are then connected to the sampling converter,

which then converts the microwave signals in IF signals using harmonic sampling

method. The power meter (sensor) and HPR provide necessary information on abso-

lute power and phase used for LSNA calibration. The HPR is a step recovery diode

(SRD) which generates a very stable pulse containing many frequencies.

4.3 Class A Conﬁguration

4.3.1 DC-IV Characteristics

In order to determine the optimum operating point for biasing, DC-IV characteristics were ﬁrst obtained. For this, both Vgs and Vds were varied from 0 to 1.2 V.

Fig. 4.3 shows the DC-IV characteristics of the measured device and the simulated results of weak and normal device models. It can be inferred from Fig. 4.3 that as

Vgs increases, the DUT behaves similar to the normal model.

4.3.2 Common Source Conﬁguration

The DUT was ﬁrst operated in the saturation mode. The bias voltages were chosen as VGS = 0.9 V and VDS = 0.8 V. The RF excitation was 0.3 V at the fundamental frequency of 4 GHz. The source and the load impedances were set as 50 Ω. The number of harmonics were limited to 4 because the LSNA cannot facilitate measurements for signals at frequencies higher than 20 GHz as mentioned

in section 4.2. With these conditions, the injected (a) and the reﬂected (b) parameters

were acquired using LSNA.

Next, the device model was simulated in ADS. Fig. 4.4 shows the schematic ﬁle

in ADS. The source and the load impedances for the harmonics were calculated from

the a and b parameters measured from the DUT using LSNA in order to reproduce

26 DCIV CHARACTERISTICS 18 weak 16 normal Measured 14

8 (mA) ds I 6

−2 0 0.2 0.4 0.6 0.8 1 V (V) ds

Figure 4.3: DC-IV characteristics of the DUT

Device Model Simulation Set Up

DC Biasing Circuits

DUT

Gate Extrinsic Network Drain Extrinsic Network

Device Dimensions DUT Operating conditions

Source and Load Impedances

Figure 4.4: ADS schematic for Class A saturation mode

27 I vs time ds 16 measured weak 14 normal strong 12

8 (mA) ds I

0 0 0.1 0.2 0.3 0.4 0.5 time (nS)

(a)

V vs time V vs time gs ds 1.4 1.3 mesuured measured weak weak 1.3 normal 1.2 normal strong strong 1.2 1.1

1.1 1 (V) 1 (V)) 0.9 gs ds V V

0.9 0.8

0.8 0.7

0.7 0.6

0.5 0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5 time (nS) time (nS)

(b) (c)

Figure 4.5: Current and Voltage plots for Class A PA operating in the saturation region

the exact experimental conditions during the simulations. In addition, the simulated

a and b parameters were obtained using two 4-port S-parameter networks at both the input and the output sides. The Gate and the Drain extrinsic parameters were also added to account for any variation in the simulation results. Simulations were carried out by using the Harmonic Balance Simulator provided in ADS [22].

28 I vs V I vs V ds gs ds ds 16 16 measured measured weak weak normal normal strong strong 14 14

12 12

10 10

8 8 (mA) (mA) ds ds I I

6 6

4 4

2 2

0 0 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 V (V) V (V) gs ds (a) (b)

Figure 4.6: Ids vs Vgs and Ids vs Vds loadlines for the Class A Power Ampliﬁer operating in the saturation region

Fig. 4.5 compares the iv plots of the measured data of the DUT with the simulated data of weak, normal and strong device models. Fig. 4.5(b) indicates that the similar input swing is given to all the devices. From the Ids plot and the Vds plots, as in

Fig. 4.5 (a) and (c), it can be inferred that the DUT is closer to the normal device model. This is in agreement with DC-IV characteristics shown in Fig. 4.3.

Fig. 4.6 depicts the Ids vs Vgs and the Ids vs Vds loadlines for the measured and the simulated devices. The wide hysteresis in the measured Ids vs Vgs characteristic

29 I vs time ds 12 measured weak normal 10 strong

6 (mA) ds I

0 0 0.1 0.2 0.3 0.4 0.5 time (nS)

(a)

V vs time V vs time gs ds 1.4 0.65 mesuured measured weak weak 0.6 1.3 normal normal strong strong 0.55 1.2

0.5 1.1 0.45 (V) 1 (V)) gs ds V V 0.4 0.9 0.35

0.8 0.3

0.7 0.25

0.2 0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5 time (nS) time (nS)

(b) (c)

Figure 4.7: Current and voltage plots for Class A Power Ampliﬁer operating in the Linear region

in Fig. 4.6(a) suggests that there is additional capacitance in the Gate which is not accounted by the model.

The DUT was then operated in the linear mode for which, Vds was reduced to 0.4

V, the rest remaining the same. The current and voltage plots, thus obtained, are illustrated in Fig. 4.7.

From the current plot in Fig. 4.7(a) it can be inferred that in the linear mode, the

DUT characteristics are closer to those of the weak model. On the other hand, from

30 I vs V I vs V ds gs ds ds 12 12 measured measured weak weak normal normal strong strong

10 10

8 8

6 6 (mA) (mA) ds ds I I

Wide Hysteresis 4 4

2 2

0 0 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 V (V) V (V) gs ds (a) (b)

Figure 4.8: Ids vs Vgs and Ids vs Vds loadlines for the Class A Power Ampliﬁer operating in the linear region

the Vds in Fig. 4.7(c), the DUT characteristics are closer to the normal model. This ambiguity was resolved by analyzing the loadlines plot. The input and the output loadlines are shown in the Fig. 4.8.

Again, a wide hysteresis is observed in the Ids vs Vgs plot, in Fig. 4.8, for measured

DUT indicating the presence of unaccounted Gate capacitance. In addition from

Fig. 4.8(a) and (b), it can be inferred that the DUT characteristics are closer the

weak model when the device is operated in the linear mode.

31 Figure 4.9: Test Bench for analyzing Class A Power Ampliﬁers in Common Gate Conﬁguration

4.3.3 Common Gate Conﬁguration

A special test bench was designed for analyzing the devices based on Common

Gate conﬁguration. Fig. 4.9 shows the designed test bench. Now, the extrinsic pads

are embedded for the Source and the Drain terminals. A large resistor is added

to the Gate biasing network. In additional, the Gate is ac grounded using a large

capacitance.

Fig. 4.10 presents the DC-IV characteristics of the DUT designed for Common

Gate conﬁguration. It can be inferred that the DUT performance will be between that of the normal and the weak model.

The DUT was operated in the saturation mode. The bias voltages were chosen as

VGS = 0.9 V and VDG = −0.1 V. The RF excitation was 0.3 V at the fundamental

frequency of 4 GHz. The source and the load impedances were set as 50 Ω. The num-

ber of harmonics were limited to 4 due to the limitations stated earlier in section 4.2.

32 DCIV CHARACTERISTICS 14 weak 12 normal Measured

6 (mA) ds I

−2 0 0.2 0.4 0.6 0.8 1 V (V) ds

Figure 4.10: DC-IV characteristics of the DUT in the Common Gate conﬁguration

With these conditions, the injected (a) and the reﬂected (b) parameters were acquired

using LSNA.

Fig. 4.11 outlines the schematic used for running simulations in ADS. A large

capacitor (C = 1000 pF) is added to the gate for ac grounding. Also, the substrate is

connected to the ground causing body eﬀect. The source and the load impedances for

the harmonics were calculated from the a and the b parameters measured from the

DUT using LSNA. The gate extrinsic pad, which was used for the Common Source

Network, is now removed. Instead, the source and the drain extrinsic pad networks

are added whose values were extracted using the method explained in Chapter 3.

Table 4.1 reports the extracted resistive and the reactive parameters. Finally, in

order to increase the ﬁdelity of the simulations, the input stimuli is given for the

33 PARAMETER R10 C10 R11 R12 L10 R20 C20 R21 R22 L20 ( Ω) (fF) ( Ω) ( Ω) (pH) ( Ω) (fF) ( Ω) ( Ω) (pH) VALUE 8.25 32.8 0.78 580 35.8 8.93 31.5 1.01 570 54.86

Table 4.1: Source and Drain Extrinsic Parameters

Simulation Set Up

Device Model

Capacitor for AC grounding

Drain Extrinsic Network DUT

Source Extrinsic Network

Source and Drain Impedances Device Dimensions Input Stimuli

Figure 4.11: ADS schematic for Common Gate Class A Power ampliﬁer

fundamental as well as the harmonics. These were obtained from the measurement data of the DUT.

Fig. 4.12 delineates the current and the voltage waveforms for the DUT, the weak and the normal device models. As suggested by the DC-IV characteristics in

Fig. 4.10, the device has Ids characteristic is between the weak and the normal model.

Fig. 4.12(b) and (c) are Vsg and Vdg waveforms as the Gate is common here.

34 I vs time ds 14 measured weak 12 normal

6 (mA) ds I

−2 0 0.1 0.2 0.3 0.4 0.5 time (nS)

(a)

V vs time V vs time sg dg −0.5 0.3 measured measured weak weak −0.6 normal 0.2 normal

−0.7 0.1

−0.8 0 (V) −0.9 (V)) sg dg V V −0.1 −1

−0.2 −1.1

−1.2 −0.3

−1.3 −0.4 0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5 time (nS) time (nS)

(b) (c)

Figure 4.12: Current and Voltage waveforms for Class A ampliﬁer operating in Com- mon Gate Conﬁguration

35 I vs V I vs V ds sg ds dg 14 14 measured measured weak weak normal normal

12 12

10 10

8 8

6 6 (mA) (mA) ds ds I I

4 4

2 2

0 0

−2 −2 −1.3 −1.2 −1.1 −1 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0 0.1 0.2 0.3 V (V) V (V) sg dg (a) (b)

Figure 4.13: Input and Output loadlines for Class A ampliﬁer operating in Common Gate Conﬁguration

Fig. 4.13 shows the input and the output loadlines for the devices. It can be

inferred that the performance of DUT is closer to the weak model.

4.4 Class B Conﬁguration

4.4.1 Experimental Setup

In order to run the MOSFET in Class B mode, the DC biasing at the Gate, VGS, must be adjusted. It is set equal to the threshold voltage, VT H . This will ensure than

36 VD

V 2ω D ZL ( 0 )= 0 M

v (2ω ) v (ω 0 ) 2 0 1 VS

Figure 4.14: Schematic for the experimental set-up for the characterization of the Class B Power Ampliﬁer

the output current, Ids is equal to 0. As mentioned in section 4.1, non-linear distortion

is added to the output waveform during Class B operation. This can be minimized

by performing active load-pull at 2ω0 where the load impedance ZL(2ω0) = 0 as

ΓL(2ω0) ≈ 16 180. This will result in the output voltage component at 2ω0 to be approximately equal to zero. By this way, harmonic distortion can be reduced at the output. Fig. 4.14 shows the active load-pull scheme for Class B ampliﬁer.

4.4.2 ADS Implementation

As the only changes in the ADS schematic will be in VGS and ΓL(2ω0), it is not

reproduce here.

Fig. 4.15 shows the current and the voltage waveforms for the DUT, the weak ,

the strong and the normal device models. It can be inferred that the device has Ids

and the Vds characteristics similar to the strong model. Note the harmonics produced

when the DUT is in OFF state. A detailed analysis will be conducted in the next

chapter.

37 I vs time ds 9 measured 8 weak normal 7 strong

4 (mA) ds I 3

−1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 time (nS)

(a)

V vs time V vs time gs ds 1.4 1.05 measured measured weak weak 1.2 1 normal normal strong 0.95 strong 1

0.9 0.8 0.85 (V) 0.6 (V)) gs ds V V 0.8 0.4 0.75

0.2 0.7

0 0.65

−0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 time (nS) time (nS)

(b) (c)

Figure 4.15: Current and Voltage waveforms for Class B ampliﬁer operating in Com- mon Source Conﬁguration

38 I vs V I vs V ds gs ds ds 9 9 measured measured weak weak normal normal strong strong 8 8

7 7

6 6

5 5

4 4 (mA) (mA) ds ds I I

3 3

2 2

1 1

0 0

−1 −1 −0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 V (V) V (V) gs ds

(a) (b)

Figure 4.16: Input and Output loadlines for Class B ampliﬁer operating in Common Source Conﬁguration

Fig. 4.16 compares the input and the output loadlines for the four cases which gives similar inferences as made with the class A ampliﬁers.

4.5 Conclusion

In this chapter, different classes of Power Amplifiers were explained with the ac- cent on Class A and Class B amplifiers. Different topologies of amplifiers were also discussed. The salient features of LSNA were explained. Next, Class A amplifiers in common source as well as common gate configuration were analyzed, both experi-

mentally as well as using ADS. Finally, Class B ampliﬁers were analyzed by canceling

the output voltage at 2ω0 to reduce the non-linear distortion due to second harmonic.

39 CHAPTER 5

DETAIL ANALYSIS OF THE HARMONICS ON THE DEVICE PERFORMANCE

5.1 Introduction

A pure tone RF signal is devoid of any harmonics as it comprises of only one signal. Unfortunately, this relates to an ideal situation. In the real world, harmonics are always associated with RF signals. Most of the commercial available RF systems

are designed to minimize these harmonics. In a good RF ampliﬁer, the harmonics are

generally weaker than the actual signal.

Harmonics are caused due to diﬀerent reasons. The main cause of the generation

of harmonics is the non-linearity of the active components like FETs, BJTs and

diodes. Generally, for baseband operations, these components are assumed to be

working as linear devices. But at very high frequencies, additional capacitances need

to be accounted in these devices which leads to non-linearity. As a result, the higher

order terms lead to additional signals at frequencies that are integral multiples of the

fundamental frequency. Harmonics are also caused due to inter modulation of various

signals in the channel. This is of great concern among Communication Engineers as

these inter modulations cause unwanted interband signals that signiﬁcantly reduce

40 the performance. Finally, harmonics can also be caused by the operating conditions of an amplifier. It has already been mentioned in 4.1 that during the OFF period of a transistor in a Class B amplifier, non-linear distortion are introduced. A detailed theoretical harmonic analysis in Class B power amplifier has been covered in the classic paper by Snider [23].

In this chapter, the discussion will be limited to the non-linearity in devices.

5.2 Mathematical Analysis of Harmonics

In this section, a mathematical analysis of harmonics is presented. For a detailed analysis of distortions caused by individual harmonics, refer [24].

Let us assume that a single tone sinusoidal input is applied to a non-linear system.

vin = vac sin(ω0t) (5.1)

As the system is a non-linear system, the output voltage will depend on the input as follows:-

2 2 3 3 vout = Vdc + a1vac sin(ω0t) + a2vac sin (ω0t) + a3vac sin (ω0t) + . . . (5.2)

This can be further reduced as follows:-

3 2 4 3vac vac vac v = V + a1v +a3 +. . . sin(ω0t)− a2 +a4 +. . . cos(2ω0t)+. . . (5.3) out dc ac 4 2 2 Eqn. 5.4 shows the ﬁnal generalized expression of the output voltage.

vout = Vdc + a2p+1 sin (2p + 1)ω0t + a2p cos 2pω0t (5.4) p=0 X odd harmonics even har monics | {z41 } | {z } From Eqn. 5.4 it can be inferred that the even harmonics are cosine functions while the odd harmonics are sine function. Moreover, it can be seen that the constant term

ap depends on number of harmonics considered. For example, if only 4 harmonics are

considered, then the value of the constant term a3 will be diﬀerent than the value

of a3 when 8 harmonics are considered. Based on this concept, the next section will analyze the optimum number of harmonics to be considered for the characterization of the given device.

5.3 Figure of Merits

In order to perform qualitative analysis, it is necessary to identify certain parameters which give a unique identity to every waveform. In this analysis, two such

ﬁgure of merits were introduced. The ﬁrst one is called the Root Mean Square Error

(RMSE) which is mathematically deﬁned as the square root of the diﬀerence between

the squares of two diﬀerent waveforms. Here, the waveforms were analyzed in the

frequency domain. The expression for RMSE is given by :-

2 N 2 RMSE = I A ω = 0 − I B ω = 0 + 2 I A nω0 − I B nω0 v u n=1 u X t (5.5)

where I[A] means that the number of harmonics used for constructing I is A, n refers

to the nth harmonic and ω0 refers to the fundamental frequency.

Another ﬁgure of merit was chosen as the maximum deviation between two wave-

forms. This gives the maximum diﬀerence between two waveforms during a complete

period. The expression for maximum deviation is given by:-

42 maxdev = max I[A] − I[B] (5.6) The convergence limit for these ﬁgure of merits was set to 10−3 mA.

5.4 Analysis of Class A Power Ampliﬁer in Saturation Mode

In order to find out the optimum number of harmonics that have a considerable effect the device performance, four orders were chosen namely 4, 10, 15 and 20. Before proceeding with the determination of the figure of merits, a graphical analysis was performed. Fig. 5.1 shows the graphical analysis of the output current Ids. The

first frame shows the complete Ids time-domain characteristics for class A operation in saturation mode. In the next frame, a magnified portion is depicted to check the proximity of the waveforms with respect to one another. At this resolution, it can be seen that is considerable distance between the waveform constructed with 4 harmonics with those constructed with 10, 15 and 20 harmonics. A portion of this is again magnified in the final frame, where the waveform with order 10 has considerable distance from order 15 and 20. This gives us an idea on the trend of the effect of the harmonics on the current waveform. It can be inferred that within the desired convergence goal, the waveforms at order = 15 and 20 followed each other. This will be justified by determining the figure of merits.

Table 5.1 shows the ﬁgure of merits which were determined using post-simulation analysis in MATLAB. Three deviations have been reported namely, deviation from

Order 4 to 10, 10 to 15 and 15 to 20. This measures the degree of closeness of the waveform constructed from a particular number of harmonics to the other. Another

43 Output Current comparison for order of harmonics as 4, 10,15 and 20 Output Current comparison for order of harmonics as 4, 10,15 and 20 16 Order = 4 15.2 Order = 4 14 Order = 10 15.15 Order = 10

Order = 15 15.1 Order = 15 12 Order = 20 Order = 20 15.05 10 15

(mA) 14.95 (mA) ds ds I 6 I 14.9

14.85 4

14.8 2 14.75

0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 2.6 2.62 2.64 2.66 2.68 2.7 2.72 −10 −10 time (ns) x 10 time (ns) x 10

Output Current comparison for order of harmonics as 4, 10,15 and 20 15.098 Order = 4 15.097 Order = 10 Order = 15 15.096 Order = 20 15.095

15.094 (mA) ds I 15.093

15.092

15.091

2.6285 2.629 2.6295 2.63 2.6305 −10 time (ns) x 10

Figure 5.1: Graphical analysis to determine the optimum number of harmonics for Class A operation

44 PARAMETER Deviation from Deviation from Deviation from (mA) order 4 to 10 order 10 to 15 order 15 to 20 RMSE (magnitude) 0.0082 8.654 × 10−5 1.54 × 10−4 −4 maxdev 0.0303 0.0016 2.94 × 10

Table 5.1: Figure of merits for class A operation in saturation mode

thing to notice here is that only the magnitude of RMSE has been reported here as

the phase deviation will be nominal in this case.

It can be inferred from Table 5.1 that the convergence target has been reached for both the parameters when the deviation is measured from order 15 to 20. It

is important to notice here is that even though the magnitude of RMSE for the

deviation from order 10 to 15 has a lesser value than the deviation from order 15

to 20, yet the maxdev has not reach the convergence limit. Hence, order 20 is the

optimum number of harmonics to reconstruct the waveform.

It was mentioned in the section 4.2 that during these measurements, the mea-

surements in LSNA were limited to the signals up to 20 GHz. As a result,it will be

interesting to compare the output currents Ids constructed using the ﬁrst 4 harmonics

for order 4, 10, 15 and 20. As all these waveforms consist only 4 harmonics, there

should not be considerable diﬀerence between them. This analysis is required to com-

pare the reconstructed signals with the actual DUT performance. Fig. 5.2 compares

the reconstructed Ids from the 4 harmonics for the order 4, 10, 15 and 20. Table 5.2

shows the ﬁgure of merits calculated for these waveforms. It can be seen that all of

them are below the convergence limit.

45 Comparison of the I reconstructed from the 4 harmonics for order 4, 10,15 and 20 ds 0.02 Order = 4

0.018 Order = 10 Order = 15 0.016 Order = 20

0.014

0.012 (A)

ds 0.01 I

0.008

0.006

0.004

0.002 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 time (ns)

Figure 5.2: Comparison of the reconstructed Ids for Class A saturation mode

PARAMETER Deviation from Deviation from Deviation from (mA) order 4 to 10 order 10 to 15 order 15 to 20 RMSE (magnitude) 3.0763 × 10−6 3.0745 × 10−6 3.0742 × 10−6 −5 −5 −5 maxdev 1.0511 × 10 1.0517 × 10 1.0519 × 10

Table 5.2: Figure of merits for reconstructed waveforms from 4 harmonics for Class A operation in saturation mode

46 Comparison of I reconstructed from the 4 harmonics ds 20 Order = 4 18 Order = measured Order = 20(4) 16 Order = 20(20)

10 (mA) ds I 8

0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 time (ns)

Figure 5.3: Comparison of the reconstructed Ids for DUT and strong model in saturation mode

PARAMETER Deviation from DUT Deviation from DUT Deviation from (mA) to model with N= 4 to model with N = 20 order 4 to 20 RMSE (magnitude) 1.658 × 10−3 1.662 × 10−3 1.461 × 10−5 −5 −5 −5 maxdev 2.051 × 10 2.124 × 10 1.052 × 10

Table 5.3: Figure of merits for Ids plot for DUT and strong model for Class A operation in saturation mode

Comparisons can also be made on the performance of diﬀerent device models with respect to the DUT. In order to avoid reiteration, only the strong device model will be analyzed here. Fig. 5.3 compares the DUT’s Ids characteristics with the waveform containing 4 and 20 harmonics and the reconstructed waveform with the

ﬁrst 4 harmonics for order 20. The ﬁgure of merits are shown in Table 5.3. A good

agreement can be seen between the waveform with 4 harmonics and the reconstructed waveform with the ﬁrst 4 harmonics for order 20.

47 Output Current comparison for order of harmonics as 4, 10,15 and 20 Output Current comparison for order of harmonics as 4, 10,15 and 20 16 Order = 4 Order = 4 14 Order = 10 3 Order = 10

12 Order = 15 2.5 Order = 15 Order = 20 Order = 20 10 2

8 1.5 (mA) 6 (mA) 1 ds ds I I

4 0.5

2 0

0 −0.5

−2 −1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0.8 1 1.2 1.4 1.6 1.8 −10 −10 time (ns) x 10 time (ns) x 10

Output Current comparison for order of harmonics as 4, 10,15 and 20

0.6

0.55

0.5

0.45

0.4

(mA) 0.35 ds I 0.3

0.25 Order = 4 0.2 Order = 10

0.15 Order = 15

0.1 Order = 20

7.2 7.4 7.6 7.8 8 8.2 8.4 −11 time (ns) x 10

Figure 5.4: Graphical analysis to determine the optimum number of harmonics for Class B operation

5.5 Analysis of Class B ampliﬁer

Fig. 5.4 shows the graphical analysis of the output Ids. It can be inferred that the number of harmonics were increased. The waveform in the the cutoﬀ region had shorter ﬂuctuations and was relatively smoother. Also, the waveforms at order 15 and

20 followed each other within the convergence limit. The figure of merits have been determined in Table 5.4. The optimum number of harmonic effects can be furthered studied as done for Class A Power Amplifiers.

48 PARAMETER Deviation from Deviation from Deviation from (mA) order 4 to 10 order 10 to 15 order 15 to 20 RMSE (magnitude) 0.0051 0.0015 9.267 × 10−4 maxdev 0.3586 0.0246 0.0027

Table 5.4: Figure of merits for class B operation

5.6 Conclusion

In this chapter, the eﬀect of harmonics on the device characteristics was studied.

First, the order where the convergence limit was satisﬁed was determined and was

found to be 20 based on the ﬁgure of merits RMSE and maxdev. Next the waveforms reconstructed with the ﬁrst for harmonics for orders 4, 10, 15 and 20 were compared.

Convergence limit was achieved for all these cases. Finally, the DUT performance was compared with the order 4 and 20. Recently, the LSNA has been upgraded

to facilitate measurements for frequencies up to 50 GHz. As a result, the eﬀect of harmonics with frequencies greater than 16 GHz can be studied in the future.

49 CHAPTER 6

VERIFICATION OF DEVICE SYMMETRY

6.1 Introduction

In theory, MOSFETs are physically symmetric with respect to the source and the drain terminals. This means that theoretically it is possible to interchange the role of the source and the drain terminals and expect similar response. However, it has been identified that the conventional FET model shows deviation due to the discontinuities in the higher order derivatives that occur due to the change from Vgs to Vgd in the device models when the source and the drain terminals are interchanged [25]. By discontinuities we mean that the derivatives do not exist as they have different limits at their left and right hand extremes as Vds approaches zero leading to the matrices representing the model being singular. This is not a desirable feature when MOSFETs are used in RFIC applications. AC and DC schemes have been developed to verify the symmetric behavior of MOSFET owing to source-drain reversal [26]. In this section, schemes will be developed using LSNA to test the symmetry of the DUT as well as the device models in common gate configuration.

50 Vg

S D V V 1 B 2 v in,1 v in,2

Figure 6.1: Experimental Setup to determine the device symmetry

6.2 Experimental Setup

Fig. 6.1 illustrates the test bench developed to perform device symmetry tests.

Here, the purpose was to match the response of the Common Gate device models

with the DUT under diﬀerent input conditions. The source and the drain dc biasing

was set to zero while the gate was biased with Vg = 0.9 volts. Moreover, the devices

were tested at both low (600 MHz) as well as high (4 GHz) frequencies to account

for all the linear and non-linear components in the model. The RF excitation applied

was 0.3 V. Table 6.1 shows the diﬀerent input voltage schemes applied. In scheme A,

same RF signal is applied at both the source and the drain terminals. In scheme B

and C, the input signals are 1800 and 900 out of phase respectively. The anti-phase

source and drain excitations enable the analysis of the gate charge symmetry and the

in-phase excitations enable the source and drain charge symmetry [26].

51 CASE v1(V ) v2(V ) A vin vin6 0 B vin vin6 180 C vin vin6 90

Table 6.1: Input signal schemes for testing device symmetry

6.3 ADS Implementation

The ADS schematic used for testing device symmetry is shown in Fig. 6.2. Voltage sources are now added at both the source and the drain terminals while the substrate is grounded . Additional RC ﬁlter bank has been added at the gate biasing network.

The source and the drain are grounded. Current probes have been added to both the source and the drain terminals to measure the respective currents. The injected and the reﬂected parameters (a, b) are measured using the 4-port S-parameter block.

6.4 Comparison of measured and simulated results

Fig. 6.3-6.8 delineate the current and voltage waveforms comparing the DUT as well as the device model performance to verify device symmetry. I1t and V1t refer to the current and voltage waveforms measured at the source terminal while I2t and V2t refer to the current and voltage waveforms measured at the drain terminal. Moreover,

Fig. 6.3-6.5 are measured at the fundamental frequency of 4 GHz and Fig. 6.6-6.8 are measured at the fundamental frequency of 600 MHz.

Based on these plots, it can be inferred that excellent match is seen for the cases

B and C. On the other hand, for case A where the signals injected at the source and the drain are in-phase, there is considerable irregularity in the current waveforms.

52 Figure 6.2: ADS setup for testing device symmetry

Moreover, the extrema for I2t are much greater than that for I1t. This suggests diﬀerence in source and drain impedance. Also, the non-linearity in source for DUT

is diﬀerent from the drain of the DUT which in turn matches with those shown by

the source and the drain of the device model. Further, non-linearity can be observed

in the current waveforms for case A and C while none are present in case B. This

suggests that the non-linearities get canceled when the injected signals are 1800 out

of phase at both 4 GHz and 600 MHz. In case B, almost perfect matching is observed

at both 4 GHz and 600 MHz.

The non-linearities observed in case C are similar for both the DUT as well as

the model. This means that the non-linearities that caused variation in the DUT and

model performance in case A get eliminated when the input excitations are 900 out

of phase. This study concludes that there is some asymmetry between the source and

53 I vs time I vs time 1t 2t 2 2 measured measured

1.5 weak 1.5 weak normal normal strong strong 1 1

0.5 0.5

0 0 (mA) (mA) 1t I 2t

−0.5 I −0.5

−1 −1

−1.5 −1.5

−2 −2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 time (nS) time (nS) (a) (b)

V vs time V vs time 1t 2t −0.4 −0.4 measured measured −0.5 weak −0.5 weak normal normal −0.6 strong −0.6 strong

−0.7 −0.7

−0.8 −0.8

−0.9 (V) −0.9 (V)) 2t 1t V V −1 −1

−1.1 −1.1

−1.2 −1.2

−1.3 −1.3

−1.4 −1.4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 time (nS) time (nS) (c) (d)

Figure 6.3: Current and voltage plots for case A at 4 GHz

54 I vs time 1t I vs time 2t 10 10 measured measured 8 weak 8 weak normal normal 6 strong 6 strong

4 4

2 2

0 0 (mA) (mA) 1t 2t I −2 I −2

−4 −4

−6 −6

−8 −8

−10 −10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 time (nS) time (nS) (a) (b)

V vs time V vs time 1t 2t −0.75 −0.65 measured measured

weak −0.7 weak normal normal −0.8 strong strong −0.75

−0.8 −0.85

(V) −0.85 (V)) 2t 1t V V −0.9 −0.9

−0.95 −0.95

−1

−1 −1.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 time (nS) time (nS) (c) (d)

Figure 6.4: Current and voltage plots for case B at 4 GHz

55 I vs time I vs time 1t 2t 6 8 measured measured

weak 6 weak 4 normal normal strong strong 4

2 2

0 0 (mA) (mA) 1t 2t I I −2 −2

−4

−4 −6

−6 −8 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 time (nS) time (nS) (a) (b)

V vs time V vs time 1t 2t −0.4 −0.4 measured measured −0.5 weak −0.5 weak normal normal −0.6 strong −0.6 strong

−0.7 −0.7

−0.8 −0.8 (V) (V)) 2t 1t −0.9 −0.9 V V

−1 −1

−1.1 −1.1

−1.2 −1.2

−1.3 −1.3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 time (nS) time (nS) (c) (d)

Figure 6.5: Current and voltage plots for case C at 4 GHz

56 I vs time I vs time 1t 2t 0.3 0.4 measured measured

weak 0.3 weak 0.2 normal normal strong strong 0.2 0.1

0.1 0

0 (mA) (mA)

1t −0.1 2t I I −0.1

−0.2 −0.2

−0.3 −0.3

−0.4 −0.4 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 time (nS) time (nS) (a) (b)

V vs time V vs time 1t 2t −0.2 −0.2 measured measured weak weak −0.4 normal −0.4 normal strong strong

−0.6 −0.6

−0.8 −0.8 (V) (V)) 2t 1t

−1 V −1 V

−1.2 −1.2

−1.4 −1.4

−1.6 −1.6 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 time (nS) time (nS) (c) (d)

Figure 6.6: Current and voltage plots for case A at 600 MHz

57 I vs time I vs time 1t 2t 8 8 measured measured

6 weak 6 weak normal normal strong strong 4 4

2 2

0 0 (mA) (mA) 1t 2t I I −2 −2

−4 −4

−6 −6

−8 −8 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 time (nS) time (nS) (a) (b)

V vs time V vs time 1t 2t −0.8 −0.8 measured measured −0.82 weak −0.82 weak normal normal −0.84 strong −0.84 strong

−0.86 −0.86

−0.88 −0.88

−0.9 (V) −0.9 (V)) 2t 1t V V −0.92 −0.92

−0.94 −0.94

−0.96 −0.96

−0.98 −0.98

−1 −1 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 time (nS) time (nS) (c) (d)

Figure 6.7: Current and voltage plots for case B at 600 MHz

58 I vs time I vs time 1t 2t 8 8 measured measured

weak 6 weak 6 normal normal strong 4 strong 4

2 2

0 (mA) (mA) 2t 1t 0 I I −2

−2 −4

−4 −6

−6 −8 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 time (nS) time (nS) (a) (b)

V vs time V vs time 1t 2t −0.4 −0.4 measured measured −0.5 weak −0.5 weak normal normal −0.6 strong −0.6 strong

−0.7 −0.7

−0.8 −0.8 (V) (V)) 2t 1t −0.9 −0.9 V V

−1 −1

−1.1 −1.1

−1.2 −1.2

−1.3 −1.3 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 time (nS) time (nS) (c) (d)

Figure 6.8: Current and voltage plots for case C at 600 MHz

59 the drain terminals of the DUT while the source and drain terminals of the device model show the same non-linear characteristics. The only asymmetry in the device model is in the resistive component as the variation is only in the extrema of their current waveforms.

6.5 Conclusion

In this chapter, schemes were introduced to verify the device symmetry about the source and the drain terminals for both the DUT and the device models. After comparing the current and voltage waveforms at both the source and the drain, it can be concluded that the DUT has some asymmetry as the current characteristics are not similar at 600 MHz. In fact, more non-linearities are present at the drain side. Finally, another inference was made regarding the diﬀerence in the resistive component of the device model.

60 CHAPTER 7

SUBSTRATE EXTRACTION

7.1 Introduction

There is tremendous signiﬁcance of substrate modeling for RF applications [11].

It has been studied that the substrate network accounts for 50% of the output admittance [6]. Consequently, diﬀerent models for the substrate have been studied in literature [12]- [15]. These models have been explained in detail in section 2.3.2. One important factor to consider here is that all these models have been extracted from the small signal S-parameters measured using a VNA [11]. This set forths a question on the validity of the substrate network for Power Ampliﬁers operating at frequencies

greater than 10 GHz as the non-linearities introduced will not be accounted for in the

model. As a result, in this chapter, substrate extraction will be investigated using

LSNA.

7.2 Experimental Setup

Fig. 7.1 shows the test bench developed to perform substrate extraction. It is similar to the test bench used for device symmetry as shown in Fig. 6.1. In this set of experiments, the device will be operated in the COLD condition [16]. In other words,

61 Vg

S D V V 1 B 2 v in,1 v in,2

Figure 7.1: Experimental Setup to perform substrate extraction

CASE v1(V ) v2(V ) 1 vin 0 2 0 vin 3 vin vin6 0 4 vin vin6 180

Table 7.1: Input signal schemes for performing substrate extraction

the intrinsic device will be operating in the OFF condition. As a result, VS and VD are set to zero volts and VG is varied from −0.3 V to −1.0 V. The RF excitation is set at 0.5 V for operating frequencies at both 600 MHz and 4 GHz.

Table 7.1 reports the diﬀerent input voltage schemes applied. In scheme 1, only

the source is excited while in scheme 2 the drain side is only excited. In scheme 3,

same RF signal is applied at both the source and the drain terminals and in scheme

4, the RF signals applied at the source and the drain terminals are 1800 out of phase.

62 Figure 7.2: ADS setup for performing substrate extraction

7.3 ADS Implementation

The ADS schematic used for performing substrate extraction is illustrated in

Fig. 7.2. It is similar to the one used for verifying the device symmetry. The only

change has been made on the gate biasing as the device is now operating in the COLD

state.

7.4 Comparison of measured and simulated results

As the device is operating in the COLD state, the performance of the device

model should be the same, irrespective of the fact whether it is weak, normal or

strong model.

Fig. 7.3- 7.6 show the injected, reﬂected, current and voltage waveforms for case

3 where same excitation is given to both the source and the drain terminals of the

63 a vs time a vs time 1t 2t 0.3 0.25 measured measured simulated 0.2 simulated 0.2 0.15

0.1 0.1

0.05 0 (V) (V) 0 1t −0.1 2t a a −0.05

−0.2 −0.1

−0.15 −0.3 −0.2

−0.4 −0.25 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 time (nS) time (nS)

b vs time b vs time 1t 2t 0.3 0.25 measured measured simulated 0.2 simulated 0.2 0.15

0.1 0.1

0.05 0 (V) (V) 0 2t 1t −0.1 b b −0.05

−0.2 −0.1

−0.15 −0.3 −0.2

−0.4 −0.25 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 time (nS) time (nS)

Figure 7.3: Injected (a) and reﬂected (b) waveforms for case 3 with vin = −0.3 V at 600 MHz

MOSFET. The fundamental frequency of these waveforms is 600 MHz. Here, the waveforms at 4 GHz are not shown as there was no ambiguity in the results. Finally, the other cases were not considered to avoid redundancy.

First, the waveforms will be studied when the gate voltage Vg = −0.3 V. Fig. 7.3 shows that a phase shift is observed in the reﬂected waveforms where the b of the simulated device model lags the b of the measured DUT. Similar phase shift is observed

in the voltage waveforms shown in Fig. 7.4. Finally, the current waveforms in Fig. 7.4

64 I vs time I vs time 1t 2t 0.2 0.15 measured measured simulated simulated 0.15 0.1

0.1 0.05

0.05 0 (mA) 0 (mA) −0.05 1t 2t I I

−0.05 −0.1

−0.1 −0.15

−0.15 −0.2 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 time (nS) time (nS)

V vs time V vs time 1t 2t 0.8 1 measured measured 0.7 simulated simulated 0.8 0.6

0.5 0.6

0.4 0.4

(V) 0.3 (V)

1t 2t 0.2

V 0.2 V

0.1 0

0 −0.2 −0.1

−0.2 −0.4 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 time (nS) time (nS)

Figure 7.4: Current and voltage waveforms for case 3 with vin = −0.3 V at 600 MHz

65 a vs time a vs time 1t 2t 0.3 0.25 measured measured simulated 0.2 simulated 0.2 0.15

0.1 0.1

0.05 0 (V) (V) 0 1t −0.1 2t a a −0.05

−0.2 −0.1

−0.15 −0.3 −0.2

−0.4 −0.25 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 time (nS) time (nS)

b vs time b vs time 1t 2t 0.3 0.25 measured measured simulated 0.2 simulated 0.2 0.15

0.1 0.1

0.05 0

(V) (V) 0

1t −0.1 2t

b b −0.05

−0.2 −0.1

−0.15 −0.3 −0.2

−0.4 −0.25 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 time (nS) time (nS)

Figure 7.5: Injected (a) and reﬂected (b) waveforms for case 3 with vin = −1 V at 600 MHz

66 I vs time I vs time 1t 2t 0.2 0.2 measured measured simulated simulated 0.15 0.15

0.1 0.1

0.05 0.05 (mA) 0 (mA) 0 1t 2t I I

−0.05 −0.05

−0.1 −0.1

−0.15 −0.15 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 time (nS) time (nS)

V vs time V vs time 1t 2t 1.5 2 measured measured 1.4 simulated simulated 1.8 1.3 1.6 1.2 1.4 1.1 (V) 1 (V) 1.2 1t 2t V 0.9 V 1 0.8 0.8 0.7 0.6 0.6

0.5 0.4 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 time (nS) time (nS)

Figure 7.6: Current and voltage waveforms for case 3 with vin = −1 V at 600 MHz

67 show that for the actual DUT, non-linearities can be observed in the source current

and cannot be observed in the drain current. This shows that there is additional reactive component in the source-bulk impedance of the DUT. On the other hand, similar non-linearities can be observed in both the source and the drain currents of the simulated device model. Moreover, larger current swing is observed in the DUT than the device model. This shows that the device model does not accurately model the substrate of the DUT.

The device is now analyzed when the gate voltage Vg = −1 V. In this case, it can be observed for the DUT, that the non-linearities are present in the source current and absent in the drain current. This is similar to the trend observed in the DUT when Vg = −0.3 V. On the other hand, there are no non-linearities observed in the source and the drain currents for the simulated device model.

7.5 Conclusion

In this chapter, the trends in the device substrate were investigated. The device was operated in the COLD state to make sure that the intrinsic device is turned OFF exposing only the substrate to the input excitations. Four schemes were introduced to study the substrate. Comparisons between the injected, reﬂected, current and voltage waveforms for two diﬀerent gate bias voltages (-0.3 V and 1.0 V) were produced. It was inferred that certain non-linearities were present at the source which were not accounted by the device model.

68 CHAPTER 8

ENVELOPE SIMULATIONS FOR PULSED IV/RF EXCITATIONS

8.1 Introduction

Pulsed IV characteristics are a set of measurements where the device (already operating at a fixed quiescent point) is excited with pulses short enough to avoid memory effects such as traps, thermal effects and parasitic BJTs [27], [28]. Generally, these measurements are facilitated for HEMTs and other exotic devices as they suffer from large trap effects which interfere in the characterization process. On the other hand, traps are more forgiving in the case of MOSFETs which do not suffer from slow memory effects. As a result, MOSFETs can be used to test Pulsed RF measurements experimental setup [29].

8.2 Envelope Simulations in ADS

While the Harmonic Balance Simulator in ADS is an excellent tool to analysis non- linear circuits, its limitation lies on the fact that it can only compute steady state solution [22] and therefore, is not suitable for modulated RF signals. This is of great concern to simulate Pulsed RF and IV measurements in ADS environment. In order

69 to facilitate such measurements, ADS oﬀers circuit envelope simulation tool [30]. This

tool combines features of time and frequency domain representation, oﬀering fast and

complete analysis of modulated RF signals.

Since a modulated envelope signal is represented in the time domain, RF load-

lines can be constructed by post-processing in MATLAB after the acquisition of the

amplitude and phase of the IV waveforms from the envelope simulations [21].

8.3 ADS Implementation

Fig. 8.1 shows the ADS schematic used for performing pulsed RF-IV simulations.

It is similar to the one used for Class A and B simulations with the diﬀerence in the

pulsed-DC voltage sources at the gate and drain terminals and pulsed-RF excitation

at the source terminal. The RF pulse generated here has a duty cycle of 0.33% and

0.33 µs pulse duration. The main lobe of the sinc spectrrum consists of 601 tones

in the bandwidth of about 6 MHz. The drain pulse has a duty rate of 1% and 1 µs

duration which is short enough to achieve the targeted isothermal condition [21].

8.4 Results

Fig. 8.2 shows the comparison of the DC-IV/CW-RF loadlines between the mea-

sured DUT and simulated device using circuit envelope simulation in ADS. A reason-

able agreement is seen between the simulations and the measurements. For simula-

tion, ΓL(2ω0) = 16 180 is applied for the ideal class-B operation.

On the contrary, considerable variation was observed between the simulated and

the measured characteristics when the pulsed- IV/RF excitations are used. This is shown by Fig. 8.3. This is mainly due to the fact that the used BSIM4 model lacks

70 PULSED−DC PULSED−DC GATE BIAS DRAIN BIAS

PULSE−RF EXCITATION

DEVICE

Figure 8.1: Pulsed RF- IV simulation setup in ADS

information regarding the memory eﬀects. In order words, due to the absence of

memory eﬀects data, the CW-RF and Pulsed-RF are the same. In order to facilitate

the pulsed-RF simulations, ideal perfect SHORTs, ΓL(2ω) = ΓL(3ω) = ΓL(4ω) =

16 180 were considered for the harmonic load terminations.

8.5 Conclusion

In this chapter, pulsed measurements schemes were introduced. A brief overview of circuit envelope simulation tool in ADS was presented. Next, implementation of pulsed-IV/RF simulations in ADS using circuit envelope simulation was discussed.

The post processing was done in MATLAB. Finally, the measurement and the simulation results were compared and inferences were drawn.

71 25 Measurement Simulation

15 (mA) DS I 10

−0.2 0 0.2 0.4 0.6 0.8 1 1.2 V (V) GS (a) Gate load-line

25 Measurement Simulation

15 (mA) DS I 10

0 0.2 0.4 0.6 0.8 1 1.2 V (V) DS (b) Drain load-line

Figure 8.2: Comparison of the DC-IV/CW-RF load-lines between the measurement and ADS circuit envelope simulation

72 25 Measurement Simulation

15 (mA) DS I 10

−0.2 0 0.2 0.4 0.6 0.8 1 1.2 V (V) GS (a) Gate load-line

25 Measurement Simulation

15 (mA) DS I 10

0 0.2 0.4 0.6 0.8 1 1.2 V (V) DS (b) Drain load-line

Figure 8.3: Comparison of the pulsed-IV/RF load-lines between the measurement and ADS circuit envelope simulation

73 CHAPTER 9

CONCLUSION AND FUTURE WORK

As the market demand is increasing for more robust RFICs operating in the GHz range, it is quintessential to devote more resources to model RF MOSFET models that can provide higher ﬁdelity when compared with the fabricated devices. A complete RF

MOSFET includes bondwire, extrinsic resistive and reactive network, native intrinsic

transistor and a thermal sub-network. The main aim of this thesis was to cover most of the salient features of RF device modeling.

The extrinsic resistive and reactive components are extracted based on cold-FET

method. The S-parameters over a range of frequencies can be acquired using modeling

tools like IC-CAP. These can be then ﬁtted to the respective networks by using tools like ADS and MATLAB. A thorough investigation was performed on the device in both CS and CG conﬁguration for class A and B operations. This provided great

wealth of information on the device performance at diﬀerent bias conditions. In

future, the device can be studied by de-embedding these components. Further, other

Power Ampliﬁer classes such as C, E and F should be explored. It will be interesting

to study the device performance for switching applications.

As mentioned earlier, harmonics can have a signiﬁcant impact on the eﬃciency

of RFICs. Therefore, it becomes a necessity to study the impact of the harmonics

74 to ﬁnd out the optimum number of harmonics beyond which there is no considerable change in the performance. For the given device, it was found that order 20 is the optimum number of harmonics. This was made possible via both graphical as well as

analytical approach using appropriate ﬁgure of merits.

As RF devices operate at strong inversion saturation, it is essential to establish

excellent device symmetry between the source and the drain terminals. Schemes were

developed to identify the asymmetry between the two terminals and it was determined

that the DUT had certain singularities at the source-drain reversal.

Schemes were also introduced to perform substrate extraction. It was observed

that at 600 MHz certain non-linearity was observed at the source side of the DUT.

Another interesting observation was made on the disappearance of non-linearities as

the gate biasing was reduce from -0.3 V to -1 V. This work can be further extended to

the development of indigenous models to make the entire extraction process viable.

ADS can be used to develop the optimization algorithms and goals to facilitate these

extractions.

Finally, pulsed-IV/RF simulations were developed in ADS using circuit envelope

simulation tool. This was useful in determining the validity of the setup as memory

eﬀects were not observed for the MOSFETs. On the other hand, traps were observed

on GaN HEMTs which is in agreement with the theoretical concepts.

To conclude, RF device modeling involves myriad of interesting research areas

to investigate. With the growing scalability in the die area, it becomes even more

challenging for the device engineers to produce models with high accuracy.

75 BIBLIOGRAPHY

[1] G. E. Moore, “Progress in digital Integrated Circuits,” IEDM Tech. Dig., pp. 11– 14, dec 1975.

[2] B. Razavi, Design of Analog CMOS Integrated Circuits. McGraw-Hill Higher Education, First ed., 2001.

[3] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge University Press, 1998.

[4] C. G. Sodini, P. K. Ko, and J. L. Moll, “The Eﬀect of High Fields on MOS Device and circuit Performance,” IEEE Tran. on Electron Devices, vol. 31, pp. 1386– 1393, oct 1984.

[5] Y. Tsividis, Operation and Modeling of the MOS Transistor. McGraw-Hill, Sec- ond ed., 1999.

[6] S. H. Jen, C. C. Enz, D. R. Pehlke, M. Schr¨oter, and B. J. Sheu, “Accurate Modeling and Parameter Extraction for MOS Transistors Valid up to 10 GHz,” IEEE tran. on Electron Devices, vol. 46, pp. 2217–2227, nov 1999.

[7] Y. Cheng, M. Chan, K. Hui, M. Jeng, Z. Liu, J. Huang, K. Chen, J. Chen, R. Tu, P. K. Ko, and C. Hu, BSIM3v3 Manual (Final Version). The Regents of the University of California, 1996.

[8] X. Xi, M. Dunga, J. He, W. Liu, K. M. Cao, X. Jin, J. J. Ou, M. Chan, A. M. Niknejad, and C. Hu, BSIM4.3.0 MOSFET model. The Regents of the University of California, 2003.

[9] Y. C. King, H. Fujioka, S. Kamohara, K. Chen, and C. Hu, “DC electrical oxide thickness model for quantization of the inversion layer in MOSFETs,” Semicond. Sci. Technol., vol. 13, pp. 963–966, 1998.

[10] W. Liu, X. Jin, Y. King, and C. Hu, “An eﬃcient and accurate compact model for thin-oxide-MOSFET intrinsic capacitance considering the ﬁnite charge layer thickness,” IEEE Trans. Electron Devices, vol. 46, pp. 1070–1072, may 1999.

76 [11] T. Ytterdal, Y. Cheng, and T. Fjeldly, Device Modeling for Analog and RF CMOS Circuit Design. Wiley, First ed., 2003.

[12] S. F. Lin and K. Mayaram, “Substrate Network Modeling for CMOS RF Circuit Simulation,” in IEEE Custom Integrated Circuits Conference, pp. 583–586, 1999.

[13] J. J. Ou, X. Jin, I. MA, C. Hu, and P. R. Gray, “CMOS RF Modeling for GHz Communication IC’s,” in Symposium on VLSI Technology Digest of Technical Papers, pp. 94–95, 1998.

[14] W. Liu, R. Gharpurey, M. C. Chang, U. Erdogan, R. Aggarwal, and J. P. Mat- tia, “R.F. MOSFET Modeling Accounting for Distributed Substrate and Channel Resistances with Emphasis on the BSIM3v3 SPICE Model,” Tech. Dig. Interna- tional Electron Device Meeting (IEDM), pp. 309–312, 1997.

[15] Y. Cheng, M. Schr¨oter, C. Enz, M. Matloubian, and D. Pehlke, “R.F. MOS- FET Issues of Deep-submicron MOSFETs for Circuit Design,” in International Conference on Solid-State and Integrated Circuit Technology, pp. 309–312, 1998.

[16] P. H. Aaen, J. A. Pl´a, and J. Wood, Modeling and Characterization of RF and Microwave Power FETs. Cambridge University Press, 2007.

[17] G. Dambrine, A. Cappy, F. Heliodore, and E. Playez, “A New Method for Deter- mining the FET Small-Signal Equivalent Circuit,” IEEE Trans. on Microwave Theory and Techniques, vol. 36, no. 7, pp. 1151–1159, 1988.

[18] S. C. Cripps, RF Power Ampliﬁers for Wireless Communications. Artech House, Second ed., 2006.

[19] See the online website of Non-linear RF Laboratory http://www.ece.osu.edu/∼/roblin/lsna/.

[20] “Large-Signal Network Analyzer System Manual.” NMDG Engineering.

[21] S. J. Doo, New Pulsed-IV Pulsed-RF Measurement Techniques for Characterizing Power FETs for Pulsed-RF Power Ampliﬁer Design. PhD thesis, The Ohio State University, 2008.

[22] “Guide to Harmonic Balance Simulation in ADS.” Agilent Technologies sep 2004.

[23] D. M. Snider, “A Theoretical Analysis and Experimental Conﬁrmation of the Optimally Loaded and Overdriven RF Power Ampliﬁer,” IEEE Trans. on Elec- tron Devices, vol. ED-14, pp. 851–857, dec 1967.

[24] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. Wiley, Fourth ed., 2001.

77 [25] N. Scheinberg and A. Pinkhasov, “A computer Simulation Model for Simulat- ing Distortion in FET Resistors,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, pp. 981–989, sep 2000.

[26] C. C. McAndrew, “Validation of MOSFET model Source-Drain Symmetry,” IEEE Trans. on Electron Devices, vol. 53, pp. 2202–2206, sep 2006.

[27] P. Roblin and H. Rohdin, High-Speed Heterostructure Devices. Cambridge Uni- versity Press, First ed., 2002.

[28] J. Scott, J. C. Rathmell, A. Parker, and M. Sayed, “Pulsed Device Measurements and Applications,” IEEE Trans. on Microwave Theory and Techniques, vol. 44, pp. 2718–2723, dec 1996.

[29] S. J. Doo, P. Roblin, V. Balasubramanian, R. Taylor, K. Dandu, G. H. Jessen, and R. Rojas, “Adaptive Second Harmonic Active Load for Pulsed-IV/RF Class- B Operation,” ARFTG 70th Conference, Tempe, AZ, nov. 2007.

[30] “Circuit Envelope Simulation.” Agilent Technologies aug 2005.