Am437x Sitara™ Processors Datasheet

Product Order Technical Tools & Support & Reference Folder Now Documents Software Community Design AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851E –JUNE 2014–REVISED JANUARY 2019 AM437x Sitara™ Processors 1 Device Overview 1.1 Features 1 • Highlights – Secure Control Module (SCM) (Avaliable Only – Sitara™ ARM® Cortex®-A9 32-Bit RISC on AM437xHS Devices) Processor With Processing Speed up to – Emulation and Debug 1000 MHz – JTAG – NEON™ SIMD Coprocessor and Vector – Embedded Trace Buffer Floating Point (VFPv3) Coprocessor – Interrupt Controller – 32KB of Both L1 Instruction and Data Cache • On-Chip Memory (Shared L3 RAM) – 256KB of L2 Cache or L3 RAM – 256KB of General-Purpose On-Chip Memory – 32-Bit LPDDR2, DDR3, and DDR3L Support Controller (OCMC) RAM – General-Purpose Memory Support (NAND, – Accessible to All Masters NOR, SRAM) Supporting up to 16-Bit ECC – Supports Retention for Fast Wakeup – SGX530 Graphics Engine – Up to 512KB of Total Internal RAM – Display Subsystem (256KB of ARM Memory Configured as L3 RAM – Programmable Real-Time Unit Subsystem and + 256KB of OCMC RAM) Industrial Communication Subsystem (PRU- • External Memory Interfaces (EMIFs) ICSS) – DDR Controllers: – Real-Time Clock (RTC) – LPDDR2: 266-MHz Clock (LPDDR2-533 Data – Up to Two USB 2.0 High-Speed Dual-Role Rate) (Host or Device) Ports With Integrated PHY – DDR3 and DDR3L: 400-MHz Clock (DDR- – 10, 100, and 1000 Ethernet Switch Supporting 800 Data Rate) up to Two Ports – 32-Bit Data Bus – Serial Interfaces: – 2GB of Total Addressable Space – Two Controller Area Network (CAN) Ports – Supports One x32, Two x16, or Four x8 – Six UARTs, Two McASPs, Five McSPIs, Memory Device Configurations Three I2C Ports, One QSPI, and One HDQ or • General-Purpose Memory Controller (GPMC) 1-Wire – Flexible 8- and 16-Bit Asynchronous Memory – Security Interface With up to Seven Chip Selects (NAND, – Crypto Hardware Accelerators (AES, SHA, NOR, Muxed-NOR, and SRAM) RNG, DES, and 3DES) – Uses BCH Code to Support 4-, 8-, or 16-Bit – Secure Boot (Avaliable Only on AM437x ECC High-Security [AM437xHS] Devices) – Uses Hamming Code to Support 1-Bit ECC – Two 12-Bit Successive Approximation Register • Error Locator Module (ELM) (SAR) ADCs – Used With the GPMC to Locate Addresses of – Up to Three 32-Bit Enhanced Capture (eCAP) Data Errors From Syndrome Polynomials Modules Generated Using a BCH Algorithm – Up to Three Enhanced Quadrature Encoder – Supports 4-, 8-, and 16-Bit Per 512-Byte Block Pulse (eQEP) Modules Error Location Based on BCH Algorithms – Up to Six Enhanced High-Resolution PWM • Programmable Real-Time Unit Subsystem and (eHRPWM) Modules Industrial Communication Subsystem (PRU-ICSS) • MPU Subsystem – Supports Protocols such as EtherCAT®, – ARM Cortex-A9 32-Bit RISC Microprocessor PROFIBUS®, PROFINET®, and EtherNet/IP™, With Processing Speed up to 1000 MHz EnDat 2.2, and More – 32KB of Both L1 Instruction and Data Cache – Two Programmable Real-Time Units (PRUs) – 256KB of L2 Cache (Option to Configure as L3 Subsystems With Two PRU Cores Each RAM) – Each Core is a 32-Bit Load and Store RISC – 256KB of On-Chip Boot ROM Processor Capable of Running at 200 MHz – 64KB of On-Chip RAM 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. AM4372, AM4376, AM4377, AM4378, AM4379 SPRS851E –JUNE 2014–REVISED JANUARY 2019 www.ti.com – 12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of – Three Switchable Power Domains (MPU Instruction RAM With Single-Error Detection Subsystem, SGX530 [GFX], Peripherals and (Parity) Infrastructure [PER]) – 8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of – Dynamic Voltage Frequency Scaling (DVFS) Data RAM With Single-Error Detection • Real-Time Clock (RTC) (Parity) – Real-Time Date (Day, Month, Year, and Day of – Single-Cycle 32-Bit Multiplier With 64-Bit Week) and Time (Hours, Minutes, and Seconds) Accumulator Information – Enhanced GPIO Module Provides Shift-In – Internal 32.768-kHz Oscillator, RTC Logic, and and Shift-Out Support and Parallel Latch on 1.1-V Internal LDO External Signal – Independent Power-On-Reset – 12KB (PRU-ICSS1 Only) of Shared RAM With (RTC_PWRONRSTn) Input Single-Error Detection (Parity) – Dedicated Input Pin (RTC_WAKEUP) for – Three 120-Byte Register Banks Accessible by External Wake Events Each PRU – Programmable Alarm Can Generate Internal – Interrupt Controller Module (INTC) for Handling Interrupts to the PRCM for Wakeup or Cortex- System Input Events A9 for Event Notification – Local Interconnect Bus for Connecting Internal – Programmable Alarm Can Be Used With and External Masters to the Resources Inside External Output (RTC_PMIC_EN) to Enable the the PRU-ICSS Power-Management IC to Restore Non-RTC – Peripherals Inside the PRU-ICSS Power Domains – One UART Port With Flow Control Pins, • Peripherals Supports up to 12 Mbps – Up to Two USB 2.0 High-Speed Dual-Role – One eCAP Module (Host or Device) Ports With Integrated PHY – Two MII Ethernet Ports that Support Industrial – Up to Two Industrial Gigabit Ethernet MACs Ethernet, such as EtherCAT (10, 100, and 1000 Mbps) – One MDIO Port – Integrated Switch – Industrial Communication is Supported by Two – Each MAC Supports MII, RMII, and RGMII PRU-ICSS Subsystems and MDIO Interfaces • Power, Reset, and Clock Management (PRCM) – Ethernet MACs and Switch Can Operate Module Independent of Other Functions – Controls the Entry and Exit of Deep-Sleep – IEEE 1588v2 Precision Time Protocol (PTP) Modes – Up to Two CAN Ports – Responsible for Sleep Sequencing, Power – Supports CAN Version 2 Parts A and B Domain Switch-Off Sequencing, Wake-Up – Up to Two Multichannel Audio Serial Ports Sequencing, and Power Domain Switch-On (McASPs) Sequencing – Transmit and Receive Clocks up to 50 MHz – Clocks – Up to Four Serial Data Pins Per McASP Port – Integrated High-Frequency Oscillator Used to With Independent TX and RX Clocks Generate a Reference Clock (19.2, 24, 25, – Supports Time Division Multiplexing (TDM), and 26 MHz) for Various System and Inter-IC Sound (I2S), and Similar Formats Peripheral Clocks – Supports Digital Audio Interface Transmission – Supports Individual Clock Enable and Disable (SPDIF, IEC60958-1, and AES-3 Formats) Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption – FIFO Buffers for Transmit and Receive (256 Bytes) – Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB, and – Up to Six UARTs Peripherals [MMC and SD, UART, SPI, I2C], – All UARTs Support IrDA and CIR Modes L3, L4, Ethernet, GFX [SGX530], and LCD – All UARTs Support RTS and CTS Flow Pixel Clock) Control – Power – UART1 Supports Full Modem Control – Two Nonswitchable Power Domains (RTC – Up to Five Master and Slave McSPIs and Wake-Up Logic [WAKE-UP]) – McSPI0–McSPI2 Support up to Four Chip Selects 2 Device Overview Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM4372 AM4376 AM4377 AM4378 AM4379 AM4372, AM4376, AM4377, AM4378, AM4379 www.ti.com SPRS851E –JUNE 2014–REVISED JANUARY 2019 – McSPI3 and McSPI4 Support up to Two Chip (Palletized: 1-, 2-, 4-, and 8-Bits Per Pixel; Selects RGB 16- and 24-Bits Per Pixel; and YUV – Up to 48 MHz 4:2:2) – One Quad-SPI – 256- × 24-Bit Entries Palette in RGB – Supports eXecute In Place (XIP) from Serial – Up to 2048 × 2048 Resolution NOR FLASH – Display Support – One Dallas 1-Wire® and HDQ Serial Interface – Four Types of Displays Are Supported: – Up to Three MMC, SD, and SDIO Ports Passive and Active Colors; Passive and – 1-, 4-, and 8-Bit MMC, SD, and SDIO Modes Active Monochromes – 1.8- or 3.3-V Operation on All Ports – 4- and 8-Bit Monochrome Passive Panel – Up to 48-MHz Clock Interface Support (15 Grayscale Levels Supported Using Dithering Block) – Supports Card Detect and Write Protect – RGB 8-Bit Color Passive Panel Interface – Complies With MMC4.3 and SD and SDIO Support (3,375 Colors Supported for Color 2.0 Specifications 2 Panel Using Dithering Block) – Up to Three I C Master and Slave Interfaces – RGB 12-, 16-, 18-, and 24-Bit Active – Standard Mode (up to 100 kHz) Panel Interface Support (Replicated or – Fast Mode (up to 400 kHz) Dithered Encoded Pixel Values) – Up to Six Banks of General-Purpose I/O (GPIO) – Remote Frame Buffer (Embedded in the – 32 GPIOs per Bank (Multiplexed With Other LCD Panel) Support Through the RFBI Functional Pins) Module – GPIOs Can be Used as Interrupt Inputs (up – Partial Refresh of the Remote Frame to Two Interrupt Inputs per Bank) Buffer Through the RFBI Module – Up to Three External DMA Event Inputs That – Partial Display Can Also be Used as Interrupt Inputs – Multiple Cycles Output Format on 8-, 9-, – Twelve 32-Bit General-Purpose Timers 12-, and 16-Bit Interface (TDM) – DMTIMER1 is a 1-ms Timer Used for – Signal Processing Operating System (OS) Ticks – Overlay and Windowing Support for One – DMTIMER4–DMTIMER7 are Pinned Out Graphics Layer (RGB or CLUT) and Two – One Public Watchdog Timer Video Layers (YUV 4:2:2, RGB16, and – One Free-Running, High-Resolution 32-kHz RGB24) Counter (synctimer32K) – RGB 24-Bit Support on the Display – One Secure Watchdog Timer (Avaliable Only on Interface, Optionally Dithered to RGB AM437xHS Devices) 18‑Bit Pixel Output Plus 6-Bit Frame Rate – SGX530 3D Graphics Engine Control (Spatial and Temporal) – Tile-Based Architecture Delivering up to 20M – Transparency Color Key (Source and Poly/sec Destination) – Universal Scalable Shader Engine is a – Synchronized

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